Simulation Results

Simulation Results: aes/gcm_masked

28/08/2026 21:54:34 DVSim: v1.49.0 sha: a099412 json Branch: master Tool: xcelium [unknown]

Validation stages

V1		0.00%
V2		1.57%
V2S		0.00%
V3		0.00%

0/24 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
wake_up				1
	aes_wake_up	0.834s	0.000us	1
smoke				10
	aes_smoke	0.895s	0.000us	10
csr_hw_reset				1
	aes_csr_hw_reset	0.851s	0.000us	1
csr_rw				5
	aes_csr_rw	0.912s	0.000us	5
csr_bit_bash				1
	aes_csr_bit_bash	0.851s	0.000us	1
csr_aliasing				1
	aes_csr_aliasing	0.838s	0.000us	1
csr_mem_rw_with_rand_reset				5
	aes_csr_mem_rw_with_rand_reset	0.882s	0.000us	5
regwen_csr_and_corresponding_lockable_csr				6
	aes_csr_rw	0.912s	0.000us	5
	aes_csr_aliasing	0.838s	0.000us	1

5/319 passed

1.57 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
algorithm				0	70	0.00
	aes_smoke	0.895s	0.000us	0	10	0.00
	aes_config_error	0.910s	0.000us	0	50	0.00
	aes_stress	0.908s	0.000us	0	10	0.00
key_length				0	70	0.00
	aes_smoke	0.895s	0.000us	0	10	0.00
	aes_config_error	0.910s	0.000us	0	50	0.00
	aes_stress	0.908s	0.000us	0	10	0.00
back2back				0	35	0.00
	aes_stress	0.908s	0.000us	0	10	0.00
	aes_b2b	1.434s	0.000us	0	25	0.00
backpressure				0	10	0.00
	aes_stress	0.908s	0.000us	0	10	0.00
multi_message				0	95	0.00
	aes_smoke	0.895s	0.000us	0	10	0.00
	aes_config_error	0.910s	0.000us	0	50	0.00
	aes_stress	0.908s	0.000us	0	10	0.00
	aes_alert_reset	0.893s	0.000us	0	25	0.00
failure_test				0	85	0.00
	aes_man_cfg_err	1.282s	0.000us	0	10	0.00
	aes_config_error	0.910s	0.000us	0	50	0.00
	aes_alert_reset	0.893s	0.000us	0	25	0.00
trigger_clear_test				0	10	0.00
	aes_clear	0.872s	0.000us	0	10	0.00
nist_test_vectors				0	1	0.00
	aes_nist_vectors	0.854s	0.000us	0	1	0.00
nist_test_vectors_gcm				0	1	0.00
	aes_nist_vectors_gcm	0.832s	0.000us	0	1	0.00
reset_recovery				0	25	0.00
	aes_alert_reset	0.893s	0.000us	0	25	0.00
stress				0	10	0.00
	aes_stress	0.908s	0.000us	0	10	0.00
sideload				0	20	0.00
	aes_stress	0.908s	0.000us	0	10	0.00
	aes_sideload	0.882s	0.000us	0	10	0.00
deinitialization				0	10	0.00
	aes_deinit	0.878s	0.000us	0	10	0.00
stress_all				5	10	50.00
	aes_stress_all	25.000s	1591.371us	5	10	50.00
gcm_save_and_restore				0	100	0.00
	aes_gcm_save_restore	1.431s	0.000us	0	100	0.00
alert_test				0	10	0.00
	aes_alert_test	0.869s	0.000us	0	10	0.00
tl_d_oob_addr_access				0	25	0.00
	aes_tl_errors	1.405s	0.000us	0	25	0.00
tl_d_illegal_access				0	25	0.00
	aes_tl_errors	1.405s	0.000us	0	25	0.00
tl_d_outstanding_access				0	12	0.00
	aes_csr_hw_reset	0.851s	0.000us	0	1	0.00
	aes_csr_rw	0.912s	0.000us	0	5	0.00
	aes_csr_aliasing	0.838s	0.000us	0	1	0.00
	aes_same_csr_outstanding	0.866s	0.000us	0	5	0.00
tl_d_partial_access				0	12	0.00
	aes_csr_hw_reset	0.851s	0.000us	0	1	0.00
	aes_csr_rw	0.912s	0.000us	0	5	0.00
	aes_csr_aliasing	0.838s	0.000us	0	1	0.00
	aes_same_csr_outstanding	0.866s	0.000us	0	5	0.00

V2S

0/1170 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
reseeding				10
	aes_reseed	0.873s	0.000us	10
fault_inject				660
	aes_fi	0.887s	0.000us	10
	aes_control_fi	1.596s	0.000us	300
	aes_cipher_fi	1.620s	0.000us	350
shadow_reg_update_error				20
	aes_shadow_reg_errors	0.917s	0.000us	20
shadow_reg_read_clear_staged_value				20
	aes_shadow_reg_errors	0.917s	0.000us	20
shadow_reg_storage_error				20
	aes_shadow_reg_errors	0.917s	0.000us	20
shadowed_reset_glitch				20
	aes_shadow_reg_errors	0.917s	0.000us	20
shadow_reg_update_error_with_csr_rw				20
	aes_shadow_reg_errors_with_csr_rw	0.884s	0.000us	20
tl_intg_err				30
	aes_sec_cm	0.881s	0.000us	5
	aes_tl_intg_err	0.879s	0.000us	25
sec_cm_bus_integrity				25
	aes_tl_intg_err	0.879s	0.000us	25
sec_cm_lc_escalate_en_intersig_mubi				25
	aes_alert_reset	0.893s	0.000us	25
sec_cm_main_config_shadow				20
	aes_shadow_reg_errors	0.917s	0.000us	20
sec_cm_gcm_config_shadow				20
	aes_shadow_reg_errors	0.917s	0.000us	20
sec_cm_main_config_sparse				145
	aes_smoke	0.895s	0.000us	10
	aes_stress	0.908s	0.000us	10
	aes_alert_reset	0.893s	0.000us	25
	aes_core_fi	1.344s	0.000us	100
sec_cm_gcm_config_sparse				260
	aes_gcm_save_restore	1.431s	0.000us	100
	aes_config_error	0.910s	0.000us	50
	aes_stress	0.908s	0.000us	10
	aes_core_fi	1.344s	0.000us	100
sec_cm_aux_config_shadow				20
	aes_shadow_reg_errors	0.917s	0.000us	20
sec_cm_aux_config_regwen				20
	aes_readability	0.890s	0.000us	10
	aes_stress	0.908s	0.000us	10
sec_cm_key_sideload				20
	aes_stress	0.908s	0.000us	10
	aes_sideload	0.882s	0.000us	10
sec_cm_key_sw_unreadable				10
	aes_readability	0.890s	0.000us	10
sec_cm_data_reg_sw_unreadable				10
	aes_readability	0.890s	0.000us	10
sec_cm_key_sec_wipe				10
	aes_readability	0.890s	0.000us	10
sec_cm_iv_config_sec_wipe				10
	aes_readability	0.890s	0.000us	10
sec_cm_data_reg_sec_wipe				10
	aes_readability	0.890s	0.000us	10
sec_cm_data_reg_key_sca				10
	aes_stress	0.908s	0.000us	10
sec_cm_key_masking				10
	aes_stress	0.908s	0.000us	10
sec_cm_main_fsm_sparse				10
	aes_fi	0.887s	0.000us	10
sec_cm_main_fsm_redun				685
	aes_fi	0.887s	0.000us	10
	aes_control_fi	1.596s	0.000us	300
	aes_cipher_fi	1.620s	0.000us	350
	aes_ctr_fi	1.536s	0.000us	25
sec_cm_cipher_fsm_sparse				10
	aes_fi	0.887s	0.000us	10
sec_cm_cipher_fsm_redun				660
	aes_fi	0.887s	0.000us	10
	aes_control_fi	1.596s	0.000us	300
	aes_cipher_fi	1.620s	0.000us	350
sec_cm_cipher_ctr_redun				350
	aes_cipher_fi	1.620s	0.000us	350
sec_cm_ctr_fsm_sparse				10
	aes_fi	0.887s	0.000us	10
sec_cm_ctr_fsm_redun				335
	aes_fi	0.887s	0.000us	10
	aes_control_fi	1.596s	0.000us	300
	aes_ctr_fi	1.536s	0.000us	25
sec_cm_ghash_fsm_sparse				10
	aes_fi	0.887s	0.000us	10
sec_cm_ctrl_sparse				685
	aes_fi	0.887s	0.000us	10
	aes_control_fi	1.596s	0.000us	300
	aes_cipher_fi	1.620s	0.000us	350
	aes_ctr_fi	1.536s	0.000us	25
sec_cm_main_fsm_global_esc				25
	aes_alert_reset	0.893s	0.000us	25
sec_cm_main_fsm_local_esc				685
	aes_fi	0.887s	0.000us	10
	aes_control_fi	1.596s	0.000us	300
	aes_cipher_fi	1.620s	0.000us	350
	aes_ctr_fi	1.536s	0.000us	25
sec_cm_cipher_fsm_local_esc				685
	aes_fi	0.887s	0.000us	10
	aes_control_fi	1.596s	0.000us	300
	aes_cipher_fi	1.620s	0.000us	350
	aes_ctr_fi	1.536s	0.000us	25
sec_cm_ctr_fsm_local_esc				335
	aes_fi	0.887s	0.000us	10
	aes_control_fi	1.596s	0.000us	300
	aes_ctr_fi	1.536s	0.000us	25
sec_cm_ghash_fsm_local_esc				100
	aes_ghash_fi	0.907s	0.000us	90
	aes_fi	0.887s	0.000us	10
sec_cm_data_reg_local_esc				660
	aes_fi	0.887s	0.000us	10
	aes_control_fi	1.596s	0.000us	300
	aes_cipher_fi	1.620s	0.000us	350

0/10 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	10	0.00
	aes_stress_all_with_rand_reset	0.884s	0.000us	0	10	0.00

Error Messages

	Test	seed	line	log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				1291 test runs
	aes_nist_vectors_gcm	21713695195551905294035641413644909624661234923286261086588008116265155557048	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_nist_vectors_gcm/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/xcelium.d -r tb +SVSEED=2515531448 +UVM_TESTNAME=aes_wake_up_test +UVM_TEST_SEQ=aes_nist_vectors_gcm_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/default/0.aes_nist_vectors_gcm.2515531448 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope default -covtest 0.aes_nist_vectors_gcm.2515531448 -covoverwrite' seed=21713695195551905294035641413644909624661234923286261086588008116265155557048 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21713695195551905294035641413644909624661234923286261086588008116265155557048 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_nist_vectors_gcm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_wake_up_test uvm_test_seq=aes_nist_vectors_gcm_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_gcm_save_restore	27518942462634122299775158549501707973954302401513501072457474125333371104025	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_gcm_save_restore/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/xcelium.d -r tb +SVSEED=907881241 +UVM_TESTNAME=aes_gcm_save_restore_test +UVM_TEST_SEQ=aes_gcm_save_restore_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/default/0.aes_gcm_save_restore.907881241 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope default -covtest 0.aes_gcm_save_restore.907881241 -covoverwrite' seed=27518942462634122299775158549501707973954302401513501072457474125333371104025 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27518942462634122299775158549501707973954302401513501072457474125333371104025 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_gcm_save_restore/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_gcm_save_restore_test uvm_test_seq=aes_gcm_save_restore_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_ghash_fi	64312598369065620614263117888984135236809852080428270952477048218652833658708	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_ghash_fi/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/xcelium.d -r tb +SVSEED=1879488340 +UVM_TESTNAME=aes_ghash_fi_test +UVM_TEST_SEQ=aes_ghash_fi_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/default/0.aes_ghash_fi.1879488340 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope default -covtest 0.aes_ghash_fi.1879488340 -covoverwrite' seed=64312598369065620614263117888984135236809852080428270952477048218652833658708 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64312598369065620614263117888984135236809852080428270952477048218652833658708 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_ghash_fi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_ghash_fi_test uvm_test_seq=aes_ghash_fi_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_wake_up	54468407858558290885091710035055541826338231968054912313614593852666357202952	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_wake_up/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/xcelium.d -r tb +SVSEED=3063660552 +UVM_TESTNAME=aes_wake_up_test +UVM_TEST_SEQ=aes_wake_up_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/default/0.aes_wake_up.3063660552 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope default -covtest 0.aes_wake_up.3063660552 -covoverwrite' seed=54468407858558290885091710035055541826338231968054912313614593852666357202952 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54468407858558290885091710035055541826338231968054912313614593852666357202952 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_wake_up/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_wake_up_test uvm_test_seq=aes_wake_up_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_nist_vectors	99156763253358906411885393072998042741799060465713166333454266174647516067611	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_nist_vectors/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/xcelium.d -r tb +SVSEED=3235968795 +UVM_TESTNAME=aes_wake_up_test +UVM_TEST_SEQ=aes_nist_vectors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/default/0.aes_nist_vectors.3235968795 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope default -covtest 0.aes_nist_vectors.3235968795 -covoverwrite' seed=99156763253358906411885393072998042741799060465713166333454266174647516067611 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99156763253358906411885393072998042741799060465713166333454266174647516067611 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_nist_vectors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_wake_up_test uvm_test_seq=aes_nist_vectors_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_deinit	76235495550329762623735183280636134407569602324099645042982702236136468448918	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_deinit/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/xcelium.d -r tb +SVSEED=2742879894 +UVM_TESTNAME=aes_deinit_test +UVM_TEST_SEQ=aes_deinit_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/default/0.aes_deinit.2742879894 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope default -covtest 0.aes_deinit.2742879894 -covoverwrite' seed=76235495550329762623735183280636134407569602324099645042982702236136468448918 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76235495550329762623735183280636134407569602324099645042982702236136468448918 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_deinit/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_deinit_test uvm_test_seq=aes_deinit_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_man_cfg_err	79002937973807955837173195604572914737397909344133508582314546122393575241310	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_man_cfg_err/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/xcelium.d -r tb +SVSEED=3713545822 +UVM_TESTNAME=aes_manual_config_err_test +UVM_TEST_SEQ=aes_manual_config_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/default/0.aes_man_cfg_err.3713545822 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope default -covtest 0.aes_man_cfg_err.3713545822 -covoverwrite' seed=79002937973807955837173195604572914737397909344133508582314546122393575241310 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79002937973807955837173195604572914737397909344133508582314546122393575241310 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_man_cfg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_manual_config_err_test uvm_test_seq=aes_manual_config_err_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_readability	107127936309715054772793318530269925595455675030735531936744528763936246170556	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_readability/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/xcelium.d -r tb +SVSEED=2627568572 +UVM_TESTNAME=aes_fi_test +UVM_TEST_SEQ=aes_readability_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/default/0.aes_readability.2627568572 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope default -covtest 0.aes_readability.2627568572 -covoverwrite' seed=107127936309715054772793318530269925595455675030735531936744528763936246170556 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107127936309715054772793318530269925595455675030735531936744528763936246170556 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_readability/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_fi_test uvm_test_seq=aes_readability_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_smoke	66848162290711684835806744868863425397885126651154215314662122896299800721741	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_smoke/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/xcelium.d -r tb +SVSEED=162330957 +UVM_TESTNAME=aes_smoke_test +UVM_TEST_SEQ=aes_stress_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/default/0.aes_smoke.162330957 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope default -covtest 0.aes_smoke.162330957 -covoverwrite' seed=66848162290711684835806744868863425397885126651154215314662122896299800721741 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66848162290711684835806744868863425397885126651154215314662122896299800721741 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_smoke_test uvm_test_seq=aes_stress_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_config_error	3080556920013424523970604971943944490738486956178102285814001783642502936969	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_config_error/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/xcelium.d -r tb +SVSEED=803420553 +UVM_TESTNAME=aes_config_error_test +UVM_TEST_SEQ=aes_stress_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/default/0.aes_config_error.803420553 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope default -covtest 0.aes_config_error.803420553 -covoverwrite' seed=3080556920013424523970604971943944490738486956178102285814001783642502936969 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3080556920013424523970604971943944490738486956178102285814001783642502936969 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_config_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_config_error_test uvm_test_seq=aes_stress_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_stress	63520267294049773163322887070624324876256832257664248526139744941754988318508	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_stress/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/xcelium.d -r tb +SVSEED=2491109164 +UVM_TESTNAME=aes_stress_test +UVM_TEST_SEQ=aes_stress_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/default/0.aes_stress.2491109164 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope default -covtest 0.aes_stress.2491109164 -covoverwrite' seed=63520267294049773163322887070624324876256832257664248526139744941754988318508 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63520267294049773163322887070624324876256832257664248526139744941754988318508 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_stress_test uvm_test_seq=aes_stress_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_b2b	28129994648303215027907564980801464248256698440701956335072323605451085890576	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_b2b/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/xcelium.d -r tb +SVSEED=1658504208 +UVM_TESTNAME=aes_b2b_test +UVM_TEST_SEQ=aes_stress_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/default/0.aes_b2b.1658504208 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope default -covtest 0.aes_b2b.1658504208 -covoverwrite' seed=28129994648303215027907564980801464248256698440701956335072323605451085890576 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28129994648303215027907564980801464248256698440701956335072323605451085890576 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_b2b/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_b2b_test uvm_test_seq=aes_stress_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_clear	62627372268919669746387655982730718824412409453099447565369374764553296151589	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_clear/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/xcelium.d -r tb +SVSEED=3739485221 +UVM_TESTNAME=aes_clear_test +UVM_TEST_SEQ=aes_stress_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/default/0.aes_clear.3739485221 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope default -covtest 0.aes_clear.3739485221 -covoverwrite' seed=62627372268919669746387655982730718824412409453099447565369374764553296151589 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62627372268919669746387655982730718824412409453099447565369374764553296151589 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_clear/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_clear_test uvm_test_seq=aes_stress_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_alert_reset	79609722815069031462503751836440351148789685190827388381220006407172264066420	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_alert_reset/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/xcelium.d -r tb +SVSEED=887127412 +UVM_TESTNAME=aes_alert_reset_test +UVM_TEST_SEQ=aes_alert_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/default/0.aes_alert_reset.887127412 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope default -covtest 0.aes_alert_reset.887127412 -covoverwrite' seed=79609722815069031462503751836440351148789685190827388381220006407172264066420 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79609722815069031462503751836440351148789685190827388381220006407172264066420 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_alert_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_alert_reset_test uvm_test_seq=aes_alert_reset_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_sideload	96505890025180337444649036677422424429790091528137158801490231850579748871986	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_sideload/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/xcelium.d -r tb +SVSEED=888037170 +UVM_TESTNAME=aes_sideload_test +UVM_TEST_SEQ=aes_stress_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/default/0.aes_sideload.888037170 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope default -covtest 0.aes_sideload.888037170 -covoverwrite' seed=96505890025180337444649036677422424429790091528137158801490231850579748871986 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96505890025180337444649036677422424429790091528137158801490231850579748871986 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_sideload/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_sideload_test uvm_test_seq=aes_stress_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_reseed	68433487033141775573691556325346351319045752693240986274641445102922057652002	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_reseed/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/xcelium.d -r tb +SVSEED=408950562 +UVM_TESTNAME=aes_reseed_test +UVM_TEST_SEQ=aes_reseed_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/default/0.aes_reseed.408950562 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope default -covtest 0.aes_reseed.408950562 -covoverwrite' seed=68433487033141775573691556325346351319045752693240986274641445102922057652002 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68433487033141775573691556325346351319045752693240986274641445102922057652002 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_reseed/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_reseed_test uvm_test_seq=aes_reseed_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_fi	5969882438789035583603368145432253111215491490746474008010409053065643928714	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_fi/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/xcelium.d -r tb +SVSEED=3102059658 +UVM_TESTNAME=aes_alert_reset_test +UVM_TEST_SEQ=aes_fi_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/default/0.aes_fi.3102059658 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope default -covtest 0.aes_fi.3102059658 -covoverwrite' seed=5969882438789035583603368145432253111215491490746474008010409053065643928714 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5969882438789035583603368145432253111215491490746474008010409053065643928714 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_fi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_alert_reset_test uvm_test_seq=aes_fi_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_control_fi	101333184315237173304475192260573543108801586143840298151282263136507432207839	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_control_fi/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/xcelium.d -r tb +SVSEED=2205615583 +UVM_TESTNAME=aes_fi_test +UVM_TEST_SEQ=aes_control_fi_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/default/0.aes_control_fi.2205615583 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope default -covtest 0.aes_control_fi.2205615583 -covoverwrite' seed=101333184315237173304475192260573543108801586143840298151282263136507432207839 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101333184315237173304475192260573543108801586143840298151282263136507432207839 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_control_fi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_fi_test uvm_test_seq=aes_control_fi_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_cipher_fi	48951577192867905880553069750135360778630660010661059324828321873536286047732	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_cipher_fi/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/xcelium.d -r tb +SVSEED=1843248628 +UVM_TESTNAME=aes_fi_test +UVM_TEST_SEQ=aes_cipher_fi_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/default/0.aes_cipher_fi.1843248628 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope default -covtest 0.aes_cipher_fi.1843248628 -covoverwrite' seed=48951577192867905880553069750135360778630660010661059324828321873536286047732 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48951577192867905880553069750135360778630660010661059324828321873536286047732 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_cipher_fi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_fi_test uvm_test_seq=aes_cipher_fi_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_ctr_fi	79793696353147117025444361427731484244249986166218886898349047388962500817745	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_ctr_fi/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/xcelium.d -r tb +SVSEED=179745617 +UVM_TESTNAME=aes_fi_test +UVM_TEST_SEQ=aes_ctr_fi_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/default/0.aes_ctr_fi.179745617 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope default -covtest 0.aes_ctr_fi.179745617 -covoverwrite' seed=79793696353147117025444361427731484244249986166218886898349047388962500817745 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79793696353147117025444361427731484244249986166218886898349047388962500817745 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_ctr_fi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_fi_test uvm_test_seq=aes_ctr_fi_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_core_fi	70595069947568894747741072765261882357982095827914915425454486738520803183032	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_core_fi/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/xcelium.d -r tb +SVSEED=217123256 +UVM_TESTNAME=aes_fi_test +UVM_TEST_SEQ=aes_core_fi_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/default/0.aes_core_fi.217123256 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope default -covtest 0.aes_core_fi.217123256 -covoverwrite' seed=70595069947568894747741072765261882357982095827914915425454486738520803183032 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70595069947568894747741072765261882357982095827914915425454486738520803183032 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_core_fi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_fi_test uvm_test_seq=aes_core_fi_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_stress_all_with_rand_reset	48289874853265899349683867044773673466556134840457133194400203639271068677436	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aes_stress_all_vseq +uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/xcelium.d -r tb +SVSEED=2631808316 +UVM_TESTNAME=aes_base_test +UVM_TEST_SEQ=aes_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/default/0.aes_stress_all_with_rand_reset.2631808316 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope default -covtest 0.aes_stress_all_with_rand_reset.2631808316 -covoverwrite' seed=48289874853265899349683867044773673466556134840457133194400203639271068677436 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48289874853265899349683867044773673466556134840457133194400203639271068677436 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_base_test uvm_test_seq=aes_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_sec_cm	82271650839205391981069186421365615389219597958087743226435452890052980532986	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/xcelium.d -r tb +SVSEED=560097018 +UVM_TESTNAME=aes_base_test +UVM_TEST_SEQ=aes_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/default/0.aes_sec_cm.560097018 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope default -covtest 0.aes_sec_cm.560097018 -covoverwrite' seed=82271650839205391981069186421365615389219597958087743226435452890052980532986 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82271650839205391981069186421365615389219597958087743226435452890052980532986 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_base_test uvm_test_seq=aes_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_tl_errors	21520362355888008007889033216694464421154618038488164059587147862774635816674	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_tl_errors/latest run_opts='+run_tl_errors +uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=47703778 +UVM_TESTNAME=aes_base_test +UVM_TEST_SEQ=aes_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/cover_reg_top/0.aes_tl_errors.47703778 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.aes_tl_errors.47703778 -covoverwrite' seed=21520362355888008007889033216694464421154618038488164059587147862774635816674 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21520362355888008007889033216694464421154618038488164059587147862774635816674 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_base_test uvm_test_seq=aes_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_tl_intg_err	101892000906582018876638936298115005890248727672463049753139977421315304883076	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=395346820 +UVM_TESTNAME=aes_base_test +UVM_TEST_SEQ=aes_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/cover_reg_top/0.aes_tl_intg_err.395346820 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.aes_tl_intg_err.395346820 -covoverwrite' seed=101892000906582018876638936298115005890248727672463049753139977421315304883076 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101892000906582018876638936298115005890248727672463049753139977421315304883076 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_base_test uvm_test_seq=aes_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_shadow_reg_errors	65565769702737884228142854548330674105252236181333389798048292150341601477543	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=447366055 +UVM_TESTNAME=aes_base_test +UVM_TEST_SEQ=aes_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/cover_reg_top/0.aes_shadow_reg_errors.447366055 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.aes_shadow_reg_errors.447366055 -covoverwrite' seed=65565769702737884228142854548330674105252236181333389798048292150341601477543 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65565769702737884228142854548330674105252236181333389798048292150341601477543 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_base_test uvm_test_seq=aes_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_shadow_reg_errors_with_csr_rw	108597725899366573297892485664093551432496164799778538188064645871464191258774	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=976122006 +UVM_TESTNAME=aes_base_test +UVM_TEST_SEQ=aes_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/cover_reg_top/0.aes_shadow_reg_errors_with_csr_rw.976122006 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.aes_shadow_reg_errors_with_csr_rw.976122006 -covoverwrite' seed=108597725899366573297892485664093551432496164799778538188064645871464191258774 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108597725899366573297892485664093551432496164799778538188064645871464191258774 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_base_test uvm_test_seq=aes_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_csr_hw_reset	5603705232855560741394782220466841284618218013791785621517515201508790009180	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_csr_hw_reset/latest run_opts='+csr_hw_reset +en_scb=0 +uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3342892380 +UVM_TESTNAME=aes_base_test +UVM_TEST_SEQ=aes_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/cover_reg_top/0.aes_csr_hw_reset.3342892380 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.aes_csr_hw_reset.3342892380 -covoverwrite' seed=5603705232855560741394782220466841284618218013791785621517515201508790009180 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5603705232855560741394782220466841284618218013791785621517515201508790009180 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_base_test uvm_test_seq=aes_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_csr_rw	18757642548955765224860104834424578778048931127062365247596190197171206114565	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_csr_rw/latest run_opts='+csr_rw +en_scb=0 +uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3375779077 +UVM_TESTNAME=aes_base_test +UVM_TEST_SEQ=aes_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/cover_reg_top/0.aes_csr_rw.3375779077 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.aes_csr_rw.3375779077 -covoverwrite' seed=18757642548955765224860104834424578778048931127062365247596190197171206114565 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18757642548955765224860104834424578778048931127062365247596190197171206114565 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_base_test uvm_test_seq=aes_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_csr_bit_bash	23254770098537605933040176013583526797044076764532392875144114917144556589029	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_csr_bit_bash/latest run_opts='+csr_bit_bash +en_scb=0 +uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2030424037 +UVM_TESTNAME=aes_base_test +UVM_TEST_SEQ=aes_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/cover_reg_top/0.aes_csr_bit_bash.2030424037 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.aes_csr_bit_bash.2030424037 -covoverwrite' seed=23254770098537605933040176013583526797044076764532392875144114917144556589029 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23254770098537605933040176013583526797044076764532392875144114917144556589029 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_base_test uvm_test_seq=aes_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_csr_aliasing	76113213501587082111252299366840667287567064634361960825197995987358176859392	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_csr_aliasing/latest run_opts='+csr_aliasing +en_scb=0 +uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1451054336 +UVM_TESTNAME=aes_base_test +UVM_TEST_SEQ=aes_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/cover_reg_top/0.aes_csr_aliasing.1451054336 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.aes_csr_aliasing.1451054336 -covoverwrite' seed=76113213501587082111252299366840667287567064634361960825197995987358176859392 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76113213501587082111252299366840667287567064634361960825197995987358176859392 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_base_test uvm_test_seq=aes_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_same_csr_outstanding	58169821317589612543387443736544263567543149164330516140670876516000132274725	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3876362789 +UVM_TESTNAME=aes_base_test +UVM_TEST_SEQ=aes_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/cover_reg_top/0.aes_same_csr_outstanding.3876362789 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.aes_same_csr_outstanding.3876362789 -covoverwrite' seed=58169821317589612543387443736544263567543149164330516140670876516000132274725 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58169821317589612543387443736544263567543149164330516140670876516000132274725 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_base_test uvm_test_seq=aes_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_csr_mem_rw_with_rand_reset	53376724845521111255293186072818326613935227253175268085349195102566435900315	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2711735195 +UVM_TESTNAME=aes_base_test +UVM_TEST_SEQ=aes_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/cover_reg_top/0.aes_csr_mem_rw_with_rand_reset.2711735195 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.aes_csr_mem_rw_with_rand_reset.2711735195 -covoverwrite' seed=53376724845521111255293186072818326613935227253175268085349195102566435900315 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53376724845521111255293186072818326613935227253175268085349195102566435900315 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_base_test uvm_test_seq=aes_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_alert_test	101995882759843147830130459364950651495518165091910215534667814121157805532670	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_alert_test/latest run_opts='+run_alert_test +en_scb=0 +uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/xcelium.d -r tb +SVSEED=1500308990 +UVM_TESTNAME=aes_base_test +UVM_TEST_SEQ=aes_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/default/0.aes_alert_test.1500308990 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope default -covtest 0.aes_alert_test.1500308990 -covoverwrite' seed=101995882759843147830130459364950651495518165091910215534667814121157805532670 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101995882759843147830130459364950651495518165091910215534667814121157805532670 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/0.aes_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_base_test uvm_test_seq=aes_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_gcm_save_restore	106041911712779017423537921405550704216472855274734332476059257163948846702290	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/1.aes_gcm_save_restore/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/xcelium.d -r tb +SVSEED=3180814034 +UVM_TESTNAME=aes_gcm_save_restore_test +UVM_TEST_SEQ=aes_gcm_save_restore_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/default/1.aes_gcm_save_restore.3180814034 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope default -covtest 1.aes_gcm_save_restore.3180814034 -covoverwrite' seed=106041911712779017423537921405550704216472855274734332476059257163948846702290 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106041911712779017423537921405550704216472855274734332476059257163948846702290 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/1.aes_gcm_save_restore/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_gcm_save_restore_test uvm_test_seq=aes_gcm_save_restore_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_ghash_fi	43984772473565702583151381232606128146216186102977753338406471276454268296547	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/1.aes_ghash_fi/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/xcelium.d -r tb +SVSEED=277011811 +UVM_TESTNAME=aes_ghash_fi_test +UVM_TEST_SEQ=aes_ghash_fi_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/default/1.aes_ghash_fi.277011811 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope default -covtest 1.aes_ghash_fi.277011811 -covoverwrite' seed=43984772473565702583151381232606128146216186102977753338406471276454268296547 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43984772473565702583151381232606128146216186102977753338406471276454268296547 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/1.aes_ghash_fi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_ghash_fi_test uvm_test_seq=aes_ghash_fi_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_deinit	102067359432663350197695680745064046427164240575667943650549089060821045205724	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/1.aes_deinit/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/xcelium.d -r tb +SVSEED=3431062236 +UVM_TESTNAME=aes_deinit_test +UVM_TEST_SEQ=aes_deinit_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/default/1.aes_deinit.3431062236 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope default -covtest 1.aes_deinit.3431062236 -covoverwrite' seed=102067359432663350197695680745064046427164240575667943650549089060821045205724 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102067359432663350197695680745064046427164240575667943650549089060821045205724 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/1.aes_deinit/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_deinit_test uvm_test_seq=aes_deinit_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_man_cfg_err	89159397875923142610610758592797087570655080368657293517728226995467223607807	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/1.aes_man_cfg_err/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/xcelium.d -r tb +SVSEED=133999103 +UVM_TESTNAME=aes_manual_config_err_test +UVM_TEST_SEQ=aes_manual_config_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/default/1.aes_man_cfg_err.133999103 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope default -covtest 1.aes_man_cfg_err.133999103 -covoverwrite' seed=89159397875923142610610758592797087570655080368657293517728226995467223607807 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89159397875923142610610758592797087570655080368657293517728226995467223607807 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/1.aes_man_cfg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_manual_config_err_test uvm_test_seq=aes_manual_config_err_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_readability	100829619855391027628379937408778778911257342056454798416911652902626181074656	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/1.aes_readability/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/default/xcelium.d -r tb +SVSEED=1900891872 +UVM_TESTNAME=aes_fi_test +UVM_TEST_SEQ=aes_readability_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage/default/1.aes_readability.1900891872 -covworkdir /nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/coverage -covscope default -covtest 1.aes_readability.1900891872 -covoverwrite' seed=100829619855391027628379937408778778911257342056454798416911652902626181074656 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100829619855391027628379937408778778911257342056454798416911652902626181074656 --run-dir=/nightly/current_run/scratch/master/aes_gcm_masked-sim-xcelium/1.aes_readability/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_fi_test uvm_test_seq=aes_readability_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126