Simulation Results

Simulation Results: aes/gcm_unmasked

28/08/2026 21:54:34 DVSim: v1.49.0 sha: a099412 json Branch: master Tool: xcelium [unknown]

Validation stages

V1		0.00%
V2		1.38%
V2S		0.00%
V3		0.00%

0/24 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
wake_up				1
	aes_wake_up	0.866s	0.000us	1
smoke				10
	aes_smoke	0.879s	0.000us	10
csr_hw_reset				1
	aes_csr_hw_reset	0.829s	0.000us	1
csr_rw				5
	aes_csr_rw	0.856s	0.000us	5
csr_bit_bash				1
	aes_csr_bit_bash	0.829s	0.000us	1
csr_aliasing				1
	aes_csr_aliasing	0.841s	0.000us	1
csr_mem_rw_with_rand_reset				5
	aes_csr_mem_rw_with_rand_reset	1.353s	0.000us	5
regwen_csr_and_corresponding_lockable_csr				6
	aes_csr_rw	0.856s	0.000us	5
	aes_csr_aliasing	0.841s	0.000us	1

3/218 passed

1.38 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
algorithm				0	70	0.00
	aes_smoke	0.879s	0.000us	0	10	0.00
	aes_config_error	1.418s	0.000us	0	50	0.00
	aes_stress	1.353s	0.000us	0	10	0.00
key_length				0	70	0.00
	aes_smoke	0.879s	0.000us	0	10	0.00
	aes_config_error	1.418s	0.000us	0	50	0.00
	aes_stress	1.353s	0.000us	0	10	0.00
back2back				0	35	0.00
	aes_stress	1.353s	0.000us	0	10	0.00
	aes_b2b	1.357s	0.000us	0	25	0.00
backpressure				0	10	0.00
	aes_stress	1.353s	0.000us	0	10	0.00
multi_message				0	95	0.00
	aes_smoke	0.879s	0.000us	0	10	0.00
	aes_config_error	1.418s	0.000us	0	50	0.00
	aes_stress	1.353s	0.000us	0	10	0.00
	aes_alert_reset	1.835s	0.000us	0	25	0.00
failure_test				0	85	0.00
	aes_man_cfg_err	0.948s	0.000us	0	10	0.00
	aes_config_error	1.418s	0.000us	0	50	0.00
	aes_alert_reset	1.835s	0.000us	0	25	0.00
trigger_clear_test				0	10	0.00
	aes_clear	0.911s	0.000us	0	10	0.00
nist_test_vectors				0	1	0.00
	aes_nist_vectors	0.819s	0.000us	0	1	0.00
reset_recovery				0	25	0.00
	aes_alert_reset	1.835s	0.000us	0	25	0.00
stress				0	10	0.00
	aes_stress	1.353s	0.000us	0	10	0.00
sideload				0	20	0.00
	aes_stress	1.353s	0.000us	0	10	0.00
	aes_sideload	1.317s	0.000us	0	10	0.00
deinitialization				0	10	0.00
	aes_deinit	0.912s	0.000us	0	10	0.00
stress_all				3	10	30.00
	aes_stress_all	10802.000s	0.000us	3	10	30.00
alert_test				0	10	0.00
	aes_alert_test	0.904s	0.000us	0	10	0.00
tl_d_oob_addr_access				0	25	0.00
	aes_tl_errors	0.876s	0.000us	0	25	0.00
tl_d_illegal_access				0	25	0.00
	aes_tl_errors	0.876s	0.000us	0	25	0.00
tl_d_outstanding_access				0	12	0.00
	aes_csr_hw_reset	0.829s	0.000us	0	1	0.00
	aes_csr_rw	0.856s	0.000us	0	5	0.00
	aes_csr_aliasing	0.841s	0.000us	0	1	0.00
	aes_same_csr_outstanding	0.858s	0.000us	0	5	0.00
tl_d_partial_access				0	12	0.00
	aes_csr_hw_reset	0.829s	0.000us	0	1	0.00
	aes_csr_rw	0.856s	0.000us	0	5	0.00
	aes_csr_aliasing	0.841s	0.000us	0	1	0.00
	aes_same_csr_outstanding	0.858s	0.000us	0	5	0.00

V2S

0/980 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
reseeding				10
	aes_reseed	1.320s	0.000us	10
fault_inject				660
	aes_fi	0.869s	0.000us	10
	aes_control_fi	1.611s	0.000us	300
	aes_cipher_fi	1.695s	0.000us	350
shadow_reg_update_error				20
	aes_shadow_reg_errors	1.374s	0.000us	20
shadow_reg_read_clear_staged_value				20
	aes_shadow_reg_errors	1.374s	0.000us	20
shadow_reg_storage_error				20
	aes_shadow_reg_errors	1.374s	0.000us	20
shadowed_reset_glitch				20
	aes_shadow_reg_errors	1.374s	0.000us	20
shadow_reg_update_error_with_csr_rw				20
	aes_shadow_reg_errors_with_csr_rw	1.384s	0.000us	20
tl_intg_err				30
	aes_sec_cm	0.862s	0.000us	5
	aes_tl_intg_err	1.400s	0.000us	25
sec_cm_bus_integrity				25
	aes_tl_intg_err	1.400s	0.000us	25
sec_cm_lc_escalate_en_intersig_mubi				25
	aes_alert_reset	1.835s	0.000us	25
sec_cm_main_config_shadow				20
	aes_shadow_reg_errors	1.374s	0.000us	20
sec_cm_gcm_config_shadow				20
	aes_shadow_reg_errors	1.374s	0.000us	20
sec_cm_main_config_sparse				145
	aes_smoke	0.879s	0.000us	10
	aes_stress	1.353s	0.000us	10
	aes_alert_reset	1.835s	0.000us	25
	aes_core_fi	1.369s	0.000us	100
sec_cm_gcm_config_sparse				160
	aes_config_error	1.418s	0.000us	50
	aes_stress	1.353s	0.000us	10
	aes_core_fi	1.369s	0.000us	100
sec_cm_aux_config_shadow				20
	aes_shadow_reg_errors	1.374s	0.000us	20
sec_cm_aux_config_regwen				20
	aes_readability	1.303s	0.000us	10
	aes_stress	1.353s	0.000us	10
sec_cm_key_sideload				20
	aes_stress	1.353s	0.000us	10
	aes_sideload	1.317s	0.000us	10
sec_cm_key_sw_unreadable				10
	aes_readability	1.303s	0.000us	10
sec_cm_data_reg_sw_unreadable				10
	aes_readability	1.303s	0.000us	10
sec_cm_key_sec_wipe				10
	aes_readability	1.303s	0.000us	10
sec_cm_iv_config_sec_wipe				10
	aes_readability	1.303s	0.000us	10
sec_cm_data_reg_sec_wipe				10
	aes_readability	1.303s	0.000us	10
sec_cm_data_reg_key_sca				10
	aes_stress	1.353s	0.000us	10
sec_cm_key_masking				10
	aes_stress	1.353s	0.000us	10
sec_cm_main_fsm_sparse				10
	aes_fi	0.869s	0.000us	10
sec_cm_main_fsm_redun				685
	aes_fi	0.869s	0.000us	10
	aes_control_fi	1.611s	0.000us	300
	aes_cipher_fi	1.695s	0.000us	350
	aes_ctr_fi	0.880s	0.000us	25
sec_cm_cipher_fsm_sparse				10
	aes_fi	0.869s	0.000us	10
sec_cm_cipher_fsm_redun				660
	aes_fi	0.869s	0.000us	10
	aes_control_fi	1.611s	0.000us	300
	aes_cipher_fi	1.695s	0.000us	350
sec_cm_cipher_ctr_redun				350
	aes_cipher_fi	1.695s	0.000us	350
sec_cm_ctr_fsm_sparse				10
	aes_fi	0.869s	0.000us	10
sec_cm_ctr_fsm_redun				335
	aes_fi	0.869s	0.000us	10
	aes_control_fi	1.611s	0.000us	300
	aes_ctr_fi	0.880s	0.000us	25
sec_cm_ghash_fsm_sparse				10
	aes_fi	0.869s	0.000us	10
sec_cm_ctrl_sparse				685
	aes_fi	0.869s	0.000us	10
	aes_control_fi	1.611s	0.000us	300
	aes_cipher_fi	1.695s	0.000us	350
	aes_ctr_fi	0.880s	0.000us	25
sec_cm_main_fsm_global_esc				25
	aes_alert_reset	1.835s	0.000us	25
sec_cm_main_fsm_local_esc				685
	aes_fi	0.869s	0.000us	10
	aes_control_fi	1.611s	0.000us	300
	aes_cipher_fi	1.695s	0.000us	350
	aes_ctr_fi	0.880s	0.000us	25
sec_cm_cipher_fsm_local_esc				685
	aes_fi	0.869s	0.000us	10
	aes_control_fi	1.611s	0.000us	300
	aes_cipher_fi	1.695s	0.000us	350
	aes_ctr_fi	0.880s	0.000us	25
sec_cm_ctr_fsm_local_esc				335
	aes_fi	0.869s	0.000us	10
	aes_control_fi	1.611s	0.000us	300
	aes_ctr_fi	0.880s	0.000us	25
sec_cm_ghash_fsm_local_esc				10
	aes_fi	0.869s	0.000us	10
sec_cm_data_reg_local_esc				660
	aes_fi	0.869s	0.000us	10
	aes_control_fi	1.611s	0.000us	300
	aes_cipher_fi	1.695s	0.000us	350

0/10 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	10	0.00
	aes_stress_all_with_rand_reset	0.913s	0.000us	0	10	0.00

Error Messages

	Test	seed	line	log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				1100 test runs
	aes_wake_up	19018207948073439556851046198609829764109634764693368174161147519768321049449	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_wake_up/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/xcelium.d -r tb +SVSEED=2864956265 +UVM_TESTNAME=aes_wake_up_test +UVM_TEST_SEQ=aes_wake_up_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/default/0.aes_wake_up.2864956265 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope default -covtest 0.aes_wake_up.2864956265 -covoverwrite' seed=19018207948073439556851046198609829764109634764693368174161147519768321049449 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19018207948073439556851046198609829764109634764693368174161147519768321049449 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_wake_up/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_wake_up_test uvm_test_seq=aes_wake_up_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_nist_vectors	7473022254001804377258679842780939009940935875394304367505817108086323278870	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_nist_vectors/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/xcelium.d -r tb +SVSEED=134870038 +UVM_TESTNAME=aes_wake_up_test +UVM_TEST_SEQ=aes_nist_vectors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/default/0.aes_nist_vectors.134870038 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope default -covtest 0.aes_nist_vectors.134870038 -covoverwrite' seed=7473022254001804377258679842780939009940935875394304367505817108086323278870 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7473022254001804377258679842780939009940935875394304367505817108086323278870 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_nist_vectors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_wake_up_test uvm_test_seq=aes_nist_vectors_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_deinit	75016307499096364876594505344919795007766569278779084771977359254634324212378	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_deinit/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/xcelium.d -r tb +SVSEED=1532148378 +UVM_TESTNAME=aes_deinit_test +UVM_TEST_SEQ=aes_deinit_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/default/0.aes_deinit.1532148378 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope default -covtest 0.aes_deinit.1532148378 -covoverwrite' seed=75016307499096364876594505344919795007766569278779084771977359254634324212378 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75016307499096364876594505344919795007766569278779084771977359254634324212378 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_deinit/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_deinit_test uvm_test_seq=aes_deinit_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_man_cfg_err	115741292074415804130358260877539643194233439152442870417272524360408085464394	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_man_cfg_err/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/xcelium.d -r tb +SVSEED=2232845642 +UVM_TESTNAME=aes_manual_config_err_test +UVM_TEST_SEQ=aes_manual_config_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/default/0.aes_man_cfg_err.2232845642 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope default -covtest 0.aes_man_cfg_err.2232845642 -covoverwrite' seed=115741292074415804130358260877539643194233439152442870417272524360408085464394 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115741292074415804130358260877539643194233439152442870417272524360408085464394 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_man_cfg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_manual_config_err_test uvm_test_seq=aes_manual_config_err_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_readability	64087284603429913070600481086104130061308515268401549903462696548768494945591	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_readability/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/xcelium.d -r tb +SVSEED=616072503 +UVM_TESTNAME=aes_fi_test +UVM_TEST_SEQ=aes_readability_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/default/0.aes_readability.616072503 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope default -covtest 0.aes_readability.616072503 -covoverwrite' seed=64087284603429913070600481086104130061308515268401549903462696548768494945591 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64087284603429913070600481086104130061308515268401549903462696548768494945591 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_readability/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_fi_test uvm_test_seq=aes_readability_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_smoke	99386320375954681914898932886490988839680565713978029947174421526412937161205	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_smoke/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/xcelium.d -r tb +SVSEED=661154293 +UVM_TESTNAME=aes_smoke_test +UVM_TEST_SEQ=aes_stress_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/default/0.aes_smoke.661154293 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope default -covtest 0.aes_smoke.661154293 -covoverwrite' seed=99386320375954681914898932886490988839680565713978029947174421526412937161205 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99386320375954681914898932886490988839680565713978029947174421526412937161205 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_smoke_test uvm_test_seq=aes_stress_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_config_error	104392335712784929230185862408401997752117317590909057358538615699672528934259	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_config_error/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/xcelium.d -r tb +SVSEED=1246844275 +UVM_TESTNAME=aes_config_error_test +UVM_TEST_SEQ=aes_stress_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/default/0.aes_config_error.1246844275 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope default -covtest 0.aes_config_error.1246844275 -covoverwrite' seed=104392335712784929230185862408401997752117317590909057358538615699672528934259 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104392335712784929230185862408401997752117317590909057358538615699672528934259 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_config_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_config_error_test uvm_test_seq=aes_stress_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_stress	69605668695337335506261832139032948386331700444881196495270067518324880996171	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_stress/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/xcelium.d -r tb +SVSEED=3107223371 +UVM_TESTNAME=aes_stress_test +UVM_TEST_SEQ=aes_stress_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/default/0.aes_stress.3107223371 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope default -covtest 0.aes_stress.3107223371 -covoverwrite' seed=69605668695337335506261832139032948386331700444881196495270067518324880996171 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69605668695337335506261832139032948386331700444881196495270067518324880996171 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_stress_test uvm_test_seq=aes_stress_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_b2b	7221726651691930183521662868707101041448103413678100919161324669047036634712	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_b2b/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/xcelium.d -r tb +SVSEED=1014163032 +UVM_TESTNAME=aes_b2b_test +UVM_TEST_SEQ=aes_stress_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/default/0.aes_b2b.1014163032 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope default -covtest 0.aes_b2b.1014163032 -covoverwrite' seed=7221726651691930183521662868707101041448103413678100919161324669047036634712 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7221726651691930183521662868707101041448103413678100919161324669047036634712 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_b2b/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_b2b_test uvm_test_seq=aes_stress_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_clear	69479589788755074154253839426054127995707794316272786158903846405384776971098	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_clear/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/xcelium.d -r tb +SVSEED=840430426 +UVM_TESTNAME=aes_clear_test +UVM_TEST_SEQ=aes_stress_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/default/0.aes_clear.840430426 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope default -covtest 0.aes_clear.840430426 -covoverwrite' seed=69479589788755074154253839426054127995707794316272786158903846405384776971098 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69479589788755074154253839426054127995707794316272786158903846405384776971098 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_clear/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_clear_test uvm_test_seq=aes_stress_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_alert_reset	30117511908191425327841508320990366405767645610092571762375027517809416584007	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_alert_reset/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/xcelium.d -r tb +SVSEED=503429959 +UVM_TESTNAME=aes_alert_reset_test +UVM_TEST_SEQ=aes_alert_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/default/0.aes_alert_reset.503429959 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope default -covtest 0.aes_alert_reset.503429959 -covoverwrite' seed=30117511908191425327841508320990366405767645610092571762375027517809416584007 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30117511908191425327841508320990366405767645610092571762375027517809416584007 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_alert_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_alert_reset_test uvm_test_seq=aes_alert_reset_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_sideload	30259694475909595513658382951410271078960837063121225607633861123000830392649	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_sideload/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/xcelium.d -r tb +SVSEED=957217097 +UVM_TESTNAME=aes_sideload_test +UVM_TEST_SEQ=aes_stress_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/default/0.aes_sideload.957217097 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope default -covtest 0.aes_sideload.957217097 -covoverwrite' seed=30259694475909595513658382951410271078960837063121225607633861123000830392649 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30259694475909595513658382951410271078960837063121225607633861123000830392649 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_sideload/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_sideload_test uvm_test_seq=aes_stress_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_reseed	57628484536215316944842430663013236891738516126849914018843411131642371532880	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_reseed/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/xcelium.d -r tb +SVSEED=2198235216 +UVM_TESTNAME=aes_reseed_test +UVM_TEST_SEQ=aes_reseed_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/default/0.aes_reseed.2198235216 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope default -covtest 0.aes_reseed.2198235216 -covoverwrite' seed=57628484536215316944842430663013236891738516126849914018843411131642371532880 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57628484536215316944842430663013236891738516126849914018843411131642371532880 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_reseed/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_reseed_test uvm_test_seq=aes_reseed_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_fi	34139416459855061524419167987027535355039635486203265352334230933283826917937	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_fi/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/xcelium.d -r tb +SVSEED=3200868913 +UVM_TESTNAME=aes_alert_reset_test +UVM_TEST_SEQ=aes_fi_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/default/0.aes_fi.3200868913 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope default -covtest 0.aes_fi.3200868913 -covoverwrite' seed=34139416459855061524419167987027535355039635486203265352334230933283826917937 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34139416459855061524419167987027535355039635486203265352334230933283826917937 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_fi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_alert_reset_test uvm_test_seq=aes_fi_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_control_fi	70160907657712263051192770207179596865589426853982803057484057529685347874963	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_control_fi/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/xcelium.d -r tb +SVSEED=3907205267 +UVM_TESTNAME=aes_fi_test +UVM_TEST_SEQ=aes_control_fi_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/default/0.aes_control_fi.3907205267 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope default -covtest 0.aes_control_fi.3907205267 -covoverwrite' seed=70160907657712263051192770207179596865589426853982803057484057529685347874963 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70160907657712263051192770207179596865589426853982803057484057529685347874963 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_control_fi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_fi_test uvm_test_seq=aes_control_fi_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_cipher_fi	95357089941049815620305450305014554984683162123569571947203640622015846962394	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_cipher_fi/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/xcelium.d -r tb +SVSEED=319182042 +UVM_TESTNAME=aes_fi_test +UVM_TEST_SEQ=aes_cipher_fi_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/default/0.aes_cipher_fi.319182042 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope default -covtest 0.aes_cipher_fi.319182042 -covoverwrite' seed=95357089941049815620305450305014554984683162123569571947203640622015846962394 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95357089941049815620305450305014554984683162123569571947203640622015846962394 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_cipher_fi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_fi_test uvm_test_seq=aes_cipher_fi_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_ctr_fi	80596938031561832187618271817996155846007943668149121270707878420760710610096	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_ctr_fi/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/xcelium.d -r tb +SVSEED=1416101040 +UVM_TESTNAME=aes_fi_test +UVM_TEST_SEQ=aes_ctr_fi_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/default/0.aes_ctr_fi.1416101040 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope default -covtest 0.aes_ctr_fi.1416101040 -covoverwrite' seed=80596938031561832187618271817996155846007943668149121270707878420760710610096 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80596938031561832187618271817996155846007943668149121270707878420760710610096 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_ctr_fi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_fi_test uvm_test_seq=aes_ctr_fi_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_core_fi	72283906937568994801195933870067987016686237321951891070665736211905882371863	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_core_fi/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/xcelium.d -r tb +SVSEED=252458775 +UVM_TESTNAME=aes_fi_test +UVM_TEST_SEQ=aes_core_fi_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/default/0.aes_core_fi.252458775 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope default -covtest 0.aes_core_fi.252458775 -covoverwrite' seed=72283906937568994801195933870067987016686237321951891070665736211905882371863 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72283906937568994801195933870067987016686237321951891070665736211905882371863 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_core_fi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_fi_test uvm_test_seq=aes_core_fi_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_stress_all_with_rand_reset	46605194313242233250308258067106530870058175203064373326328669759930208022327	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=aes_stress_all_vseq +uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/xcelium.d -r tb +SVSEED=4055297847 +UVM_TESTNAME=aes_base_test +UVM_TEST_SEQ=aes_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/default/0.aes_stress_all_with_rand_reset.4055297847 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope default -covtest 0.aes_stress_all_with_rand_reset.4055297847 -covoverwrite' seed=46605194313242233250308258067106530870058175203064373326328669759930208022327 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46605194313242233250308258067106530870058175203064373326328669759930208022327 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_base_test uvm_test_seq=aes_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_sec_cm	43559498740639593590014214888353676270561148439895901747143912297630338525122	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/xcelium.d -r tb +SVSEED=343812034 +UVM_TESTNAME=aes_base_test +UVM_TEST_SEQ=aes_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/default/0.aes_sec_cm.343812034 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope default -covtest 0.aes_sec_cm.343812034 -covoverwrite' seed=43559498740639593590014214888353676270561148439895901747143912297630338525122 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43559498740639593590014214888353676270561148439895901747143912297630338525122 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_base_test uvm_test_seq=aes_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_tl_errors	89540771321848036438402044515161059086415686951207552802176428704306011938189	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_tl_errors/latest run_opts='+run_tl_errors +uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2273680781 +UVM_TESTNAME=aes_base_test +UVM_TEST_SEQ=aes_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/cover_reg_top/0.aes_tl_errors.2273680781 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.aes_tl_errors.2273680781 -covoverwrite' seed=89540771321848036438402044515161059086415686951207552802176428704306011938189 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89540771321848036438402044515161059086415686951207552802176428704306011938189 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_base_test uvm_test_seq=aes_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_tl_intg_err	115371579405940012318302788337753006161607006936159648944354019965773303754741	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3753357301 +UVM_TESTNAME=aes_base_test +UVM_TEST_SEQ=aes_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/cover_reg_top/0.aes_tl_intg_err.3753357301 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.aes_tl_intg_err.3753357301 -covoverwrite' seed=115371579405940012318302788337753006161607006936159648944354019965773303754741 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115371579405940012318302788337753006161607006936159648944354019965773303754741 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_base_test uvm_test_seq=aes_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_shadow_reg_errors	3146920266992191107158556331917120831833169628666572592954353148045028338700	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2310122508 +UVM_TESTNAME=aes_base_test +UVM_TEST_SEQ=aes_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/cover_reg_top/0.aes_shadow_reg_errors.2310122508 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.aes_shadow_reg_errors.2310122508 -covoverwrite' seed=3146920266992191107158556331917120831833169628666572592954353148045028338700 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3146920266992191107158556331917120831833169628666572592954353148045028338700 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_base_test uvm_test_seq=aes_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_shadow_reg_errors_with_csr_rw	35246700739155749712555269753235906444320564460307711360662851732155715668521	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1439549993 +UVM_TESTNAME=aes_base_test +UVM_TEST_SEQ=aes_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/cover_reg_top/0.aes_shadow_reg_errors_with_csr_rw.1439549993 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.aes_shadow_reg_errors_with_csr_rw.1439549993 -covoverwrite' seed=35246700739155749712555269753235906444320564460307711360662851732155715668521 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35246700739155749712555269753235906444320564460307711360662851732155715668521 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_base_test uvm_test_seq=aes_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_csr_hw_reset	29223778133571054742026463587545520942353013208949785198227412792798333648684	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_csr_hw_reset/latest run_opts='+csr_hw_reset +en_scb=0 +uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1156595500 +UVM_TESTNAME=aes_base_test +UVM_TEST_SEQ=aes_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/cover_reg_top/0.aes_csr_hw_reset.1156595500 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.aes_csr_hw_reset.1156595500 -covoverwrite' seed=29223778133571054742026463587545520942353013208949785198227412792798333648684 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29223778133571054742026463587545520942353013208949785198227412792798333648684 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_base_test uvm_test_seq=aes_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_csr_rw	100174875565941045490971614627482658442479483120389531856409985592485927881806	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_csr_rw/latest run_opts='+csr_rw +en_scb=0 +uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=835357774 +UVM_TESTNAME=aes_base_test +UVM_TEST_SEQ=aes_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/cover_reg_top/0.aes_csr_rw.835357774 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.aes_csr_rw.835357774 -covoverwrite' seed=100174875565941045490971614627482658442479483120389531856409985592485927881806 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100174875565941045490971614627482658442479483120389531856409985592485927881806 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_base_test uvm_test_seq=aes_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_csr_bit_bash	4254386706335036784598488659507184066495974920904347074495587502778351734562	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_csr_bit_bash/latest run_opts='+csr_bit_bash +en_scb=0 +uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2278674210 +UVM_TESTNAME=aes_base_test +UVM_TEST_SEQ=aes_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/cover_reg_top/0.aes_csr_bit_bash.2278674210 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.aes_csr_bit_bash.2278674210 -covoverwrite' seed=4254386706335036784598488659507184066495974920904347074495587502778351734562 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4254386706335036784598488659507184066495974920904347074495587502778351734562 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_base_test uvm_test_seq=aes_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_csr_aliasing	23908014387893155854543524048782198109228985102691982421356016739409334383895	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_csr_aliasing/latest run_opts='+csr_aliasing +en_scb=0 +uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2773497111 +UVM_TESTNAME=aes_base_test +UVM_TEST_SEQ=aes_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/cover_reg_top/0.aes_csr_aliasing.2773497111 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.aes_csr_aliasing.2773497111 -covoverwrite' seed=23908014387893155854543524048782198109228985102691982421356016739409334383895 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23908014387893155854543524048782198109228985102691982421356016739409334383895 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_base_test uvm_test_seq=aes_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_same_csr_outstanding	94450204514138566669769398414406725547899145860704857474754960525833785084414	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1377864190 +UVM_TESTNAME=aes_base_test +UVM_TEST_SEQ=aes_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/cover_reg_top/0.aes_same_csr_outstanding.1377864190 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.aes_same_csr_outstanding.1377864190 -covoverwrite' seed=94450204514138566669769398414406725547899145860704857474754960525833785084414 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94450204514138566669769398414406725547899145860704857474754960525833785084414 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_base_test uvm_test_seq=aes_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_csr_mem_rw_with_rand_reset	40333605842510130363272370971745152061306280644961326171702215051703919080827	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1267234171 +UVM_TESTNAME=aes_base_test +UVM_TEST_SEQ=aes_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/cover_reg_top/0.aes_csr_mem_rw_with_rand_reset.1267234171 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.aes_csr_mem_rw_with_rand_reset.1267234171 -covoverwrite' seed=40333605842510130363272370971745152061306280644961326171702215051703919080827 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40333605842510130363272370971745152061306280644961326171702215051703919080827 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_base_test uvm_test_seq=aes_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_alert_test	83386944376764111516907526965745153766413263455203642449423684363840119480303	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_alert_test/latest run_opts='+run_alert_test +en_scb=0 +uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/xcelium.d -r tb +SVSEED=3930955759 +UVM_TESTNAME=aes_base_test +UVM_TEST_SEQ=aes_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/default/0.aes_alert_test.3930955759 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope default -covtest 0.aes_alert_test.3930955759 -covoverwrite' seed=83386944376764111516907526965745153766413263455203642449423684363840119480303 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83386944376764111516907526965745153766413263455203642449423684363840119480303 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/0.aes_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_base_test uvm_test_seq=aes_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_deinit	101798508193253264568904683928142508290789257696583808356504698575199394980009	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/1.aes_deinit/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/xcelium.d -r tb +SVSEED=4097171625 +UVM_TESTNAME=aes_deinit_test +UVM_TEST_SEQ=aes_deinit_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/default/1.aes_deinit.4097171625 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope default -covtest 1.aes_deinit.4097171625 -covoverwrite' seed=101798508193253264568904683928142508290789257696583808356504698575199394980009 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101798508193253264568904683928142508290789257696583808356504698575199394980009 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/1.aes_deinit/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_deinit_test uvm_test_seq=aes_deinit_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_man_cfg_err	25529604865188071235985060781955863007103622558496743270306806651776902198502	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/1.aes_man_cfg_err/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/xcelium.d -r tb +SVSEED=2499376358 +UVM_TESTNAME=aes_manual_config_err_test +UVM_TEST_SEQ=aes_manual_config_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/default/1.aes_man_cfg_err.2499376358 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope default -covtest 1.aes_man_cfg_err.2499376358 -covoverwrite' seed=25529604865188071235985060781955863007103622558496743270306806651776902198502 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25529604865188071235985060781955863007103622558496743270306806651776902198502 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/1.aes_man_cfg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_manual_config_err_test uvm_test_seq=aes_manual_config_err_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_readability	26217711646512965676063365564712544686466021121992708642329611113748500247220	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/1.aes_readability/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/xcelium.d -r tb +SVSEED=1501229748 +UVM_TESTNAME=aes_fi_test +UVM_TEST_SEQ=aes_readability_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/default/1.aes_readability.1501229748 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope default -covtest 1.aes_readability.1501229748 -covoverwrite' seed=26217711646512965676063365564712544686466021121992708642329611113748500247220 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26217711646512965676063365564712544686466021121992708642329611113748500247220 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/1.aes_readability/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_fi_test uvm_test_seq=aes_readability_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_smoke	8818569218800761451707763625260574058511329636100039885057178103933477670577	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/1.aes_smoke/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/xcelium.d -r tb +SVSEED=2204978865 +UVM_TESTNAME=aes_smoke_test +UVM_TEST_SEQ=aes_stress_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/default/1.aes_smoke.2204978865 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope default -covtest 1.aes_smoke.2204978865 -covoverwrite' seed=8818569218800761451707763625260574058511329636100039885057178103933477670577 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8818569218800761451707763625260574058511329636100039885057178103933477670577 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/1.aes_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_smoke_test uvm_test_seq=aes_stress_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_config_error	43961839071992064441086313130162850442151561508370004063683307609580862632550	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/1.aes_config_error/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/xcelium.d -r tb +SVSEED=3925799526 +UVM_TESTNAME=aes_config_error_test +UVM_TEST_SEQ=aes_stress_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/default/1.aes_config_error.3925799526 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope default -covtest 1.aes_config_error.3925799526 -covoverwrite' seed=43961839071992064441086313130162850442151561508370004063683307609580862632550 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43961839071992064441086313130162850442151561508370004063683307609580862632550 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/1.aes_config_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_config_error_test uvm_test_seq=aes_stress_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_stress	40978960647022813253132156285040985709014192617113028053767872401328070295713	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/1.aes_stress/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/xcelium.d -r tb +SVSEED=2633072801 +UVM_TESTNAME=aes_stress_test +UVM_TEST_SEQ=aes_stress_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/default/1.aes_stress.2633072801 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope default -covtest 1.aes_stress.2633072801 -covoverwrite' seed=40978960647022813253132156285040985709014192617113028053767872401328070295713 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40978960647022813253132156285040985709014192617113028053767872401328070295713 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/1.aes_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_stress_test uvm_test_seq=aes_stress_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_b2b	70897037369150039455010437644472717246971025214670119138015592276192277204522	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/1.aes_b2b/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/xcelium.d -r tb +SVSEED=1773571626 +UVM_TESTNAME=aes_b2b_test +UVM_TEST_SEQ=aes_stress_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/default/1.aes_b2b.1773571626 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope default -covtest 1.aes_b2b.1773571626 -covoverwrite' seed=70897037369150039455010437644472717246971025214670119138015592276192277204522 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70897037369150039455010437644472717246971025214670119138015592276192277204522 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/1.aes_b2b/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_b2b_test uvm_test_seq=aes_stress_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	aes_clear	109021564016035856710410852670805774293424781736756328292253696454376523492114	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/1.aes_clear/latest run_opts='+uvm_set_verbosity=uvm_test_top.env.scoreboard,_ALL_,UVM_MEDIUM,run +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/default/xcelium.d -r tb +SVSEED=2269571858 +UVM_TESTNAME=aes_clear_test +UVM_TEST_SEQ=aes_stress_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage/default/1.aes_clear.2269571858 -covworkdir /nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/coverage -covscope default -covtest 1.aes_clear.2269571858 -covoverwrite' seed=109021564016035856710410852670805774293424781736756328292253696454376523492114 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109021564016035856710410852670805774293424781736756328292253696454376523492114 --run-dir=/nightly/current_run/scratch/master/aes_gcm_unmasked-sim-xcelium/1.aes_clear/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=aes_clear_test uvm_test_seq=aes_stress_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126