| V1 |
|
0.00% |
| V2 |
|
4.73% |
| V2S |
|
0.00% |
| V3 |
|
0.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 0 | 10 | 0.00 | |||
| alert_handler_smoke | 0.879s | 0.000us | 0 | 10 | 0.00 | |
| csr_hw_reset | 0 | 1 | 0.00 | |||
| alert_handler_csr_hw_reset | 0.852s | 0.000us | 0 | 1 | 0.00 | |
| csr_rw | 0 | 5 | 0.00 | |||
| alert_handler_csr_rw | 0.876s | 0.000us | 0 | 5 | 0.00 | |
| csr_bit_bash | 0 | 1 | 0.00 | |||
| alert_handler_csr_bit_bash | 1.321s | 0.000us | 0 | 1 | 0.00 | |
| csr_aliasing | 0 | 1 | 0.00 | |||
| alert_handler_csr_aliasing | 0.875s | 0.000us | 0 | 1 | 0.00 | |
| csr_mem_rw_with_rand_reset | 0 | 5 | 0.00 | |||
| alert_handler_csr_mem_rw_with_rand_reset | 0.855s | 0.000us | 0 | 5 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 0 | 6 | 0.00 | |||
| alert_handler_csr_rw | 0.876s | 0.000us | 0 | 5 | 0.00 | |
| alert_handler_csr_aliasing | 0.875s | 0.000us | 0 | 1 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| esc_accum | 0 | 25 | 0.00 | |||
| alert_handler_esc_alert_accum | 0.871s | 0.000us | 0 | 25 | 0.00 | |
| esc_timeout | 0 | 50 | 0.00 | |||
| alert_handler_esc_intr_timeout | 0.876s | 0.000us | 0 | 50 | 0.00 | |
| entropy | 0 | 25 | 0.00 | |||
| alert_handler_entropy | 1.403s | 0.000us | 0 | 25 | 0.00 | |
| sig_int_fail | 0 | 50 | 0.00 | |||
| alert_handler_sig_int_fail | 0.988s | 0.000us | 0 | 50 | 0.00 | |
| clk_skew | 0 | 10 | 0.00 | |||
| alert_handler_smoke | 0.879s | 0.000us | 0 | 10 | 0.00 | |
| random_alerts | 0 | 10 | 0.00 | |||
| alert_handler_random_alerts | 0.886s | 0.000us | 0 | 10 | 0.00 | |
| random_classes | 0 | 50 | 0.00 | |||
| alert_handler_random_classes | 1.408s | 0.000us | 0 | 50 | 0.00 | |
| ping_timeout | 0 | 50 | 0.00 | |||
| alert_handler_ping_timeout | 1.884s | 0.000us | 0 | 50 | 0.00 | |
| lpg | 0 | 100 | 0.00 | |||
| alert_handler_lpg | 0.890s | 0.000us | 0 | 50 | 0.00 | |
| alert_handler_lpg_stub_clk | 0.893s | 0.000us | 0 | 50 | 0.00 | |
| stress_all | 24 | 50 | 48.00 | |||
| alert_handler_stress_all | 4704.490s | 505356.697us | 24 | 50 | 48.00 | |
| alert_handler_entropy_stress_test | 0 | 20 | 0.00 | |||
| alert_handler_entropy_stress | 1.361s | 0.000us | 0 | 20 | 0.00 | |
| alert_handler_alert_accum_saturation | 0 | 20 | 0.00 | |||
| alert_handler_alert_accum_saturation | 0.881s | 0.000us | 0 | 20 | 0.00 | |
| intr_test | 0 | 10 | 0.00 | |||
| alert_handler_intr_test | 0.875s | 0.000us | 0 | 10 | 0.00 | |
| tl_d_oob_addr_access | 0 | 25 | 0.00 | |||
| alert_handler_tl_errors | 1.420s | 0.000us | 0 | 25 | 0.00 | |
| tl_d_illegal_access | 0 | 25 | 0.00 | |||
| alert_handler_tl_errors | 1.420s | 0.000us | 0 | 25 | 0.00 | |
| tl_d_outstanding_access | 0 | 12 | 0.00 | |||
| alert_handler_csr_hw_reset | 0.852s | 0.000us | 0 | 1 | 0.00 | |
| alert_handler_csr_rw | 0.876s | 0.000us | 0 | 5 | 0.00 | |
| alert_handler_csr_aliasing | 0.875s | 0.000us | 0 | 1 | 0.00 | |
| alert_handler_same_csr_outstanding | 0.865s | 0.000us | 0 | 5 | 0.00 | |
| tl_d_partial_access | 0 | 12 | 0.00 | |||
| alert_handler_csr_hw_reset | 0.852s | 0.000us | 0 | 1 | 0.00 | |
| alert_handler_csr_rw | 0.876s | 0.000us | 0 | 5 | 0.00 | |
| alert_handler_csr_aliasing | 0.875s | 0.000us | 0 | 1 | 0.00 | |
| alert_handler_same_csr_outstanding | 0.865s | 0.000us | 0 | 5 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| shadow_reg_update_error | 0 | 20 | 0.00 | |||
| alert_handler_shadow_reg_errors | 0.884s | 0.000us | 0 | 20 | 0.00 | |
| shadow_reg_read_clear_staged_value | 0 | 20 | 0.00 | |||
| alert_handler_shadow_reg_errors | 0.884s | 0.000us | 0 | 20 | 0.00 | |
| shadow_reg_storage_error | 0 | 20 | 0.00 | |||
| alert_handler_shadow_reg_errors | 0.884s | 0.000us | 0 | 20 | 0.00 | |
| shadowed_reset_glitch | 0 | 20 | 0.00 | |||
| alert_handler_shadow_reg_errors | 0.884s | 0.000us | 0 | 20 | 0.00 | |
| shadow_reg_update_error_with_csr_rw | 0 | 20 | 0.00 | |||
| alert_handler_shadow_reg_errors_with_csr_rw | 0.133s | 0.000us | 0 | 20 | 0.00 | |
| tl_intg_err | 0 | 30 | 0.00 | |||
| alert_handler_sec_cm | 1.328s | 0.000us | 0 | 5 | 0.00 | |
| alert_handler_tl_intg_err | 0.968s | 0.000us | 0 | 25 | 0.00 | |
| sec_cm_bus_integrity | 0 | 25 | 0.00 | |||
| alert_handler_tl_intg_err | 0.968s | 0.000us | 0 | 25 | 0.00 | |
| sec_cm_config_shadow | 0 | 20 | 0.00 | |||
| alert_handler_shadow_reg_errors | 0.884s | 0.000us | 0 | 20 | 0.00 | |
| sec_cm_ping_timer_config_regwen | 0 | 10 | 0.00 | |||
| alert_handler_smoke | 0.879s | 0.000us | 0 | 10 | 0.00 | |
| sec_cm_alert_config_regwen | 0 | 10 | 0.00 | |||
| alert_handler_smoke | 0.879s | 0.000us | 0 | 10 | 0.00 | |
| sec_cm_alert_loc_config_regwen | 0 | 10 | 0.00 | |||
| alert_handler_smoke | 0.879s | 0.000us | 0 | 10 | 0.00 | |
| sec_cm_class_config_regwen | 0 | 10 | 0.00 | |||
| alert_handler_smoke | 0.879s | 0.000us | 0 | 10 | 0.00 | |
| sec_cm_alert_intersig_diff | 0 | 50 | 0.00 | |||
| alert_handler_sig_int_fail | 0.988s | 0.000us | 0 | 50 | 0.00 | |
| sec_cm_lpg_intersig_mubi | 0 | 50 | 0.00 | |||
| alert_handler_lpg | 0.890s | 0.000us | 0 | 50 | 0.00 | |
| sec_cm_esc_intersig_diff | 0 | 50 | 0.00 | |||
| alert_handler_sig_int_fail | 0.988s | 0.000us | 0 | 50 | 0.00 | |
| sec_cm_alert_rx_intersig_bkgn_chk | 0 | 25 | 0.00 | |||
| alert_handler_entropy | 1.403s | 0.000us | 0 | 25 | 0.00 | |
| sec_cm_esc_tx_intersig_bkgn_chk | 0 | 25 | 0.00 | |||
| alert_handler_entropy | 1.403s | 0.000us | 0 | 25 | 0.00 | |
| sec_cm_esc_timer_fsm_sparse | 0 | 5 | 0.00 | |||
| alert_handler_sec_cm | 1.328s | 0.000us | 0 | 5 | 0.00 | |
| sec_cm_ping_timer_fsm_sparse | 0 | 5 | 0.00 | |||
| alert_handler_sec_cm | 1.328s | 0.000us | 0 | 5 | 0.00 | |
| sec_cm_esc_timer_fsm_local_esc | 0 | 5 | 0.00 | |||
| alert_handler_sec_cm | 1.328s | 0.000us | 0 | 5 | 0.00 | |
| sec_cm_ping_timer_fsm_local_esc | 0 | 5 | 0.00 | |||
| alert_handler_sec_cm | 1.328s | 0.000us | 0 | 5 | 0.00 | |
| sec_cm_esc_timer_fsm_global_esc | 0 | 5 | 0.00 | |||
| alert_handler_sec_cm | 1.328s | 0.000us | 0 | 5 | 0.00 | |
| sec_cm_accu_ctr_redun | 0 | 5 | 0.00 | |||
| alert_handler_sec_cm | 1.328s | 0.000us | 0 | 5 | 0.00 | |
| sec_cm_esc_timer_ctr_redun | 0 | 5 | 0.00 | |||
| alert_handler_sec_cm | 1.328s | 0.000us | 0 | 5 | 0.00 | |
| sec_cm_ping_timer_ctr_redun | 0 | 5 | 0.00 | |||
| alert_handler_sec_cm | 1.328s | 0.000us | 0 | 5 | 0.00 | |
| sec_cm_ping_timer_lfsr_redun | 0 | 5 | 0.00 | |||
| alert_handler_sec_cm | 1.328s | 0.000us | 0 | 5 | 0.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 0 | 10 | 0.00 | |||
| alert_handler_stress_all_with_rand_reset | 1.417s | 0.000us | 0 | 10 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] | 543 test runs | |||
| alert_handler_smoke | 12514060008432235569590212665519840336514247680494805090517850407809906824908 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=99276492 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.99276492' seed=12514060008432235569590212665519840336514247680494805090517850407809906824908 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12514060008432235569590212665519840336514247680494805090517850407809906824908 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_alerts | 90752237783727621639807250223383510480357875039736716758457730315427922252161 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_random_alerts/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=848236929 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.848236929' seed=90752237783727621639807250223383510480357875039736716758457730315427922252161 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90752237783727621639807250223383510480357875039736716758457730315427922252161 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_random_alerts/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_alerts_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 88009497947992807586832993588742743513833104848910999950215932548005201914153 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4224395561 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.4224395561' seed=88009497947992807586832993588742743513833104848910999950215932548005201914153 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88009497947992807586832993588742743513833104848910999950215932548005201914153 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 76607308724125540936314725068958288079091354946792215429787453894306242574784 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2595568064 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2595568064' seed=76607308724125540936314725068958288079091354946792215429787453894306242574784 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76607308724125540936314725068958288079091354946792215429787453894306242574784 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_alert_accum | 21918893970305306528964829555416093325699494964972990290937991076564119165945 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_esc_alert_accum/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2983042041 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.2983042041' seed=21918893970305306528964829555416093325699494964972990290937991076564119165945 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21918893970305306528964829555416093325699494964972990290937991076564119165945 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_esc_alert_accum/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_alert_accum_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 68777760724787597989411422788585440453524568728868384034209756435788200146632 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3438540488 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.3438540488' seed=68777760724787597989411422788585440453524568728868384034209756435788200146632 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68777760724787597989411422788585440453524568728868384034209756435788200146632 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy | 64554353791766610904672974027736752152558575531711884649172358195284294947777 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_entropy/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2137969601 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.2137969601' seed=64554353791766610904672974027736752152558575531711884649172358195284294947777 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64554353791766610904672974027736752152558575531711884649172358195284294947777 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_entropy/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 99313394989826877764043170992646196809001505623377368675942953578228299175628 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1965659852 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.1965659852' seed=99313394989826877764043170992646196809001505623377368675942953578228299175628 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99313394989826877764043170992646196809001505623377368675942953578228299175628 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 12177812590614477614853997639142506817421065069472881168555360645960948693940 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1204992948 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1204992948' seed=12177812590614477614853997639142506817421065069472881168555360645960948693940 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12177812590614477614853997639142506817421065069472881168555360645960948693940 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 70618497415567567360842661910159280590526729316643638736549100878900211381801 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1071805993 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.1071805993' seed=70618497415567567360842661910159280590526729316643638736549100878900211381801 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70618497415567567360842661910159280590526729316643638736549100878900211381801 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy_stress | 69732747394246864592214255647897964276776570372780942632117805816740679401421 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_entropy_stress/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3489021901 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.3489021901' seed=69732747394246864592214255647897964276776570372780942632117805816740679401421 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69732747394246864592214255647897964276776570372780942632117805816740679401421 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_entropy_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_stress_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors_with_csr_rw | 522149378693185221584792377946459952104126097469852829735247748567750160610 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors_with_csr_rw/latest run_opts='+test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=513290466 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.513290466' seed=522149378693185221584792377946459952104126097469852829735247748567750160610 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=522149378693185221584792377946459952104126097469852829735247748567750160610 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_alert_accum_saturation | 89330252320591364025954597959643646886322606241207266566306167941743126477285 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_alert_accum_saturation/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2471197157 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.2471197157' seed=89330252320591364025954597959643646886322606241207266566306167941743126477285 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89330252320591364025954597959643646886322606241207266566306167941743126477285 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_alert_accum_saturation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_alert_accum_saturation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_stress_all_with_rand_reset | 103241293404886382819191815949229774198639045159779730233217463700784107861707 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1547024075 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.1547024075' seed=103241293404886382819191815949229774198639045159779730233217463700784107861707 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103241293404886382819191815949229774198639045159779730233217463700784107861707 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sec_cm | 63540017187028758635233344280200462673761434501893272870662903054906921059970 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1141638786 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.1141638786' seed=63540017187028758635233344280200462673761434501893272870662903054906921059970 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63540017187028758635233344280200462673761434501893272870662903054906921059970 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors | 9454513995422208223691241750667355658337697983278544427865414396819764921209 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=65520505 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_errors.65520505' seed=9454513995422208223691241750667355658337697983278544427865414396819764921209 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9454513995422208223691241750667355658337697983278544427865414396819764921209 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_errors | 102955342372606198916915999022596009440428683049847294623124514786992418612610 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1676305794 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.1676305794' seed=102955342372606198916915999022596009440428683049847294623124514786992418612610 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102955342372606198916915999022596009440428683049847294623124514786992418612610 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_intg_err | 44219594099402581873071508343757682851614938319285864657679528791069128035795 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3064106451 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.3064106451' seed=44219594099402581873071508343757682851614938319285864657679528791069128035795 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44219594099402581873071508343757682851614938319285864657679528791069128035795 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_intr_test | 5224652594027408634007530529461164839551191020371125317444169107221458394881 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_intr_test/latest run_opts='+run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=176889601 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.176889601' seed=5224652594027408634007530529461164839551191020371125317444169107221458394881 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5224652594027408634007530529461164839551191020371125317444169107221458394881 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_csr_hw_reset | 106786718808037714849567792021032535192310855833052902627383217900120400741069 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_csr_hw_reset/latest run_opts='+csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2675720909 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2675720909' seed=106786718808037714849567792021032535192310855833052902627383217900120400741069 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106786718808037714849567792021032535192310855833052902627383217900120400741069 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_csr_rw | 58005851784081892733164605908651721168214193119002261835794954031633888892370 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_csr_rw/latest run_opts='+csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1735841234 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.1735841234' seed=58005851784081892733164605908651721168214193119002261835794954031633888892370 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58005851784081892733164605908651721168214193119002261835794954031633888892370 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_csr_bit_bash | 41045754524521822624236168804194045343822626558367307991209709639644630296051 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_csr_bit_bash/latest run_opts='+csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3653051891 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.3653051891' seed=41045754524521822624236168804194045343822626558367307991209709639644630296051 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41045754524521822624236168804194045343822626558367307991209709639644630296051 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_csr_aliasing | 60900986826753873382806318685209067155785285470686036165925943505551256367872 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_csr_aliasing/latest run_opts='+csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4021465856 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.4021465856' seed=60900986826753873382806318685209067155785285470686036165925943505551256367872 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60900986826753873382806318685209067155785285470686036165925943505551256367872 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_same_csr_outstanding | 92301216514331516742185982567397831697812655796078303735291487889196955129292 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1968100812 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_outstanding.1968100812' seed=92301216514331516742185982567397831697812655796078303735291487889196955129292 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92301216514331516742185982567397831697812655796078303735291487889196955129292 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_csr_mem_rw_with_rand_reset | 39484017264721182695401357287040713820238407611540843291785816770251964874860 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=536674412 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_mem_rw_with_rand_reset.536674412' seed=39484017264721182695401357287040713820238407611540843291785816770251964874860 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39484017264721182695401357287040713820238407611540843291785816770251964874860 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/0.alert_handler_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_smoke | 105737647791877832564683662921627685737771741148572862044438824231814499432478 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=174618654 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.174618654' seed=105737647791877832564683662921627685737771741148572862044438824231814499432478 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105737647791877832564683662921627685737771741148572862044438824231814499432478 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_alerts | 79348957520291465160120403241671916465712187218541278791212850111855407276900 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_random_alerts/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2518033252 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.2518033252' seed=79348957520291465160120403241671916465712187218541278791212850111855407276900 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79348957520291465160120403241671916465712187218541278791212850111855407276900 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_random_alerts/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_alerts_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 1540737502712148557271650359240239515105382599755200105815404991454232394906 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3985849498 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.3985849498' seed=1540737502712148557271650359240239515105382599755200105815404991454232394906 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1540737502712148557271650359240239515105382599755200105815404991454232394906 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 63327192627651426073988340412554382822226755330295845823154437088030089392471 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=211136855 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.211136855' seed=63327192627651426073988340412554382822226755330295845823154437088030089392471 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63327192627651426073988340412554382822226755330295845823154437088030089392471 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_alert_accum | 53483084615474513107152124524396794614258512777254623956988778986433500909160 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_esc_alert_accum/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1478200936 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.1478200936' seed=53483084615474513107152124524396794614258512777254623956988778986433500909160 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53483084615474513107152124524396794614258512777254623956988778986433500909160 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_esc_alert_accum/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_alert_accum_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 88010541969205499306453991196780500204983515717482487688371800154013853054495 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1279030815 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.1279030815' seed=88010541969205499306453991196780500204983515717482487688371800154013853054495 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88010541969205499306453991196780500204983515717482487688371800154013853054495 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy | 104188758577647667291356862737251881883556090719723390935020129122364712133248 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_entropy/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3043598976 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.3043598976' seed=104188758577647667291356862737251881883556090719723390935020129122364712133248 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104188758577647667291356862737251881883556090719723390935020129122364712133248 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_entropy/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 67378582130771355365432263622092470505859051482217967454473280126887896399750 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=60669830 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.60669830' seed=67378582130771355365432263622092470505859051482217967454473280126887896399750 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67378582130771355365432263622092470505859051482217967454473280126887896399750 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 104356433487862018128254487310363754340087504784220632693116685212948609862090 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=903055818 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.903055818' seed=104356433487862018128254487310363754340087504784220632693116685212948609862090 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104356433487862018128254487310363754340087504784220632693116685212948609862090 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 98395655010472319035111180584329231596377789203768554088014790445233757646055 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1694395623 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.1694395623' seed=98395655010472319035111180584329231596377789203768554088014790445233757646055 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98395655010472319035111180584329231596377789203768554088014790445233757646055 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy_stress | 18011028479764484380056437738044768674534066267522582638019525455764726049932 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_entropy_stress/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4275661964 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.4275661964' seed=18011028479764484380056437738044768674534066267522582638019525455764726049932 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18011028479764484380056437738044768674534066267522582638019525455764726049932 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_entropy_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_stress_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors_with_csr_rw | 76591553719777234409133998145258084329767354435573034633330805464749947674712 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_shadow_reg_errors_with_csr_rw/latest run_opts='+test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3594707032 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.3594707032' seed=76591553719777234409133998145258084329767354435573034633330805464749947674712 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76591553719777234409133998145258084329767354435573034633330805464749947674712 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_alert_accum_saturation | 4121219735747945330454891626627404272543113580530842575722914572205088911428 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_alert_accum_saturation/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=690827332 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.690827332' seed=4121219735747945330454891626627404272543113580530842575722914572205088911428 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4121219735747945330454891626627404272543113580530842575722914572205088911428 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_alert_accum_saturation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_alert_accum_saturation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_stress_all_with_rand_reset | 108242351237689449299766373089449063377206729785346310211346873610293756140396 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2155715436 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.2155715436' seed=108242351237689449299766373089449063377206729785346310211346873610293756140396 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108242351237689449299766373089449063377206729785346310211346873610293756140396 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sec_cm | 65990432243559669645875551024595779868262567832765449173971639717751447522213 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3606481829 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.3606481829' seed=65990432243559669645875551024595779868262567832765449173971639717751447522213 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65990432243559669645875551024595779868262567832765449173971639717751447522213 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors | 30229497944044103990934059231768457357466148746108814328445581487566157480608 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3522396832 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_errors.3522396832' seed=30229497944044103990934059231768457357466148746108814328445581487566157480608 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30229497944044103990934059231768457357466148746108814328445581487566157480608 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_errors | 80611047751403245284104203860314343425990365744155649092769739787180880039024 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4087483504 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.4087483504' seed=80611047751403245284104203860314343425990365744155649092769739787180880039024 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80611047751403245284104203860314343425990365744155649092769739787180880039024 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_intg_err | 41393814748001188441183548225894111844024964012734165591848549118481159985930 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3435436810 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.3435436810' seed=41393814748001188441183548225894111844024964012734165591848549118481159985930 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41393814748001188441183548225894111844024964012734165591848549118481159985930 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_intr_test | 90766247800656731218098912092062408225980187012918287507003995391247192501063 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_intr_test/latest run_opts='+run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=293415751 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.293415751' seed=90766247800656731218098912092062408225980187012918287507003995391247192501063 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90766247800656731218098912092062408225980187012918287507003995391247192501063 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_csr_rw | 16238850399145302268594081733010054955465526509640989062079314749951101427952 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_csr_rw/latest run_opts='+csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2215960816 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.2215960816' seed=16238850399145302268594081733010054955465526509640989062079314749951101427952 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16238850399145302268594081733010054955465526509640989062079314749951101427952 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_same_csr_outstanding | 83561576440315911097556483494981850166292469122334276844323186574124850300960 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2192001056 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outstanding.2192001056' seed=83561576440315911097556483494981850166292469122334276844323186574124850300960 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83561576440315911097556483494981850166292469122334276844323186574124850300960 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_csr_mem_rw_with_rand_reset | 36022042823564073127228278503723095273565171930491624545071590869937854802084 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=967239844 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_mem_rw_with_rand_reset.967239844' seed=36022042823564073127228278503723095273565171930491624545071590869937854802084 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36022042823564073127228278503723095273565171930491624545071590869937854802084 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/1.alert_handler_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_smoke | 96923829937026717887996214682257799682987457995362468309503784336979607047287 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2387233911 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.2387233911' seed=96923829937026717887996214682257799682987457995362468309503784336979607047287 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96923829937026717887996214682257799682987457995362468309503784336979607047287 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_alerts | 1662638637154259337186515793072431072928946463485246579621836146708417729558 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_random_alerts/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3738031126 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.3738031126' seed=1662638637154259337186515793072431072928946463485246579621836146708417729558 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1662638637154259337186515793072431072928946463485246579621836146708417729558 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_random_alerts/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_alerts_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 102055295536275305199501440787925778304601975692894459782476675319189808554153 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3359318185 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.3359318185' seed=102055295536275305199501440787925778304601975692894459782476675319189808554153 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102055295536275305199501440787925778304601975692894459782476675319189808554153 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 50548448384119213673261697515065894376098974508940708940046085021398398752748 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2505398252 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.2505398252' seed=50548448384119213673261697515065894376098974508940708940046085021398398752748 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50548448384119213673261697515065894376098974508940708940046085021398398752748 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_alert_accum | 98808182799000851478653799844088914180461324278056837064698544000143522905228 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_esc_alert_accum/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1142537356 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1142537356' seed=98808182799000851478653799844088914180461324278056837064698544000143522905228 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98808182799000851478653799844088914180461324278056837064698544000143522905228 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_esc_alert_accum/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_alert_accum_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 38519277549330679398203591574064820691501187116801220452898256065842631793774 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2020990062 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.2020990062' seed=38519277549330679398203591574064820691501187116801220452898256065842631793774 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38519277549330679398203591574064820691501187116801220452898256065842631793774 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy | 48251564239003951985972109004766296898417691212770400016789603795207879574504 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_entropy/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=334676968 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.334676968' seed=48251564239003951985972109004766296898417691212770400016789603795207879574504 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48251564239003951985972109004766296898417691212770400016789603795207879574504 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_entropy/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 18053443619037139483286904192357916806474712753071245011194924116546358917270 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1685108886 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.1685108886' seed=18053443619037139483286904192357916806474712753071245011194924116546358917270 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18053443619037139483286904192357916806474712753071245011194924116546358917270 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 26707349308975621098786092739230757073273200052328843181180426703436822396676 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1554824964 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.1554824964' seed=26707349308975621098786092739230757073273200052328843181180426703436822396676 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26707349308975621098786092739230757073273200052328843181180426703436822396676 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 1743754797959715568693933765802389821807088798170036364119994083836558559635 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=302238099 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.302238099' seed=1743754797959715568693933765802389821807088798170036364119994083836558559635 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1743754797959715568693933765802389821807088798170036364119994083836558559635 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy_stress | 43126125163716364014684286238934685460338104758528361697580283789162610970047 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_entropy_stress/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3451407807 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.3451407807' seed=43126125163716364014684286238934685460338104758528361697580283789162610970047 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43126125163716364014684286238934685460338104758528361697580283789162610970047 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_entropy_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_stress_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors_with_csr_rw | 48621673511581403493034486075142902911139947166582755952608770565831687683519 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_shadow_reg_errors_with_csr_rw/latest run_opts='+test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3310108095 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.3310108095' seed=48621673511581403493034486075142902911139947166582755952608770565831687683519 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48621673511581403493034486075142902911139947166582755952608770565831687683519 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_alert_accum_saturation | 41336446440439926801636840612056149920705617789966026686666018817372615216025 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_alert_accum_saturation/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=255724441 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.255724441' seed=41336446440439926801636840612056149920705617789966026686666018817372615216025 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41336446440439926801636840612056149920705617789966026686666018817372615216025 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_alert_accum_saturation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_alert_accum_saturation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_stress_all_with_rand_reset | 53867174144323304031148110526467943586177321531653221813544714146426258571320 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1382137912 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.1382137912' seed=53867174144323304031148110526467943586177321531653221813544714146426258571320 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53867174144323304031148110526467943586177321531653221813544714146426258571320 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sec_cm | 53788006246177119080701402357818138129091650924449910385874271661886196604453 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1372249637 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.1372249637' seed=53788006246177119080701402357818138129091650924449910385874271661886196604453 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53788006246177119080701402357818138129091650924449910385874271661886196604453 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors | 78296188034629459548529577745905113098322469034164540751351050426108060267174 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2278716070 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_errors.2278716070' seed=78296188034629459548529577745905113098322469034164540751351050426108060267174 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78296188034629459548529577745905113098322469034164540751351050426108060267174 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_errors | 46088719444920105225876822898848559272518413673630443487715073434118042776568 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3389092856 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.3389092856' seed=46088719444920105225876822898848559272518413673630443487715073434118042776568 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46088719444920105225876822898848559272518413673630443487715073434118042776568 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_intg_err | 82130622908404497330997816683198227362189610224930502464210384993270275457444 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1136083364 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.1136083364' seed=82130622908404497330997816683198227362189610224930502464210384993270275457444 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82130622908404497330997816683198227362189610224930502464210384993270275457444 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_intr_test | 33418327369405540501598703581479699076754005744079819461527314253905869762335 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_intr_test/latest run_opts='+run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1419865887 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.1419865887' seed=33418327369405540501598703581479699076754005744079819461527314253905869762335 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33418327369405540501598703581479699076754005744079819461527314253905869762335 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_csr_rw | 85250540671245264837652712586041855520487084595958431068618029830689275826068 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_csr_rw/latest run_opts='+csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3466121108 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.3466121108' seed=85250540671245264837652712586041855520487084595958431068618029830689275826068 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85250540671245264837652712586041855520487084595958431068618029830689275826068 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_same_csr_outstanding | 15244043491300684182292231268053600406705485474475300492789638967647952934374 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=635934182 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outstanding.635934182' seed=15244043491300684182292231268053600406705485474475300492789638967647952934374 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15244043491300684182292231268053600406705485474475300492789638967647952934374 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_csr_mem_rw_with_rand_reset | 61394464358499777904585352040576298767792473063156659466484009830803359724826 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2439836954 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_mem_rw_with_rand_reset.2439836954' seed=61394464358499777904585352040576298767792473063156659466484009830803359724826 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61394464358499777904585352040576298767792473063156659466484009830803359724826 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/2.alert_handler_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_smoke | 21210958744125586202944348831229907027744634211591898535014138085354560393040 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2098827088 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.2098827088' seed=21210958744125586202944348831229907027744634211591898535014138085354560393040 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21210958744125586202944348831229907027744634211591898535014138085354560393040 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_alerts | 56841982207431067268126497679114508997606626400512461860929303174521907190310 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_random_alerts/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1402870310 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1402870310' seed=56841982207431067268126497679114508997606626400512461860929303174521907190310 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56841982207431067268126497679114508997606626400512461860929303174521907190310 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_random_alerts/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_alerts_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 112167951783976531212231970857449777442718741448802534617280950488747761990607 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=945552335 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.945552335' seed=112167951783976531212231970857449777442718741448802534617280950488747761990607 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112167951783976531212231970857449777442718741448802534617280950488747761990607 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 2946176143163148948934319068224556547234729676548030625594992780457917232080 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1858286544 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.1858286544' seed=2946176143163148948934319068224556547234729676548030625594992780457917232080 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2946176143163148948934319068224556547234729676548030625594992780457917232080 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_alert_accum | 6246434136675758280528058255438464764776369179028647945299400184698508871195 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_esc_alert_accum/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1150748187 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.1150748187' seed=6246434136675758280528058255438464764776369179028647945299400184698508871195 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6246434136675758280528058255438464764776369179028647945299400184698508871195 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_esc_alert_accum/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_alert_accum_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 111715469988319561007619300978065184819280793089908339603663951834472596174644 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=569177908 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.569177908' seed=111715469988319561007619300978065184819280793089908339603663951834472596174644 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111715469988319561007619300978065184819280793089908339603663951834472596174644 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy | 54068344052615209336202884318231825182567282910332283621527395401013862108069 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_entropy/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2333117349 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2333117349' seed=54068344052615209336202884318231825182567282910332283621527395401013862108069 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54068344052615209336202884318231825182567282910332283621527395401013862108069 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_entropy/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 87516736109003903641557981011544650273455763432246359268423912852389199276038 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3008555014 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.3008555014' seed=87516736109003903641557981011544650273455763432246359268423912852389199276038 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87516736109003903641557981011544650273455763432246359268423912852389199276038 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 90138228858709684161715552990881412920028210630955971437317034441735765684885 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1924592277 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.1924592277' seed=90138228858709684161715552990881412920028210630955971437317034441735765684885 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90138228858709684161715552990881412920028210630955971437317034441735765684885 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 66483314022275025557732435747312872314120429721220414327271532475663325461350 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4215929702 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.4215929702' seed=66483314022275025557732435747312872314120429721220414327271532475663325461350 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66483314022275025557732435747312872314120429721220414327271532475663325461350 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy_stress | 2261656499160701672737842027955809293979575940197370611054419247262173433502 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_entropy_stress/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3353284254 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.3353284254' seed=2261656499160701672737842027955809293979575940197370611054419247262173433502 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2261656499160701672737842027955809293979575940197370611054419247262173433502 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_entropy_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_stress_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors_with_csr_rw | 47080830652569008097463293197402322759349147986529607878130914792159222118380 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_shadow_reg_errors_with_csr_rw/latest run_opts='+test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1850161132 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.1850161132' seed=47080830652569008097463293197402322759349147986529607878130914792159222118380 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47080830652569008097463293197402322759349147986529607878130914792159222118380 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_alert_accum_saturation | 45594444111632278629434203334167255696864545233670933640939774614116089502866 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_alert_accum_saturation/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4233141394 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.4233141394' seed=45594444111632278629434203334167255696864545233670933640939774614116089502866 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45594444111632278629434203334167255696864545233670933640939774614116089502866 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_alert_accum_saturation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_alert_accum_saturation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_stress_all_with_rand_reset | 272940586250349896926444849214734931383061317399995853382127816634670381297 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2135030001 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.2135030001' seed=272940586250349896926444849214734931383061317399995853382127816634670381297 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=272940586250349896926444849214734931383061317399995853382127816634670381297 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sec_cm | 78956989676651284998295367199630413773920873534205634232153030943167884512284 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2143243292 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.2143243292' seed=78956989676651284998295367199630413773920873534205634232153030943167884512284 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78956989676651284998295367199630413773920873534205634232153030943167884512284 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors | 16407577566151969506769506518827270407714909079036182608204556582738113312792 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=520861720 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_errors.520861720' seed=16407577566151969506769506518827270407714909079036182608204556582738113312792 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16407577566151969506769506518827270407714909079036182608204556582738113312792 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_errors | 17679452759956603739520274043848864509547301203823749053868642476730166051764 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3912270772 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.3912270772' seed=17679452759956603739520274043848864509547301203823749053868642476730166051764 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17679452759956603739520274043848864509547301203823749053868642476730166051764 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_intg_err | 85400003920819721855424285148004803844021877650304895374383324215503680305406 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4075157758 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.4075157758' seed=85400003920819721855424285148004803844021877650304895374383324215503680305406 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85400003920819721855424285148004803844021877650304895374383324215503680305406 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_intr_test | 103667198304146821926398446422844404423462367462821979085925110109536897579699 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_intr_test/latest run_opts='+run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1402845875 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.1402845875' seed=103667198304146821926398446422844404423462367462821979085925110109536897579699 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103667198304146821926398446422844404423462367462821979085925110109536897579699 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_csr_rw | 65521361273726078969371610490562950353058385862286592262124525720468371501983 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_csr_rw/latest run_opts='+csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4104090527 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.4104090527' seed=65521361273726078969371610490562950353058385862286592262124525720468371501983 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65521361273726078969371610490562950353058385862286592262124525720468371501983 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_same_csr_outstanding | 33151785379452020720731189750674797688757149747284192352862799098705183392726 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2108048342 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_outstanding.2108048342' seed=33151785379452020720731189750674797688757149747284192352862799098705183392726 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33151785379452020720731189750674797688757149747284192352862799098705183392726 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_csr_mem_rw_with_rand_reset | 7470434735001120300196089259009707084023182772926669915298786744348894751340 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2721245804 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_mem_rw_with_rand_reset.2721245804' seed=7470434735001120300196089259009707084023182772926669915298786744348894751340 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7470434735001120300196089259009707084023182772926669915298786744348894751340 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/3.alert_handler_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_smoke | 94635644035353191361855000411224678054819991273712476499449254362950217525742 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3489688046 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.3489688046' seed=94635644035353191361855000411224678054819991273712476499449254362950217525742 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94635644035353191361855000411224678054819991273712476499449254362950217525742 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_alerts | 9648236388091816128792226317495598883339846121584169939751758584890237594265 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_random_alerts/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2933074585 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.2933074585' seed=9648236388091816128792226317495598883339846121584169939751758584890237594265 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9648236388091816128792226317495598883339846121584169939751758584890237594265 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_random_alerts/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_alerts_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 88125259989878460363764688112855598695239500721708991574343002742927855154808 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=959411832 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.959411832' seed=88125259989878460363764688112855598695239500721708991574343002742927855154808 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88125259989878460363764688112855598695239500721708991574343002742927855154808 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 55421470294853865555491182848424204638826937501878030074410913011583537320721 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3874951953 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.3874951953' seed=55421470294853865555491182848424204638826937501878030074410913011583537320721 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55421470294853865555491182848424204638826937501878030074410913011583537320721 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_alert_accum | 66379963283237161002516092005122605219664671201311436671758405297644909632225 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_esc_alert_accum/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4238088929 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.4238088929' seed=66379963283237161002516092005122605219664671201311436671758405297644909632225 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66379963283237161002516092005122605219664671201311436671758405297644909632225 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_esc_alert_accum/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_alert_accum_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 49473314251810379738874140057026054638518898503894732073472268488540252978143 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=202030047 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.202030047' seed=49473314251810379738874140057026054638518898503894732073472268488540252978143 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49473314251810379738874140057026054638518898503894732073472268488540252978143 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy | 85180193836138331840108345754342758986730760342608992594939367353689955626141 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_entropy/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4291292317 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.4291292317' seed=85180193836138331840108345754342758986730760342608992594939367353689955626141 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85180193836138331840108345754342758986730760342608992594939367353689955626141 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_entropy/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 49406837143545924987722692773937539728182308180355272016297317493780511465146 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=718020282 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.718020282' seed=49406837143545924987722692773937539728182308180355272016297317493780511465146 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49406837143545924987722692773937539728182308180355272016297317493780511465146 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 96748848913788242281343530343248155885871623142910874584160326856939939635846 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=184099462 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.184099462' seed=96748848913788242281343530343248155885871623142910874584160326856939939635846 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96748848913788242281343530343248155885871623142910874584160326856939939635846 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 22385648533538699032024154436609344626733049194252853442095660926679028378855 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3916213479 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.3916213479' seed=22385648533538699032024154436609344626733049194252853442095660926679028378855 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22385648533538699032024154436609344626733049194252853442095660926679028378855 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy_stress | 97482675614865457302519730094542918721354031987843208143865532326644885826116 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_entropy_stress/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3643353668 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.3643353668' seed=97482675614865457302519730094542918721354031987843208143865532326644885826116 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97482675614865457302519730094542918721354031987843208143865532326644885826116 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_entropy_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_stress_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors_with_csr_rw | 3983847801533694456160850118349682019756917389773791115397205044791340358618 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_shadow_reg_errors_with_csr_rw/latest run_opts='+test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2513886170 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.2513886170' seed=3983847801533694456160850118349682019756917389773791115397205044791340358618 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3983847801533694456160850118349682019756917389773791115397205044791340358618 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_alert_accum_saturation | 49683692943353867741811282326184707782993515255710533683988768974784264815153 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_alert_accum_saturation/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1495679537 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.1495679537' seed=49683692943353867741811282326184707782993515255710533683988768974784264815153 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49683692943353867741811282326184707782993515255710533683988768974784264815153 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_alert_accum_saturation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_alert_accum_saturation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_stress_all_with_rand_reset | 62236892311091105767757814652625312715435135328920129064666257188748594204121 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3814149593 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.3814149593' seed=62236892311091105767757814652625312715435135328920129064666257188748594204121 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62236892311091105767757814652625312715435135328920129064666257188748594204121 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sec_cm | 82922392546506160223002885862283300456840196895635149857432989294241649398245 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3074036197 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.3074036197' seed=82922392546506160223002885862283300456840196895635149857432989294241649398245 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82922392546506160223002885862283300456840196895635149857432989294241649398245 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors | 81171769236213572808969345903216517997055444765700322043265555916202792317330 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=498463122 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_errors.498463122' seed=81171769236213572808969345903216517997055444765700322043265555916202792317330 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81171769236213572808969345903216517997055444765700322043265555916202792317330 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_errors | 70442455021098148133325464744727945297672849015011593012874969909129760855442 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2343949714 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.2343949714' seed=70442455021098148133325464744727945297672849015011593012874969909129760855442 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70442455021098148133325464744727945297672849015011593012874969909129760855442 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_intg_err | 16656078356994778718440834326761326886035120075733476045279139358038516824103 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3263166503 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.3263166503' seed=16656078356994778718440834326761326886035120075733476045279139358038516824103 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16656078356994778718440834326761326886035120075733476045279139358038516824103 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_intr_test | 109077959491386855152683120697696370458781609507814229908236463541670913205267 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_intr_test/latest run_opts='+run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4262421523 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.4262421523' seed=109077959491386855152683120697696370458781609507814229908236463541670913205267 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109077959491386855152683120697696370458781609507814229908236463541670913205267 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_csr_rw | 45405752039957214264967564092788491527530187175639387729299290542963298690844 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_csr_rw/latest run_opts='+csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3654575900 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.3654575900' seed=45405752039957214264967564092788491527530187175639387729299290542963298690844 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45405752039957214264967564092788491527530187175639387729299290542963298690844 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_same_csr_outstanding | 81852838925777124678139664356906806501004935684180639311500670717024523863628 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3929884236 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outstanding.3929884236' seed=81852838925777124678139664356906806501004935684180639311500670717024523863628 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81852838925777124678139664356906806501004935684180639311500670717024523863628 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_csr_mem_rw_with_rand_reset | 37041977410080493353186127001899180281518943929521246802896949037317000644638 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3416901662 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_mem_rw_with_rand_reset.3416901662' seed=37041977410080493353186127001899180281518943929521246802896949037317000644638 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37041977410080493353186127001899180281518943929521246802896949037317000644638 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/4.alert_handler_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_smoke | 31113369375312769725772662055418380524618130214686162322470927871167983809146 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2916643450 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.2916643450' seed=31113369375312769725772662055418380524618130214686162322470927871167983809146 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31113369375312769725772662055418380524618130214686162322470927871167983809146 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_alerts | 100540038024507000157783176909449137654772974602748127517274411550347822050627 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_random_alerts/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1648831811 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1648831811' seed=100540038024507000157783176909449137654772974602748127517274411550347822050627 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100540038024507000157783176909449137654772974602748127517274411550347822050627 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_random_alerts/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_alerts_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 12707265442163599994969749744748663054059331986498376215189946376355199897045 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3233336789 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3233336789' seed=12707265442163599994969749744748663054059331986498376215189946376355199897045 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12707265442163599994969749744748663054059331986498376215189946376355199897045 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 13235090953177283559516658565410140188982833585822067260480708214642643828205 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1619262957 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.1619262957' seed=13235090953177283559516658565410140188982833585822067260480708214642643828205 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13235090953177283559516658565410140188982833585822067260480708214642643828205 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_alert_accum | 17058591608490560581602395738919345415187118220041884581187505328797838265159 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_esc_alert_accum/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3843607367 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3843607367' seed=17058591608490560581602395738919345415187118220041884581187505328797838265159 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17058591608490560581602395738919345415187118220041884581187505328797838265159 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_esc_alert_accum/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_alert_accum_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 87238413862515399865162883947736983709536365474313277193008676979313574921764 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3232482852 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.3232482852' seed=87238413862515399865162883947736983709536365474313277193008676979313574921764 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87238413862515399865162883947736983709536365474313277193008676979313574921764 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy | 110298363127818186603026556379836889814647402345014103364068446870226293429965 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_entropy/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=603657933 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.603657933' seed=110298363127818186603026556379836889814647402345014103364068446870226293429965 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110298363127818186603026556379836889814647402345014103364068446870226293429965 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_entropy/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 76066623832423497450580576515285318812642898006631463112146957879314507155075 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3136079491 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.3136079491' seed=76066623832423497450580576515285318812642898006631463112146957879314507155075 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76066623832423497450580576515285318812642898006631463112146957879314507155075 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 80455356607448833745504862863629425667321145437339916285446877616205474394016 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=80048032 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.80048032' seed=80455356607448833745504862863629425667321145437339916285446877616205474394016 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80455356607448833745504862863629425667321145437339916285446877616205474394016 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 19872644513800331764145324280882470624244321157906226154752827807369385484887 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3064734295 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.3064734295' seed=19872644513800331764145324280882470624244321157906226154752827807369385484887 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19872644513800331764145324280882470624244321157906226154752827807369385484887 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy_stress | 2298485221611405199949250706211368903672884144512574116883718356151056078117 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_entropy_stress/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1112937765 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1112937765' seed=2298485221611405199949250706211368903672884144512574116883718356151056078117 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2298485221611405199949250706211368903672884144512574116883718356151056078117 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_entropy_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_stress_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors_with_csr_rw | 32100440565727492081360560092297432003543022637055634892583378121432803614306 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_shadow_reg_errors_with_csr_rw/latest run_opts='+test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1349820002 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.1349820002' seed=32100440565727492081360560092297432003543022637055634892583378121432803614306 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32100440565727492081360560092297432003543022637055634892583378121432803614306 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_alert_accum_saturation | 91926763478063296737119351856143029904952004430104510153950719754125492937768 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_alert_accum_saturation/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=140043304 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.140043304' seed=91926763478063296737119351856143029904952004430104510153950719754125492937768 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91926763478063296737119351856143029904952004430104510153950719754125492937768 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_alert_accum_saturation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_alert_accum_saturation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_stress_all_with_rand_reset | 71558126691906668719510524654535434828759388605300938022605847021892913380085 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1193851637 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.1193851637' seed=71558126691906668719510524654535434828759388605300938022605847021892913380085 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71558126691906668719510524654535434828759388605300938022605847021892913380085 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors | 332924591149495556269312666401534722559683158123641918459484923521926357498 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1186128378 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_errors.1186128378' seed=332924591149495556269312666401534722559683158123641918459484923521926357498 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=332924591149495556269312666401534722559683158123641918459484923521926357498 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_errors | 25484414795190694631324012154840156069457408700125328432917131841201098083113 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2372553513 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.2372553513' seed=25484414795190694631324012154840156069457408700125328432917131841201098083113 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25484414795190694631324012154840156069457408700125328432917131841201098083113 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_intg_err | 75210990219387864707939401058426865475830898579923861885711026172777235783040 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3435699584 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.3435699584' seed=75210990219387864707939401058426865475830898579923861885711026172777235783040 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75210990219387864707939401058426865475830898579923861885711026172777235783040 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_intr_test | 26212602811764740350431292284296027988393697149511387463659857114030784143238 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_intr_test/latest run_opts='+run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3182452614 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.3182452614' seed=26212602811764740350431292284296027988393697149511387463659857114030784143238 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26212602811764740350431292284296027988393697149511387463659857114030784143238 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/5.alert_handler_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_smoke | 5283995210665876974624629045496186136683209897278153951609476479660204913302 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2608493206 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.2608493206' seed=5283995210665876974624629045496186136683209897278153951609476479660204913302 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5283995210665876974624629045496186136683209897278153951609476479660204913302 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_alerts | 918424202499455205381415679317610010239427286093518311442945827604176848679 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_random_alerts/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3804251943 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3804251943' seed=918424202499455205381415679317610010239427286093518311442945827604176848679 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=918424202499455205381415679317610010239427286093518311442945827604176848679 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_random_alerts/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_alerts_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 79463964719174552961349890375698878625888464259755495227079244856719062938621 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3612947453 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.3612947453' seed=79463964719174552961349890375698878625888464259755495227079244856719062938621 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79463964719174552961349890375698878625888464259755495227079244856719062938621 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 37001444606753543330301241180592964102032223927390594436920603491353981784760 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3707409080 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.3707409080' seed=37001444606753543330301241180592964102032223927390594436920603491353981784760 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37001444606753543330301241180592964102032223927390594436920603491353981784760 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_alert_accum | 23325128735882251617653406903293092435622423328128732586134814916518796521393 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_esc_alert_accum/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=755953585 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.755953585' seed=23325128735882251617653406903293092435622423328128732586134814916518796521393 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23325128735882251617653406903293092435622423328128732586134814916518796521393 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_esc_alert_accum/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_alert_accum_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 34803092078830576263330627554677110626724248533583113697787830390222151860117 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1264435093 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.1264435093' seed=34803092078830576263330627554677110626724248533583113697787830390222151860117 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34803092078830576263330627554677110626724248533583113697787830390222151860117 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy | 5038520629249849336436402118125236575782578197833664704292007718052733266341 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_entropy/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=362162597 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.362162597' seed=5038520629249849336436402118125236575782578197833664704292007718052733266341 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5038520629249849336436402118125236575782578197833664704292007718052733266341 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_entropy/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 20636621168637967932897025037114359047707893070869242155876505420191663702212 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1501348036 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.1501348036' seed=20636621168637967932897025037114359047707893070869242155876505420191663702212 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20636621168637967932897025037114359047707893070869242155876505420191663702212 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 106274511895194510095506633938700215584967387258881187782792533743955765299477 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=830933269 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.830933269' seed=106274511895194510095506633938700215584967387258881187782792533743955765299477 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106274511895194510095506633938700215584967387258881187782792533743955765299477 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 102826174863062334388648916948263246903009586266344894819036684438681738962816 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=294020992 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.294020992' seed=102826174863062334388648916948263246903009586266344894819036684438681738962816 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102826174863062334388648916948263246903009586266344894819036684438681738962816 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy_stress | 27830347667103813392271541251463118085011077672478061346601756388527522017592 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_entropy_stress/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=572879160 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.572879160' seed=27830347667103813392271541251463118085011077672478061346601756388527522017592 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27830347667103813392271541251463118085011077672478061346601756388527522017592 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_entropy_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_stress_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors_with_csr_rw | 7477660069578261444282975084434783280385245666599378168724122077034140062483 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_shadow_reg_errors_with_csr_rw/latest run_opts='+test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=16175891 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.16175891' seed=7477660069578261444282975084434783280385245666599378168724122077034140062483 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7477660069578261444282975084434783280385245666599378168724122077034140062483 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_alert_accum_saturation | 3508564931781175060613839106976471735838345519347575399058461875645801448492 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_alert_accum_saturation/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2775467052 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.2775467052' seed=3508564931781175060613839106976471735838345519347575399058461875645801448492 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3508564931781175060613839106976471735838345519347575399058461875645801448492 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_alert_accum_saturation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_alert_accum_saturation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_stress_all_with_rand_reset | 74155232648927749001550252855086405665935479071650801472697704055533379600407 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3363913751 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.3363913751' seed=74155232648927749001550252855086405665935479071650801472697704055533379600407 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74155232648927749001550252855086405665935479071650801472697704055533379600407 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors | 48895493184049357085457141975050014430495035798229820857429865301017189090847 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1300956703 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_errors.1300956703' seed=48895493184049357085457141975050014430495035798229820857429865301017189090847 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48895493184049357085457141975050014430495035798229820857429865301017189090847 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_errors | 18057546775628285077611755775140676365584961840023315832625188690811527871634 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1067695250 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.1067695250' seed=18057546775628285077611755775140676365584961840023315832625188690811527871634 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18057546775628285077611755775140676365584961840023315832625188690811527871634 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_intg_err | 20349244233122417828599146016069570256524819143126533224068825236047162080746 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1853980138 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.1853980138' seed=20349244233122417828599146016069570256524819143126533224068825236047162080746 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20349244233122417828599146016069570256524819143126533224068825236047162080746 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_intr_test | 60228181014210266470984592942492865684168120097626075488758987395984051528575 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_intr_test/latest run_opts='+run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1075962751 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.1075962751' seed=60228181014210266470984592942492865684168120097626075488758987395984051528575 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60228181014210266470984592942492865684168120097626075488758987395984051528575 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/6.alert_handler_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_smoke | 87999818465627491936770204072418589863135833328290474546595604101926465126710 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=666976566 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.666976566' seed=87999818465627491936770204072418589863135833328290474546595604101926465126710 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87999818465627491936770204072418589863135833328290474546595604101926465126710 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_alerts | 64924511512469058859941879544656350504684132306750150006247976807495533023990 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_random_alerts/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=678122230 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.678122230' seed=64924511512469058859941879544656350504684132306750150006247976807495533023990 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64924511512469058859941879544656350504684132306750150006247976807495533023990 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_random_alerts/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_alerts_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 68685016494871969135688405229281180115959352713682499183185109922039719046051 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2165615523 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.2165615523' seed=68685016494871969135688405229281180115959352713682499183185109922039719046051 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68685016494871969135688405229281180115959352713682499183185109922039719046051 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 79016420610960004742318687874780146646238474837939945149357293381364777027176 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2312439400 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2312439400' seed=79016420610960004742318687874780146646238474837939945149357293381364777027176 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79016420610960004742318687874780146646238474837939945149357293381364777027176 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_alert_accum | 80584692865234048398420080114905397373502413672076296655723303129768658926334 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_esc_alert_accum/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2291071742 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.2291071742' seed=80584692865234048398420080114905397373502413672076296655723303129768658926334 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80584692865234048398420080114905397373502413672076296655723303129768658926334 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_esc_alert_accum/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_alert_accum_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 99048442325248849257135958253772940439340824173610236838898222987589344065961 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1555331497 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.1555331497' seed=99048442325248849257135958253772940439340824173610236838898222987589344065961 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99048442325248849257135958253772940439340824173610236838898222987589344065961 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy | 49571290339244319807484294496565447809142553022469420096583306878270509811063 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_entropy/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2613183863 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.2613183863' seed=49571290339244319807484294496565447809142553022469420096583306878270509811063 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49571290339244319807484294496565447809142553022469420096583306878270509811063 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_entropy/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 71599635411849321437320132584022641174059276306675936393942421166961896114947 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1753926403 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.1753926403' seed=71599635411849321437320132584022641174059276306675936393942421166961896114947 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71599635411849321437320132584022641174059276306675936393942421166961896114947 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 4674441876935990550590037416745912614738112797587880500582665626979042304200 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4237533384 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.4237533384' seed=4674441876935990550590037416745912614738112797587880500582665626979042304200 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4674441876935990550590037416745912614738112797587880500582665626979042304200 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 464595873438265702573798979914385486521870788437442095870670515188526031408 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1775313456 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.1775313456' seed=464595873438265702573798979914385486521870788437442095870670515188526031408 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=464595873438265702573798979914385486521870788437442095870670515188526031408 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy_stress | 61565878178522666804922243573369542727753345069603452819542446040300749598907 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_entropy_stress/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3980931259 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.3980931259' seed=61565878178522666804922243573369542727753345069603452819542446040300749598907 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61565878178522666804922243573369542727753345069603452819542446040300749598907 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_entropy_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_stress_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors_with_csr_rw | 105275037402227069842336286652089342016443740322558755493998867806798643742505 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_shadow_reg_errors_with_csr_rw/latest run_opts='+test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3419162409 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.3419162409' seed=105275037402227069842336286652089342016443740322558755493998867806798643742505 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105275037402227069842336286652089342016443740322558755493998867806798643742505 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_alert_accum_saturation | 449440516185937861639051334998516138117900341882740023639044519498205739074 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_alert_accum_saturation/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=857585730 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.857585730' seed=449440516185937861639051334998516138117900341882740023639044519498205739074 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=449440516185937861639051334998516138117900341882740023639044519498205739074 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_alert_accum_saturation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_alert_accum_saturation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_stress_all_with_rand_reset | 55875236802476184438635562931223947269774057524782851806664058906129271582443 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4168314603 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.4168314603' seed=55875236802476184438635562931223947269774057524782851806664058906129271582443 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55875236802476184438635562931223947269774057524782851806664058906129271582443 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors | 37196796820995550173231739317592289359567360503727597678890445227733773074185 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1847213833 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_errors.1847213833' seed=37196796820995550173231739317592289359567360503727597678890445227733773074185 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37196796820995550173231739317592289359567360503727597678890445227733773074185 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_errors | 1861998720733106025040070116548558496587286458930708950266664373758821756435 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2354146835 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2354146835' seed=1861998720733106025040070116548558496587286458930708950266664373758821756435 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1861998720733106025040070116548558496587286458930708950266664373758821756435 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_intg_err | 50037173255707673707322525580929644748072899226954890112041464440851341814573 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1517071149 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.1517071149' seed=50037173255707673707322525580929644748072899226954890112041464440851341814573 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50037173255707673707322525580929644748072899226954890112041464440851341814573 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_intr_test | 70898957077574225102547437138079148563652966713254319741396311442182780283950 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_intr_test/latest run_opts='+run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1132522542 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.1132522542' seed=70898957077574225102547437138079148563652966713254319741396311442182780283950 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70898957077574225102547437138079148563652966713254319741396311442182780283950 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/7.alert_handler_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_smoke | 103742439901978135562050837268207842387716754200612902034085910424468437380838 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=125611750 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.125611750' seed=103742439901978135562050837268207842387716754200612902034085910424468437380838 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103742439901978135562050837268207842387716754200612902034085910424468437380838 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_alerts | 41194446397726108583477197120487040478107411050882233862658439799348336372985 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_random_alerts/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2429660409 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.2429660409' seed=41194446397726108583477197120487040478107411050882233862658439799348336372985 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41194446397726108583477197120487040478107411050882233862658439799348336372985 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_random_alerts/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_alerts_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 107492950069003741659820240612609437448377176433864362843892271044123629099970 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=112106434 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.112106434' seed=107492950069003741659820240612609437448377176433864362843892271044123629099970 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107492950069003741659820240612609437448377176433864362843892271044123629099970 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 112338274687131767381595170310335545675102450215877263505202586220493933177521 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=444132017 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.444132017' seed=112338274687131767381595170310335545675102450215877263505202586220493933177521 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112338274687131767381595170310335545675102450215877263505202586220493933177521 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_alert_accum | 111433155801039002507069785241057053433960259851313066385334753857989878235423 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_esc_alert_accum/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=518013215 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.518013215' seed=111433155801039002507069785241057053433960259851313066385334753857989878235423 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111433155801039002507069785241057053433960259851313066385334753857989878235423 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_esc_alert_accum/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_alert_accum_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 82568623411514216081149213705399604358785075523524884833404036059287893761581 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1513283117 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.1513283117' seed=82568623411514216081149213705399604358785075523524884833404036059287893761581 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82568623411514216081149213705399604358785075523524884833404036059287893761581 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy | 39516947615115625549921867124493432943169740124181761093179931409497666424767 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_entropy/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1692471231 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.1692471231' seed=39516947615115625549921867124493432943169740124181761093179931409497666424767 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39516947615115625549921867124493432943169740124181761093179931409497666424767 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_entropy/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 111544675591508338840314980585871739302612883766233070423261839402101992679527 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3796985959 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.3796985959' seed=111544675591508338840314980585871739302612883766233070423261839402101992679527 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111544675591508338840314980585871739302612883766233070423261839402101992679527 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 30416357613716450643149131094517662856287070054600239177787925428791963974687 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1576696863 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.1576696863' seed=30416357613716450643149131094517662856287070054600239177787925428791963974687 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30416357613716450643149131094517662856287070054600239177787925428791963974687 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 19282511643142852487227211991006543972666936969248923792239573245530452279640 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1410089304 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.1410089304' seed=19282511643142852487227211991006543972666936969248923792239573245530452279640 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19282511643142852487227211991006543972666936969248923792239573245530452279640 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy_stress | 33106791391115287760341458778703484181192137081908717079448604884808427386135 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_entropy_stress/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4156044567 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.4156044567' seed=33106791391115287760341458778703484181192137081908717079448604884808427386135 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33106791391115287760341458778703484181192137081908717079448604884808427386135 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_entropy_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_stress_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors_with_csr_rw | 71762269940436823930610698160209259458096397529593510369998247198165194204390 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_shadow_reg_errors_with_csr_rw/latest run_opts='+test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3288294630 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.3288294630' seed=71762269940436823930610698160209259458096397529593510369998247198165194204390 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71762269940436823930610698160209259458096397529593510369998247198165194204390 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_alert_accum_saturation | 10967440578243127404472864659118904578533912831828061960127305040107813652829 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_alert_accum_saturation/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=68602205 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.68602205' seed=10967440578243127404472864659118904578533912831828061960127305040107813652829 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10967440578243127404472864659118904578533912831828061960127305040107813652829 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_alert_accum_saturation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_alert_accum_saturation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_stress_all_with_rand_reset | 42636780093723805892214752327836374836609027982448191052499331282431074152754 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3354177842 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.3354177842' seed=42636780093723805892214752327836374836609027982448191052499331282431074152754 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42636780093723805892214752327836374836609027982448191052499331282431074152754 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors | 112691512251297920402015960354590765505468438584721686340987859787085074181865 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1297919721 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_errors.1297919721' seed=112691512251297920402015960354590765505468438584721686340987859787085074181865 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112691512251297920402015960354590765505468438584721686340987859787085074181865 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_errors | 23337448958444201328715872899278971770248016473830158981707534390544075824641 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2302909953 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.2302909953' seed=23337448958444201328715872899278971770248016473830158981707534390544075824641 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23337448958444201328715872899278971770248016473830158981707534390544075824641 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_intg_err | 29073907076582076078095960417121160171656429231498078877103573040219625745848 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1311370680 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.1311370680' seed=29073907076582076078095960417121160171656429231498078877103573040219625745848 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29073907076582076078095960417121160171656429231498078877103573040219625745848 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_intr_test | 70138746285365534959683701738126816556384775583515971702494765060347940623968 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_intr_test/latest run_opts='+run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3748976224 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.3748976224' seed=70138746285365534959683701738126816556384775583515971702494765060347940623968 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70138746285365534959683701738126816556384775583515971702494765060347940623968 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/8.alert_handler_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_smoke | 81000944745617749955719203165335708075222694255824911510592036420807206107632 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_smoke/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=83098096 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.83098096' seed=81000944745617749955719203165335708075222694255824911510592036420807206107632 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81000944745617749955719203165335708075222694255824911510592036420807206107632 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_alerts | 65215361121213070228617437094840168704939064533141971897488833517968454966617 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_random_alerts/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4025081177 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.4025081177' seed=65215361121213070228617437094840168704939064533141971897488833517968454966617 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65215361121213070228617437094840168704939064533141971897488833517968454966617 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_random_alerts/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_alerts_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 23583126908265535994762219425763600105507876575493473315967031524523782520126 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1684094270 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.1684094270' seed=23583126908265535994762219425763600105507876575493473315967031524523782520126 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23583126908265535994762219425763600105507876575493473315967031524523782520126 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 107472743897547730637411431395146382133988962232386043053772649511412789903177 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=144146249 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.144146249' seed=107472743897547730637411431395146382133988962232386043053772649511412789903177 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107472743897547730637411431395146382133988962232386043053772649511412789903177 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_alert_accum | 81413939333541969088349147137828706402261131525663572716968350607545082185059 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_esc_alert_accum/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3520202083 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3520202083' seed=81413939333541969088349147137828706402261131525663572716968350607545082185059 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81413939333541969088349147137828706402261131525663572716968350607545082185059 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_esc_alert_accum/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_alert_accum_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 6970343490072390709798964824557079884048745414758670404583730105396250768743 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2942006631 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.2942006631' seed=6970343490072390709798964824557079884048745414758670404583730105396250768743 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6970343490072390709798964824557079884048745414758670404583730105396250768743 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy | 30436308340295491693282928035496306381979182564006658324828369794427290764510 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_entropy/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4068852958 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.4068852958' seed=30436308340295491693282928035496306381979182564006658324828369794427290764510 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30436308340295491693282928035496306381979182564006658324828369794427290764510 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_entropy/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 19624376071008688681383837775117870665446170590957471665641509341963788844459 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3000597931 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3000597931' seed=19624376071008688681383837775117870665446170590957471665641509341963788844459 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19624376071008688681383837775117870665446170590957471665641509341963788844459 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 66919695068853422813278964101649931357757937018225913454800036525811803420859 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3337418939 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.3337418939' seed=66919695068853422813278964101649931357757937018225913454800036525811803420859 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66919695068853422813278964101649931357757937018225913454800036525811803420859 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 21535881577426863158056312905874510822259970846761189769329853228230725554185 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=132075529 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.132075529' seed=21535881577426863158056312905874510822259970846761189769329853228230725554185 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21535881577426863158056312905874510822259970846761189769329853228230725554185 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy_stress | 86203274572916371924580348960690366123645182052163788220155144987971150593506 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_entropy_stress/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2620308962 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.2620308962' seed=86203274572916371924580348960690366123645182052163788220155144987971150593506 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86203274572916371924580348960690366123645182052163788220155144987971150593506 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_entropy_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_stress_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors_with_csr_rw | 41481603333879966956753926646274544556160988845094900985888403575571015952916 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_shadow_reg_errors_with_csr_rw/latest run_opts='+test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2733533716 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.2733533716' seed=41481603333879966956753926646274544556160988845094900985888403575571015952916 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41481603333879966956753926646274544556160988845094900985888403575571015952916 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_alert_accum_saturation | 18974710290969418875865648900217368166245980237506638602534256613090210051610 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_alert_accum_saturation/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3011999258 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.3011999258' seed=18974710290969418875865648900217368166245980237506638602534256613090210051610 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18974710290969418875865648900217368166245980237506638602534256613090210051610 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_alert_accum_saturation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_alert_accum_saturation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_stress_all_with_rand_reset | 57756378684333407293878476324927218943634863448684646115083315702655259951044 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3669409732 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.3669409732' seed=57756378684333407293878476324927218943634863448684646115083315702655259951044 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57756378684333407293878476324927218943634863448684646115083315702655259951044 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors | 66120896289247169412988501982724363980446856734065629461273388235351144546404 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=385630308 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_errors.385630308' seed=66120896289247169412988501982724363980446856734065629461273388235351144546404 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66120896289247169412988501982724363980446856734065629461273388235351144546404 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_errors | 9029704764489731278896937505061547911330383155128390358304055765150275662597 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4119261957 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.4119261957' seed=9029704764489731278896937505061547911330383155128390358304055765150275662597 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9029704764489731278896937505061547911330383155128390358304055765150275662597 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_intg_err | 102926910129048355628000514739926745025127227742645221058879126762869565224416 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3099653600 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.3099653600' seed=102926910129048355628000514739926745025127227742645221058879126762869565224416 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102926910129048355628000514739926745025127227742645221058879126762869565224416 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_intr_test | 56279898680258656043340060906127155231257072871206209476267924645685047235877 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_intr_test/latest run_opts='+run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1747096869 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.1747096869' seed=56279898680258656043340060906127155231257072871206209476267924645685047235877 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56279898680258656043340060906127155231257072871206209476267924645685047235877 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/9.alert_handler_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 16750519461899991982251103560531030191514008406359571605779378289365687444219 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/10.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4035420923 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.4035420923' seed=16750519461899991982251103560531030191514008406359571605779378289365687444219 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16750519461899991982251103560531030191514008406359571605779378289365687444219 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/10.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 67413372977254428482079809630994907283340078426406485297517392489590364621332 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/10.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3175926292 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.3175926292' seed=67413372977254428482079809630994907283340078426406485297517392489590364621332 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67413372977254428482079809630994907283340078426406485297517392489590364621332 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/10.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_alert_accum | 87266071841250489904393288449486663000881012225459134795301650927597392411715 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/10.alert_handler_esc_alert_accum/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=579255363 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.579255363' seed=87266071841250489904393288449486663000881012225459134795301650927597392411715 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87266071841250489904393288449486663000881012225459134795301650927597392411715 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/10.alert_handler_esc_alert_accum/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_alert_accum_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 10934026314854637972999924919585723685998430065948889618970758925672611733900 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/10.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4279918988 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.4279918988' seed=10934026314854637972999924919585723685998430065948889618970758925672611733900 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10934026314854637972999924919585723685998430065948889618970758925672611733900 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/10.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy | 28241115839138255723670525864754484878093660559932639380320451107892655223641 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/10.alert_handler_entropy/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4069978969 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.4069978969' seed=28241115839138255723670525864754484878093660559932639380320451107892655223641 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28241115839138255723670525864754484878093660559932639380320451107892655223641 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/10.alert_handler_entropy/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 70605379635072356252348305631541810546995270090065827922269315379928977237084 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/10.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=256762972 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.256762972' seed=70605379635072356252348305631541810546995270090065827922269315379928977237084 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70605379635072356252348305631541810546995270090065827922269315379928977237084 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/10.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 12699722851459360523010821490834541587730488311591197041714672815450990465667 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/10.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1161187971 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.1161187971' seed=12699722851459360523010821490834541587730488311591197041714672815450990465667 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12699722851459360523010821490834541587730488311591197041714672815450990465667 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/10.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 112255002435997745433908588221730247220153374842244416481272762104648434207874 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/10.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=947408002 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.947408002' seed=112255002435997745433908588221730247220153374842244416481272762104648434207874 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112255002435997745433908588221730247220153374842244416481272762104648434207874 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/10.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy_stress | 1320741627477482362359459130335867805666375737492407205508737727898256251008 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/10.alert_handler_entropy_stress/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3959789696 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.3959789696' seed=1320741627477482362359459130335867805666375737492407205508737727898256251008 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1320741627477482362359459130335867805666375737492407205508737727898256251008 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/10.alert_handler_entropy_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_stress_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors_with_csr_rw | 33429414824521051420821517764610898683178311798417431871289195224567058868376 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/10.alert_handler_shadow_reg_errors_with_csr_rw/latest run_opts='+test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2084382872 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.2084382872' seed=33429414824521051420821517764610898683178311798417431871289195224567058868376 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33429414824521051420821517764610898683178311798417431871289195224567058868376 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/10.alert_handler_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_alert_accum_saturation | 84433636064779941094972500157211692579080365905943342901104106827434497666724 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/10.alert_handler_alert_accum_saturation/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3443519140 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.3443519140' seed=84433636064779941094972500157211692579080365905943342901104106827434497666724 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84433636064779941094972500157211692579080365905943342901104106827434497666724 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/10.alert_handler_alert_accum_saturation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_alert_accum_saturation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors | 6439714710871537614151919498129899853732426783891770212565298074763954250106 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/10.alert_handler_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1815372154 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_errors.1815372154' seed=6439714710871537614151919498129899853732426783891770212565298074763954250106 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6439714710871537614151919498129899853732426783891770212565298074763954250106 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/10.alert_handler_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_errors | 47287177854925065320726150377983708212664216488614188329157625865086357672767 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/10.alert_handler_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1436488511 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.1436488511' seed=47287177854925065320726150377983708212664216488614188329157625865086357672767 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47287177854925065320726150377983708212664216488614188329157625865086357672767 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/10.alert_handler_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_intg_err | 85408594779582033452465578116472687093557670989601672175623741603216811342289 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/10.alert_handler_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1645197777 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.1645197777' seed=85408594779582033452465578116472687093557670989601672175623741603216811342289 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85408594779582033452465578116472687093557670989601672175623741603216811342289 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/10.alert_handler_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 2659592155704455650902670446604183009583784107773559917374503543614718155939 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/11.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3261668515 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.3261668515' seed=2659592155704455650902670446604183009583784107773559917374503543614718155939 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2659592155704455650902670446604183009583784107773559917374503543614718155939 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/11.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 111220996271647275458789835918605976315647366087693508446487932236949606793610 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/11.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2445967754 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2445967754' seed=111220996271647275458789835918605976315647366087693508446487932236949606793610 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111220996271647275458789835918605976315647366087693508446487932236949606793610 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/11.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_alert_accum | 88094207996408818176249545816609485725650084020195844618806678050323751941210 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/11.alert_handler_esc_alert_accum/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1177203802 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.1177203802' seed=88094207996408818176249545816609485725650084020195844618806678050323751941210 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88094207996408818176249545816609485725650084020195844618806678050323751941210 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/11.alert_handler_esc_alert_accum/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_alert_accum_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 90477727838315881307718083328602290829690685628762298748251712555334227612677 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/11.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2952680453 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.2952680453' seed=90477727838315881307718083328602290829690685628762298748251712555334227612677 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90477727838315881307718083328602290829690685628762298748251712555334227612677 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/11.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy | 34340076165472060930961947341719298715579575985617913824341994827545099897782 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/11.alert_handler_entropy/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3400010678 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.3400010678' seed=34340076165472060930961947341719298715579575985617913824341994827545099897782 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34340076165472060930961947341719298715579575985617913824341994827545099897782 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/11.alert_handler_entropy/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 69382350005362687117989185856845683073576384080031612207357493151260927515744 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/11.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3992116320 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.3992116320' seed=69382350005362687117989185856845683073576384080031612207357493151260927515744 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69382350005362687117989185856845683073576384080031612207357493151260927515744 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/11.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 83143448552200319729098664147415411424155596708127104962021614986331735426601 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/11.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1162053161 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1162053161' seed=83143448552200319729098664147415411424155596708127104962021614986331735426601 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83143448552200319729098664147415411424155596708127104962021614986331735426601 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/11.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 98105138559322064078908174619255181223090447105860060074534497441914052675374 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/11.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3898083118 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.3898083118' seed=98105138559322064078908174619255181223090447105860060074534497441914052675374 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98105138559322064078908174619255181223090447105860060074534497441914052675374 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/11.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy_stress | 21024811647018270043196553280141814691907211806888117944380692700499189911695 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/11.alert_handler_entropy_stress/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1365463183 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.1365463183' seed=21024811647018270043196553280141814691907211806888117944380692700499189911695 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21024811647018270043196553280141814691907211806888117944380692700499189911695 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/11.alert_handler_entropy_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_stress_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors_with_csr_rw | 61257092250462435874837551837585987465127944972638254208699425288857835229688 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/11.alert_handler_shadow_reg_errors_with_csr_rw/latest run_opts='+test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1614762488 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.1614762488' seed=61257092250462435874837551837585987465127944972638254208699425288857835229688 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61257092250462435874837551837585987465127944972638254208699425288857835229688 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/11.alert_handler_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_alert_accum_saturation | 33956355473613663783656751454370569950173941006776510402635800411576232658219 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/11.alert_handler_alert_accum_saturation/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3317777707 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.3317777707' seed=33956355473613663783656751454370569950173941006776510402635800411576232658219 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33956355473613663783656751454370569950173941006776510402635800411576232658219 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/11.alert_handler_alert_accum_saturation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_alert_accum_saturation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors | 15468374460457661100647522987474843589319322516857053289010327501602528883806 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/11.alert_handler_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3282236510 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_errors.3282236510' seed=15468374460457661100647522987474843589319322516857053289010327501602528883806 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15468374460457661100647522987474843589319322516857053289010327501602528883806 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/11.alert_handler_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_errors | 49297547303578476454783404134878671987456066295274384126455781912985635631803 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/11.alert_handler_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1603252923 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.1603252923' seed=49297547303578476454783404134878671987456066295274384126455781912985635631803 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49297547303578476454783404134878671987456066295274384126455781912985635631803 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/11.alert_handler_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_intg_err | 50343298121927201833497949428676982075014811612512747976201482918832825230035 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/11.alert_handler_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2825446099 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.2825446099' seed=50343298121927201833497949428676982075014811612512747976201482918832825230035 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50343298121927201833497949428676982075014811612512747976201482918832825230035 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/11.alert_handler_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 97497953515846499805963286717297448812444833443402665453542783086429884569874 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/12.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=562747666 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.562747666' seed=97497953515846499805963286717297448812444833443402665453542783086429884569874 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97497953515846499805963286717297448812444833443402665453542783086429884569874 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/12.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 78977430678961459309491245333314827887934562517683816352680371879659548188964 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/12.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2754617636 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.2754617636' seed=78977430678961459309491245333314827887934562517683816352680371879659548188964 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78977430678961459309491245333314827887934562517683816352680371879659548188964 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/12.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_alert_accum | 81055503554789272010267761346818573066480664240118872896593947389000666890119 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/12.alert_handler_esc_alert_accum/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=394313607 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.394313607' seed=81055503554789272010267761346818573066480664240118872896593947389000666890119 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81055503554789272010267761346818573066480664240118872896593947389000666890119 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/12.alert_handler_esc_alert_accum/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_alert_accum_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 58052812215708949873376301342561445743274013108110919599036564881485042537311 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/12.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3650605919 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.3650605919' seed=58052812215708949873376301342561445743274013108110919599036564881485042537311 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58052812215708949873376301342561445743274013108110919599036564881485042537311 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/12.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy | 61397157608069022998179070861169691339852460313472449524742263356125274116791 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/12.alert_handler_entropy/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1689981623 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.1689981623' seed=61397157608069022998179070861169691339852460313472449524742263356125274116791 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61397157608069022998179070861169691339852460313472449524742263356125274116791 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/12.alert_handler_entropy/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 87739775439960790699415444891126898295955180876525577855853569196283090656729 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/12.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3869990361 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.3869990361' seed=87739775439960790699415444891126898295955180876525577855853569196283090656729 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87739775439960790699415444891126898295955180876525577855853569196283090656729 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/12.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 91300226783055239467786182207690520493349440197013335726477950021780357472914 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/12.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2435539602 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.2435539602' seed=91300226783055239467786182207690520493349440197013335726477950021780357472914 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91300226783055239467786182207690520493349440197013335726477950021780357472914 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/12.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 63213749125209276178746269059258141332936348807016710160356098496468025899653 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/12.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3177216645 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.3177216645' seed=63213749125209276178746269059258141332936348807016710160356098496468025899653 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63213749125209276178746269059258141332936348807016710160356098496468025899653 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/12.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy_stress | 58032455198773209259259433120289190213741734200553198101659599265246118358944 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/12.alert_handler_entropy_stress/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1655386016 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.1655386016' seed=58032455198773209259259433120289190213741734200553198101659599265246118358944 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58032455198773209259259433120289190213741734200553198101659599265246118358944 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/12.alert_handler_entropy_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_stress_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors_with_csr_rw | 64408386062448020295066319209956326640361018677071709938277765563248763998478 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/12.alert_handler_shadow_reg_errors_with_csr_rw/latest run_opts='+test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1243615502 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.1243615502' seed=64408386062448020295066319209956326640361018677071709938277765563248763998478 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64408386062448020295066319209956326640361018677071709938277765563248763998478 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/12.alert_handler_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_alert_accum_saturation | 37594601950056665462832485086100770348205997477731740580256326182602821279817 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/12.alert_handler_alert_accum_saturation/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1066606665 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.1066606665' seed=37594601950056665462832485086100770348205997477731740580256326182602821279817 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37594601950056665462832485086100770348205997477731740580256326182602821279817 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/12.alert_handler_alert_accum_saturation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_alert_accum_saturation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors | 115233663437688672681935253533410197559475320903613651254792147419253624671322 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/12.alert_handler_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=679087194 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_errors.679087194' seed=115233663437688672681935253533410197559475320903613651254792147419253624671322 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115233663437688672681935253533410197559475320903613651254792147419253624671322 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/12.alert_handler_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_errors | 45032809167388095427581162460565564227020242408090483226647969887930608470902 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/12.alert_handler_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=299322230 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.299322230' seed=45032809167388095427581162460565564227020242408090483226647969887930608470902 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45032809167388095427581162460565564227020242408090483226647969887930608470902 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/12.alert_handler_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_intg_err | 23776207311129227789817805570631907120147178866561013052890674197025299371012 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/12.alert_handler_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2562724868 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.2562724868' seed=23776207311129227789817805570631907120147178866561013052890674197025299371012 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23776207311129227789817805570631907120147178866561013052890674197025299371012 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/12.alert_handler_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 2232576264769041521987075134631909049112572957697957609505546583017055503535 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/13.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1069466799 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.1069466799' seed=2232576264769041521987075134631909049112572957697957609505546583017055503535 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2232576264769041521987075134631909049112572957697957609505546583017055503535 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/13.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 55396920906876486293149533286641084664842739729568030318191770288115775583519 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/13.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=400438559 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.400438559' seed=55396920906876486293149533286641084664842739729568030318191770288115775583519 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55396920906876486293149533286641084664842739729568030318191770288115775583519 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/13.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_alert_accum | 114696590660889174714869137644162204618853666273699524015989105122394374630699 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/13.alert_handler_esc_alert_accum/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3143068971 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.3143068971' seed=114696590660889174714869137644162204618853666273699524015989105122394374630699 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114696590660889174714869137644162204618853666273699524015989105122394374630699 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/13.alert_handler_esc_alert_accum/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_alert_accum_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 76080720852995888011425008993234677911335174947630856518779774962982734112134 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/13.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4043154822 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.4043154822' seed=76080720852995888011425008993234677911335174947630856518779774962982734112134 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76080720852995888011425008993234677911335174947630856518779774962982734112134 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/13.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy | 9037624699141732034333008657684157661311452481389643526924560083076319049978 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/13.alert_handler_entropy/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3982784762 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.3982784762' seed=9037624699141732034333008657684157661311452481389643526924560083076319049978 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9037624699141732034333008657684157661311452481389643526924560083076319049978 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/13.alert_handler_entropy/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 80962652866506383639609907008975373942104063330589796515558384589880850266851 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/13.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=472005347 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.472005347' seed=80962652866506383639609907008975373942104063330589796515558384589880850266851 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80962652866506383639609907008975373942104063330589796515558384589880850266851 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/13.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 55748820359998858317426555382140529423393610399429245162076306963388357274377 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/13.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2047208201 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.2047208201' seed=55748820359998858317426555382140529423393610399429245162076306963388357274377 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55748820359998858317426555382140529423393610399429245162076306963388357274377 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/13.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 106285240956692428591430503581293448212472044755883738625162055647685244197807 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/13.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3950353327 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.3950353327' seed=106285240956692428591430503581293448212472044755883738625162055647685244197807 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106285240956692428591430503581293448212472044755883738625162055647685244197807 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/13.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy_stress | 34871365975081088623602686704678860957904005459338346551935492042837932959179 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/13.alert_handler_entropy_stress/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3688949195 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3688949195' seed=34871365975081088623602686704678860957904005459338346551935492042837932959179 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34871365975081088623602686704678860957904005459338346551935492042837932959179 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/13.alert_handler_entropy_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_stress_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors_with_csr_rw | 33457198019783749453544426768688276679311142546763810883580935826390063815367 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/13.alert_handler_shadow_reg_errors_with_csr_rw/latest run_opts='+test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1101044423 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.1101044423' seed=33457198019783749453544426768688276679311142546763810883580935826390063815367 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33457198019783749453544426768688276679311142546763810883580935826390063815367 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/13.alert_handler_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_alert_accum_saturation | 56499585134569685550171260907992849271429723979830509165502517899573020967011 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/13.alert_handler_alert_accum_saturation/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3077947491 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.3077947491' seed=56499585134569685550171260907992849271429723979830509165502517899573020967011 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56499585134569685550171260907992849271429723979830509165502517899573020967011 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/13.alert_handler_alert_accum_saturation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_alert_accum_saturation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors | 101725870880583695924437166361474614960985057770852126185136010969593222716842 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/13.alert_handler_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=538893738 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_errors.538893738' seed=101725870880583695924437166361474614960985057770852126185136010969593222716842 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101725870880583695924437166361474614960985057770852126185136010969593222716842 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/13.alert_handler_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_errors | 63375035866871133829764230438599098766035887924376788261470935410545325619661 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/13.alert_handler_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4160862669 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.4160862669' seed=63375035866871133829764230438599098766035887924376788261470935410545325619661 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63375035866871133829764230438599098766035887924376788261470935410545325619661 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/13.alert_handler_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_intg_err | 109564901105275643929235798557962507785853798935615684017330577157404816824880 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/13.alert_handler_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3776961072 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3776961072' seed=109564901105275643929235798557962507785853798935615684017330577157404816824880 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109564901105275643929235798557962507785853798935615684017330577157404816824880 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/13.alert_handler_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 84271596915702457776610628003612594755575687781496682976144865671455105661954 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/14.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2852436994 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.2852436994' seed=84271596915702457776610628003612594755575687781496682976144865671455105661954 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84271596915702457776610628003612594755575687781496682976144865671455105661954 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/14.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 65384912048424399400719768567093058131004948488129816091224185079567734803407 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/14.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2489584591 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.2489584591' seed=65384912048424399400719768567093058131004948488129816091224185079567734803407 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65384912048424399400719768567093058131004948488129816091224185079567734803407 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/14.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_alert_accum | 72738003199143923095731265863527356952000988342355386058373453931676320905936 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/14.alert_handler_esc_alert_accum/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2925247184 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.2925247184' seed=72738003199143923095731265863527356952000988342355386058373453931676320905936 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72738003199143923095731265863527356952000988342355386058373453931676320905936 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/14.alert_handler_esc_alert_accum/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_alert_accum_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 38610715714089398171702368148356706010404302422881330760334758399226531660426 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/14.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3503407754 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.3503407754' seed=38610715714089398171702368148356706010404302422881330760334758399226531660426 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38610715714089398171702368148356706010404302422881330760334758399226531660426 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/14.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy | 85951126007450794485839440699386188918503323289673531989491967893695736440109 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/14.alert_handler_entropy/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1654777133 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.1654777133' seed=85951126007450794485839440699386188918503323289673531989491967893695736440109 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85951126007450794485839440699386188918503323289673531989491967893695736440109 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/14.alert_handler_entropy/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 12090061430357169925271655139434539106391580665319753253970485659184947107244 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/14.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3468006828 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3468006828' seed=12090061430357169925271655139434539106391580665319753253970485659184947107244 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12090061430357169925271655139434539106391580665319753253970485659184947107244 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/14.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 23444522946028692803690611715736071568734983876385119571824658310434853196510 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/14.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1562088158 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1562088158' seed=23444522946028692803690611715736071568734983876385119571824658310434853196510 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23444522946028692803690611715736071568734983876385119571824658310434853196510 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/14.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 84443368334319144729925768917244455581971644187301851060750274627632629444095 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/14.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3352980991 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.3352980991' seed=84443368334319144729925768917244455581971644187301851060750274627632629444095 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84443368334319144729925768917244455581971644187301851060750274627632629444095 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/14.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy_stress | 109430236697740182925640498846326938434664180295807003674439947111444944944304 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/14.alert_handler_entropy_stress/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2137160880 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2137160880' seed=109430236697740182925640498846326938434664180295807003674439947111444944944304 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109430236697740182925640498846326938434664180295807003674439947111444944944304 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/14.alert_handler_entropy_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_stress_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors_with_csr_rw | 45268812656872172713792380127579254679476526897252130294096302444535516325743 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/14.alert_handler_shadow_reg_errors_with_csr_rw/latest run_opts='+test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3002427247 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.3002427247' seed=45268812656872172713792380127579254679476526897252130294096302444535516325743 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45268812656872172713792380127579254679476526897252130294096302444535516325743 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/14.alert_handler_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_alert_accum_saturation | 79138513775507383325368278550139697706085612795035424852246329095118019151052 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/14.alert_handler_alert_accum_saturation/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=225494220 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.225494220' seed=79138513775507383325368278550139697706085612795035424852246329095118019151052 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79138513775507383325368278550139697706085612795035424852246329095118019151052 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/14.alert_handler_alert_accum_saturation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_alert_accum_saturation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors | 66653009931456716522601943376413133886259301421176165526925897035762430702621 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/14.alert_handler_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3096769565 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_errors.3096769565' seed=66653009931456716522601943376413133886259301421176165526925897035762430702621 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66653009931456716522601943376413133886259301421176165526925897035762430702621 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/14.alert_handler_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_errors | 101416476290286825169795180256966305038838694491552458686198515640418761496125 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/14.alert_handler_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2855589437 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.2855589437' seed=101416476290286825169795180256966305038838694491552458686198515640418761496125 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101416476290286825169795180256966305038838694491552458686198515640418761496125 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/14.alert_handler_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_intg_err | 11827975774587265539832324228875181224532096609660407197037996280226474966393 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/14.alert_handler_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1029520761 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.1029520761' seed=11827975774587265539832324228875181224532096609660407197037996280226474966393 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11827975774587265539832324228875181224532096609660407197037996280226474966393 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/14.alert_handler_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 8170005722661503082519238240960948583284272866723946545570578379696313541981 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/15.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1230579037 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.1230579037' seed=8170005722661503082519238240960948583284272866723946545570578379696313541981 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8170005722661503082519238240960948583284272866723946545570578379696313541981 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/15.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 72315120665626676861485887892152435475915725720296567465297741070979842863008 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/15.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2777051040 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.2777051040' seed=72315120665626676861485887892152435475915725720296567465297741070979842863008 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72315120665626676861485887892152435475915725720296567465297741070979842863008 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/15.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_alert_accum | 99158648660334850361322888380679431299784527855798318381522006220618540505190 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/15.alert_handler_esc_alert_accum/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=845928550 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.845928550' seed=99158648660334850361322888380679431299784527855798318381522006220618540505190 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99158648660334850361322888380679431299784527855798318381522006220618540505190 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/15.alert_handler_esc_alert_accum/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_alert_accum_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 22267478636032862650597296760775898655310772887260901332543970387840817656266 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/15.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1541894602 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.1541894602' seed=22267478636032862650597296760775898655310772887260901332543970387840817656266 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22267478636032862650597296760775898655310772887260901332543970387840817656266 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/15.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy | 75935425622068404101663227045773556749176458628162825491108469703214986805471 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/15.alert_handler_entropy/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=590725343 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.590725343' seed=75935425622068404101663227045773556749176458628162825491108469703214986805471 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75935425622068404101663227045773556749176458628162825491108469703214986805471 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/15.alert_handler_entropy/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 61390476348526291452816668270957061712539308858676886197504844845574293521890 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/15.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=231966178 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.231966178' seed=61390476348526291452816668270957061712539308858676886197504844845574293521890 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61390476348526291452816668270957061712539308858676886197504844845574293521890 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/15.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 72013501026804184964117180287329831795391168631837142216424090671576947761358 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/15.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1238507726 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.1238507726' seed=72013501026804184964117180287329831795391168631837142216424090671576947761358 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72013501026804184964117180287329831795391168631837142216424090671576947761358 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/15.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 109243672043979725348660987981011615024533312453648504676515032191389156201383 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/15.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4029109159 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.4029109159' seed=109243672043979725348660987981011615024533312453648504676515032191389156201383 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109243672043979725348660987981011615024533312453648504676515032191389156201383 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/15.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy_stress | 51086664653230629884363994600429084353449399815252827414352473112572256024740 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/15.alert_handler_entropy_stress/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=592935076 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.592935076' seed=51086664653230629884363994600429084353449399815252827414352473112572256024740 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51086664653230629884363994600429084353449399815252827414352473112572256024740 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/15.alert_handler_entropy_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_stress_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors_with_csr_rw | 71927846042844220407621009436619018589209921178652964626732318676123239339193 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/15.alert_handler_shadow_reg_errors_with_csr_rw/latest run_opts='+test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2370065593 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.2370065593' seed=71927846042844220407621009436619018589209921178652964626732318676123239339193 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71927846042844220407621009436619018589209921178652964626732318676123239339193 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/15.alert_handler_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_alert_accum_saturation | 57878109972831932048183221778861966300151365620394149176246058980046000561707 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/15.alert_handler_alert_accum_saturation/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3217759787 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.3217759787' seed=57878109972831932048183221778861966300151365620394149176246058980046000561707 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57878109972831932048183221778861966300151365620394149176246058980046000561707 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/15.alert_handler_alert_accum_saturation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_alert_accum_saturation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors | 4313052393258838213508821668031155457615158522383962546029940173633213410329 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/15.alert_handler_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2356390937 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_errors.2356390937' seed=4313052393258838213508821668031155457615158522383962546029940173633213410329 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4313052393258838213508821668031155457615158522383962546029940173633213410329 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/15.alert_handler_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_errors | 107418522089114630980078762813620220973350492261910427357996994649253475926798 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/15.alert_handler_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=381305614 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.381305614' seed=107418522089114630980078762813620220973350492261910427357996994649253475926798 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107418522089114630980078762813620220973350492261910427357996994649253475926798 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/15.alert_handler_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_intg_err | 104559364353191152234583911899901520560296647288186370787441150190674013992810 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/15.alert_handler_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1347565418 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1347565418' seed=104559364353191152234583911899901520560296647288186370787441150190674013992810 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104559364353191152234583911899901520560296647288186370787441150190674013992810 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/15.alert_handler_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 58937773585485605286969558737447429287844926732468666206811767763599955161172 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/16.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2405003348 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.2405003348' seed=58937773585485605286969558737447429287844926732468666206811767763599955161172 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58937773585485605286969558737447429287844926732468666206811767763599955161172 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/16.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 51330256553223551849677311782246116217036275301883133494859948846833141292199 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/16.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1173363879 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.1173363879' seed=51330256553223551849677311782246116217036275301883133494859948846833141292199 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51330256553223551849677311782246116217036275301883133494859948846833141292199 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/16.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_alert_accum | 26812523352350889845240203979499088374448580933991924226116709163751226875237 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/16.alert_handler_esc_alert_accum/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2114329957 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.2114329957' seed=26812523352350889845240203979499088374448580933991924226116709163751226875237 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26812523352350889845240203979499088374448580933991924226116709163751226875237 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/16.alert_handler_esc_alert_accum/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_alert_accum_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 75473617828683790742289649232379082922642673353851104501204023942436768767953 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/16.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3917012945 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.3917012945' seed=75473617828683790742289649232379082922642673353851104501204023942436768767953 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75473617828683790742289649232379082922642673353851104501204023942436768767953 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/16.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy | 105515753982981002509569306164717968636595575085872092171252740279012519973033 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/16.alert_handler_entropy/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3476951209 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.3476951209' seed=105515753982981002509569306164717968636595575085872092171252740279012519973033 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105515753982981002509569306164717968636595575085872092171252740279012519973033 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/16.alert_handler_entropy/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 114033486863358121100065127796366980570466447252239117333710211350330580967097 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/16.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2213060281 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.2213060281' seed=114033486863358121100065127796366980570466447252239117333710211350330580967097 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114033486863358121100065127796366980570466447252239117333710211350330580967097 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/16.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 99192631606355118590685986218362722132338921309804161098594984199003838862304 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/16.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1281610720 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.1281610720' seed=99192631606355118590685986218362722132338921309804161098594984199003838862304 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99192631606355118590685986218362722132338921309804161098594984199003838862304 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/16.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 81021056931417891627547443992560586169601501535792899871548746540405113582005 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/16.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2964681141 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.2964681141' seed=81021056931417891627547443992560586169601501535792899871548746540405113582005 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81021056931417891627547443992560586169601501535792899871548746540405113582005 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/16.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy_stress | 40103796353817098054851315982638809637157919451428145650674782352105863801670 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/16.alert_handler_entropy_stress/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=668101446 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.668101446' seed=40103796353817098054851315982638809637157919451428145650674782352105863801670 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40103796353817098054851315982638809637157919451428145650674782352105863801670 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/16.alert_handler_entropy_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_stress_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors_with_csr_rw | 2456449483323530996410770626826063560546319115630536501932993818852284767238 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/16.alert_handler_shadow_reg_errors_with_csr_rw/latest run_opts='+test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3971292166 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.3971292166' seed=2456449483323530996410770626826063560546319115630536501932993818852284767238 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2456449483323530996410770626826063560546319115630536501932993818852284767238 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/16.alert_handler_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_alert_accum_saturation | 26172731211291249646580953549227629821809260870549411744847755208261456432126 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/16.alert_handler_alert_accum_saturation/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4083747838 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.4083747838' seed=26172731211291249646580953549227629821809260870549411744847755208261456432126 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26172731211291249646580953549227629821809260870549411744847755208261456432126 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/16.alert_handler_alert_accum_saturation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_alert_accum_saturation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors | 24440240573355578317143393844382252524941513769158923572916260346061269855045 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/16.alert_handler_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1324968773 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_errors.1324968773' seed=24440240573355578317143393844382252524941513769158923572916260346061269855045 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24440240573355578317143393844382252524941513769158923572916260346061269855045 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/16.alert_handler_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_errors | 82701653694632117956548475139778760132441288629798261156841625004716069240430 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/16.alert_handler_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2051292782 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.2051292782' seed=82701653694632117956548475139778760132441288629798261156841625004716069240430 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82701653694632117956548475139778760132441288629798261156841625004716069240430 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/16.alert_handler_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_intg_err | 83547401162708775235026360536573334288610746248835004974034490931170651792967 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/16.alert_handler_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4024821319 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.4024821319' seed=83547401162708775235026360536573334288610746248835004974034490931170651792967 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83547401162708775235026360536573334288610746248835004974034490931170651792967 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/16.alert_handler_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 27037201040225754651054805375733051128893669455700687637059516103301321778702 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2380064270 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2380064270' seed=27037201040225754651054805375733051128893669455700687637059516103301321778702 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27037201040225754651054805375733051128893669455700687637059516103301321778702 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 72519821595871179137124954975102426191631500061402359678641725518695120285990 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3635458342 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3635458342' seed=72519821595871179137124954975102426191631500061402359678641725518695120285990 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72519821595871179137124954975102426191631500061402359678641725518695120285990 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_alert_accum | 52793761242085104410538075971242940018662047153018431428117273830934623776935 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_esc_alert_accum/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=368537767 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.368537767' seed=52793761242085104410538075971242940018662047153018431428117273830934623776935 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=52793761242085104410538075971242940018662047153018431428117273830934623776935 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_esc_alert_accum/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_alert_accum_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 45714743028980640460566262231007167553856480555096233902856518153609386092648 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3383453800 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.3383453800' seed=45714743028980640460566262231007167553856480555096233902856518153609386092648 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45714743028980640460566262231007167553856480555096233902856518153609386092648 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy | 79355796310060942926868275004694581130905905343918074536894806621632924900817 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_entropy/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3805961681 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3805961681' seed=79355796310060942926868275004694581130905905343918074536894806621632924900817 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79355796310060942926868275004694581130905905343918074536894806621632924900817 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_entropy/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 107476712255051032651317723752632677511958230417710311872359383220892594864697 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1792803385 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1792803385' seed=107476712255051032651317723752632677511958230417710311872359383220892594864697 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107476712255051032651317723752632677511958230417710311872359383220892594864697 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 29369429489548705517884697206494704896715106462064995803068360883197237373340 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=573417884 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.573417884' seed=29369429489548705517884697206494704896715106462064995803068360883197237373340 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29369429489548705517884697206494704896715106462064995803068360883197237373340 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 96639078726714169860991513276062790754037164870157049936063275643934717043989 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2162746645 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.2162746645' seed=96639078726714169860991513276062790754037164870157049936063275643934717043989 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96639078726714169860991513276062790754037164870157049936063275643934717043989 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy_stress | 53921230406691067645891339869357173795078642648353884305514204151637611764306 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_entropy_stress/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1603394130 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1603394130' seed=53921230406691067645891339869357173795078642648353884305514204151637611764306 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53921230406691067645891339869357173795078642648353884305514204151637611764306 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_entropy_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_stress_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors_with_csr_rw | 93098240699053610424006339327109333422211591714582943381219333316462042815830 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_shadow_reg_errors_with_csr_rw/latest run_opts='+test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3951435094 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3951435094' seed=93098240699053610424006339327109333422211591714582943381219333316462042815830 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93098240699053610424006339327109333422211591714582943381219333316462042815830 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_alert_accum_saturation | 37986908548358195855477751534728988942399412993500053534284690492108618845486 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_alert_accum_saturation/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3760180526 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.3760180526' seed=37986908548358195855477751534728988942399412993500053534284690492108618845486 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37986908548358195855477751534728988942399412993500053534284690492108618845486 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_alert_accum_saturation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_alert_accum_saturation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors | 7812697502882241589864538511400275170650822410837264357225829190969857948986 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3713809722 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_errors.3713809722' seed=7812697502882241589864538511400275170650822410837264357225829190969857948986 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7812697502882241589864538511400275170650822410837264357225829190969857948986 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_errors | 14891127249518866617076572432842430428816568685274681941565249044440045201185 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3775014689 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3775014689' seed=14891127249518866617076572432842430428816568685274681941565249044440045201185 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=14891127249518866617076572432842430428816568685274681941565249044440045201185 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_intg_err | 29941863692987437999650381336684016999341473053406825780824921348315692002175 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2174348159 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.2174348159' seed=29941863692987437999650381336684016999341473053406825780824921348315692002175 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29941863692987437999650381336684016999341473053406825780824921348315692002175 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/17.alert_handler_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 32237307665110387407295387762848178473237234280185337244957002864257913002364 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/18.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2378635644 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.2378635644' seed=32237307665110387407295387762848178473237234280185337244957002864257913002364 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32237307665110387407295387762848178473237234280185337244957002864257913002364 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/18.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 5295178049713653487557613527524412431065171007274964725983191479107994048317 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/18.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2248202045 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.2248202045' seed=5295178049713653487557613527524412431065171007274964725983191479107994048317 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5295178049713653487557613527524412431065171007274964725983191479107994048317 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/18.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_alert_accum | 25709382401625149420832542405833638593917251411881228512033459968487957748519 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/18.alert_handler_esc_alert_accum/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2088524583 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.2088524583' seed=25709382401625149420832542405833638593917251411881228512033459968487957748519 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25709382401625149420832542405833638593917251411881228512033459968487957748519 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/18.alert_handler_esc_alert_accum/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_alert_accum_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 81728089151528649288547525679312397831602912212903025852959993983608818098477 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/18.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2034622765 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2034622765' seed=81728089151528649288547525679312397831602912212903025852959993983608818098477 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81728089151528649288547525679312397831602912212903025852959993983608818098477 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/18.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy | 46475759653854612055941414929111479718243098239142497981784593703053402404434 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/18.alert_handler_entropy/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3464328786 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.3464328786' seed=46475759653854612055941414929111479718243098239142497981784593703053402404434 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46475759653854612055941414929111479718243098239142497981784593703053402404434 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/18.alert_handler_entropy/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 8605002633872873482319831799264083903814441214428521394586948347047563861035 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/18.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1409129515 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.1409129515' seed=8605002633872873482319831799264083903814441214428521394586948347047563861035 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8605002633872873482319831799264083903814441214428521394586948347047563861035 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/18.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 112717209014430035799493525810385685839826438825877797300889936628343892700155 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/18.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2668456955 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.2668456955' seed=112717209014430035799493525810385685839826438825877797300889936628343892700155 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112717209014430035799493525810385685839826438825877797300889936628343892700155 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/18.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 37030250629406677459040509012753434089427098151003026034084812326915582433207 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/18.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3973552055 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.3973552055' seed=37030250629406677459040509012753434089427098151003026034084812326915582433207 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37030250629406677459040509012753434089427098151003026034084812326915582433207 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/18.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy_stress | 58656090342634552955544017798395645509791875615755179640123828009969506416914 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/18.alert_handler_entropy_stress/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2935322898 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.2935322898' seed=58656090342634552955544017798395645509791875615755179640123828009969506416914 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58656090342634552955544017798395645509791875615755179640123828009969506416914 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/18.alert_handler_entropy_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_stress_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors_with_csr_rw | 81556435470470286813733639868825716338665774259945709818098731758779444835809 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/18.alert_handler_shadow_reg_errors_with_csr_rw/latest run_opts='+test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=446510561 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.446510561' seed=81556435470470286813733639868825716338665774259945709818098731758779444835809 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81556435470470286813733639868825716338665774259945709818098731758779444835809 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/18.alert_handler_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_alert_accum_saturation | 9003154975178295754597325504839523875663985849653113323049805562576308357248 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/18.alert_handler_alert_accum_saturation/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=741951616 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.741951616' seed=9003154975178295754597325504839523875663985849653113323049805562576308357248 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9003154975178295754597325504839523875663985849653113323049805562576308357248 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/18.alert_handler_alert_accum_saturation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_alert_accum_saturation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors | 115051009132856118206970914652381212938864502498622313660997381612206709721121 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/18.alert_handler_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2631321633 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_errors.2631321633' seed=115051009132856118206970914652381212938864502498622313660997381612206709721121 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115051009132856118206970914652381212938864502498622313660997381612206709721121 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/18.alert_handler_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_errors | 81679692686034745973009232532671063148027483798773522481068865676426898553202 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/18.alert_handler_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3202857330 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.3202857330' seed=81679692686034745973009232532671063148027483798773522481068865676426898553202 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81679692686034745973009232532671063148027483798773522481068865676426898553202 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/18.alert_handler_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_intg_err | 89203669835010378988764503121199149899213183320971525391126192183039683239053 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/18.alert_handler_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1657052301 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.1657052301' seed=89203669835010378988764503121199149899213183320971525391126192183039683239053 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89203669835010378988764503121199149899213183320971525391126192183039683239053 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/18.alert_handler_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 66727846157787375945976310425868329772651610904402082117729471950713492868103 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/19.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2988444679 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.2988444679' seed=66727846157787375945976310425868329772651610904402082117729471950713492868103 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66727846157787375945976310425868329772651610904402082117729471950713492868103 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/19.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 84125369653170752333477959596132737363271361834789217150009735562061627023261 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/19.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2529976221 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.2529976221' seed=84125369653170752333477959596132737363271361834789217150009735562061627023261 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84125369653170752333477959596132737363271361834789217150009735562061627023261 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/19.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_alert_accum | 79722294997648575072693340877569341407965285891044784829945488368829774387218 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/19.alert_handler_esc_alert_accum/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2119653394 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.2119653394' seed=79722294997648575072693340877569341407965285891044784829945488368829774387218 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79722294997648575072693340877569341407965285891044784829945488368829774387218 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/19.alert_handler_esc_alert_accum/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_alert_accum_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 3246202800161312615366085291040395161003700060827555193477645493574836571260 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/19.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3219278972 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.3219278972' seed=3246202800161312615366085291040395161003700060827555193477645493574836571260 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3246202800161312615366085291040395161003700060827555193477645493574836571260 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/19.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy | 25773214790181887785474023568942643333829159876791118109459455595869184101416 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/19.alert_handler_entropy/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1883671592 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.1883671592' seed=25773214790181887785474023568942643333829159876791118109459455595869184101416 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25773214790181887785474023568942643333829159876791118109459455595869184101416 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/19.alert_handler_entropy/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 40853574328810297955412472538548775780948740906634942973534954650103749611131 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/19.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3984658043 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3984658043' seed=40853574328810297955412472538548775780948740906634942973534954650103749611131 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40853574328810297955412472538548775780948740906634942973534954650103749611131 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/19.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 36115796795141982097509640509771335564816580100960082600005182442464259682738 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/19.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1651122 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.1651122' seed=36115796795141982097509640509771335564816580100960082600005182442464259682738 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36115796795141982097509640509771335564816580100960082600005182442464259682738 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/19.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 35356019639245187354132399398824325342480822976262310550962499695754982775876 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/19.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4211924036 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.4211924036' seed=35356019639245187354132399398824325342480822976262310550962499695754982775876 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35356019639245187354132399398824325342480822976262310550962499695754982775876 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/19.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy_stress | 20663603918016619442009872479947793062739195357054893420886379664901712367612 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/19.alert_handler_entropy_stress/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3487027196 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.3487027196' seed=20663603918016619442009872479947793062739195357054893420886379664901712367612 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20663603918016619442009872479947793062739195357054893420886379664901712367612 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/19.alert_handler_entropy_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_stress_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors_with_csr_rw | 32779195590888960803575400980721395124277592933259173909023379314317856002787 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/19.alert_handler_shadow_reg_errors_with_csr_rw/latest run_opts='+test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=321049315 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.321049315' seed=32779195590888960803575400980721395124277592933259173909023379314317856002787 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32779195590888960803575400980721395124277592933259173909023379314317856002787 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/19.alert_handler_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_alert_accum_saturation | 20304511974307593681336249731272848764078139904435738383255822934198316528234 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/19.alert_handler_alert_accum_saturation/latest run_opts='+en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1009349226 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.1009349226' seed=20304511974307593681336249731272848764078139904435738383255822934198316528234 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20304511974307593681336249731272848764078139904435738383255822934198316528234 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/19.alert_handler_alert_accum_saturation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_alert_accum_saturation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_shadow_reg_errors | 8218130184072864923360411826281160423515814415625497919847371303570297060876 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/19.alert_handler_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=10485260 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_errors.10485260' seed=8218130184072864923360411826281160423515814415625497919847371303570297060876 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8218130184072864923360411826281160423515814415625497919847371303570297060876 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/19.alert_handler_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_errors | 13576366793885195297598549236215472366420080621171548565829122199890439001640 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/19.alert_handler_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1730762280 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.1730762280' seed=13576366793885195297598549236215472366420080621171548565829122199890439001640 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13576366793885195297598549236215472366420080621171548565829122199890439001640 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/19.alert_handler_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_intg_err | 77902993750862493984227459562913309964523271343668816962936935694505235979384 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/19.alert_handler_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3586137208 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.3586137208' seed=77902993750862493984227459562913309964523271343668816962936935694505235979384 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77902993750862493984227459562913309964523271343668816962936935694505235979384 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/19.alert_handler_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 65968003405108984240833333602021405944703312072587842032445094967971372842388 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/20.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=898350484 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.898350484' seed=65968003405108984240833333602021405944703312072587842032445094967971372842388 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65968003405108984240833333602021405944703312072587842032445094967971372842388 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/20.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 24911712513929650036272829092351766076389000725750120631567138229530350244313 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/20.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1759171033 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.1759171033' seed=24911712513929650036272829092351766076389000725750120631567138229530350244313 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24911712513929650036272829092351766076389000725750120631567138229530350244313 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/20.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_alert_accum | 25145189952421165481069005516773452542257630250767280032111001098361720802729 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/20.alert_handler_esc_alert_accum/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1552944553 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.1552944553' seed=25145189952421165481069005516773452542257630250767280032111001098361720802729 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25145189952421165481069005516773452542257630250767280032111001098361720802729 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/20.alert_handler_esc_alert_accum/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_alert_accum_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 100829464809632190760738436400436455782635255957523480118573988794870656936014 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/20.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2379229262 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.2379229262' seed=100829464809632190760738436400436455782635255957523480118573988794870656936014 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100829464809632190760738436400436455782635255957523480118573988794870656936014 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/20.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy | 11605341834769713711605509629241897564711071247608271529669834588267371144316 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/20.alert_handler_entropy/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=575775868 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.575775868' seed=11605341834769713711605509629241897564711071247608271529669834588267371144316 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11605341834769713711605509629241897564711071247608271529669834588267371144316 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/20.alert_handler_entropy/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 82226247519779025181649315639878950148080580395683584362672178535575704637556 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/20.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=912593012 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.912593012' seed=82226247519779025181649315639878950148080580395683584362672178535575704637556 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82226247519779025181649315639878950148080580395683584362672178535575704637556 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/20.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 57228352498908938054894160582741675622609760475414412912504791311726346812830 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/20.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1180745118 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.1180745118' seed=57228352498908938054894160582741675622609760475414412912504791311726346812830 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57228352498908938054894160582741675622609760475414412912504791311726346812830 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/20.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 63789607241473913649339723178848840490843114356547088165023898209744212865976 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/20.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2025206712 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2025206712' seed=63789607241473913649339723178848840490843114356547088165023898209744212865976 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63789607241473913649339723178848840490843114356547088165023898209744212865976 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/20.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_errors | 66270162369873900009369301768597623627501903631692189134400243436023822454870 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/20.alert_handler_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4000878678 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_tl_errors.4000878678' seed=66270162369873900009369301768597623627501903631692189134400243436023822454870 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66270162369873900009369301768597623627501903631692189134400243436023822454870 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/20.alert_handler_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_intg_err | 68165179566872250554552642480693662541084384051330539474177237700563422375149 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/20.alert_handler_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3910626541 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_tl_intg_err.3910626541' seed=68165179566872250554552642480693662541084384051330539474177237700563422375149 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68165179566872250554552642480693662541084384051330539474177237700563422375149 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/20.alert_handler_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 77375137594280405866218913745858218737417168667826485542779607363793024372022 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/21.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3853700406 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.3853700406' seed=77375137594280405866218913745858218737417168667826485542779607363793024372022 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77375137594280405866218913745858218737417168667826485542779607363793024372022 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/21.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 41237363718231576421616280628310798663749020190191249202196737522707989742421 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/21.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3545449301 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3545449301' seed=41237363718231576421616280628310798663749020190191249202196737522707989742421 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41237363718231576421616280628310798663749020190191249202196737522707989742421 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/21.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_alert_accum | 65367519651408486521447645494046372896594552872856413476208372080489300859812 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/21.alert_handler_esc_alert_accum/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1080138660 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.1080138660' seed=65367519651408486521447645494046372896594552872856413476208372080489300859812 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65367519651408486521447645494046372896594552872856413476208372080489300859812 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/21.alert_handler_esc_alert_accum/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_alert_accum_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 110320034861422639091861799520562303328800367815205423527555107856351132604862 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/21.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1748195774 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.1748195774' seed=110320034861422639091861799520562303328800367815205423527555107856351132604862 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110320034861422639091861799520562303328800367815205423527555107856351132604862 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/21.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy | 4087415819037344249328097237332769050218518766494827042881621192078660721055 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/21.alert_handler_entropy/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1648351647 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.1648351647' seed=4087415819037344249328097237332769050218518766494827042881621192078660721055 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4087415819037344249328097237332769050218518766494827042881621192078660721055 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/21.alert_handler_entropy/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 50168409331736710673895833004186121928824857462747528351008713078654025570618 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/21.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4271610170 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.4271610170' seed=50168409331736710673895833004186121928824857462747528351008713078654025570618 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50168409331736710673895833004186121928824857462747528351008713078654025570618 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/21.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 64623759501868819961854725758612669471391859623841110656565473859002829342549 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/21.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2700576597 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.2700576597' seed=64623759501868819961854725758612669471391859623841110656565473859002829342549 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64623759501868819961854725758612669471391859623841110656565473859002829342549 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/21.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 110672895060320568954598686170061976710908266073815931929027119225827561665805 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/21.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=285832461 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.285832461' seed=110672895060320568954598686170061976710908266073815931929027119225827561665805 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110672895060320568954598686170061976710908266073815931929027119225827561665805 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/21.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_errors | 83771611486834163288983431614081300296905959699875017121356547553324350045564 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/21.alert_handler_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1529347452 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_tl_errors.1529347452' seed=83771611486834163288983431614081300296905959699875017121356547553324350045564 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83771611486834163288983431614081300296905959699875017121356547553324350045564 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/21.alert_handler_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_intg_err | 16287812029238291927325871737717556870626176171196774606613933563979724026553 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/21.alert_handler_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1103164089 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_tl_intg_err.1103164089' seed=16287812029238291927325871737717556870626176171196774606613933563979724026553 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16287812029238291927325871737717556870626176171196774606613933563979724026553 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/21.alert_handler_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 25388184004337729724384598234021401231105008408993305302089214075893058368644 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/22.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2218521732 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2218521732' seed=25388184004337729724384598234021401231105008408993305302089214075893058368644 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25388184004337729724384598234021401231105008408993305302089214075893058368644 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/22.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 17058730164690571735823826449975808070035681050325542067237958095208030093159 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/22.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=420953959 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.420953959' seed=17058730164690571735823826449975808070035681050325542067237958095208030093159 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17058730164690571735823826449975808070035681050325542067237958095208030093159 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/22.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_alert_accum | 102958209406484410504598056421540335515505002986876631383003210104577444052048 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/22.alert_handler_esc_alert_accum/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1053326416 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.1053326416' seed=102958209406484410504598056421540335515505002986876631383003210104577444052048 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102958209406484410504598056421540335515505002986876631383003210104577444052048 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/22.alert_handler_esc_alert_accum/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_alert_accum_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 94235739174417503467477308502133962452910054666042670547814855358338704369042 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/22.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1811703186 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.1811703186' seed=94235739174417503467477308502133962452910054666042670547814855358338704369042 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94235739174417503467477308502133962452910054666042670547814855358338704369042 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/22.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy | 4156515727539940108944668050452551249057582739307707614046648114421608130843 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/22.alert_handler_entropy/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2491066651 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.2491066651' seed=4156515727539940108944668050452551249057582739307707614046648114421608130843 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4156515727539940108944668050452551249057582739307707614046648114421608130843 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/22.alert_handler_entropy/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 98208336190615118264163981570082301920491432305809600053627379722038937858848 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/22.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2371040032 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.2371040032' seed=98208336190615118264163981570082301920491432305809600053627379722038937858848 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98208336190615118264163981570082301920491432305809600053627379722038937858848 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/22.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 68480209412191505635820713512582418379931009227227839555763971035830170632274 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/22.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=74137682 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.74137682' seed=68480209412191505635820713512582418379931009227227839555763971035830170632274 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68480209412191505635820713512582418379931009227227839555763971035830170632274 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/22.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 111811699442066639341793433782035731587365977830665422073446126483471422691220 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/22.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3119749012 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.3119749012' seed=111811699442066639341793433782035731587365977830665422073446126483471422691220 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111811699442066639341793433782035731587365977830665422073446126483471422691220 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/22.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_errors | 110005707194340745075214519121424033142873362544645354293052104622354510780395 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/22.alert_handler_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=463345643 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_tl_errors.463345643' seed=110005707194340745075214519121424033142873362544645354293052104622354510780395 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110005707194340745075214519121424033142873362544645354293052104622354510780395 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/22.alert_handler_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_intg_err | 113312231584975338194275349760617378636670868972261302423004971726474613603380 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/22.alert_handler_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2015345716 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_tl_intg_err.2015345716' seed=113312231584975338194275349760617378636670868972261302423004971726474613603380 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113312231584975338194275349760617378636670868972261302423004971726474613603380 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/22.alert_handler_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 75235069943176571363489726355198386012109670465258401960478944334136856385727 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/23.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2387712191 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.2387712191' seed=75235069943176571363489726355198386012109670465258401960478944334136856385727 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75235069943176571363489726355198386012109670465258401960478944334136856385727 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/23.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 106726011162075301527269911683751798284043717713497495037066398484063406070570 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/23.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1138826026 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.1138826026' seed=106726011162075301527269911683751798284043717713497495037066398484063406070570 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106726011162075301527269911683751798284043717713497495037066398484063406070570 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/23.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_alert_accum | 3027069592292741332674490213029938829923639702445818496202081503732374595145 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/23.alert_handler_esc_alert_accum/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=485910089 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.485910089' seed=3027069592292741332674490213029938829923639702445818496202081503732374595145 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3027069592292741332674490213029938829923639702445818496202081503732374595145 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/23.alert_handler_esc_alert_accum/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_alert_accum_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 3822750361217760856391747469263568712704565367219861715976898268508674546262 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/23.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3080149590 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.3080149590' seed=3822750361217760856391747469263568712704565367219861715976898268508674546262 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3822750361217760856391747469263568712704565367219861715976898268508674546262 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/23.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy | 38320993850381246018818600803867454722800219245214103195247454355610867605331 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/23.alert_handler_entropy/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1607737171 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.1607737171' seed=38320993850381246018818600803867454722800219245214103195247454355610867605331 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38320993850381246018818600803867454722800219245214103195247454355610867605331 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/23.alert_handler_entropy/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 18662299362294033229355191734290115180854508045676188728973340325284915978852 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/23.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2375295588 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.2375295588' seed=18662299362294033229355191734290115180854508045676188728973340325284915978852 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18662299362294033229355191734290115180854508045676188728973340325284915978852 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/23.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 73270369941003166550760192331101905152131531238923332737612084324181934738308 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/23.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1742867332 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.1742867332' seed=73270369941003166550760192331101905152131531238923332737612084324181934738308 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73270369941003166550760192331101905152131531238923332737612084324181934738308 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/23.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 22518403802646503907092250028197297567681362901422123698092816987902758791648 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/23.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1961535968 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.1961535968' seed=22518403802646503907092250028197297567681362901422123698092816987902758791648 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22518403802646503907092250028197297567681362901422123698092816987902758791648 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/23.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_errors | 45736231169651602624745600601251079185344255894672863317505144892390632439729 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/23.alert_handler_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2981216177 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_tl_errors.2981216177' seed=45736231169651602624745600601251079185344255894672863317505144892390632439729 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45736231169651602624745600601251079185344255894672863317505144892390632439729 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/23.alert_handler_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_intg_err | 25768992154548345087754193300391561389177963916707589706483252442085694912476 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/23.alert_handler_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=941635548 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_tl_intg_err.941635548' seed=25768992154548345087754193300391561389177963916707589706483252442085694912476 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25768992154548345087754193300391561389177963916707589706483252442085694912476 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/23.alert_handler_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 76336173646481663193474711979169166668595058309203936092056490282568885459361 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/24.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2505824673 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2505824673' seed=76336173646481663193474711979169166668595058309203936092056490282568885459361 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76336173646481663193474711979169166668595058309203936092056490282568885459361 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/24.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 27678099285340904766918063232794443303621156918718368702425917707410604188419 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/24.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=412246787 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.412246787' seed=27678099285340904766918063232794443303621156918718368702425917707410604188419 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27678099285340904766918063232794443303621156918718368702425917707410604188419 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/24.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_alert_accum | 84976664768814196057315634707090145844973977908678451095290847006447909614296 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/24.alert_handler_esc_alert_accum/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3250991832 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.3250991832' seed=84976664768814196057315634707090145844973977908678451095290847006447909614296 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84976664768814196057315634707090145844973977908678451095290847006447909614296 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/24.alert_handler_esc_alert_accum/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_alert_accum_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 75506287513930643505393098266495215698694334229874419195703515318494416918430 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/24.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3496269726 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.3496269726' seed=75506287513930643505393098266495215698694334229874419195703515318494416918430 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75506287513930643505393098266495215698694334229874419195703515318494416918430 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/24.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_entropy | 84221328970075238685727922414636094670224024774455594050595755721722136563226 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/24.alert_handler_entropy/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4020964890 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.4020964890' seed=84221328970075238685727922414636094670224024774455594050595755721722136563226 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84221328970075238685727922414636094670224024774455594050595755721722136563226 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/24.alert_handler_entropy/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_entropy_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 111407993800136503763302994895166298492537589044861814872408689674959986575907 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/24.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=651905571 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.651905571' seed=111407993800136503763302994895166298492537589044861814872408689674959986575907 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111407993800136503763302994895166298492537589044861814872408689674959986575907 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/24.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 30058497423969515994947971738074130856606633785571367511526316945506566422834 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/24.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=602161458 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.602161458' seed=30058497423969515994947971738074130856606633785571367511526316945506566422834 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30058497423969515994947971738074130856606633785571367511526316945506566422834 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/24.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 5826752866809077651172432063698812826801252735389723335379386799852084599202 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/24.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2786662818 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.2786662818' seed=5826752866809077651172432063698812826801252735389723335379386799852084599202 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5826752866809077651172432063698812826801252735389723335379386799852084599202 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/24.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_errors | 88850975188480588292729124145675014254042984539299436875493631390250473247452 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/24.alert_handler_tl_errors/latest run_opts='+run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2660127452 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_tl_errors.2660127452' seed=88850975188480588292729124145675014254042984539299436875493631390250473247452 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88850975188480588292729124145675014254042984539299436875493631390250473247452 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/24.alert_handler_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_tl_intg_err | 67789610361848513340768880042714354035032979889360668100608200132160239582059 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/24.alert_handler_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3476437867 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_tl_intg_err.3476437867' seed=67789610361848513340768880042714354035032979889360668100608200132160239582059 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67789610361848513340768880042714354035032979889360668100608200132160239582059 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/24.alert_handler_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 109551659596389237377453090320307761201249535589341626761572524542204209302363 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/25.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3467152219 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.3467152219' seed=109551659596389237377453090320307761201249535589341626761572524542204209302363 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109551659596389237377453090320307761201249535589341626761572524542204209302363 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/25.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 80489527683640448936423864224151499417725901882291212341820240663791979122832 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/25.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3668365456 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.3668365456' seed=80489527683640448936423864224151499417725901882291212341820240663791979122832 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80489527683640448936423864224151499417725901882291212341820240663791979122832 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/25.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 114371427561619142804211394342977537988073309402706557901812388704038391306198 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/25.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2321733590 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.2321733590' seed=114371427561619142804211394342977537988073309402706557901812388704038391306198 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114371427561619142804211394342977537988073309402706557901812388704038391306198 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/25.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 35711940763757995718255196516205819711716423701343270049128204864990370208902 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/25.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3331202182 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.3331202182' seed=35711940763757995718255196516205819711716423701343270049128204864990370208902 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35711940763757995718255196516205819711716423701343270049128204864990370208902 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/25.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 94287618621522607697920777974858505905400470924032060436358440322224041792219 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/25.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3507524315 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.3507524315' seed=94287618621522607697920777974858505905400470924032060436358440322224041792219 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94287618621522607697920777974858505905400470924032060436358440322224041792219 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/25.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 75697763926548058340504207869201540183726893263841953231244204133955405252356 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/25.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3912664836 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.3912664836' seed=75697763926548058340504207869201540183726893263841953231244204133955405252356 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75697763926548058340504207869201540183726893263841953231244204133955405252356 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/25.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 95109128901722806507260906612337613871961661102373037875222936114013635236969 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/26.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=915821673 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.915821673' seed=95109128901722806507260906612337613871961661102373037875222936114013635236969 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95109128901722806507260906612337613871961661102373037875222936114013635236969 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/26.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 56214814717749580507846072324145852781360639439260313901493531784373610441205 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/26.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=467364341 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.467364341' seed=56214814717749580507846072324145852781360639439260313901493531784373610441205 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56214814717749580507846072324145852781360639439260313901493531784373610441205 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/26.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 77797485168133809400550795144429067963012453817793799238597787647199013541349 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/26.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=226268645 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.226268645' seed=77797485168133809400550795144429067963012453817793799238597787647199013541349 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77797485168133809400550795144429067963012453817793799238597787647199013541349 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/26.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 23811971399839786837766355037883246632435549018347589674847254878624704402302 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/26.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2557776766 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.2557776766' seed=23811971399839786837766355037883246632435549018347589674847254878624704402302 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23811971399839786837766355037883246632435549018347589674847254878624704402302 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/26.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 38995689254938482057548587308125449973657384944404568146207156052411047469884 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/26.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4159693628 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.4159693628' seed=38995689254938482057548587308125449973657384944404568146207156052411047469884 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38995689254938482057548587308125449973657384944404568146207156052411047469884 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/26.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 89642282455014528476744456210004770724417035953479200939484684109940134789310 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/26.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3741073598 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.3741073598' seed=89642282455014528476744456210004770724417035953479200939484684109940134789310 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89642282455014528476744456210004770724417035953479200939484684109940134789310 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/26.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 4832031702890743240301890795469222190953117249491254262894472660547754437294 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/27.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3979782830 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.3979782830' seed=4832031702890743240301890795469222190953117249491254262894472660547754437294 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4832031702890743240301890795469222190953117249491254262894472660547754437294 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/27.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 86179467507788518096297625631937023892198531684902146906070334350899756603014 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/27.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=468391558 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.468391558' seed=86179467507788518096297625631937023892198531684902146906070334350899756603014 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86179467507788518096297625631937023892198531684902146906070334350899756603014 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/27.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 19432263708485762335525786506433707280672634628096970679802818487651597047368 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/27.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2854508104 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.2854508104' seed=19432263708485762335525786506433707280672634628096970679802818487651597047368 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19432263708485762335525786506433707280672634628096970679802818487651597047368 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/27.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 54443589723840807560932268249622566238161051127620352075355087046154205778940 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/27.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1963709436 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.1963709436' seed=54443589723840807560932268249622566238161051127620352075355087046154205778940 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54443589723840807560932268249622566238161051127620352075355087046154205778940 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/27.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 21520245670281859566499529009660341838903902558648911676145326056952927924545 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/27.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2499064129 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.2499064129' seed=21520245670281859566499529009660341838903902558648911676145326056952927924545 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21520245670281859566499529009660341838903902558648911676145326056952927924545 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/27.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 70371065141208480903779531781664318030153422847000212891937860093886695540513 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/27.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3588032289 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3588032289' seed=70371065141208480903779531781664318030153422847000212891937860093886695540513 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70371065141208480903779531781664318030153422847000212891937860093886695540513 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/27.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 110817112375249149006757170652691524954986418054796350529120466100356481315475 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/28.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2134930067 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.2134930067' seed=110817112375249149006757170652691524954986418054796350529120466100356481315475 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110817112375249149006757170652691524954986418054796350529120466100356481315475 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/28.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 70324744119541016702058455518828359491158677809729979203555184908779774471195 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/28.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1073409051 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.1073409051' seed=70324744119541016702058455518828359491158677809729979203555184908779774471195 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70324744119541016702058455518828359491158677809729979203555184908779774471195 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/28.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 8763068152822903088133038597398005872999641747543611439161131150882136442780 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/28.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1929168796 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.1929168796' seed=8763068152822903088133038597398005872999641747543611439161131150882136442780 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8763068152822903088133038597398005872999641747543611439161131150882136442780 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/28.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 73024324535924343731790051560387534612153968175636635240780500912533192898811 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/28.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3123771643 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.3123771643' seed=73024324535924343731790051560387534612153968175636635240780500912533192898811 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73024324535924343731790051560387534612153968175636635240780500912533192898811 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/28.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 106157563395702040413250806856355502022068221920064507764067418271829118797878 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/28.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1104791606 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.1104791606' seed=106157563395702040413250806856355502022068221920064507764067418271829118797878 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106157563395702040413250806856355502022068221920064507764067418271829118797878 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/28.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 76761141926314401572249570572473554640824703202112700930123481171491096238529 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/28.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1696733633 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.1696733633' seed=76761141926314401572249570572473554640824703202112700930123481171491096238529 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76761141926314401572249570572473554640824703202112700930123481171491096238529 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/28.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 52420467782423826582633827050420738122590576455249986579251325553894502665974 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/29.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4060057334 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.4060057334' seed=52420467782423826582633827050420738122590576455249986579251325553894502665974 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=52420467782423826582633827050420738122590576455249986579251325553894502665974 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/29.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 108746662627693258365510795423877574761094609403194688715644136002489711374358 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/29.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1480634390 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.1480634390' seed=108746662627693258365510795423877574761094609403194688715644136002489711374358 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108746662627693258365510795423877574761094609403194688715644136002489711374358 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/29.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 47629224904172760710177634729568329124224429822921434622744405964591067965180 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/29.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2271094524 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.2271094524' seed=47629224904172760710177634729568329124224429822921434622744405964591067965180 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47629224904172760710177634729568329124224429822921434622744405964591067965180 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/29.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 16802787510406884225233133677218319608791601022520812836055186174317738263404 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/29.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2685600620 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.2685600620' seed=16802787510406884225233133677218319608791601022520812836055186174317738263404 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16802787510406884225233133677218319608791601022520812836055186174317738263404 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/29.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 10635222961090087809668675205137044447875787070249526446672781038700128237542 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/29.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2084173798 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.2084173798' seed=10635222961090087809668675205137044447875787070249526446672781038700128237542 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10635222961090087809668675205137044447875787070249526446672781038700128237542 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/29.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 115001002622114792190483131398422219442266024043414334549399131471772989438204 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/29.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3607279868 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.3607279868' seed=115001002622114792190483131398422219442266024043414334549399131471772989438204 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115001002622114792190483131398422219442266024043414334549399131471772989438204 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/29.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 44782007355641704319635072887998151628748245861454096814664453837880963269676 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/30.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=210666540 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.210666540' seed=44782007355641704319635072887998151628748245861454096814664453837880963269676 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44782007355641704319635072887998151628748245861454096814664453837880963269676 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/30.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 70163750672688878332886759143322253003306519324405795370087734159085549351557 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/30.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=403141253 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.403141253' seed=70163750672688878332886759143322253003306519324405795370087734159085549351557 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70163750672688878332886759143322253003306519324405795370087734159085549351557 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/30.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 20907910973564314584241978483954912787628400993843132865298131326402378459428 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/30.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=476965156 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.476965156' seed=20907910973564314584241978483954912787628400993843132865298131326402378459428 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20907910973564314584241978483954912787628400993843132865298131326402378459428 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/30.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 43779598806538653785260486896991142518653621804334104595173812408020868318890 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/30.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=217892522 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.217892522' seed=43779598806538653785260486896991142518653621804334104595173812408020868318890 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43779598806538653785260486896991142518653621804334104595173812408020868318890 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/30.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 113003724558918703252796889569705149385593771689934857521531399437028172736621 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/30.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1332455533 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1332455533' seed=113003724558918703252796889569705149385593771689934857521531399437028172736621 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113003724558918703252796889569705149385593771689934857521531399437028172736621 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/30.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 89310581891443464761543638778602131383804254227501609145450340827253536552870 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/30.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4030298022 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.4030298022' seed=89310581891443464761543638778602131383804254227501609145450340827253536552870 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89310581891443464761543638778602131383804254227501609145450340827253536552870 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/30.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 34169072873145261687085621019946039970153608545617009670604095110950761902611 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/31.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2316939795 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.2316939795' seed=34169072873145261687085621019946039970153608545617009670604095110950761902611 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34169072873145261687085621019946039970153608545617009670604095110950761902611 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/31.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 62474933870864994805377112791536084695569257284120056907751788811172542929160 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/31.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3447970056 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.3447970056' seed=62474933870864994805377112791536084695569257284120056907751788811172542929160 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62474933870864994805377112791536084695569257284120056907751788811172542929160 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/31.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 24188975077223199875145243296906829035634068927395670513674872216430966681346 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/31.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4042206978 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.4042206978' seed=24188975077223199875145243296906829035634068927395670513674872216430966681346 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24188975077223199875145243296906829035634068927395670513674872216430966681346 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/31.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 10637857136169719435632492264936379757767910711648467137224949000388822556517 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/31.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2845433701 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.2845433701' seed=10637857136169719435632492264936379757767910711648467137224949000388822556517 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10637857136169719435632492264936379757767910711648467137224949000388822556517 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/31.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 96251618582820637723882460722815289180139862053863126479624807712619442964888 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/31.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=966756760 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.966756760' seed=96251618582820637723882460722815289180139862053863126479624807712619442964888 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96251618582820637723882460722815289180139862053863126479624807712619442964888 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/31.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 100965079804391456117976880142065619988960046503685109320438469483769761859613 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/31.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=244287517 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.244287517' seed=100965079804391456117976880142065619988960046503685109320438469483769761859613 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100965079804391456117976880142065619988960046503685109320438469483769761859613 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/31.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 48854662097772801678398113817723894709461528960570841039391374516746588958938 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/32.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=939176154 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.939176154' seed=48854662097772801678398113817723894709461528960570841039391374516746588958938 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48854662097772801678398113817723894709461528960570841039391374516746588958938 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/32.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 114254820041347242202334443806993795798915668844970908359566591545666036452711 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/32.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2449362279 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.2449362279' seed=114254820041347242202334443806993795798915668844970908359566591545666036452711 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114254820041347242202334443806993795798915668844970908359566591545666036452711 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/32.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 103719927042647913298236253638807232155556158827225912130337389555708704380453 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/32.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=91280933 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.91280933' seed=103719927042647913298236253638807232155556158827225912130337389555708704380453 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103719927042647913298236253638807232155556158827225912130337389555708704380453 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/32.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 89610566254749572320976793955203144953849896645832595403030307664093110381463 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/32.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1519692695 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.1519692695' seed=89610566254749572320976793955203144953849896645832595403030307664093110381463 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89610566254749572320976793955203144953849896645832595403030307664093110381463 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/32.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 58677058117571775892632122665872635889971706844641436567071240771416342695908 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/32.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1950912484 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.1950912484' seed=58677058117571775892632122665872635889971706844641436567071240771416342695908 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58677058117571775892632122665872635889971706844641436567071240771416342695908 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/32.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 111014397647787908039369123920829413628839304586209478232704327844400665202052 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/32.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1832914308 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.1832914308' seed=111014397647787908039369123920829413628839304586209478232704327844400665202052 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111014397647787908039369123920829413628839304586209478232704327844400665202052 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/32.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 76225481843511958631510465970121428044537808231340207374132852399120314964648 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/33.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1904908968 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.1904908968' seed=76225481843511958631510465970121428044537808231340207374132852399120314964648 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76225481843511958631510465970121428044537808231340207374132852399120314964648 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/33.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 111171585668521401452690056627152324886578028510575984481198558104850435177197 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/33.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3214179053 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.3214179053' seed=111171585668521401452690056627152324886578028510575984481198558104850435177197 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111171585668521401452690056627152324886578028510575984481198558104850435177197 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/33.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 113652654353456109601921380973115186804500496514702045362095757485914903804062 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/33.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=160430238 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.160430238' seed=113652654353456109601921380973115186804500496514702045362095757485914903804062 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113652654353456109601921380973115186804500496514702045362095757485914903804062 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/33.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 38569668799782168414298050888921964330115408944758321246795822350762355496523 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/33.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3779368523 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3779368523' seed=38569668799782168414298050888921964330115408944758321246795822350762355496523 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38569668799782168414298050888921964330115408944758321246795822350762355496523 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/33.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 88726688715071125044928710440770672134819289768257059213978034770768460285510 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/33.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=550274630 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.550274630' seed=88726688715071125044928710440770672134819289768257059213978034770768460285510 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88726688715071125044928710440770672134819289768257059213978034770768460285510 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/33.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 42290537290245595620589332460164307283134799803298072551237110918488874864454 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/33.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1650249542 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.1650249542' seed=42290537290245595620589332460164307283134799803298072551237110918488874864454 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42290537290245595620589332460164307283134799803298072551237110918488874864454 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/33.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 34697337120673002077897360864318952015831123241539587059959906261379154651356 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/34.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2074552540 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.2074552540' seed=34697337120673002077897360864318952015831123241539587059959906261379154651356 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34697337120673002077897360864318952015831123241539587059959906261379154651356 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/34.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 19483571267922715267599923719188196376521128596589045630404974413948561043695 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/34.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4038766831 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.4038766831' seed=19483571267922715267599923719188196376521128596589045630404974413948561043695 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19483571267922715267599923719188196376521128596589045630404974413948561043695 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/34.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 96412507249812967089984839907202300213223014204224721475729637566742129195640 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/34.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=551205496 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.551205496' seed=96412507249812967089984839907202300213223014204224721475729637566742129195640 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96412507249812967089984839907202300213223014204224721475729637566742129195640 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/34.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 114981040194062903397415623538587049204464487153616382625195438979987183805307 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/34.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3143934843 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.3143934843' seed=114981040194062903397415623538587049204464487153616382625195438979987183805307 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114981040194062903397415623538587049204464487153616382625195438979987183805307 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/34.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 88755944520917492642397299814452568667573792252944306420895825961126443995949 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/34.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=454415149 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.454415149' seed=88755944520917492642397299814452568667573792252944306420895825961126443995949 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88755944520917492642397299814452568667573792252944306420895825961126443995949 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/34.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 107437569093793634101415260950376336682019486340358898757364336982173296169831 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/34.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3527742311 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.3527742311' seed=107437569093793634101415260950376336682019486340358898757364336982173296169831 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107437569093793634101415260950376336682019486340358898757364336982173296169831 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/34.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 101512463160034281677046964185207190619197317022690006305972919530651486463257 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/35.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3560908057 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.3560908057' seed=101512463160034281677046964185207190619197317022690006305972919530651486463257 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101512463160034281677046964185207190619197317022690006305972919530651486463257 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/35.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 56924671221034784666409284171675864995258121908081345241362802866719186744918 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/35.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2820929110 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2820929110' seed=56924671221034784666409284171675864995258121908081345241362802866719186744918 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56924671221034784666409284171675864995258121908081345241362802866719186744918 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/35.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 29114340891342643005885719032112732762102090167016424462586258445532853592035 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/35.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2603507683 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.2603507683' seed=29114340891342643005885719032112732762102090167016424462586258445532853592035 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29114340891342643005885719032112732762102090167016424462586258445532853592035 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/35.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 50062079047813070717212292695099409756278650458955423605207455457179966407275 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/35.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3611853419 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.3611853419' seed=50062079047813070717212292695099409756278650458955423605207455457179966407275 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50062079047813070717212292695099409756278650458955423605207455457179966407275 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/35.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 79590326089927704691992329989601403954711104655134400599503057775598240947930 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/35.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1202872026 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.1202872026' seed=79590326089927704691992329989601403954711104655134400599503057775598240947930 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79590326089927704691992329989601403954711104655134400599503057775598240947930 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/35.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 92759980708913453395349818917717353866768199184994627075611243561756229904617 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/35.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1484794089 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.1484794089' seed=92759980708913453395349818917717353866768199184994627075611243561756229904617 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92759980708913453395349818917717353866768199184994627075611243561756229904617 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/35.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 38727456243108637288617889333989721941301866013048876028163360192066495218111 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/36.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1216905663 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.1216905663' seed=38727456243108637288617889333989721941301866013048876028163360192066495218111 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38727456243108637288617889333989721941301866013048876028163360192066495218111 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/36.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 57243259048457086060821296153082964706321921719587619045784985183086104694078 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/36.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3579727166 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.3579727166' seed=57243259048457086060821296153082964706321921719587619045784985183086104694078 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57243259048457086060821296153082964706321921719587619045784985183086104694078 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/36.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 18785894944516430500447269542039342881301657786164808846518024932805886547695 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/36.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4013364975 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.4013364975' seed=18785894944516430500447269542039342881301657786164808846518024932805886547695 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18785894944516430500447269542039342881301657786164808846518024932805886547695 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/36.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 1119817104543561056973490448262284079642526018310332269575258731821367174848 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/36.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2758420160 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.2758420160' seed=1119817104543561056973490448262284079642526018310332269575258731821367174848 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1119817104543561056973490448262284079642526018310332269575258731821367174848 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/36.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 49508300656808206897053496412036823392727121496053986591349283197862519836748 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/36.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3847819340 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3847819340' seed=49508300656808206897053496412036823392727121496053986591349283197862519836748 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49508300656808206897053496412036823392727121496053986591349283197862519836748 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/36.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 12926705528857383145604284036503078013161329561703313031601206396384854477988 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/36.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1112607908 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.1112607908' seed=12926705528857383145604284036503078013161329561703313031601206396384854477988 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12926705528857383145604284036503078013161329561703313031601206396384854477988 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/36.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 43767215989977022581367298921979822959153500552271461075462095377261385987618 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/37.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4243043874 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.4243043874' seed=43767215989977022581367298921979822959153500552271461075462095377261385987618 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43767215989977022581367298921979822959153500552271461075462095377261385987618 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/37.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 98276497825916475651508511133570892384326833232795723259177815570171368652509 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/37.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=349781725 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.349781725' seed=98276497825916475651508511133570892384326833232795723259177815570171368652509 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98276497825916475651508511133570892384326833232795723259177815570171368652509 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/37.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 114769941077859023324649094207468102182889825771343502498975395012864340185734 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/37.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1540412038 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1540412038' seed=114769941077859023324649094207468102182889825771343502498975395012864340185734 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114769941077859023324649094207468102182889825771343502498975395012864340185734 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/37.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 83240959748089141318830693274766572021831863198696950442125053996658105873472 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/37.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2072605760 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2072605760' seed=83240959748089141318830693274766572021831863198696950442125053996658105873472 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83240959748089141318830693274766572021831863198696950442125053996658105873472 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/37.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 106454967524175086828757077439373339349802523701551440974646413849047686985088 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/37.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3776722304 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.3776722304' seed=106454967524175086828757077439373339349802523701551440974646413849047686985088 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106454967524175086828757077439373339349802523701551440974646413849047686985088 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/37.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 82027147161423352412020114885458856044906780390192764880688226363190730898849 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/37.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2222800289 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.2222800289' seed=82027147161423352412020114885458856044906780390192764880688226363190730898849 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82027147161423352412020114885458856044906780390192764880688226363190730898849 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/37.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 93531306161892452123779496055670336411574000721704367101146860793926742380398 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/38.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1601376110 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.1601376110' seed=93531306161892452123779496055670336411574000721704367101146860793926742380398 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93531306161892452123779496055670336411574000721704367101146860793926742380398 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/38.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 8798860715205748777429974747929716913188244996875110339196564340702304691479 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/38.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=295331095 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.295331095' seed=8798860715205748777429974747929716913188244996875110339196564340702304691479 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8798860715205748777429974747929716913188244996875110339196564340702304691479 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/38.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 114467162425839429901920158758507706447683970329961874526912933726937368229133 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/38.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1712059661 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.1712059661' seed=114467162425839429901920158758507706447683970329961874526912933726937368229133 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114467162425839429901920158758507706447683970329961874526912933726937368229133 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/38.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 8577018511449967481960428528199189332905110523881111447814512677640554120190 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/38.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4191912958 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.4191912958' seed=8577018511449967481960428528199189332905110523881111447814512677640554120190 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8577018511449967481960428528199189332905110523881111447814512677640554120190 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/38.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 34402246100716900605305138180879367583172890461119358432412659291423046308239 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/38.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3004371343 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.3004371343' seed=34402246100716900605305138180879367583172890461119358432412659291423046308239 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34402246100716900605305138180879367583172890461119358432412659291423046308239 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/38.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 113259181003171119518087764008668629442411145384606695745332688191593463673498 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/38.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3860853402 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.3860853402' seed=113259181003171119518087764008668629442411145384606695745332688191593463673498 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113259181003171119518087764008668629442411145384606695745332688191593463673498 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/38.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 15877515442406822975279214376044532181848723740685800874173106039747405966440 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/39.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3104337000 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.3104337000' seed=15877515442406822975279214376044532181848723740685800874173106039747405966440 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15877515442406822975279214376044532181848723740685800874173106039747405966440 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/39.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 90483815935102156800783951611427422926377664905530858483537124289074968495189 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/39.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2778301525 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.2778301525' seed=90483815935102156800783951611427422926377664905530858483537124289074968495189 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90483815935102156800783951611427422926377664905530858483537124289074968495189 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/39.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 38748285958697452383182504690251568363135329795961471505632860137292348707393 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/39.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2952974913 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.2952974913' seed=38748285958697452383182504690251568363135329795961471505632860137292348707393 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38748285958697452383182504690251568363135329795961471505632860137292348707393 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/39.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 88269226923659919863716447789402614737556079085064183522224241603479673387604 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/39.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1865300564 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1865300564' seed=88269226923659919863716447789402614737556079085064183522224241603479673387604 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88269226923659919863716447789402614737556079085064183522224241603479673387604 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/39.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 92300667139492800128211572049969612654887210306595938210695390935712629975136 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/39.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1259268192 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.1259268192' seed=92300667139492800128211572049969612654887210306595938210695390935712629975136 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92300667139492800128211572049969612654887210306595938210695390935712629975136 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/39.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 100547888330732245347618507645196719620403929553977002987254316795639512087607 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/39.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4187667511 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.4187667511' seed=100547888330732245347618507645196719620403929553977002987254316795639512087607 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100547888330732245347618507645196719620403929553977002987254316795639512087607 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/39.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 66613808057454079891463111581125314454617437923113095249676497933525225033622 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/40.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2709245846 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.2709245846' seed=66613808057454079891463111581125314454617437923113095249676497933525225033622 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66613808057454079891463111581125314454617437923113095249676497933525225033622 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/40.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 18552068870804828520161990122969142455711117805805018375143699377949861258728 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/40.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4034176488 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.4034176488' seed=18552068870804828520161990122969142455711117805805018375143699377949861258728 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18552068870804828520161990122969142455711117805805018375143699377949861258728 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/40.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 110519148143323895162616074886811523282300731437397690697728210885162762663956 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/40.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1323202580 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.1323202580' seed=110519148143323895162616074886811523282300731437397690697728210885162762663956 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110519148143323895162616074886811523282300731437397690697728210885162762663956 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/40.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 55844988976373758963115255464867477717774093646611840288364097024064478779422 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/40.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1478236190 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.1478236190' seed=55844988976373758963115255464867477717774093646611840288364097024064478779422 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55844988976373758963115255464867477717774093646611840288364097024064478779422 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/40.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 44474854880551257578808545849843765154940712561592042648526878603187107551524 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/40.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=814373156 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.814373156' seed=44474854880551257578808545849843765154940712561592042648526878603187107551524 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44474854880551257578808545849843765154940712561592042648526878603187107551524 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/40.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 25429676023156519256255342516391892486747732222610652094989313868054991292524 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/40.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=204294252 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.204294252' seed=25429676023156519256255342516391892486747732222610652094989313868054991292524 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25429676023156519256255342516391892486747732222610652094989313868054991292524 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/40.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 60865729038421158231692241652272500768590598915477933451251732168617606435701 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/41.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2685064053 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.2685064053' seed=60865729038421158231692241652272500768590598915477933451251732168617606435701 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60865729038421158231692241652272500768590598915477933451251732168617606435701 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/41.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 21833615287850302852168522210879298225191663532852453636577713077078232190493 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/41.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2086981149 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.2086981149' seed=21833615287850302852168522210879298225191663532852453636577713077078232190493 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21833615287850302852168522210879298225191663532852453636577713077078232190493 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/41.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 20291103019128495750052411410604101810112816318507935118609044481497014485474 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/41.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1715749346 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.1715749346' seed=20291103019128495750052411410604101810112816318507935118609044481497014485474 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20291103019128495750052411410604101810112816318507935118609044481497014485474 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/41.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 110108668965617219145214236524551230051896401371408108907204479830691412555276 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/41.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1250539020 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.1250539020' seed=110108668965617219145214236524551230051896401371408108907204479830691412555276 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110108668965617219145214236524551230051896401371408108907204479830691412555276 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/41.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 86045397146841076322511499475045028182254657420748087826593899115437637502006 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/41.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3059221558 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.3059221558' seed=86045397146841076322511499475045028182254657420748087826593899115437637502006 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86045397146841076322511499475045028182254657420748087826593899115437637502006 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/41.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 93173285169828749305848732484488787628096688391256448535702377677683222754653 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/41.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3635262813 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.3635262813' seed=93173285169828749305848732484488787628096688391256448535702377677683222754653 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93173285169828749305848732484488787628096688391256448535702377677683222754653 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/41.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 109992960277757831852133778376920409593420923692311756528405378383316095097240 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/42.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1341938072 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.1341938072' seed=109992960277757831852133778376920409593420923692311756528405378383316095097240 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109992960277757831852133778376920409593420923692311756528405378383316095097240 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/42.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 36343384315574632079738394095145402219740392621923481082460620513899960555202 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/42.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=155670210 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.155670210' seed=36343384315574632079738394095145402219740392621923481082460620513899960555202 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36343384315574632079738394095145402219740392621923481082460620513899960555202 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/42.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 108448932940421472380853360748239837763765931351407303393063794019137470835087 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/42.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4127959439 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.4127959439' seed=108448932940421472380853360748239837763765931351407303393063794019137470835087 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108448932940421472380853360748239837763765931351407303393063794019137470835087 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/42.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 13997968911225926808560427590033894996987782965620197530489140406747890317069 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/42.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=643168013 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.643168013' seed=13997968911225926808560427590033894996987782965620197530489140406747890317069 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13997968911225926808560427590033894996987782965620197530489140406747890317069 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/42.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 64332540095935243437498620543012943701585919312613440814140685670980002592519 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/42.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1195980551 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.1195980551' seed=64332540095935243437498620543012943701585919312613440814140685670980002592519 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64332540095935243437498620543012943701585919312613440814140685670980002592519 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/42.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 21903138492555512757393097589329816160656689356493576971687579456024766686210 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/42.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3714688002 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.3714688002' seed=21903138492555512757393097589329816160656689356493576971687579456024766686210 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21903138492555512757393097589329816160656689356493576971687579456024766686210 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/42.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 70619273036533640357352434265983469758958035993281264534147320768384833932418 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/43.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4049587330 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.4049587330' seed=70619273036533640357352434265983469758958035993281264534147320768384833932418 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70619273036533640357352434265983469758958035993281264534147320768384833932418 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/43.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 51960966356005485916768538438935415999532608624857605948959956832895938896152 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/43.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2767495448 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.2767495448' seed=51960966356005485916768538438935415999532608624857605948959956832895938896152 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51960966356005485916768538438935415999532608624857605948959956832895938896152 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/43.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 100527740629276151238308471842266916542815618230972790338144695624030707892246 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/43.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=487702550 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.487702550' seed=100527740629276151238308471842266916542815618230972790338144695624030707892246 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100527740629276151238308471842266916542815618230972790338144695624030707892246 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/43.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 26155847942135165074099749407529450900791414981276060191336290283538365887987 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/43.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4245763571 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.4245763571' seed=26155847942135165074099749407529450900791414981276060191336290283538365887987 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26155847942135165074099749407529450900791414981276060191336290283538365887987 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/43.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 73172906935495276149091361188054180556484822224590463514468587151339704051704 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/43.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=931424248 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.931424248' seed=73172906935495276149091361188054180556484822224590463514468587151339704051704 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73172906935495276149091361188054180556484822224590463514468587151339704051704 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/43.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 35384158108674812788315417579308795661972416371208533972505314819310928670087 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/43.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3172609415 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.3172609415' seed=35384158108674812788315417579308795661972416371208533972505314819310928670087 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35384158108674812788315417579308795661972416371208533972505314819310928670087 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/43.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 82100055816699357072554964320290338660496679563419508367006811630324183002356 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/44.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3516198132 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.3516198132' seed=82100055816699357072554964320290338660496679563419508367006811630324183002356 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82100055816699357072554964320290338660496679563419508367006811630324183002356 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/44.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 94750401271029953222542830519156750516714123774409775352622663036036046061820 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/44.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1774649596 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.1774649596' seed=94750401271029953222542830519156750516714123774409775352622663036036046061820 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94750401271029953222542830519156750516714123774409775352622663036036046061820 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/44.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 10286939426597254984911252226450080282930942564358598581203812536121730742600 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/44.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3126540616 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.3126540616' seed=10286939426597254984911252226450080282930942564358598581203812536121730742600 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10286939426597254984911252226450080282930942564358598581203812536121730742600 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/44.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 67527612073679660590510290446180860449759918454823795797477885302868459427774 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/44.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=27039678 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.27039678' seed=67527612073679660590510290446180860449759918454823795797477885302868459427774 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67527612073679660590510290446180860449759918454823795797477885302868459427774 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/44.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 6488386716382170934507124344749000745029057240811602556238692923472775966097 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/44.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3754913169 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.3754913169' seed=6488386716382170934507124344749000745029057240811602556238692923472775966097 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6488386716382170934507124344749000745029057240811602556238692923472775966097 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/44.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 85840725895514921943916177610764112739739722684626223354146353532814507813851 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/44.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2692131803 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.2692131803' seed=85840725895514921943916177610764112739739722684626223354146353532814507813851 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85840725895514921943916177610764112739739722684626223354146353532814507813851 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/44.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 36298968868600966242349125323360055928323484946404812146233245559339135921442 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/45.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2579361058 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.2579361058' seed=36298968868600966242349125323360055928323484946404812146233245559339135921442 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36298968868600966242349125323360055928323484946404812146233245559339135921442 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/45.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 63555603623378524604931284134544334300529323050599922740092379847996794749290 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/45.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1980252522 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.1980252522' seed=63555603623378524604931284134544334300529323050599922740092379847996794749290 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63555603623378524604931284134544334300529323050599922740092379847996794749290 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/45.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 79646598509267780037832577151405354202099660725851299238010937274900900806430 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/45.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2059206430 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.2059206430' seed=79646598509267780037832577151405354202099660725851299238010937274900900806430 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79646598509267780037832577151405354202099660725851299238010937274900900806430 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/45.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 111268720458249313215081633282603129173218963122420162927025795862585466320888 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/45.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2296543224 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.2296543224' seed=111268720458249313215081633282603129173218963122420162927025795862585466320888 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111268720458249313215081633282603129173218963122420162927025795862585466320888 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/45.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 63668598731504002311682600515175225168413907297027665242951328642116773459114 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/45.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3443504298 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3443504298' seed=63668598731504002311682600515175225168413907297027665242951328642116773459114 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63668598731504002311682600515175225168413907297027665242951328642116773459114 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/45.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 40097243959217976222000701946873663277800672804162210770428584760237386193536 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/45.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3466418816 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.3466418816' seed=40097243959217976222000701946873663277800672804162210770428584760237386193536 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40097243959217976222000701946873663277800672804162210770428584760237386193536 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/45.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 32921415632802214039573959931670889768522083903241539053539117682736280516486 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/46.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3856545670 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.3856545670' seed=32921415632802214039573959931670889768522083903241539053539117682736280516486 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32921415632802214039573959931670889768522083903241539053539117682736280516486 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/46.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 103067808063896134842213606635932110056773386369239820690002209908935752364864 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/46.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2226860864 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.2226860864' seed=103067808063896134842213606635932110056773386369239820690002209908935752364864 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103067808063896134842213606635932110056773386369239820690002209908935752364864 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/46.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 39184628012513468818270367034922842551591968566945244423359648480818708718085 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/46.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1583718917 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.1583718917' seed=39184628012513468818270367034922842551591968566945244423359648480818708718085 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39184628012513468818270367034922842551591968566945244423359648480818708718085 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/46.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 63560920046380444183348708740905753816228251627602250017061949605004362044249 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/46.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2539836249 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.2539836249' seed=63560920046380444183348708740905753816228251627602250017061949605004362044249 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63560920046380444183348708740905753816228251627602250017061949605004362044249 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/46.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 48292798228577295452809431988254356512831621243375022164057382661978717178087 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/46.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=541083879 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.541083879' seed=48292798228577295452809431988254356512831621243375022164057382661978717178087 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48292798228577295452809431988254356512831621243375022164057382661978717178087 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/46.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 75546302738589537948651002154991887963419512620534500667976239716813135541625 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/46.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2176972153 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.2176972153' seed=75546302738589537948651002154991887963419512620534500667976239716813135541625 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75546302738589537948651002154991887963419512620534500667976239716813135541625 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/46.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 8469826820179797003556407369755280458820199397387737130022107181458884042155 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/47.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4163018155 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.4163018155' seed=8469826820179797003556407369755280458820199397387737130022107181458884042155 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8469826820179797003556407369755280458820199397387737130022107181458884042155 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/47.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 113096431062032573959559288469023479612953935826790402344781238113977424965453 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/47.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3045879629 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.3045879629' seed=113096431062032573959559288469023479612953935826790402344781238113977424965453 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113096431062032573959559288469023479612953935826790402344781238113977424965453 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/47.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 77205900798046936307792133667280513250052375105358266154761127480364748551131 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/47.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3744510939 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.3744510939' seed=77205900798046936307792133667280513250052375105358266154761127480364748551131 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77205900798046936307792133667280513250052375105358266154761127480364748551131 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/47.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 34157446475201071409707925852650025740051478751862302850200399685581877998398 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/47.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=487519038 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.487519038' seed=34157446475201071409707925852650025740051478751862302850200399685581877998398 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34157446475201071409707925852650025740051478751862302850200399685581877998398 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/47.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 34876781020838830092136077482042905138320039797190403736609922195477422822345 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/47.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3106296777 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.3106296777' seed=34876781020838830092136077482042905138320039797190403736609922195477422822345 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34876781020838830092136077482042905138320039797190403736609922195477422822345 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/47.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 2145842844399673864757722906510137137163858541913933879419759369132721691714 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/47.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3193035842 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3193035842' seed=2145842844399673864757722906510137137163858541913933879419759369132721691714 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2145842844399673864757722906510137137163858541913933879419759369132721691714 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/47.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 98155364281971510675806067378633122565603432232964536243324822230047743689412 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/48.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=601506500 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.601506500' seed=98155364281971510675806067378633122565603432232964536243324822230047743689412 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98155364281971510675806067378633122565603432232964536243324822230047743689412 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/48.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 53170521555452371819813507425612443378423787129869871755451061762303751986858 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/48.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4122058410 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.4122058410' seed=53170521555452371819813507425612443378423787129869871755451061762303751986858 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53170521555452371819813507425612443378423787129869871755451061762303751986858 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/48.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 16092245700800273190159081623450000931284364542421522560412812332510718917066 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/48.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=165083594 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.165083594' seed=16092245700800273190159081623450000931284364542421522560412812332510718917066 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16092245700800273190159081623450000931284364542421522560412812332510718917066 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/48.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 114954434914992532325505843163354348134246287479693422689094741449330451937804 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/48.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2850159116 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.2850159116' seed=114954434914992532325505843163354348134246287479693422689094741449330451937804 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114954434914992532325505843163354348134246287479693422689094741449330451937804 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/48.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 38190186771007384736067687141626567050801137126742067362164651493257282135055 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/48.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2334991375 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.2334991375' seed=38190186771007384736067687141626567050801137126742067362164651493257282135055 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38190186771007384736067687141626567050801137126742067362164651493257282135055 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/48.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 80128015996898591501342486024888146576799719910156220433135337765403755800930 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/48.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1789127010 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.1789127010' seed=80128015996898591501342486024888146576799719910156220433135337765403755800930 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80128015996898591501342486024888146576799719910156220433135337765403755800930 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/48.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_random_classes | 7563781613259875110901480766529362184561735821295998330364180149400749248883 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/49.alert_handler_random_classes/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=681087347 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.681087347' seed=7563781613259875110901480766529362184561735821295998330364180149400749248883 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7563781613259875110901480766529362184561735821295998330364180149400749248883 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/49.alert_handler_random_classes/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_random_classes_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_esc_intr_timeout | 110720384903898587659422029011305828689196537699038940394527545392653156521951 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/49.alert_handler_esc_intr_timeout/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=261920735 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.261920735' seed=110720384903898587659422029011305828689196537699038940394527545392653156521951 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110720384903898587659422029011305828689196537699038940394527545392653156521951 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/49.alert_handler_esc_intr_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_esc_intr_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_sig_int_fail | 46157967118335920187514299651315631117532833686477318330644987435969791704796 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/49.alert_handler_sig_int_fail/latest run_opts='+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1102102236 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.1102102236' seed=46157967118335920187514299651315631117532833686477318330644987435969791704796 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46157967118335920187514299651315631117532833686477318330644987435969791704796 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/49.alert_handler_sig_int_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_sig_int_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_ping_timeout | 104808317722459022032437171712704430801834146634546397576491676348588302375487 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/49.alert_handler_ping_timeout/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=400923199 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.400923199' seed=104808317722459022032437171712704430801834146634546397576491676348588302375487 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104808317722459022032437171712704430801834146634546397576491676348588302375487 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/49.alert_handler_ping_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_ping_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg | 48891272159070342469032893620997351631403379185620444365640953261583848415503 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/49.alert_handler_lpg/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1668260111 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.1668260111' seed=48891272159070342469032893620997351631403379185620444365640953261583848415503 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48891272159070342469032893620997351631403379185620444365640953261583848415503 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/49.alert_handler_lpg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| alert_handler_lpg_stub_clk | 34585085351742379606997015153929779566474939839744100996356572336269741115596 | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/alert_handler-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/49.alert_handler_lpg_stub_clk/latest run_opts='+test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3817720012 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.3817720012' seed=34585085351742379606997015153929779566474939839744100996356572336269741115596 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34585085351742379606997015153929779566474939839744100996356572336269741115596 --run-dir=/nightly/current_run/scratch/master/alert_handler-sim-vcs/49.alert_handler_lpg_stub_clk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=alert_handler_base_test uvm_test_seq=alert_handler_lpg_stub_clk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
|
|
| Error-[FCULIBNF] Ucapi library not found | 25 test runs | |||
| alert_handler_stress_all | 102534669354381439154121257977840901177585902786157039331437668608448597661800 | 543 |
Unable to locate ucapi library at
/nas/lowrisc/tools/synopsys/vcs/U-2023.03-SP2/linux64/lib/libucapi.so.
|
|
| alert_handler_stress_all | 70798461548484965923036492183683318844462537098394639074784509963867968650694 | 376 |
Unable to locate ucapi library at
/nas/lowrisc/tools/synopsys/vcs/U-2023.03-SP2/linux64/lib/libucapi.so.
|
|
| alert_handler_stress_all | 81451102459309871197047977738071109545301536876768948088982336371520179527419 | 213 |
Unable to locate ucapi library at
/nas/lowrisc/tools/synopsys/vcs/U-2023.03-SP2/linux64/lib/libucapi.so.
|
|
| alert_handler_stress_all | 33320835839705070926964418387270259337170233845244076256493693368647401132930 | 221 |
Unable to locate ucapi library at
/nas/lowrisc/tools/synopsys/vcs/U-2023.03-SP2/linux64/lib/libucapi.so.
|
|
| alert_handler_stress_all | 101143983803828396465151159534147622784277492997099043714940099508232655715934 | 191 |
Unable to locate ucapi library at
/nas/lowrisc/tools/synopsys/vcs/U-2023.03-SP2/linux64/lib/libucapi.so.
|
|
| alert_handler_stress_all | 49511323095103932049396840764846966933383234945984076966518020885345277034372 | 477 |
Unable to locate ucapi library at
/nas/lowrisc/tools/synopsys/vcs/U-2023.03-SP2/linux64/lib/libucapi.so.
|
|
| alert_handler_stress_all | 16459425823695986390700391010303145035668086665682460469093891494417430551981 | 351 |
Unable to locate ucapi library at
/nas/lowrisc/tools/synopsys/vcs/U-2023.03-SP2/linux64/lib/libucapi.so.
|
|
| alert_handler_stress_all | 14163248883268219952022561450703935151216954861577005669757223140708105698815 | 330 |
Unable to locate ucapi library at
/nas/lowrisc/tools/synopsys/vcs/U-2023.03-SP2/linux64/lib/libucapi.so.
|
|
| alert_handler_stress_all | 33858010101024664772186966422024503512979626455717048366523851897210597170701 | 352 |
Unable to locate ucapi library at
/nas/lowrisc/tools/synopsys/vcs/U-2023.03-SP2/linux64/lib/libucapi.so.
|
|
| alert_handler_stress_all | 23150039623082358927132674682779711963057987745551843102032988840017538335944 | 171 |
Unable to locate ucapi library at
/nas/lowrisc/tools/synopsys/vcs/U-2023.03-SP2/linux64/lib/libucapi.so.
|
|
| alert_handler_stress_all | 49342001769720517457278504833223030218392432704722415014900149895512528350556 | 306 |
Unable to locate ucapi library at
/nas/lowrisc/tools/synopsys/vcs/U-2023.03-SP2/linux64/lib/libucapi.so.
|
|
| alert_handler_stress_all | 7462601877882183390913024825032366636548151002974987206385302291890266611242 | 455 |
Unable to locate ucapi library at
/nas/lowrisc/tools/synopsys/vcs/U-2023.03-SP2/linux64/lib/libucapi.so.
|
|
| alert_handler_stress_all | 87773052491929050167323849015907458247175085520265480298697658655225376043310 | 442 |
Unable to locate ucapi library at
/nas/lowrisc/tools/synopsys/vcs/U-2023.03-SP2/linux64/lib/libucapi.so.
|
|
| alert_handler_stress_all | 10510047428073510147150095074377701178332314220196900966410685599953841251459 | 397 |
Unable to locate ucapi library at
/nas/lowrisc/tools/synopsys/vcs/U-2023.03-SP2/linux64/lib/libucapi.so.
|
|
| alert_handler_stress_all | 106937952702939900233286015061891473978727602407590176250499163636728617267730 | 264 |
Unable to locate ucapi library at
/nas/lowrisc/tools/synopsys/vcs/U-2023.03-SP2/linux64/lib/libucapi.so.
|
|
| alert_handler_stress_all | 40264983464279995099687034708577674591945373301654549040927086105951296108968 | 309 |
Unable to locate ucapi library at
/nas/lowrisc/tools/synopsys/vcs/U-2023.03-SP2/linux64/lib/libucapi.so.
|
|
| alert_handler_stress_all | 34635337844159012727269730103842211014940356866508499381578237674514355770893 | 463 |
Unable to locate ucapi library at
/nas/lowrisc/tools/synopsys/vcs/U-2023.03-SP2/linux64/lib/libucapi.so.
|
|
| alert_handler_stress_all | 108745645420069145195136494785419310075253131026823541698071528064562885991261 | 551 |
Unable to locate ucapi library at
/nas/lowrisc/tools/synopsys/vcs/U-2023.03-SP2/linux64/lib/libucapi.so.
|
|
| alert_handler_stress_all | 105384211335706516429774264747388063645102462681460713333705689991321216664847 | 252 |
Unable to locate ucapi library at
/nas/lowrisc/tools/synopsys/vcs/U-2023.03-SP2/linux64/lib/libucapi.so.
|
|
| alert_handler_stress_all | 23824993388380624508031706729589521369277067980937254228409624229883936121902 | 387 |
Unable to locate ucapi library at
/nas/lowrisc/tools/synopsys/vcs/U-2023.03-SP2/linux64/lib/libucapi.so.
|
|
| alert_handler_stress_all | 92677966036796694835527023431359586071943354521498316922602418296203158555626 | 228 |
Unable to locate ucapi library at
/nas/lowrisc/tools/synopsys/vcs/U-2023.03-SP2/linux64/lib/libucapi.so.
|
|
| alert_handler_stress_all | 4018758278949485593839889043238225366693229718803203144229533347643619980344 | 205 |
Unable to locate ucapi library at
/nas/lowrisc/tools/synopsys/vcs/U-2023.03-SP2/linux64/lib/libucapi.so.
|
|
| alert_handler_stress_all | 17624042903265367246044941496031583212360562737148317461589470635033790835745 | 229 |
Unable to locate ucapi library at
/nas/lowrisc/tools/synopsys/vcs/U-2023.03-SP2/linux64/lib/libucapi.so.
|
|
| alert_handler_stress_all | 44909945322697077811238371723737333177856358303555766402848055703936215340887 | 450 |
Unable to locate ucapi library at
/nas/lowrisc/tools/synopsys/vcs/U-2023.03-SP2/linux64/lib/libucapi.so.
|
|
| alert_handler_stress_all | 109067928746976638433983396969903159974254223872510646188170588251254325394157 | 328 |
Unable to locate ucapi library at
/nas/lowrisc/tools/synopsys/vcs/U-2023.03-SP2/linux64/lib/libucapi.so.
|
|
| UVM_ERROR (alert_handler_scoreboard.sv:258) scoreboard [scoreboard] Unexpected interrupt value in cfg.intr_vif.pins[*]: saw *, but expected *. (is_int_err = *, local_alert_type = LocalEscIntFail) | 1 test run | |||
| alert_handler_stress_all | 4342149333731327154820203412220328754675803545287632687820262769016758851110 | 119 |
UVM_INFO @ 2250634801 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| Job returned a non-zero exit code: * | 1 test run | |||
| alert_handler | None | None |
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk cov_merge cov_merge_cmd=urg cov_merge_opts='-lca -full64 -noreport +urg+lic+wait -merge_across_libs -show tests -flex_merge union -dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/default.vdb -dir /nightly/current_run/scratch/master/alert_handler-sim-vcs/coverage/cover_reg_top.vdb -dbname /nightly/current_run/scratch/master/alert_handler-sim-vcs/cov_merge/merged.vdb'
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:109: cov_merge] Error 126
|
|
| Job cancelled because one of its dependencies failed or was killed. | 1 test run | |||
| alert_handler | None | None | ||