Simulation Results: clkmgr

 
28/08/2026 21:54:34 DVSim: v1.49.0 sha: a099412 json Branch: master Tool: vcs [unknown]
Validation stages
V1
0.00%
V2
0.00%
V2S
0.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 0 10 0.00
clkmgr_smoke 1.383s 0.000us 0 10 0.00
csr_hw_reset 0 1 0.00
clkmgr_csr_hw_reset 0.835s 0.000us 0 1 0.00
csr_rw 0 5 0.00
clkmgr_csr_rw 0.883s 0.000us 0 5 0.00
csr_bit_bash 0 1 0.00
clkmgr_csr_bit_bash 0.839s 0.000us 0 1 0.00
csr_aliasing 0 1 0.00
clkmgr_csr_aliasing 0.856s 0.000us 0 1 0.00
csr_mem_rw_with_rand_reset 0 5 0.00
clkmgr_csr_mem_rw_with_rand_reset 1.336s 0.000us 0 5 0.00
regwen_csr_and_corresponding_lockable_csr 0 6 0.00
clkmgr_csr_rw 0.883s 0.000us 0 5 0.00
clkmgr_csr_aliasing 0.856s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 0 10 0.00
clkmgr_peri 1.314s 0.000us 0 10 0.00
trans_enables 0 10 0.00
clkmgr_trans 1.357s 0.000us 0 10 0.00
clk_status 0 10 0.00
clkmgr_clk_status 1.412s 0.000us 0 10 0.00
jitter 0 10 0.00
clkmgr_smoke 1.383s 0.000us 0 10 0.00
frequency 0 10 0.00
clkmgr_frequency 1.434s 0.000us 0 10 0.00
frequency_timeout 0 10 0.00
clkmgr_frequency_timeout 1.332s 0.000us 0 10 0.00
frequency_overflow 0 10 0.00
clkmgr_frequency 1.434s 0.000us 0 10 0.00
stress_all 0 10 0.00
clkmgr_stress_all 2.560s 204.495us 0 10 0.00
alert_test 0 10 0.00
clkmgr_alert_test 1.917s 0.000us 0 10 0.00
tl_d_oob_addr_access 0 25 0.00
clkmgr_tl_errors 1.386s 0.000us 0 25 0.00
tl_d_illegal_access 0 25 0.00
clkmgr_tl_errors 1.386s 0.000us 0 25 0.00
tl_d_outstanding_access 0 12 0.00
clkmgr_csr_hw_reset 0.835s 0.000us 0 1 0.00
clkmgr_csr_rw 0.883s 0.000us 0 5 0.00
clkmgr_csr_aliasing 0.856s 0.000us 0 1 0.00
clkmgr_same_csr_outstanding 1.881s 0.000us 0 5 0.00
tl_d_partial_access 0 12 0.00
clkmgr_csr_hw_reset 0.835s 0.000us 0 1 0.00
clkmgr_csr_rw 0.883s 0.000us 0 5 0.00
clkmgr_csr_aliasing 0.856s 0.000us 0 1 0.00
clkmgr_same_csr_outstanding 1.881s 0.000us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 30 0.00
clkmgr_sec_cm 1.378s 0.000us 0 5 0.00
clkmgr_tl_intg_err 1.437s 0.000us 0 25 0.00
shadow_reg_update_error 0 20 0.00
clkmgr_shadow_reg_errors 1.387s 0.000us 0 20 0.00
shadow_reg_read_clear_staged_value 0 20 0.00
clkmgr_shadow_reg_errors 1.387s 0.000us 0 20 0.00
shadow_reg_storage_error 0 20 0.00
clkmgr_shadow_reg_errors 1.387s 0.000us 0 20 0.00
shadowed_reset_glitch 0 20 0.00
clkmgr_shadow_reg_errors 1.387s 0.000us 0 20 0.00
shadow_reg_update_error_with_csr_rw 0 20 0.00
clkmgr_shadow_reg_errors_with_csr_rw 1.850s 0.000us 0 20 0.00
sec_cm_bus_integrity 0 25 0.00
clkmgr_tl_intg_err 1.437s 0.000us 0 25 0.00
sec_cm_meas_clk_bkgn_chk 0 10 0.00
clkmgr_frequency 1.434s 0.000us 0 10 0.00
sec_cm_timeout_clk_bkgn_chk 0 10 0.00
clkmgr_frequency_timeout 1.332s 0.000us 0 10 0.00
sec_cm_meas_config_shadow 0 20 0.00
clkmgr_shadow_reg_errors 1.387s 0.000us 0 20 0.00
sec_cm_idle_intersig_mubi 0 10 0.00
clkmgr_idle_intersig_mubi 1.424s 0.000us 0 10 0.00
sec_cm_jitter_config_mubi 0 5 0.00
clkmgr_csr_rw 0.883s 0.000us 0 5 0.00
sec_cm_idle_ctr_redun 0 5 0.00
clkmgr_sec_cm 1.378s 0.000us 0 5 0.00
sec_cm_meas_config_regwen 0 5 0.00
clkmgr_csr_rw 0.883s 0.000us 0 5 0.00
sec_cm_clk_ctrl_config_regwen 0 5 0.00
clkmgr_csr_rw 0.883s 0.000us 0 5 0.00
prim_count_check 0 5 0.00
clkmgr_sec_cm 1.378s 0.000us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 0 10 0.00
clkmgr_regwen 1.335s 0.000us 0 10 0.00
stress_all_with_rand_reset 0 10 0.00
clkmgr_stress_all_with_rand_reset 0.862s 0.000us 0 10 0.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 213 test runs
clkmgr_smoke 111609025765358032508693175303148996675622767320064172789691607550854829379676 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_smoke/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3072528476 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_smoke.3072528476' seed=111609025765358032508693175303148996675622767320064172789691607550854829379676 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111609025765358032508693175303148996675622767320064172789691607550854829379676 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_frequency 59793381854709461474098635919588968127349264331905086657450488587602071960860 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_frequency/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1938865436 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency.1938865436' seed=59793381854709461474098635919588968127349264331905086657450488587602071960860 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=59793381854709461474098635919588968127349264331905086657450488587602071960860 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_frequency/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_frequency_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_frequency_timeout 86649515299266753558367264932047260464281144430123876956939632596827152081194 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_frequency_timeout/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2914804010 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_frequency_timeout.2914804010' seed=86649515299266753558367264932047260464281144430123876956939632596827152081194 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86649515299266753558367264932047260464281144430123876956939632596827152081194 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_frequency_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_frequency_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_peri 86408603260557450465007885310039989793781710236043893146181230355035134865439 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_peri/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4284723231 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_peri.4284723231' seed=86408603260557450465007885310039989793781710236043893146181230355035134865439 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86408603260557450465007885310039989793781710236043893146181230355035134865439 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_peri/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_peri_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_trans 100217950159714402079175778290950130849889802446559398286499321260575766936832 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_trans/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=127466752 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_trans.127466752' seed=100217950159714402079175778290950130849889802446559398286499321260575766936832 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100217950159714402079175778290950130849889802446559398286499321260575766936832 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_clk_status 30512782604291438301258227465234178327895620663375311317385152998483096410248 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_clk_status/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3836123272 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_clk_status.3836123272' seed=30512782604291438301258227465234178327895620663375311317385152998483096410248 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30512782604291438301258227465234178327895620663375311317385152998483096410248 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_clk_status/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_clk_status_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_idle_intersig_mubi 82699239481175397468404618625614949765663262220078143436938044088366279143142 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_idle_intersig_mubi/latest run_opts='+clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3467882214 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_idle_intersig_mubi.3467882214' seed=82699239481175397468404618625614949765663262220078143436938044088366279143142 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82699239481175397468404618625614949765663262220078143436938044088366279143142 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_idle_intersig_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_regwen 80636984870190325681594669934620231269328859164037091794947691232759479899633 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_regwen/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3289748977 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_regwen.3289748977' seed=80636984870190325681594669934620231269328859164037091794947691232759479899633 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80636984870190325681594669934620231269328859164037091794947691232759479899633 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors 67559069804801583299544393407642635670985483775786166842374971540414828142644 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1528586292 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors.1528586292' seed=67559069804801583299544393407642635670985483775786166842374971540414828142644 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67559069804801583299544393407642635670985483775786166842374971540414828142644 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors_with_csr_rw 105293586873365425243775255899855967794841519723651428489226650121820247501123 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3330091331 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_shadow_reg_errors_with_csr_rw.3330091331' seed=105293586873365425243775255899855967794841519723651428489226650121820247501123 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105293586873365425243775255899855967794841519723651428489226650121820247501123 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_sec_cm 108469152100604343187077750479859934601185031587143521558708471275150674017681 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3719609745 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_sec_cm.3719609745' seed=108469152100604343187077750479859934601185031587143521558708471275150674017681 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108469152100604343187077750479859934601185031587143521558708471275150674017681 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_stress_all_with_rand_reset 70480626655519234400897160419368778458294395839503793154359835978101841114325 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2193274069 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_stress_all_with_rand_reset.2193274069' seed=70480626655519234400897160419368778458294395839503793154359835978101841114325 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70480626655519234400897160419368778458294395839503793154359835978101841114325 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_errors 57675525255106889657751641354083982250942203203149611329787474802423267471053 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_tl_errors/latest run_opts='+run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2422615757 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_tl_errors.2422615757' seed=57675525255106889657751641354083982250942203203149611329787474802423267471053 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57675525255106889657751641354083982250942203203149611329787474802423267471053 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_intg_err 19035728106982113989370828090615834655436412013813735712855821682126033577123 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3414221987 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_tl_intg_err.3414221987' seed=19035728106982113989370828090615834655436412013813735712855821682126033577123 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19035728106982113989370828090615834655436412013813735712855821682126033577123 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_alert_test 103492657569048576303045624624240467735796109258110893428223866872255116060537 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_alert_test/latest run_opts='+run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4033980281 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.clkmgr_alert_test.4033980281' seed=103492657569048576303045624624240467735796109258110893428223866872255116060537 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103492657569048576303045624624240467735796109258110893428223866872255116060537 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_csr_hw_reset 83332987987506317749093671259694567931867123191302867020739949370784139548481 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_hw_reset/latest run_opts='+csr_hw_reset +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=166827841 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_hw_reset.166827841' seed=83332987987506317749093671259694567931867123191302867020739949370784139548481 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83332987987506317749093671259694567931867123191302867020739949370784139548481 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_csr_rw 9969018356855284553683341952640552698137727737770956388080938787790527158649 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_rw/latest run_opts='+csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2342017401 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_rw.2342017401' seed=9969018356855284553683341952640552698137727737770956388080938787790527158649 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9969018356855284553683341952640552698137727737770956388080938787790527158649 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_csr_bit_bash 113630285702747628591722850993904589790214628239857775363278242182520824328472 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_bit_bash/latest run_opts='+csr_bit_bash +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1996681496 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_bit_bash.1996681496' seed=113630285702747628591722850993904589790214628239857775363278242182520824328472 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113630285702747628591722850993904589790214628239857775363278242182520824328472 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_csr_aliasing 69703548663714642972534162111271035423069557179355702426804873482846569136053 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_aliasing/latest run_opts='+csr_aliasing +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2239135669 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_aliasing.2239135669' seed=69703548663714642972534162111271035423069557179355702426804873482846569136053 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69703548663714642972534162111271035423069557179355702426804873482846569136053 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_same_csr_outstanding 9750214079336730016071832080887455635880973142346786449372425181146247725735 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=154796711 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_same_csr_outstanding.154796711' seed=9750214079336730016071832080887455635880973142346786449372425181146247725735 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9750214079336730016071832080887455635880973142346786449372425181146247725735 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_csr_mem_rw_with_rand_reset 42327379477617698995802846499290075773238681082860892932681336117453983809462 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3406266294 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.clkmgr_csr_mem_rw_with_rand_reset.3406266294' seed=42327379477617698995802846499290075773238681082860892932681336117453983809462 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42327379477617698995802846499290075773238681082860892932681336117453983809462 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/0.clkmgr_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_smoke 47524323585875034586456462902834332417268857051678247556445320340054278630745 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_smoke/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=166686041 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_smoke.166686041' seed=47524323585875034586456462902834332417268857051678247556445320340054278630745 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47524323585875034586456462902834332417268857051678247556445320340054278630745 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_frequency 93845760882897771129254436563790990320968770199683204111388761720701315089121 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_frequency/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1793229537 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency.1793229537' seed=93845760882897771129254436563790990320968770199683204111388761720701315089121 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93845760882897771129254436563790990320968770199683204111388761720701315089121 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_frequency/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_frequency_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_frequency_timeout 55434070379014850895731970268937625676767016651905046199344155346288325971683 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_frequency_timeout/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=530075363 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_frequency_timeout.530075363' seed=55434070379014850895731970268937625676767016651905046199344155346288325971683 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55434070379014850895731970268937625676767016651905046199344155346288325971683 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_frequency_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_frequency_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_peri 108674013053170215754951654634478607688892561208641465639117283401860252758645 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_peri/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=337703541 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_peri.337703541' seed=108674013053170215754951654634478607688892561208641465639117283401860252758645 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108674013053170215754951654634478607688892561208641465639117283401860252758645 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_peri/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_peri_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_trans 11517412381089176545223614922725444746523494076410506317927244529168463609828 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_trans/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1220198372 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_trans.1220198372' seed=11517412381089176545223614922725444746523494076410506317927244529168463609828 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11517412381089176545223614922725444746523494076410506317927244529168463609828 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_clk_status 34778087085171222519800314798890652385361817028322915063625411713180827246981 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_clk_status/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2618417541 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_clk_status.2618417541' seed=34778087085171222519800314798890652385361817028322915063625411713180827246981 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34778087085171222519800314798890652385361817028322915063625411713180827246981 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_clk_status/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_clk_status_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_idle_intersig_mubi 99016136208129776707448114947687136650590497873464228541382443347637069096373 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_idle_intersig_mubi/latest run_opts='+clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=383460789 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_idle_intersig_mubi.383460789' seed=99016136208129776707448114947687136650590497873464228541382443347637069096373 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99016136208129776707448114947687136650590497873464228541382443347637069096373 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_idle_intersig_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_regwen 12621937123508744392276910141160611494819536190165325643950020963200849871320 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_regwen/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1375404504 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_regwen.1375404504' seed=12621937123508744392276910141160611494819536190165325643950020963200849871320 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12621937123508744392276910141160611494819536190165325643950020963200849871320 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors 106262746699479615471647553623883506469745130465355858794367678571454383698871 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2212410295 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_shadow_reg_errors.2212410295' seed=106262746699479615471647553623883506469745130465355858794367678571454383698871 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106262746699479615471647553623883506469745130465355858794367678571454383698871 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors_with_csr_rw 9620029946479178591862472997795869977230972002399488390578558833695335039745 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=310297345 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_shadow_reg_errors_with_csr_rw.310297345' seed=9620029946479178591862472997795869977230972002399488390578558833695335039745 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9620029946479178591862472997795869977230972002399488390578558833695335039745 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_sec_cm 3344511451781552874172365182278537725746129394174953697028085286363360080360 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3654496744 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_sec_cm.3654496744' seed=3344511451781552874172365182278537725746129394174953697028085286363360080360 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3344511451781552874172365182278537725746129394174953697028085286363360080360 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_stress_all_with_rand_reset 36942055589083327579050945811172288090238559433190495055512952000327367515949 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1445715757 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_stress_all_with_rand_reset.1445715757' seed=36942055589083327579050945811172288090238559433190495055512952000327367515949 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36942055589083327579050945811172288090238559433190495055512952000327367515949 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_errors 9817240210960247259275404767451110245995162812588713952508954422416809792518 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_tl_errors/latest run_opts='+run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4128117766 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_tl_errors.4128117766' seed=9817240210960247259275404767451110245995162812588713952508954422416809792518 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9817240210960247259275404767451110245995162812588713952508954422416809792518 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_intg_err 15560388342325934217292912034992504787808679997469972837811011695819436992723 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3922864339 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_tl_intg_err.3922864339' seed=15560388342325934217292912034992504787808679997469972837811011695819436992723 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15560388342325934217292912034992504787808679997469972837811011695819436992723 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_alert_test 23499488598134339805766516699288387900230275569530605024847315267787896844493 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_alert_test/latest run_opts='+run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3130192077 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.clkmgr_alert_test.3130192077' seed=23499488598134339805766516699288387900230275569530605024847315267787896844493 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23499488598134339805766516699288387900230275569530605024847315267787896844493 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_csr_rw 27664161769812147898377952049007977082887431616060576754918164628803865183019 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_csr_rw/latest run_opts='+csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4060513067 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_rw.4060513067' seed=27664161769812147898377952049007977082887431616060576754918164628803865183019 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27664161769812147898377952049007977082887431616060576754918164628803865183019 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_same_csr_outstanding 100140646929307199655529148666673793961417861733734379895768464554635318708035 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=156157763 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_same_csr_outstanding.156157763' seed=100140646929307199655529148666673793961417861733734379895768464554635318708035 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100140646929307199655529148666673793961417861733734379895768464554635318708035 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_csr_mem_rw_with_rand_reset 61709156578216754166872581859128116354707906308598877939361454890414627466046 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=628992830 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.clkmgr_csr_mem_rw_with_rand_reset.628992830' seed=61709156578216754166872581859128116354707906308598877939361454890414627466046 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61709156578216754166872581859128116354707906308598877939361454890414627466046 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/1.clkmgr_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_smoke 100248983605524017884834016485713544428416732538182064106610522364460224490797 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_smoke/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=964701485 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_smoke.964701485' seed=100248983605524017884834016485713544428416732538182064106610522364460224490797 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100248983605524017884834016485713544428416732538182064106610522364460224490797 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_frequency 60610702740449763595765840160249851915752748680154470742887760942064688650202 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_frequency/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=430397402 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency.430397402' seed=60610702740449763595765840160249851915752748680154470742887760942064688650202 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60610702740449763595765840160249851915752748680154470742887760942064688650202 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_frequency/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_frequency_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_frequency_timeout 77861472502427281022097884471543647079124854219083593910570064554450606702600 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_frequency_timeout/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1132281864 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_frequency_timeout.1132281864' seed=77861472502427281022097884471543647079124854219083593910570064554450606702600 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77861472502427281022097884471543647079124854219083593910570064554450606702600 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_frequency_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_frequency_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_peri 84459643396784147449232034044646390286412296122446066743127581485330640209570 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_peri/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=769984162 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_peri.769984162' seed=84459643396784147449232034044646390286412296122446066743127581485330640209570 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84459643396784147449232034044646390286412296122446066743127581485330640209570 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_peri/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_peri_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_trans 21608582629339798779872375968297939344023282786630230032172200852923544526684 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_trans/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3643301724 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_trans.3643301724' seed=21608582629339798779872375968297939344023282786630230032172200852923544526684 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21608582629339798779872375968297939344023282786630230032172200852923544526684 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_clk_status 9400182472762901507727154893881945872991691056521469044485016575801357587835 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_clk_status/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=12408187 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_clk_status.12408187' seed=9400182472762901507727154893881945872991691056521469044485016575801357587835 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9400182472762901507727154893881945872991691056521469044485016575801357587835 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_clk_status/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_clk_status_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_idle_intersig_mubi 52951886167892449621713556998564698491450155534817685202167901757764627218195 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_idle_intersig_mubi/latest run_opts='+clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1401569043 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_idle_intersig_mubi.1401569043' seed=52951886167892449621713556998564698491450155534817685202167901757764627218195 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=52951886167892449621713556998564698491450155534817685202167901757764627218195 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_idle_intersig_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_regwen 102856408876235195895254778289905469783793614311625772800777733804434930722548 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_regwen/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1428874996 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_regwen.1428874996' seed=102856408876235195895254778289905469783793614311625772800777733804434930722548 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102856408876235195895254778289905469783793614311625772800777733804434930722548 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors 46646995527105237206677563470931056425004297464040845337490544817064834479153 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=68138033 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors.68138033' seed=46646995527105237206677563470931056425004297464040845337490544817064834479153 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46646995527105237206677563470931056425004297464040845337490544817064834479153 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors_with_csr_rw 62146012054932018830955925202869754708060365792857090532483421524137884383652 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=252049828 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_shadow_reg_errors_with_csr_rw.252049828' seed=62146012054932018830955925202869754708060365792857090532483421524137884383652 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62146012054932018830955925202869754708060365792857090532483421524137884383652 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_sec_cm 43723470599191530289107096005202099715857240156787814046783509663253467328969 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2073653705 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_sec_cm.2073653705' seed=43723470599191530289107096005202099715857240156787814046783509663253467328969 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43723470599191530289107096005202099715857240156787814046783509663253467328969 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_stress_all_with_rand_reset 29673733775923194980694164566231827979445144616533149814320030735553833942062 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2734636078 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_stress_all_with_rand_reset.2734636078' seed=29673733775923194980694164566231827979445144616533149814320030735553833942062 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29673733775923194980694164566231827979445144616533149814320030735553833942062 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_errors 29787694444421663130162951760562571958341056517218632389090319465498360815156 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_tl_errors/latest run_opts='+run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=101850676 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_tl_errors.101850676' seed=29787694444421663130162951760562571958341056517218632389090319465498360815156 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29787694444421663130162951760562571958341056517218632389090319465498360815156 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_intg_err 55654483892226405919011027259971902874674461518854232048756846412260653530306 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3675913410 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_tl_intg_err.3675913410' seed=55654483892226405919011027259971902874674461518854232048756846412260653530306 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55654483892226405919011027259971902874674461518854232048756846412260653530306 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_alert_test 77029999977416831024909502147459331326327544628106807422064411520668706358409 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_alert_test/latest run_opts='+run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2545501321 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.clkmgr_alert_test.2545501321' seed=77029999977416831024909502147459331326327544628106807422064411520668706358409 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77029999977416831024909502147459331326327544628106807422064411520668706358409 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_csr_rw 2846976190492063777664431864259956635619298541236399595467732175838271960102 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_csr_rw/latest run_opts='+csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2308895782 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_rw.2308895782' seed=2846976190492063777664431864259956635619298541236399595467732175838271960102 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2846976190492063777664431864259956635619298541236399595467732175838271960102 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_same_csr_outstanding 103380452597285844937260070378985564237908806077785134868620229997376741998720 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1856667776 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_same_csr_outstanding.1856667776' seed=103380452597285844937260070378985564237908806077785134868620229997376741998720 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103380452597285844937260070378985564237908806077785134868620229997376741998720 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_csr_mem_rw_with_rand_reset 76876021228733043627441130079346492295079036591643206267169146876474651073659 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3646184571 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.clkmgr_csr_mem_rw_with_rand_reset.3646184571' seed=76876021228733043627441130079346492295079036591643206267169146876474651073659 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76876021228733043627441130079346492295079036591643206267169146876474651073659 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/2.clkmgr_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_smoke 91384681103166163641599068191630720034146068435076391472172889251921885791120 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_smoke/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3439723408 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_smoke.3439723408' seed=91384681103166163641599068191630720034146068435076391472172889251921885791120 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91384681103166163641599068191630720034146068435076391472172889251921885791120 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_frequency 71203625835525138541653005839564190378198222270898967696104088165531610607771 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_frequency/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=867528859 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency.867528859' seed=71203625835525138541653005839564190378198222270898967696104088165531610607771 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71203625835525138541653005839564190378198222270898967696104088165531610607771 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_frequency/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_frequency_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_frequency_timeout 75859618991754277703236559653343958375992971577809869613075376468647461539841 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_frequency_timeout/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2372947969 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_frequency_timeout.2372947969' seed=75859618991754277703236559653343958375992971577809869613075376468647461539841 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75859618991754277703236559653343958375992971577809869613075376468647461539841 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_frequency_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_frequency_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_peri 49583547859600927510772657327759403066254028496720906039838311988555302272409 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_peri/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1249869209 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_peri.1249869209' seed=49583547859600927510772657327759403066254028496720906039838311988555302272409 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49583547859600927510772657327759403066254028496720906039838311988555302272409 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_peri/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_peri_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_trans 83486173075189323162170181024092624258211071183503871873612993926693709002945 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_trans/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2432547009 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_trans.2432547009' seed=83486173075189323162170181024092624258211071183503871873612993926693709002945 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83486173075189323162170181024092624258211071183503871873612993926693709002945 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_clk_status 90330888114624600327149694560374749949468000389230815177743562122086702819816 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_clk_status/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1093577192 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_clk_status.1093577192' seed=90330888114624600327149694560374749949468000389230815177743562122086702819816 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90330888114624600327149694560374749949468000389230815177743562122086702819816 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_clk_status/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_clk_status_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_idle_intersig_mubi 58374275988700798381645093449290032783570541764295486610180504544618570552355 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_idle_intersig_mubi/latest run_opts='+clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1959498787 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_idle_intersig_mubi.1959498787' seed=58374275988700798381645093449290032783570541764295486610180504544618570552355 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58374275988700798381645093449290032783570541764295486610180504544618570552355 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_idle_intersig_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_regwen 84451614284495161470479936989391152290792672972603029153000188846211981129483 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_regwen/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3639621387 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_regwen.3639621387' seed=84451614284495161470479936989391152290792672972603029153000188846211981129483 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84451614284495161470479936989391152290792672972603029153000188846211981129483 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors 6169017457355288105641440721095588910566373154247301158631708787200867926400 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3561980288 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_shadow_reg_errors.3561980288' seed=6169017457355288105641440721095588910566373154247301158631708787200867926400 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6169017457355288105641440721095588910566373154247301158631708787200867926400 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors_with_csr_rw 38908685670745610340984401101430891517665305315897425443126011146232092875231 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4153596383 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_shadow_reg_errors_with_csr_rw.4153596383' seed=38908685670745610340984401101430891517665305315897425443126011146232092875231 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38908685670745610340984401101430891517665305315897425443126011146232092875231 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_sec_cm 92851087375619420544253168889691661384119299156691344291885506494685466378242 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3966550018 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_sec_cm.3966550018' seed=92851087375619420544253168889691661384119299156691344291885506494685466378242 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92851087375619420544253168889691661384119299156691344291885506494685466378242 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_stress_all_with_rand_reset 80067159266372080834390809099596831316409701461387819922235387567738662040341 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2372285205 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_stress_all_with_rand_reset.2372285205' seed=80067159266372080834390809099596831316409701461387819922235387567738662040341 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80067159266372080834390809099596831316409701461387819922235387567738662040341 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_errors 28832676738962224505937584207370160654362236989300732951427751167940959278269 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_tl_errors/latest run_opts='+run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3820360893 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_tl_errors.3820360893' seed=28832676738962224505937584207370160654362236989300732951427751167940959278269 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28832676738962224505937584207370160654362236989300732951427751167940959278269 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_intg_err 1582448757392371493528576024459157577082384742897995300120257222337008467255 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3473898807 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_tl_intg_err.3473898807' seed=1582448757392371493528576024459157577082384742897995300120257222337008467255 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1582448757392371493528576024459157577082384742897995300120257222337008467255 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_alert_test 25489461292160106023044280298902061715893841667245404151869425178640524346967 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_alert_test/latest run_opts='+run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3982329431 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.clkmgr_alert_test.3982329431' seed=25489461292160106023044280298902061715893841667245404151869425178640524346967 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25489461292160106023044280298902061715893841667245404151869425178640524346967 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_csr_rw 13175792979196760838671789928744547005371955170546852987373776345610475021007 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_csr_rw/latest run_opts='+csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2329944783 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_rw.2329944783' seed=13175792979196760838671789928744547005371955170546852987373776345610475021007 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13175792979196760838671789928744547005371955170546852987373776345610475021007 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_same_csr_outstanding 83625769527460246462134284595922034109831451297052404049056460502494526039895 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3806848855 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_same_csr_outstanding.3806848855' seed=83625769527460246462134284595922034109831451297052404049056460502494526039895 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83625769527460246462134284595922034109831451297052404049056460502494526039895 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_csr_mem_rw_with_rand_reset 34621427993163260699025386949709739581965511248009192000299146628934887253279 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3012273439 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.clkmgr_csr_mem_rw_with_rand_reset.3012273439' seed=34621427993163260699025386949709739581965511248009192000299146628934887253279 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34621427993163260699025386949709739581965511248009192000299146628934887253279 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/3.clkmgr_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_smoke 42178069327084374674465814592711349850021907606931362258714339715620636799029 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_smoke/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3101503541 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_smoke.3101503541' seed=42178069327084374674465814592711349850021907606931362258714339715620636799029 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42178069327084374674465814592711349850021907606931362258714339715620636799029 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_frequency 109476990972141856932283823046986925658552211673072697600090809979255297313530 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_frequency/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3566635770 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency.3566635770' seed=109476990972141856932283823046986925658552211673072697600090809979255297313530 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109476990972141856932283823046986925658552211673072697600090809979255297313530 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_frequency/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_frequency_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_frequency_timeout 42535634874628123286038209302120332797887330493323670959980078465018135305654 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_frequency_timeout/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3345997238 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_frequency_timeout.3345997238' seed=42535634874628123286038209302120332797887330493323670959980078465018135305654 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42535634874628123286038209302120332797887330493323670959980078465018135305654 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_frequency_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_frequency_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_peri 19230986662617558257980477947039593811313957567137887241868312984089680731531 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_peri/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4034190731 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_peri.4034190731' seed=19230986662617558257980477947039593811313957567137887241868312984089680731531 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19230986662617558257980477947039593811313957567137887241868312984089680731531 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_peri/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_peri_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_trans 15411193406361716075577992327412847109944602581395066233070218374941236793512 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_trans/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1060901032 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_trans.1060901032' seed=15411193406361716075577992327412847109944602581395066233070218374941236793512 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15411193406361716075577992327412847109944602581395066233070218374941236793512 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_clk_status 55496438574042485312551005738741489802905153957789703398332548997456025987359 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_clk_status/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2792728863 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_clk_status.2792728863' seed=55496438574042485312551005738741489802905153957789703398332548997456025987359 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55496438574042485312551005738741489802905153957789703398332548997456025987359 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_clk_status/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_clk_status_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_idle_intersig_mubi 65613535152522211689522404315713488717944331026942573162054745591887218416594 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_idle_intersig_mubi/latest run_opts='+clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3194559442 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_idle_intersig_mubi.3194559442' seed=65613535152522211689522404315713488717944331026942573162054745591887218416594 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65613535152522211689522404315713488717944331026942573162054745591887218416594 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_idle_intersig_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_regwen 55679025756897143647742135588529273725116207813749825323492413103115747583213 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_regwen/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3469599981 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_regwen.3469599981' seed=55679025756897143647742135588529273725116207813749825323492413103115747583213 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55679025756897143647742135588529273725116207813749825323492413103115747583213 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors 94856243195173529752509511626782447350197165208388340178344076662986132829862 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2508076710 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors.2508076710' seed=94856243195173529752509511626782447350197165208388340178344076662986132829862 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94856243195173529752509511626782447350197165208388340178344076662986132829862 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors_with_csr_rw 33596739163676236909643269448170439310321222649757808366630825768662932246352 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4119973712 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_shadow_reg_errors_with_csr_rw.4119973712' seed=33596739163676236909643269448170439310321222649757808366630825768662932246352 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33596739163676236909643269448170439310321222649757808366630825768662932246352 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_sec_cm 109405981232063963802559907210587093968627386902560862563628452813747862178584 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3085765400 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_sec_cm.3085765400' seed=109405981232063963802559907210587093968627386902560862563628452813747862178584 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109405981232063963802559907210587093968627386902560862563628452813747862178584 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_stress_all_with_rand_reset 58592922145722103143742317809444245029194092560151870087543971439670819800454 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2271987078 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_stress_all_with_rand_reset.2271987078' seed=58592922145722103143742317809444245029194092560151870087543971439670819800454 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58592922145722103143742317809444245029194092560151870087543971439670819800454 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_errors 10699037357023659145322942079781412296447032297584767324216089377560262630081 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_tl_errors/latest run_opts='+run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3224918721 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_tl_errors.3224918721' seed=10699037357023659145322942079781412296447032297584767324216089377560262630081 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10699037357023659145322942079781412296447032297584767324216089377560262630081 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_intg_err 93606190331662045688287000172979971132789082643336739914634432885326399488817 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2490188593 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_tl_intg_err.2490188593' seed=93606190331662045688287000172979971132789082643336739914634432885326399488817 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93606190331662045688287000172979971132789082643336739914634432885326399488817 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_alert_test 96204546727547677179857099903917166479224326986721440929777691341701959835675 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_alert_test/latest run_opts='+run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=81715227 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.clkmgr_alert_test.81715227' seed=96204546727547677179857099903917166479224326986721440929777691341701959835675 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96204546727547677179857099903917166479224326986721440929777691341701959835675 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_csr_rw 67718700731144666640270715334468586373397883534986973230947419968973516151921 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_csr_rw/latest run_opts='+csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2731121777 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_rw.2731121777' seed=67718700731144666640270715334468586373397883534986973230947419968973516151921 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67718700731144666640270715334468586373397883534986973230947419968973516151921 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_same_csr_outstanding 75306624283914551071293740762288189907319727912020438633853205028780632116894 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3324186270 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_same_csr_outstanding.3324186270' seed=75306624283914551071293740762288189907319727912020438633853205028780632116894 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75306624283914551071293740762288189907319727912020438633853205028780632116894 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_csr_mem_rw_with_rand_reset 86747499069641938776687899623239797565732988233857441030361293411906723197271 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2095001943 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.clkmgr_csr_mem_rw_with_rand_reset.2095001943' seed=86747499069641938776687899623239797565732988233857441030361293411906723197271 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86747499069641938776687899623239797565732988233857441030361293411906723197271 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/4.clkmgr_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_smoke 15483704524570049784548117717613602721341542721612920221636231153778544596241 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_smoke/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2402538769 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_smoke.2402538769' seed=15483704524570049784548117717613602721341542721612920221636231153778544596241 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15483704524570049784548117717613602721341542721612920221636231153778544596241 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_frequency 81161865792989626424030318854011836759509877879295460714542547587650018588582 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_frequency/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3065493414 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency.3065493414' seed=81161865792989626424030318854011836759509877879295460714542547587650018588582 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81161865792989626424030318854011836759509877879295460714542547587650018588582 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_frequency/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_frequency_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_frequency_timeout 26093862087618717666693280260008561831259261915184767987220667626174130770168 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_frequency_timeout/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3819000056 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_frequency_timeout.3819000056' seed=26093862087618717666693280260008561831259261915184767987220667626174130770168 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26093862087618717666693280260008561831259261915184767987220667626174130770168 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_frequency_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_frequency_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_peri 106321527213498341906246652352452498659192184388207575162557777640038392105606 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_peri/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4165962374 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_peri.4165962374' seed=106321527213498341906246652352452498659192184388207575162557777640038392105606 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106321527213498341906246652352452498659192184388207575162557777640038392105606 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_peri/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_peri_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_trans 26724005480315587767986836896429591023158042746108852547545209356726378172059 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_trans/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2598375067 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_trans.2598375067' seed=26724005480315587767986836896429591023158042746108852547545209356726378172059 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26724005480315587767986836896429591023158042746108852547545209356726378172059 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_clk_status 58018768682426234482612075947044359214017019684570972534104622389785636227981 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_clk_status/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2735590285 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_clk_status.2735590285' seed=58018768682426234482612075947044359214017019684570972534104622389785636227981 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58018768682426234482612075947044359214017019684570972534104622389785636227981 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_clk_status/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_clk_status_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_idle_intersig_mubi 95128538052065549920255879013694173298425478880715727038897449227011683017510 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_idle_intersig_mubi/latest run_opts='+clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=117728038 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_idle_intersig_mubi.117728038' seed=95128538052065549920255879013694173298425478880715727038897449227011683017510 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95128538052065549920255879013694173298425478880715727038897449227011683017510 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_idle_intersig_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_regwen 34895616747249991336074313257786500569831540944703555292372331192720281471003 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_regwen/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2338490395 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_regwen.2338490395' seed=34895616747249991336074313257786500569831540944703555292372331192720281471003 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34895616747249991336074313257786500569831540944703555292372331192720281471003 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors 100699845787131548143690171940375885220901891235461532637826969891152080205180 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1599141244 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_shadow_reg_errors.1599141244' seed=100699845787131548143690171940375885220901891235461532637826969891152080205180 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100699845787131548143690171940375885220901891235461532637826969891152080205180 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors_with_csr_rw 22173132781418125978269943574299176894645791657814950657657258531132370789167 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1251681071 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_shadow_reg_errors_with_csr_rw.1251681071' seed=22173132781418125978269943574299176894645791657814950657657258531132370789167 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22173132781418125978269943574299176894645791657814950657657258531132370789167 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_stress_all_with_rand_reset 43365361266422921718916937885401903857945241237411749463835700818629493156587 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4202064619 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_stress_all_with_rand_reset.4202064619' seed=43365361266422921718916937885401903857945241237411749463835700818629493156587 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43365361266422921718916937885401903857945241237411749463835700818629493156587 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_errors 84551425399163463688991859356058425901338966989173273655216249877195550755542 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_tl_errors/latest run_opts='+run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3607497430 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_tl_errors.3607497430' seed=84551425399163463688991859356058425901338966989173273655216249877195550755542 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84551425399163463688991859356058425901338966989173273655216249877195550755542 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_intg_err 57961747661678376751721900454198744387507519926159570767862567153833144165106 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3148292850 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.clkmgr_tl_intg_err.3148292850' seed=57961747661678376751721900454198744387507519926159570767862567153833144165106 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57961747661678376751721900454198744387507519926159570767862567153833144165106 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_alert_test 70222926514890462374567781961492422739894845600809787706883544638702656063100 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_alert_test/latest run_opts='+run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=552240764 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.clkmgr_alert_test.552240764' seed=70222926514890462374567781961492422739894845600809787706883544638702656063100 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70222926514890462374567781961492422739894845600809787706883544638702656063100 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/5.clkmgr_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_smoke 70385978997780450647790754976073195919577664841258516439508571124830056772744 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_smoke/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1287681160 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_smoke.1287681160' seed=70385978997780450647790754976073195919577664841258516439508571124830056772744 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70385978997780450647790754976073195919577664841258516439508571124830056772744 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_frequency 102586704485396330350459259802214602524474311477244609975165433266718099554240 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_frequency/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=19316672 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency.19316672' seed=102586704485396330350459259802214602524474311477244609975165433266718099554240 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102586704485396330350459259802214602524474311477244609975165433266718099554240 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_frequency/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_frequency_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_frequency_timeout 52900045921734621429453710985188790295624133387093892238285164387908501099775 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_frequency_timeout/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3802649855 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_frequency_timeout.3802649855' seed=52900045921734621429453710985188790295624133387093892238285164387908501099775 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=52900045921734621429453710985188790295624133387093892238285164387908501099775 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_frequency_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_frequency_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_peri 42327120713027543384958688971605376661271971138154350950152717789346442315526 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_peri/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1096877830 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_peri.1096877830' seed=42327120713027543384958688971605376661271971138154350950152717789346442315526 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42327120713027543384958688971605376661271971138154350950152717789346442315526 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_peri/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_peri_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_trans 96674676277919010217866529147913980979524624475718433652035626340453825594452 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_trans/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2783396948 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_trans.2783396948' seed=96674676277919010217866529147913980979524624475718433652035626340453825594452 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96674676277919010217866529147913980979524624475718433652035626340453825594452 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_clk_status 28384060978668904649451688348972704914232183527160082395282831497874943915161 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_clk_status/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2727228569 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_clk_status.2727228569' seed=28384060978668904649451688348972704914232183527160082395282831497874943915161 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28384060978668904649451688348972704914232183527160082395282831497874943915161 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_clk_status/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_clk_status_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_idle_intersig_mubi 76116507953644527708264684220123208673953118003657129817917746104171215519724 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_idle_intersig_mubi/latest run_opts='+clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3381723116 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_idle_intersig_mubi.3381723116' seed=76116507953644527708264684220123208673953118003657129817917746104171215519724 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76116507953644527708264684220123208673953118003657129817917746104171215519724 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_idle_intersig_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_regwen 113131266653450219371450060687409899226710412936447326301428175519739404773964 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_regwen/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2711251532 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_regwen.2711251532' seed=113131266653450219371450060687409899226710412936447326301428175519739404773964 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113131266653450219371450060687409899226710412936447326301428175519739404773964 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors 55033528966481626029672032211615787009527211271484031714847557544887142551844 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2375258404 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_shadow_reg_errors.2375258404' seed=55033528966481626029672032211615787009527211271484031714847557544887142551844 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55033528966481626029672032211615787009527211271484031714847557544887142551844 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors_with_csr_rw 91287336466343740923936745045251136964774491099560496060678258695418230101467 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1828214235 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_shadow_reg_errors_with_csr_rw.1828214235' seed=91287336466343740923936745045251136964774491099560496060678258695418230101467 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91287336466343740923936745045251136964774491099560496060678258695418230101467 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_stress_all_with_rand_reset 65367834356917937292477920445342152367543844646184038678120922991071864311587 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2448707363 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_stress_all_with_rand_reset.2448707363' seed=65367834356917937292477920445342152367543844646184038678120922991071864311587 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65367834356917937292477920445342152367543844646184038678120922991071864311587 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_errors 5881252285027663418241509492170314077170066293640149905583149292533547309784 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_tl_errors/latest run_opts='+run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3675298520 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_tl_errors.3675298520' seed=5881252285027663418241509492170314077170066293640149905583149292533547309784 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5881252285027663418241509492170314077170066293640149905583149292533547309784 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_intg_err 107075066645305924747122302241314281644693180563277963155268313885000045402448 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=177707344 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.clkmgr_tl_intg_err.177707344' seed=107075066645305924747122302241314281644693180563277963155268313885000045402448 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107075066645305924747122302241314281644693180563277963155268313885000045402448 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_alert_test 78324095646473894608470576202831613710102129729084721896033538733537236121861 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_alert_test/latest run_opts='+run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3497031941 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.clkmgr_alert_test.3497031941' seed=78324095646473894608470576202831613710102129729084721896033538733537236121861 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78324095646473894608470576202831613710102129729084721896033538733537236121861 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/6.clkmgr_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_smoke 115456484931973782875405089081979772332478513693681837618191428378113070217620 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_smoke/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3925227924 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_smoke.3925227924' seed=115456484931973782875405089081979772332478513693681837618191428378113070217620 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115456484931973782875405089081979772332478513693681837618191428378113070217620 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_frequency 29358305930959404946106608948652018015065478250104670109228864072875496920638 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_frequency/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3241891390 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency.3241891390' seed=29358305930959404946106608948652018015065478250104670109228864072875496920638 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29358305930959404946106608948652018015065478250104670109228864072875496920638 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_frequency/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_frequency_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_frequency_timeout 74976329410475221055545945211399820848909030658372758858657193785773530273423 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_frequency_timeout/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1940903567 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_frequency_timeout.1940903567' seed=74976329410475221055545945211399820848909030658372758858657193785773530273423 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74976329410475221055545945211399820848909030658372758858657193785773530273423 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_frequency_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_frequency_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_peri 66937419730771774561408346996101422763599059416174782277405649474226296816294 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_peri/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1468367526 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_peri.1468367526' seed=66937419730771774561408346996101422763599059416174782277405649474226296816294 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66937419730771774561408346996101422763599059416174782277405649474226296816294 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_peri/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_peri_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_trans 69228473478651456289964707089996597756909104404457725650640484500820866325929 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_trans/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3529465257 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_trans.3529465257' seed=69228473478651456289964707089996597756909104404457725650640484500820866325929 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69228473478651456289964707089996597756909104404457725650640484500820866325929 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_clk_status 36510074220692969390733551110458855660671854613987738303681647052484649587841 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_clk_status/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=485921921 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_clk_status.485921921' seed=36510074220692969390733551110458855660671854613987738303681647052484649587841 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36510074220692969390733551110458855660671854613987738303681647052484649587841 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_clk_status/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_clk_status_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_idle_intersig_mubi 34354236355158285850131860703405619145669568316969097976048717980520329441459 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_idle_intersig_mubi/latest run_opts='+clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4221759667 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_idle_intersig_mubi.4221759667' seed=34354236355158285850131860703405619145669568316969097976048717980520329441459 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34354236355158285850131860703405619145669568316969097976048717980520329441459 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_idle_intersig_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_regwen 5568931158449995697256077702905142331010027397896668363124398639738794873011 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_regwen/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=361304243 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_regwen.361304243' seed=5568931158449995697256077702905142331010027397896668363124398639738794873011 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5568931158449995697256077702905142331010027397896668363124398639738794873011 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors 88137289108797227398450664114415564794030919572048472420277783778891140526876 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1788179228 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors.1788179228' seed=88137289108797227398450664114415564794030919572048472420277783778891140526876 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88137289108797227398450664114415564794030919572048472420277783778891140526876 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors_with_csr_rw 25639637268090772424916583169661262243174321997839966926795331828899600937635 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2134389411 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_shadow_reg_errors_with_csr_rw.2134389411' seed=25639637268090772424916583169661262243174321997839966926795331828899600937635 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25639637268090772424916583169661262243174321997839966926795331828899600937635 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_stress_all_with_rand_reset 27679064383321345652448766344524945151363185415735741415462264393570349317730 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=40468066 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_stress_all_with_rand_reset.40468066' seed=27679064383321345652448766344524945151363185415735741415462264393570349317730 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27679064383321345652448766344524945151363185415735741415462264393570349317730 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_errors 33302566014196377269760558681064527813636166382557419736971232309012176246601 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_tl_errors/latest run_opts='+run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2486114121 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_tl_errors.2486114121' seed=33302566014196377269760558681064527813636166382557419736971232309012176246601 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33302566014196377269760558681064527813636166382557419736971232309012176246601 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_intg_err 42484881277074036782080056234095862036085448920791049035248979160203950629690 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3362595642 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.clkmgr_tl_intg_err.3362595642' seed=42484881277074036782080056234095862036085448920791049035248979160203950629690 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42484881277074036782080056234095862036085448920791049035248979160203950629690 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_alert_test 22114376957112077412616621062893944610814560724728511112469737739791143798770 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_alert_test/latest run_opts='+run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2600470514 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.clkmgr_alert_test.2600470514' seed=22114376957112077412616621062893944610814560724728511112469737739791143798770 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22114376957112077412616621062893944610814560724728511112469737739791143798770 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/7.clkmgr_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_smoke 35019372379096404765328972075974451863859049606199063807516462751437796253609 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_smoke/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3289751465 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_smoke.3289751465' seed=35019372379096404765328972075974451863859049606199063807516462751437796253609 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35019372379096404765328972075974451863859049606199063807516462751437796253609 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_frequency 24105240124135182716846725048789779851053893699099285292874171717525985005612 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_frequency/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=955486252 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency.955486252' seed=24105240124135182716846725048789779851053893699099285292874171717525985005612 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24105240124135182716846725048789779851053893699099285292874171717525985005612 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_frequency/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_frequency_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_frequency_timeout 102372440984500451725805458555328622739799589543531841830441374027137434545865 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_frequency_timeout/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=774401737 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_frequency_timeout.774401737' seed=102372440984500451725805458555328622739799589543531841830441374027137434545865 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102372440984500451725805458555328622739799589543531841830441374027137434545865 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_frequency_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_frequency_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_peri 74458902859993874108971269941054415910450525539408223347666164189389299755559 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_peri/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=757180967 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_peri.757180967' seed=74458902859993874108971269941054415910450525539408223347666164189389299755559 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74458902859993874108971269941054415910450525539408223347666164189389299755559 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_peri/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_peri_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_trans 76650526759590243830295125094049580188602895353154430498373207118603778683790 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_trans/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=177107854 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_trans.177107854' seed=76650526759590243830295125094049580188602895353154430498373207118603778683790 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76650526759590243830295125094049580188602895353154430498373207118603778683790 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_clk_status 81801273349782029792431333342086905477364281723401917409058012969572798623516 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_clk_status/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1926557468 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_clk_status.1926557468' seed=81801273349782029792431333342086905477364281723401917409058012969572798623516 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81801273349782029792431333342086905477364281723401917409058012969572798623516 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_clk_status/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_clk_status_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_idle_intersig_mubi 74681668390643255269045162429876871674140931748115671580954197491956585636539 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_idle_intersig_mubi/latest run_opts='+clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3262161595 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_idle_intersig_mubi.3262161595' seed=74681668390643255269045162429876871674140931748115671580954197491956585636539 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74681668390643255269045162429876871674140931748115671580954197491956585636539 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_idle_intersig_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_regwen 70815900236556534074944238119357824641455725043914775783445352082979660516161 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_regwen/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=559172417 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_regwen.559172417' seed=70815900236556534074944238119357824641455725043914775783445352082979660516161 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70815900236556534074944238119357824641455725043914775783445352082979660516161 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors 25853656580084849596445290576409415025326122788030673803026831829783188022053 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2508923685 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors.2508923685' seed=25853656580084849596445290576409415025326122788030673803026831829783188022053 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25853656580084849596445290576409415025326122788030673803026831829783188022053 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors_with_csr_rw 38295721738820410489360164036709395961017746501871663349108130578752309586522 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2683333210 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_shadow_reg_errors_with_csr_rw.2683333210' seed=38295721738820410489360164036709395961017746501871663349108130578752309586522 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38295721738820410489360164036709395961017746501871663349108130578752309586522 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_stress_all_with_rand_reset 82055060933840730003992692479666144795684033947069403136300968597053119355036 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2061195420 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_stress_all_with_rand_reset.2061195420' seed=82055060933840730003992692479666144795684033947069403136300968597053119355036 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82055060933840730003992692479666144795684033947069403136300968597053119355036 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_errors 92736364845194803480227347138680069318217732113648354861886083637864728567862 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_tl_errors/latest run_opts='+run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=388177974 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_tl_errors.388177974' seed=92736364845194803480227347138680069318217732113648354861886083637864728567862 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92736364845194803480227347138680069318217732113648354861886083637864728567862 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_intg_err 56295361317162681156885595436764270196084490211923227582338645295399788185278 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1683588798 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.clkmgr_tl_intg_err.1683588798' seed=56295361317162681156885595436764270196084490211923227582338645295399788185278 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56295361317162681156885595436764270196084490211923227582338645295399788185278 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_alert_test 20353821305069391749477139720078551440301391523114358707094366335348059396269 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_alert_test/latest run_opts='+run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1649924269 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.clkmgr_alert_test.1649924269' seed=20353821305069391749477139720078551440301391523114358707094366335348059396269 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20353821305069391749477139720078551440301391523114358707094366335348059396269 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/8.clkmgr_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_smoke 40574928686473198846957398781047953460966467627460988213817881422267616303408 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_smoke/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1403492656 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_smoke.1403492656' seed=40574928686473198846957398781047953460966467627460988213817881422267616303408 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40574928686473198846957398781047953460966467627460988213817881422267616303408 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_frequency 6346329680299133833055504075373931401532181226532551814773057013656933315513 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_frequency/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3918476217 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency.3918476217' seed=6346329680299133833055504075373931401532181226532551814773057013656933315513 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6346329680299133833055504075373931401532181226532551814773057013656933315513 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_frequency/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_frequency_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_frequency_timeout 93092864074829982514326851928008565503749816063157675810133983625656864855931 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_frequency_timeout/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3046627195 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_frequency_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_frequency_timeout.3046627195' seed=93092864074829982514326851928008565503749816063157675810133983625656864855931 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93092864074829982514326851928008565503749816063157675810133983625656864855931 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_frequency_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_frequency_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_peri 58268783279800630046446795763914348573209847579089131391304956515705381514993 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_peri/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4051234545 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_peri_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_peri.4051234545' seed=58268783279800630046446795763914348573209847579089131391304956515705381514993 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58268783279800630046446795763914348573209847579089131391304956515705381514993 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_peri/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_peri_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_trans 108556050248779453341925861928113106404578660299107299593849776258567458485229 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_trans/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2105242605 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_trans.2105242605' seed=108556050248779453341925861928113106404578660299107299593849776258567458485229 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108556050248779453341925861928113106404578660299107299593849776258567458485229 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_clk_status 54038915456115616064535387839238008857326479057629567062242692263215118627035 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_clk_status/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4202639579 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_clk_status_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_clk_status.4202639579' seed=54038915456115616064535387839238008857326479057629567062242692263215118627035 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54038915456115616064535387839238008857326479057629567062242692263215118627035 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_clk_status/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_clk_status_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_idle_intersig_mubi 78554364102128204656803553467744225670423805454007945610113560457336855708992 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_idle_intersig_mubi/latest run_opts='+clkmgr_mubi_mode=ClkmgrMubiIdle +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=7324992 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_trans_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_idle_intersig_mubi.7324992' seed=78554364102128204656803553467744225670423805454007945610113560457336855708992 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78554364102128204656803553467744225670423805454007945610113560457336855708992 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_idle_intersig_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_regwen 109313680281829747945321793049897503627357028545799738432293725413588223282426 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_regwen/latest run_opts='+do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1723747578 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_regwen.1723747578' seed=109313680281829747945321793049897503627357028545799738432293725413588223282426 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109313680281829747945321793049897503627357028545799738432293725413588223282426 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors 88158040630638610680644348253823290091968962068053174502320612755465272511592 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2726251624 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_shadow_reg_errors.2726251624' seed=88158040630638610680644348253823290091968962068053174502320612755465272511592 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88158040630638610680644348253823290091968962068053174502320612755465272511592 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors_with_csr_rw 94176436524191862952424479848371309905703814086455177912182576465548284456703 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3939954431 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_shadow_reg_errors_with_csr_rw.3939954431' seed=94176436524191862952424479848371309905703814086455177912182576465548284456703 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94176436524191862952424479848371309905703814086455177912182576465548284456703 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_stress_all_with_rand_reset 72095116671005515166483967283563194304777033167820694768796762346959332966613 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=clkmgr_stress_all_vseq +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3952345301 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_stress_all_with_rand_reset.3952345301' seed=72095116671005515166483967283563194304777033167820694768796762346959332966613 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72095116671005515166483967283563194304777033167820694768796762346959332966613 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_errors 112304489625527801887357058135458084870508570187951252079112520294108842440213 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_tl_errors/latest run_opts='+run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1130903061 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_tl_errors.1130903061' seed=112304489625527801887357058135458084870508570187951252079112520294108842440213 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112304489625527801887357058135458084870508570187951252079112520294108842440213 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_intg_err 58547368861986235570216277770055259231067221694809225717816219250065563530421 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=549794997 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.clkmgr_tl_intg_err.549794997' seed=58547368861986235570216277770055259231067221694809225717816219250065563530421 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58547368861986235570216277770055259231067221694809225717816219250065563530421 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_alert_test 89602608977595740457345768436208828109106304790211498086676358109097386222655 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_alert_test/latest run_opts='+run_alert_test +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1549444159 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.clkmgr_alert_test.1549444159' seed=89602608977595740457345768436208828109106304790211498086676358109097386222655 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89602608977595740457345768436208828109106304790211498086676358109097386222655 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/9.clkmgr_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors 106954571293088114000495924331900339065471707706533395262716979382045605860655 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=103519535 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_shadow_reg_errors.103519535' seed=106954571293088114000495924331900339065471707706533395262716979382045605860655 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106954571293088114000495924331900339065471707706533395262716979382045605860655 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors_with_csr_rw 93549201963398449655249270874685049505411453155681441786594034079510893791640 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2738456984 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_shadow_reg_errors_with_csr_rw.2738456984' seed=93549201963398449655249270874685049505411453155681441786594034079510893791640 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93549201963398449655249270874685049505411453155681441786594034079510893791640 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_errors 28727244424915851228252005742841434375450893297004419600896637752941798935563 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_tl_errors/latest run_opts='+run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4133669899 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_tl_errors.4133669899' seed=28727244424915851228252005742841434375450893297004419600896637752941798935563 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28727244424915851228252005742841434375450893297004419600896637752941798935563 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_intg_err 56528391465533592306816335517041015884910995529270062621992352734989818321568 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1402526368 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.clkmgr_tl_intg_err.1402526368' seed=56528391465533592306816335517041015884910995529270062621992352734989818321568 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56528391465533592306816335517041015884910995529270062621992352734989818321568 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/10.clkmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors 90614700062994111876409421272637634913043692165573748189393291579134772608906 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3903684490 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_shadow_reg_errors.3903684490' seed=90614700062994111876409421272637634913043692165573748189393291579134772608906 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90614700062994111876409421272637634913043692165573748189393291579134772608906 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors_with_csr_rw 46723884631755871195737925902207946083817163117264577850308763663451791297755 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4169665755 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_shadow_reg_errors_with_csr_rw.4169665755' seed=46723884631755871195737925902207946083817163117264577850308763663451791297755 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46723884631755871195737925902207946083817163117264577850308763663451791297755 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_errors 81590786497439013279590381326947103490528566294964196280493478099719736051941 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_tl_errors/latest run_opts='+run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3098069221 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_tl_errors.3098069221' seed=81590786497439013279590381326947103490528566294964196280493478099719736051941 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81590786497439013279590381326947103490528566294964196280493478099719736051941 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_intg_err 58487852609369814495638699137951122716280236491210905589005660449857487574670 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=529864334 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.clkmgr_tl_intg_err.529864334' seed=58487852609369814495638699137951122716280236491210905589005660449857487574670 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58487852609369814495638699137951122716280236491210905589005660449857487574670 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/11.clkmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors 111339863079385831225208025230159546142047945511075270213513465664367533468089 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2615650745 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors.2615650745' seed=111339863079385831225208025230159546142047945511075270213513465664367533468089 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111339863079385831225208025230159546142047945511075270213513465664367533468089 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors_with_csr_rw 54575924517491286978247179261050185725033224045282179350288380319958843754015 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3793716767 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_shadow_reg_errors_with_csr_rw.3793716767' seed=54575924517491286978247179261050185725033224045282179350288380319958843754015 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54575924517491286978247179261050185725033224045282179350288380319958843754015 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_errors 76853808873664762690387504494199636345707106972310889543522939672777888925835 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_tl_errors/latest run_opts='+run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1131710603 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_tl_errors.1131710603' seed=76853808873664762690387504494199636345707106972310889543522939672777888925835 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76853808873664762690387504494199636345707106972310889543522939672777888925835 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_intg_err 19903327627989220830377003421972976304172374929049228419623540586455678411331 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=894788163 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.clkmgr_tl_intg_err.894788163' seed=19903327627989220830377003421972976304172374929049228419623540586455678411331 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19903327627989220830377003421972976304172374929049228419623540586455678411331 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/12.clkmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors 78779386697101846998526203439513958045256540128707756197674555910932717655919 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2043434863 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_shadow_reg_errors.2043434863' seed=78779386697101846998526203439513958045256540128707756197674555910932717655919 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78779386697101846998526203439513958045256540128707756197674555910932717655919 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors_with_csr_rw 3888958971931499768049730618455449408063513553535923177507746955346531776029 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=533132829 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_shadow_reg_errors_with_csr_rw.533132829' seed=3888958971931499768049730618455449408063513553535923177507746955346531776029 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3888958971931499768049730618455449408063513553535923177507746955346531776029 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_errors 78141553062046421218468860417226126262531547860367441683593842107522096914364 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_tl_errors/latest run_opts='+run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=164192188 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_tl_errors.164192188' seed=78141553062046421218468860417226126262531547860367441683593842107522096914364 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78141553062046421218468860417226126262531547860367441683593842107522096914364 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_intg_err 37348964458131444617145145038268669809463426717116962156082836801309142261605 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=344563557 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.clkmgr_tl_intg_err.344563557' seed=37348964458131444617145145038268669809463426717116962156082836801309142261605 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37348964458131444617145145038268669809463426717116962156082836801309142261605 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/13.clkmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors 106965414038054438968026573194795956311137897075657156695335755106187121092803 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1195993283 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_shadow_reg_errors.1195993283' seed=106965414038054438968026573194795956311137897075657156695335755106187121092803 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106965414038054438968026573194795956311137897075657156695335755106187121092803 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors_with_csr_rw 89897631385492703243842703197709131527856208759617349027562405889698330454813 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=274869021 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_shadow_reg_errors_with_csr_rw.274869021' seed=89897631385492703243842703197709131527856208759617349027562405889698330454813 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89897631385492703243842703197709131527856208759617349027562405889698330454813 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_errors 5978728698390184670495956698604506482314766984180888489851545383659012673126 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_tl_errors/latest run_opts='+run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2798440038 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_tl_errors.2798440038' seed=5978728698390184670495956698604506482314766984180888489851545383659012673126 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5978728698390184670495956698604506482314766984180888489851545383659012673126 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_intg_err 97062346358580260759794618566557456994711902252857372839531708184618978167276 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=409127404 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.clkmgr_tl_intg_err.409127404' seed=97062346358580260759794618566557456994711902252857372839531708184618978167276 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97062346358580260759794618566557456994711902252857372839531708184618978167276 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/14.clkmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors 43807097242983366892035074527424569320967711164535614788921026155763709592115 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3321971251 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_shadow_reg_errors.3321971251' seed=43807097242983366892035074527424569320967711164535614788921026155763709592115 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43807097242983366892035074527424569320967711164535614788921026155763709592115 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors_with_csr_rw 77838569434084345962929759571359431314278058994086386429437335390201596907714 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2234028226 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_shadow_reg_errors_with_csr_rw.2234028226' seed=77838569434084345962929759571359431314278058994086386429437335390201596907714 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77838569434084345962929759571359431314278058994086386429437335390201596907714 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_errors 75785724808799675346846869988205339351094990279067652249520483036926809053328 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_tl_errors/latest run_opts='+run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2761529488 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_tl_errors.2761529488' seed=75785724808799675346846869988205339351094990279067652249520483036926809053328 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75785724808799675346846869988205339351094990279067652249520483036926809053328 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_intg_err 113380899560997049931130237121855147577481787513346687292521575378042420690836 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1846509460 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.clkmgr_tl_intg_err.1846509460' seed=113380899560997049931130237121855147577481787513346687292521575378042420690836 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113380899560997049931130237121855147577481787513346687292521575378042420690836 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/15.clkmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors 6286125895260494425992559033845755074152280196775170092490531611061412271934 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1124964158 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_shadow_reg_errors.1124964158' seed=6286125895260494425992559033845755074152280196775170092490531611061412271934 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6286125895260494425992559033845755074152280196775170092490531611061412271934 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors_with_csr_rw 75143696843356946627881769577671956264694263352438594685635726027566378879730 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=5475058 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_shadow_reg_errors_with_csr_rw.5475058' seed=75143696843356946627881769577671956264694263352438594685635726027566378879730 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75143696843356946627881769577671956264694263352438594685635726027566378879730 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_errors 40455443592204087680147966653755024864540675238609820605934134402837754384909 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_tl_errors/latest run_opts='+run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=740266509 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_tl_errors.740266509' seed=40455443592204087680147966653755024864540675238609820605934134402837754384909 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40455443592204087680147966653755024864540675238609820605934134402837754384909 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_intg_err 46667412484666028184660880005390935531645830353183061745718650273200873333265 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3088769553 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.clkmgr_tl_intg_err.3088769553' seed=46667412484666028184660880005390935531645830353183061745718650273200873333265 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46667412484666028184660880005390935531645830353183061745718650273200873333265 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/16.clkmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors 82591583690680886648821422369244040468678116365065001567282208028825428299981 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2486833357 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_shadow_reg_errors.2486833357' seed=82591583690680886648821422369244040468678116365065001567282208028825428299981 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82591583690680886648821422369244040468678116365065001567282208028825428299981 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors_with_csr_rw 71067181591733797202411021422314153006050511677502935219473135399004257821285 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1096720997 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_shadow_reg_errors_with_csr_rw.1096720997' seed=71067181591733797202411021422314153006050511677502935219473135399004257821285 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71067181591733797202411021422314153006050511677502935219473135399004257821285 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_errors 29968982685492654701309636729837612664564297173502434677690952240903312514096 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_tl_errors/latest run_opts='+run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2033327152 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_tl_errors.2033327152' seed=29968982685492654701309636729837612664564297173502434677690952240903312514096 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29968982685492654701309636729837612664564297173502434677690952240903312514096 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_intg_err 8033146572788822324791396867081883112439086530108374704105407950147353213786 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3641867098 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.clkmgr_tl_intg_err.3641867098' seed=8033146572788822324791396867081883112439086530108374704105407950147353213786 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8033146572788822324791396867081883112439086530108374704105407950147353213786 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/17.clkmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors 44208623034362747190219325913775198886321760880792692934055181153490565052594 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4113545394 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_shadow_reg_errors.4113545394' seed=44208623034362747190219325913775198886321760880792692934055181153490565052594 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44208623034362747190219325913775198886321760880792692934055181153490565052594 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors_with_csr_rw 11483793864244434562719989922603844901116599714674919440548907322562085807711 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1575118431 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_shadow_reg_errors_with_csr_rw.1575118431' seed=11483793864244434562719989922603844901116599714674919440548907322562085807711 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11483793864244434562719989922603844901116599714674919440548907322562085807711 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_errors 2972431305433378319637989140088320620702946710701368851503932950480069658818 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_tl_errors/latest run_opts='+run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4042328258 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_tl_errors.4042328258' seed=2972431305433378319637989140088320620702946710701368851503932950480069658818 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2972431305433378319637989140088320620702946710701368851503932950480069658818 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_intg_err 90344252922214971612972566818606977447608493822454267527157397640698133004108 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2133376844 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.clkmgr_tl_intg_err.2133376844' seed=90344252922214971612972566818606977447608493822454267527157397640698133004108 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90344252922214971612972566818606977447608493822454267527157397640698133004108 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/18.clkmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors 17207312868588294512332231921430934097575375049348877013747792342469938573741 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=823194029 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_shadow_reg_errors.823194029' seed=17207312868588294512332231921430934097575375049348877013747792342469938573741 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17207312868588294512332231921430934097575375049348877013747792342469938573741 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_shadow_reg_errors_with_csr_rw 71646109853197559330083321827496334871468526074561248054188138129835812143737 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1470579321 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_shadow_reg_errors_with_csr_rw.1470579321' seed=71646109853197559330083321827496334871468526074561248054188138129835812143737 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71646109853197559330083321827496334871468526074561248054188138129835812143737 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_errors 25913360268492346926074021716103542421519930785226560917524294949169664660990 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_tl_errors/latest run_opts='+run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1484297726 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_tl_errors.1484297726' seed=25913360268492346926074021716103542421519930785226560917524294949169664660990 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25913360268492346926074021716103542421519930785226560917524294949169664660990 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_intg_err 8963131688859982970210612215680996830697884679723732488368999302858970148283 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=817016251 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.clkmgr_tl_intg_err.817016251' seed=8963131688859982970210612215680996830697884679723732488368999302858970148283 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8963131688859982970210612215680996830697884679723732488368999302858970148283 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/19.clkmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_errors 21342278192783087082042724909284345473309826664560197806126673449990015861900 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/20.clkmgr_tl_errors/latest run_opts='+run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1490732172 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.clkmgr_tl_errors.1490732172' seed=21342278192783087082042724909284345473309826664560197806126673449990015861900 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21342278192783087082042724909284345473309826664560197806126673449990015861900 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/20.clkmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_intg_err 42430183429236584624804029754074103875311219207639608223735373469875769067323 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/20.clkmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1291994939 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.clkmgr_tl_intg_err.1291994939' seed=42430183429236584624804029754074103875311219207639608223735373469875769067323 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42430183429236584624804029754074103875311219207639608223735373469875769067323 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/20.clkmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_errors 77820260519463233528052060186878055277576308386949759411679495986502183939935 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/21.clkmgr_tl_errors/latest run_opts='+run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3492540255 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.clkmgr_tl_errors.3492540255' seed=77820260519463233528052060186878055277576308386949759411679495986502183939935 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77820260519463233528052060186878055277576308386949759411679495986502183939935 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/21.clkmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_intg_err 114380897675652385759699847180205110405734360239149606991849620873471690264479 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/21.clkmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3767783327 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.clkmgr_tl_intg_err.3767783327' seed=114380897675652385759699847180205110405734360239149606991849620873471690264479 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114380897675652385759699847180205110405734360239149606991849620873471690264479 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/21.clkmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_errors 80467527326771936711589083407826510291510793585393899406466367114672326165906 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/22.clkmgr_tl_errors/latest run_opts='+run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=77448594 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.clkmgr_tl_errors.77448594' seed=80467527326771936711589083407826510291510793585393899406466367114672326165906 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80467527326771936711589083407826510291510793585393899406466367114672326165906 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/22.clkmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_intg_err 34704024778910355619724441313134531093952961552787142665264541231486640798831 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/22.clkmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3644537967 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.clkmgr_tl_intg_err.3644537967' seed=34704024778910355619724441313134531093952961552787142665264541231486640798831 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34704024778910355619724441313134531093952961552787142665264541231486640798831 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/22.clkmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_errors 77424642274309887917217311232576114167650289124822149049749899045777918696475 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/23.clkmgr_tl_errors/latest run_opts='+run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=651992091 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.clkmgr_tl_errors.651992091' seed=77424642274309887917217311232576114167650289124822149049749899045777918696475 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77424642274309887917217311232576114167650289124822149049749899045777918696475 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/23.clkmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_intg_err 3437717496221396018524194444165380714386651985774420540706683174291989958293 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/23.clkmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=822447765 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.clkmgr_tl_intg_err.822447765' seed=3437717496221396018524194444165380714386651985774420540706683174291989958293 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3437717496221396018524194444165380714386651985774420540706683174291989958293 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/23.clkmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_errors 113962517627175012667549732455895650640598788671514768913206314788192048610132 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/24.clkmgr_tl_errors/latest run_opts='+run_tl_errors +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2577627988 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.clkmgr_tl_errors.2577627988' seed=113962517627175012667549732455895650640598788671514768913206314788192048610132 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113962517627175012667549732455895650640598788671514768913206314788192048610132 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/24.clkmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
clkmgr_tl_intg_err 60456156675664981104155795870150497587708355670001448498192538778312872837078 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/clkmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/24.clkmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +do_clear_all_interrupts=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=632831958 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=clkmgr_base_test +UVM_TEST_SEQ=clkmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/clkmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.clkmgr_tl_intg_err.632831958' seed=60456156675664981104155795870150497587708355670001448498192538778312872837078 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60456156675664981104155795870150497587708355670001448498192538778312872837078 --run-dir=/nightly/current_run/scratch/master/clkmgr-sim-vcs/24.clkmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=clkmgr_base_test uvm_test_seq=clkmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_vseq] Mismatch for measurement recoverable error, expected *b*, got *b* 6 test runs
clkmgr_stress_all 41152298614988336114518191154488255816042027530168431740546515007580788186605 86
UVM_INFO @ 4754556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 93134172705957019778685004487159373957062925253205254642957965445758970207815 87
UVM_INFO @ 5561757 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 59009324952570223086484417119528897179249015710788603997841793345136819577002 107
UVM_INFO @ 204495137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 44185964435972813560710736498264571334116024194744823619315657780058266163965 87
UVM_INFO @ 28186733 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 93533143744235706638718705928609764747690146101752379296609859105493441649003 86
UVM_INFO @ 17244262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 92470301937348743695176335745258980765205354952404228127217312272538591495815 155
UVM_INFO @ 68645360 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (clkmgr_base_vseq.sv:320) virtual_sequencer [clkmgr_frequency_timeout_vseq] Mismatch for timeout recoverable error, expected *b*, got *b* 4 test runs
clkmgr_stress_all 27686720947394710667808576751277614944242845172862216042550810919122335988939 104
UVM_INFO @ 143231734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 27303951064272721303113338395541501394986247678828375686850944643814704028082 88
UVM_INFO @ 7731795 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 24389826302446666151471918381857364523846571182027465812832241030702838906227 104
UVM_INFO @ 173925505 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_stress_all 9283429272581355468906349801012305616225911412237654160943270608314731178081 88
UVM_INFO @ 27676544 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job cancelled because all of its dependencies failed or were killed. 1 test run
clkmgr None None
Job cancelled because one of its dependencies failed or was killed. 1 test run
clkmgr None None