Simulation Results

Simulation Results: csrng

28/08/2026 21:54:34 DVSim: v1.49.0 sha: a099412 json Branch: master Tool: xcelium [unknown]

Validation stages

V1		0.00%
V2		1.68%
V2S		1.71%
V3		0.00%

0/38 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
smoke				25
	csrng_smoke	1.444s	0.000us	25
csr_hw_reset				1
	csrng_csr_hw_reset	0.848s	0.000us	1
csr_rw				5
	csrng_csr_rw	1.385s	0.000us	5
csr_bit_bash				1
	csrng_csr_bit_bash	0.830s	0.000us	1
csr_aliasing				1
	csrng_csr_aliasing	0.852s	0.000us	1
csr_mem_rw_with_rand_reset				5
	csrng_csr_mem_rw_with_rand_reset	0.880s	0.000us	5
regwen_csr_and_corresponding_lockable_csr				6
	csrng_csr_rw	1.385s	0.000us	5
	csrng_csr_aliasing	0.852s	0.000us	1

22/1307 passed

1.68 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
interrupts				0	200	0.00
	csrng_intr	2.461s	0.000us	0	200	0.00
alerts				0	500	0.00
	csrng_alert	2.372s	0.000us	0	500	0.00
err				0	500	0.00
	csrng_err	22.316s	0.000us	0	500	0.00
cmds				0	25	0.00
	csrng_cmds	3.003s	0.000us	0	25	0.00
life cycle				0	25	0.00
	csrng_cmds	3.003s	0.000us	0	25	0.00
stress_all				22	25	88.00
	csrng_stress_all	1157.000s	77499.687us	22	25	88.00
intr_test				0	10	0.00
	csrng_intr_test	1.372s	0.000us	0	10	0.00
alert_test				0	10	0.00
	csrng_alert_test	0.881s	0.000us	0	10	0.00
tl_d_oob_addr_access				0	25	0.00
	csrng_tl_errors	1.996s	0.000us	0	25	0.00
tl_d_illegal_access				0	25	0.00
	csrng_tl_errors	1.996s	0.000us	0	25	0.00
tl_d_outstanding_access				0	12	0.00
	csrng_csr_hw_reset	0.848s	0.000us	0	1	0.00
	csrng_csr_rw	1.385s	0.000us	0	5	0.00
	csrng_csr_aliasing	0.852s	0.000us	0	1	0.00
	csrng_same_csr_outstanding	1.330s	0.000us	0	5	0.00
tl_d_partial_access				0	12	0.00
	csrng_csr_hw_reset	0.848s	0.000us	0	1	0.00
	csrng_csr_rw	1.385s	0.000us	0	5	0.00
	csrng_csr_aliasing	0.852s	0.000us	0	1	0.00
	csrng_same_csr_outstanding	1.330s	0.000us	0	5	0.00

V2S

22/1285 passed

1.71 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				0	30	0.00
	csrng_sec_cm	1.448s	0.000us	0	5	0.00
	csrng_tl_intg_err	1.982s	0.000us	0	25	0.00
sec_cm_config_regwen				0	30	0.00
	csrng_regwen	1.408s	0.000us	0	25	0.00
	csrng_csr_rw	1.385s	0.000us	0	5	0.00
sec_cm_config_mubi				0	500	0.00
	csrng_alert	2.372s	0.000us	0	500	0.00
sec_cm_intersig_mubi				22	25	88.00
	csrng_stress_all	1157.000s	77499.687us	22	25	88.00
sec_cm_main_sm_fsm_sparse				0	705	0.00
	csrng_intr	2.461s	0.000us	0	200	0.00
	csrng_err	22.316s	0.000us	0	500	0.00
	csrng_sec_cm	1.448s	0.000us	0	5	0.00
sec_cm_cmd_stage_fsm_sparse				0	705	0.00
	csrng_intr	2.461s	0.000us	0	200	0.00
	csrng_err	22.316s	0.000us	0	500	0.00
	csrng_sec_cm	1.448s	0.000us	0	5	0.00
sec_cm_ctr_drbg_fsm_sparse				0	705	0.00
	csrng_intr	2.461s	0.000us	0	200	0.00
	csrng_err	22.316s	0.000us	0	500	0.00
	csrng_sec_cm	1.448s	0.000us	0	5	0.00
sec_cm_ctr_drbg_ctr_redun				0	705	0.00
	csrng_intr	2.461s	0.000us	0	200	0.00
	csrng_err	22.316s	0.000us	0	500	0.00
	csrng_sec_cm	1.448s	0.000us	0	5	0.00
sec_cm_gen_cmd_ctr_redun				0	705	0.00
	csrng_intr	2.461s	0.000us	0	200	0.00
	csrng_err	22.316s	0.000us	0	500	0.00
	csrng_sec_cm	1.448s	0.000us	0	5	0.00
sec_cm_ctrl_mubi				0	500	0.00
	csrng_alert	2.372s	0.000us	0	500	0.00
sec_cm_main_sm_ctr_local_esc				0	700	0.00
	csrng_intr	2.461s	0.000us	0	200	0.00
	csrng_err	22.316s	0.000us	0	500	0.00
sec_cm_constants_lc_gated				22	25	88.00
	csrng_stress_all	1157.000s	77499.687us	22	25	88.00
sec_cm_sw_genbits_bus_consistency				0	500	0.00
	csrng_alert	2.372s	0.000us	0	500	0.00
sec_cm_tile_link_bus_integrity				0	25	0.00
	csrng_tl_intg_err	1.982s	0.000us	0	25	0.00
sec_cm_aes_cipher_fsm_sparse				0	705	0.00
	csrng_intr	2.461s	0.000us	0	200	0.00
	csrng_err	22.316s	0.000us	0	500	0.00
	csrng_sec_cm	1.448s	0.000us	0	5	0.00
sec_cm_aes_cipher_fsm_redun				0	700	0.00
	csrng_intr	2.461s	0.000us	0	200	0.00
	csrng_err	22.316s	0.000us	0	500	0.00
sec_cm_aes_cipher_ctrl_sparse				0	700	0.00
	csrng_intr	2.461s	0.000us	0	200	0.00
	csrng_err	22.316s	0.000us	0	500	0.00
sec_cm_aes_cipher_fsm_local_esc				0	700	0.00
	csrng_intr	2.461s	0.000us	0	200	0.00
	csrng_err	22.316s	0.000us	0	500	0.00
sec_cm_aes_cipher_ctr_redun				0	705	0.00
	csrng_intr	2.461s	0.000us	0	200	0.00
	csrng_err	22.316s	0.000us	0	500	0.00
	csrng_sec_cm	1.448s	0.000us	0	5	0.00
sec_cm_aes_cipher_data_reg_local_esc				0	700	0.00
	csrng_intr	2.461s	0.000us	0	200	0.00
	csrng_err	22.316s	0.000us	0	500	0.00

0/10 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	10	0.00
	csrng_stress_all_with_rand_reset	1.461s	0.000us	0	10	0.00

Error Messages

	Test	seed	line	log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				1378 test runs
	csrng_smoke	88772077831709632291737444516917912203490865629341167443773865529906001538175	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/default/xcelium.d -r tb +SVSEED=478604415 +UVM_TESTNAME=csrng_smoke_test +UVM_TEST_SEQ=csrng_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/default/0.csrng_smoke.478604415 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope default -covtest 0.csrng_smoke.478604415 -covoverwrite' seed=88772077831709632291737444516917912203490865629341167443773865529906001538175 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88772077831709632291737444516917912203490865629341167443773865529906001538175 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_smoke_test uvm_test_seq=csrng_smoke_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_cmds	22385628294746154033791415872311325361033261071195834123799284715543350547175	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_cmds/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/default/xcelium.d -r tb +SVSEED=2574062311 +UVM_TESTNAME=csrng_cmds_test +UVM_TEST_SEQ=csrng_cmds_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/default/0.csrng_cmds.2574062311 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope default -covtest 0.csrng_cmds.2574062311 -covoverwrite' seed=22385628294746154033791415872311325361033261071195834123799284715543350547175 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22385628294746154033791415872311325361033261071195834123799284715543350547175 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_cmds/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_cmds_test uvm_test_seq=csrng_cmds_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_intr	476009031428598737979689651673366164091317528268971107123551464384610693537	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/default/xcelium.d -r tb +SVSEED=2750149025 +UVM_TESTNAME=csrng_intr_test +UVM_TEST_SEQ=csrng_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/default/0.csrng_intr.2750149025 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope default -covtest 0.csrng_intr.2750149025 -covoverwrite' seed=476009031428598737979689651673366164091317528268971107123551464384610693537 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=476009031428598737979689651673366164091317528268971107123551464384610693537 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_intr_test uvm_test_seq=csrng_intr_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_alert	49197241931042061482062325174567959178895357647740256061584290644228748063635	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/default/xcelium.d -r tb +SVSEED=583775123 +UVM_TESTNAME=csrng_alert_test +UVM_TEST_SEQ=csrng_alert_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/default/0.csrng_alert.583775123 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope default -covtest 0.csrng_alert.583775123 -covoverwrite' seed=49197241931042061482062325174567959178895357647740256061584290644228748063635 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49197241931042061482062325174567959178895357647740256061584290644228748063635 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_alert_test uvm_test_seq=csrng_alert_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_err	94277841713753127222718253239309855544859318851967145720865102821985597413917	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/default/xcelium.d -r tb +SVSEED=445012509 +UVM_TESTNAME=csrng_intr_test +UVM_TEST_SEQ=csrng_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/default/0.csrng_err.445012509 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope default -covtest 0.csrng_err.445012509 -covoverwrite' seed=94277841713753127222718253239309855544859318851967145720865102821985597413917 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94277841713753127222718253239309855544859318851967145720865102821985597413917 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_intr_test uvm_test_seq=csrng_err_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_regwen	25094512591693106615913925820326590094686730195883777721123421315163705508324	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_regwen/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/default/xcelium.d -r tb +SVSEED=3453157860 +UVM_TESTNAME=csrng_regwen_test +UVM_TEST_SEQ=csrng_regwen_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/default/0.csrng_regwen.3453157860 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope default -covtest 0.csrng_regwen.3453157860 -covoverwrite' seed=25094512591693106615913925820326590094686730195883777721123421315163705508324 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25094512591693106615913925820326590094686730195883777721123421315163705508324 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_regwen_test uvm_test_seq=csrng_regwen_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_stress_all_with_rand_reset	110025710649251796452763712069294379643065555227899096657818266811622048835743	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=csrng_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/default/xcelium.d -r tb +SVSEED=3226642591 +UVM_TESTNAME=csrng_base_test +UVM_TEST_SEQ=csrng_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/default/0.csrng_stress_all_with_rand_reset.3226642591 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope default -covtest 0.csrng_stress_all_with_rand_reset.3226642591 -covoverwrite' seed=110025710649251796452763712069294379643065555227899096657818266811622048835743 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110025710649251796452763712069294379643065555227899096657818266811622048835743 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_base_test uvm_test_seq=csrng_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_sec_cm	79101773243731739277866480909098652152162421723582528616548956018662047839768	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/default/xcelium.d -r tb +SVSEED=2970711576 +UVM_TESTNAME=csrng_base_test +UVM_TEST_SEQ=csrng_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/default/0.csrng_sec_cm.2970711576 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope default -covtest 0.csrng_sec_cm.2970711576 -covoverwrite' seed=79101773243731739277866480909098652152162421723582528616548956018662047839768 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79101773243731739277866480909098652152162421723582528616548956018662047839768 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_base_test uvm_test_seq=csrng_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_tl_errors	58675042621645626790330501310249765914079205024464759923016653215608008715303	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1832496167 +UVM_TESTNAME=csrng_base_test +UVM_TEST_SEQ=csrng_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/cover_reg_top/0.csrng_tl_errors.1832496167 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.csrng_tl_errors.1832496167 -covoverwrite' seed=58675042621645626790330501310249765914079205024464759923016653215608008715303 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58675042621645626790330501310249765914079205024464759923016653215608008715303 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_base_test uvm_test_seq=csrng_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_tl_intg_err	79757532587955715872155582713670673194642214714379012952761295086241442537836	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2257428844 +UVM_TESTNAME=csrng_base_test +UVM_TEST_SEQ=csrng_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/cover_reg_top/0.csrng_tl_intg_err.2257428844 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.csrng_tl_intg_err.2257428844 -covoverwrite' seed=79757532587955715872155582713670673194642214714379012952761295086241442537836 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79757532587955715872155582713670673194642214714379012952761295086241442537836 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_base_test uvm_test_seq=csrng_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_alert_test	14895660047487703194270568466836120495079518552528501786147128229070232450859	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/default/xcelium.d -r tb +SVSEED=801208107 +UVM_TESTNAME=csrng_base_test +UVM_TEST_SEQ=csrng_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/default/0.csrng_alert_test.801208107 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope default -covtest 0.csrng_alert_test.801208107 -covoverwrite' seed=14895660047487703194270568466836120495079518552528501786147128229070232450859 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=14895660047487703194270568466836120495079518552528501786147128229070232450859 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_base_test uvm_test_seq=csrng_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_intr_test	64035225828928371704074815370942659965218666916131529967972475932713128501298	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3591577650 +UVM_TESTNAME=csrng_base_test +UVM_TEST_SEQ=csrng_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/cover_reg_top/0.csrng_intr_test.3591577650 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.csrng_intr_test.3591577650 -covoverwrite' seed=64035225828928371704074815370942659965218666916131529967972475932713128501298 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64035225828928371704074815370942659965218666916131529967972475932713128501298 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_base_test uvm_test_seq=csrng_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_csr_hw_reset	89916986929053406389343544028571814467937177427520400760565941351792518076711	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_csr_hw_reset/latest run_opts='+csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2892732711 +UVM_TESTNAME=csrng_base_test +UVM_TEST_SEQ=csrng_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/cover_reg_top/0.csrng_csr_hw_reset.2892732711 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.csrng_csr_hw_reset.2892732711 -covoverwrite' seed=89916986929053406389343544028571814467937177427520400760565941351792518076711 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89916986929053406389343544028571814467937177427520400760565941351792518076711 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_base_test uvm_test_seq=csrng_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_csr_rw	101582076340069168067604904060183276925433878212881963419475592579485530940300	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=162358156 +UVM_TESTNAME=csrng_base_test +UVM_TEST_SEQ=csrng_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/cover_reg_top/0.csrng_csr_rw.162358156 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.csrng_csr_rw.162358156 -covoverwrite' seed=101582076340069168067604904060183276925433878212881963419475592579485530940300 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101582076340069168067604904060183276925433878212881963419475592579485530940300 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_base_test uvm_test_seq=csrng_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_csr_bit_bash	23436852221841749578817222523565092745936426260912680271765929390484945723938	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_csr_bit_bash/latest run_opts='+csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3657785890 +UVM_TESTNAME=csrng_base_test +UVM_TEST_SEQ=csrng_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/cover_reg_top/0.csrng_csr_bit_bash.3657785890 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.csrng_csr_bit_bash.3657785890 -covoverwrite' seed=23436852221841749578817222523565092745936426260912680271765929390484945723938 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23436852221841749578817222523565092745936426260912680271765929390484945723938 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_base_test uvm_test_seq=csrng_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_csr_aliasing	50760533779512615382731608688413563753200367222580963611234882473874603399202	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_csr_aliasing/latest run_opts='+csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1469339682 +UVM_TESTNAME=csrng_base_test +UVM_TEST_SEQ=csrng_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/cover_reg_top/0.csrng_csr_aliasing.1469339682 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.csrng_csr_aliasing.1469339682 -covoverwrite' seed=50760533779512615382731608688413563753200367222580963611234882473874603399202 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50760533779512615382731608688413563753200367222580963611234882473874603399202 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_base_test uvm_test_seq=csrng_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_same_csr_outstanding	51530220513597922983737975039048501658540149539147456074402030603637883363368	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2854707240 +UVM_TESTNAME=csrng_base_test +UVM_TEST_SEQ=csrng_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/cover_reg_top/0.csrng_same_csr_outstanding.2854707240 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.csrng_same_csr_outstanding.2854707240 -covoverwrite' seed=51530220513597922983737975039048501658540149539147456074402030603637883363368 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51530220513597922983737975039048501658540149539147456074402030603637883363368 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_base_test uvm_test_seq=csrng_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_csr_mem_rw_with_rand_reset	22835930513074260335016868529854700497391987711000743186632884606958560873642	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2432437418 +UVM_TESTNAME=csrng_base_test +UVM_TEST_SEQ=csrng_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/cover_reg_top/0.csrng_csr_mem_rw_with_rand_reset.2432437418 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.csrng_csr_mem_rw_with_rand_reset.2432437418 -covoverwrite' seed=22835930513074260335016868529854700497391987711000743186632884606958560873642 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22835930513074260335016868529854700497391987711000743186632884606958560873642 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/0.csrng_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_base_test uvm_test_seq=csrng_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_smoke	28956188376794751612323002299570967362126943347331529406793601611832799394272	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/default/xcelium.d -r tb +SVSEED=1110571488 +UVM_TESTNAME=csrng_smoke_test +UVM_TEST_SEQ=csrng_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/default/1.csrng_smoke.1110571488 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope default -covtest 1.csrng_smoke.1110571488 -covoverwrite' seed=28956188376794751612323002299570967362126943347331529406793601611832799394272 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28956188376794751612323002299570967362126943347331529406793601611832799394272 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_smoke_test uvm_test_seq=csrng_smoke_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_cmds	33935650694616588555015578819454439267286337930863411600417964839088367019095	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_cmds/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/default/xcelium.d -r tb +SVSEED=2070619223 +UVM_TESTNAME=csrng_cmds_test +UVM_TEST_SEQ=csrng_cmds_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/default/1.csrng_cmds.2070619223 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope default -covtest 1.csrng_cmds.2070619223 -covoverwrite' seed=33935650694616588555015578819454439267286337930863411600417964839088367019095 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33935650694616588555015578819454439267286337930863411600417964839088367019095 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_cmds/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_cmds_test uvm_test_seq=csrng_cmds_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_intr	42742992694219401828827942117702392560928868647433620096451923105711807708529	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/default/xcelium.d -r tb +SVSEED=2140847473 +UVM_TESTNAME=csrng_intr_test +UVM_TEST_SEQ=csrng_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/default/1.csrng_intr.2140847473 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope default -covtest 1.csrng_intr.2140847473 -covoverwrite' seed=42742992694219401828827942117702392560928868647433620096451923105711807708529 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42742992694219401828827942117702392560928868647433620096451923105711807708529 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_intr_test uvm_test_seq=csrng_intr_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_alert	115069344599098887235268599592971014872004208216827723016719987558627167022502	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/default/xcelium.d -r tb +SVSEED=101035430 +UVM_TESTNAME=csrng_alert_test +UVM_TEST_SEQ=csrng_alert_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/default/1.csrng_alert.101035430 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope default -covtest 1.csrng_alert.101035430 -covoverwrite' seed=115069344599098887235268599592971014872004208216827723016719987558627167022502 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115069344599098887235268599592971014872004208216827723016719987558627167022502 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_alert_test uvm_test_seq=csrng_alert_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_err	10289483086769329021119442498800385077927245350931517084091227305535610153125	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/default/xcelium.d -r tb +SVSEED=328329381 +UVM_TESTNAME=csrng_intr_test +UVM_TEST_SEQ=csrng_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/default/1.csrng_err.328329381 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope default -covtest 1.csrng_err.328329381 -covoverwrite' seed=10289483086769329021119442498800385077927245350931517084091227305535610153125 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10289483086769329021119442498800385077927245350931517084091227305535610153125 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_intr_test uvm_test_seq=csrng_err_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_regwen	33498180626399917790224167614286179676086729981875195147316982452313024511903	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_regwen/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/default/xcelium.d -r tb +SVSEED=3068542879 +UVM_TESTNAME=csrng_regwen_test +UVM_TEST_SEQ=csrng_regwen_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/default/1.csrng_regwen.3068542879 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope default -covtest 1.csrng_regwen.3068542879 -covoverwrite' seed=33498180626399917790224167614286179676086729981875195147316982452313024511903 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33498180626399917790224167614286179676086729981875195147316982452313024511903 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_regwen_test uvm_test_seq=csrng_regwen_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_stress_all_with_rand_reset	109143781725525087770614459798493578977796108163616499075108625637500300679284	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=csrng_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/default/xcelium.d -r tb +SVSEED=2376456308 +UVM_TESTNAME=csrng_base_test +UVM_TEST_SEQ=csrng_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/default/1.csrng_stress_all_with_rand_reset.2376456308 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope default -covtest 1.csrng_stress_all_with_rand_reset.2376456308 -covoverwrite' seed=109143781725525087770614459798493578977796108163616499075108625637500300679284 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109143781725525087770614459798493578977796108163616499075108625637500300679284 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_base_test uvm_test_seq=csrng_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_sec_cm	4342794158788268037790198736458796282791303751185051201706014091889594578548	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/default/xcelium.d -r tb +SVSEED=2716317300 +UVM_TESTNAME=csrng_base_test +UVM_TEST_SEQ=csrng_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/default/1.csrng_sec_cm.2716317300 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope default -covtest 1.csrng_sec_cm.2716317300 -covoverwrite' seed=4342794158788268037790198736458796282791303751185051201706014091889594578548 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4342794158788268037790198736458796282791303751185051201706014091889594578548 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_base_test uvm_test_seq=csrng_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_tl_errors	36885100969612213271148768981549698345433733708625422051475154184439224150868	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4165282644 +UVM_TESTNAME=csrng_base_test +UVM_TEST_SEQ=csrng_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/cover_reg_top/1.csrng_tl_errors.4165282644 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.csrng_tl_errors.4165282644 -covoverwrite' seed=36885100969612213271148768981549698345433733708625422051475154184439224150868 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36885100969612213271148768981549698345433733708625422051475154184439224150868 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_base_test uvm_test_seq=csrng_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_tl_intg_err	6050123953563945329856001058685648482150724503448347624446288582888701775431	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4203433543 +UVM_TESTNAME=csrng_base_test +UVM_TEST_SEQ=csrng_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/cover_reg_top/1.csrng_tl_intg_err.4203433543 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.csrng_tl_intg_err.4203433543 -covoverwrite' seed=6050123953563945329856001058685648482150724503448347624446288582888701775431 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6050123953563945329856001058685648482150724503448347624446288582888701775431 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_base_test uvm_test_seq=csrng_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_alert_test	101941938816078117291077195006053747590273938116893667718044844989362096558781	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/default/xcelium.d -r tb +SVSEED=4222603965 +UVM_TESTNAME=csrng_base_test +UVM_TEST_SEQ=csrng_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/default/1.csrng_alert_test.4222603965 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope default -covtest 1.csrng_alert_test.4222603965 -covoverwrite' seed=101941938816078117291077195006053747590273938116893667718044844989362096558781 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101941938816078117291077195006053747590273938116893667718044844989362096558781 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_base_test uvm_test_seq=csrng_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_intr_test	101618601468464790337779298508373573432457738701736815673802766857346018063147	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4021695275 +UVM_TESTNAME=csrng_base_test +UVM_TEST_SEQ=csrng_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/cover_reg_top/1.csrng_intr_test.4021695275 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.csrng_intr_test.4021695275 -covoverwrite' seed=101618601468464790337779298508373573432457738701736815673802766857346018063147 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101618601468464790337779298508373573432457738701736815673802766857346018063147 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_base_test uvm_test_seq=csrng_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_csr_rw	99979213597193814622994667822088729690874296549585572870965057616594602418132	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2183520212 +UVM_TESTNAME=csrng_base_test +UVM_TEST_SEQ=csrng_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/cover_reg_top/1.csrng_csr_rw.2183520212 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.csrng_csr_rw.2183520212 -covoverwrite' seed=99979213597193814622994667822088729690874296549585572870965057616594602418132 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99979213597193814622994667822088729690874296549585572870965057616594602418132 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_base_test uvm_test_seq=csrng_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_same_csr_outstanding	4918336758598114596198744433077289449290557083810467286550453563132312364388	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3813221732 +UVM_TESTNAME=csrng_base_test +UVM_TEST_SEQ=csrng_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/cover_reg_top/1.csrng_same_csr_outstanding.3813221732 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.csrng_same_csr_outstanding.3813221732 -covoverwrite' seed=4918336758598114596198744433077289449290557083810467286550453563132312364388 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4918336758598114596198744433077289449290557083810467286550453563132312364388 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_base_test uvm_test_seq=csrng_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_csr_mem_rw_with_rand_reset	95109180619244901334886435053492984024316035650442083112079641157488582616049	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=283665393 +UVM_TESTNAME=csrng_base_test +UVM_TEST_SEQ=csrng_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/cover_reg_top/1.csrng_csr_mem_rw_with_rand_reset.283665393 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.csrng_csr_mem_rw_with_rand_reset.283665393 -covoverwrite' seed=95109180619244901334886435053492984024316035650442083112079641157488582616049 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95109180619244901334886435053492984024316035650442083112079641157488582616049 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/1.csrng_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_base_test uvm_test_seq=csrng_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_smoke	34215036547309657977049650938630003558635795450725707968501847525629929613631	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/2.csrng_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/default/xcelium.d -r tb +SVSEED=2092067135 +UVM_TESTNAME=csrng_smoke_test +UVM_TEST_SEQ=csrng_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/default/2.csrng_smoke.2092067135 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope default -covtest 2.csrng_smoke.2092067135 -covoverwrite' seed=34215036547309657977049650938630003558635795450725707968501847525629929613631 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34215036547309657977049650938630003558635795450725707968501847525629929613631 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/2.csrng_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_smoke_test uvm_test_seq=csrng_smoke_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_cmds	26288114160254254144050334303133790454392076850330279753301952591507080222247	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/2.csrng_cmds/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/default/xcelium.d -r tb +SVSEED=1741035047 +UVM_TESTNAME=csrng_cmds_test +UVM_TEST_SEQ=csrng_cmds_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/default/2.csrng_cmds.1741035047 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope default -covtest 2.csrng_cmds.1741035047 -covoverwrite' seed=26288114160254254144050334303133790454392076850330279753301952591507080222247 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26288114160254254144050334303133790454392076850330279753301952591507080222247 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/2.csrng_cmds/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_cmds_test uvm_test_seq=csrng_cmds_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_intr	37655557875860258857641384364055529594117871783198038282077711685239979398835	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/2.csrng_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/default/xcelium.d -r tb +SVSEED=741365427 +UVM_TESTNAME=csrng_intr_test +UVM_TEST_SEQ=csrng_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/default/2.csrng_intr.741365427 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope default -covtest 2.csrng_intr.741365427 -covoverwrite' seed=37655557875860258857641384364055529594117871783198038282077711685239979398835 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37655557875860258857641384364055529594117871783198038282077711685239979398835 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/2.csrng_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_intr_test uvm_test_seq=csrng_intr_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_alert	71268982916113093442169540543219790708849027987313568323073118883238806340609	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/2.csrng_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/default/xcelium.d -r tb +SVSEED=1110492161 +UVM_TESTNAME=csrng_alert_test +UVM_TEST_SEQ=csrng_alert_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/default/2.csrng_alert.1110492161 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope default -covtest 2.csrng_alert.1110492161 -covoverwrite' seed=71268982916113093442169540543219790708849027987313568323073118883238806340609 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71268982916113093442169540543219790708849027987313568323073118883238806340609 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/2.csrng_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_alert_test uvm_test_seq=csrng_alert_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_err	38517815483310220744231035514599559052021811804936326483412376579106371823721	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/2.csrng_err/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/default/xcelium.d -r tb +SVSEED=1810917481 +UVM_TESTNAME=csrng_intr_test +UVM_TEST_SEQ=csrng_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/default/2.csrng_err.1810917481 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope default -covtest 2.csrng_err.1810917481 -covoverwrite' seed=38517815483310220744231035514599559052021811804936326483412376579106371823721 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38517815483310220744231035514599559052021811804936326483412376579106371823721 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/2.csrng_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_intr_test uvm_test_seq=csrng_err_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	csrng_regwen	30174440739876713523407736761158347357983895676186086160453503775560079619164	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/2.csrng_regwen/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/csrng-sim-xcelium/default/xcelium.d -r tb +SVSEED=3875910748 +UVM_TESTNAME=csrng_regwen_test +UVM_TEST_SEQ=csrng_regwen_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage/default/2.csrng_regwen.3875910748 -covworkdir /nightly/current_run/scratch/master/csrng-sim-xcelium/coverage -covscope default -covtest 2.csrng_regwen.3875910748 -covoverwrite' seed=30174440739876713523407736761158347357983895676186086160453503775560079619164 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30174440739876713523407736761158347357983895676186086160453503775560079619164 --run-dir=/nightly/current_run/scratch/master/csrng-sim-xcelium/2.csrng_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=csrng_regwen_test uvm_test_seq=csrng_regwen_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126