Simulation Results

Simulation Results: hmac

28/08/2026 21:54:34 DVSim: v1.49.0 sha: a099412 json Branch: master Tool: xcelium [unknown]

Validation stages

V1		0.00%
V2		8.38%
V2S		0.00%
V3		0.00%
unmapped		0.00%

0/23 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
smoke				10
	hmac_smoke	1.485s	0.000us	10
csr_hw_reset				1
	hmac_csr_hw_reset	0.686s	0.000us	1
csr_rw				5
	hmac_csr_rw	0.848s	0.000us	5
csr_bit_bash				1
	hmac_csr_bit_bash	0.806s	0.000us	1
csr_aliasing				1
	hmac_csr_aliasing	0.826s	0.000us	1
csr_mem_rw_with_rand_reset				5
	hmac_csr_mem_rw_with_rand_reset	1.489s	0.000us	5
regwen_csr_and_corresponding_lockable_csr				6
	hmac_csr_rw	0.848s	0.000us	5
	hmac_csr_aliasing	0.826s	0.000us	1

50/597 passed

8.38 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
long_msg				0	10	0.00
	hmac_long_msg	1.339s	0.000us	0	10	0.00
back_pressure				0	25	0.00
	hmac_back_pressure	1.501s	0.000us	0	25	0.00
test_vectors				0	365	0.00
	hmac_test_sha256_vectors	1.522s	0.000us	0	30	0.00
	hmac_test_sha384_vectors	1.524s	0.000us	0	75	0.00
	hmac_test_sha512_vectors	1.509s	0.000us	0	75	0.00
	hmac_test_hmac256_vectors	1.475s	0.000us	0	50	0.00
	hmac_test_hmac384_vectors	1.544s	0.000us	0	60	0.00
	hmac_test_hmac512_vectors	1.577s	0.000us	0	75	0.00
burst_wr				0	50	0.00
	hmac_burst_wr	1.551s	0.000us	0	50	0.00
datapath_stress				0	10	0.00
	hmac_datapath_stress	0.828s	0.000us	0	10	0.00
error				0	10	0.00
	hmac_error	0.859s	0.000us	0	10	0.00
wipe_secret				0	10	0.00
	hmac_wipe_secret	0.875s	0.000us	0	10	0.00
save_and_restore				50	155	32.26
	hmac_smoke	1.485s	0.000us	0	10	0.00
	hmac_long_msg	1.339s	0.000us	0	10	0.00
	hmac_back_pressure	1.501s	0.000us	0	25	0.00
	hmac_datapath_stress	0.828s	0.000us	0	10	0.00
	hmac_burst_wr	1.551s	0.000us	0	50	0.00
	hmac_stress_all	1155.000s	91858.423us	50	50	100.00
fifo_empty_status_interrupt				0	430	0.00
	hmac_smoke	1.485s	0.000us	0	10	0.00
	hmac_long_msg	1.339s	0.000us	0	10	0.00
	hmac_back_pressure	1.501s	0.000us	0	25	0.00
	hmac_datapath_stress	0.828s	0.000us	0	10	0.00
	hmac_wipe_secret	0.875s	0.000us	0	10	0.00
	hmac_test_sha256_vectors	1.522s	0.000us	0	30	0.00
	hmac_test_sha384_vectors	1.524s	0.000us	0	75	0.00
	hmac_test_sha512_vectors	1.509s	0.000us	0	75	0.00
	hmac_test_hmac256_vectors	1.475s	0.000us	0	50	0.00
	hmac_test_hmac384_vectors	1.544s	0.000us	0	60	0.00
	hmac_test_hmac512_vectors	1.577s	0.000us	0	75	0.00
wide_digest_configurable_key_length				50	540	9.26
	hmac_smoke	1.485s	0.000us	0	10	0.00
	hmac_long_msg	1.339s	0.000us	0	10	0.00
	hmac_back_pressure	1.501s	0.000us	0	25	0.00
	hmac_datapath_stress	0.828s	0.000us	0	10	0.00
	hmac_burst_wr	1.551s	0.000us	0	50	0.00
	hmac_error	0.859s	0.000us	0	10	0.00
	hmac_wipe_secret	0.875s	0.000us	0	10	0.00
	hmac_test_sha256_vectors	1.522s	0.000us	0	30	0.00
	hmac_test_sha384_vectors	1.524s	0.000us	0	75	0.00
	hmac_test_sha512_vectors	1.509s	0.000us	0	75	0.00
	hmac_test_hmac256_vectors	1.475s	0.000us	0	50	0.00
	hmac_test_hmac384_vectors	1.544s	0.000us	0	60	0.00
	hmac_test_hmac512_vectors	1.577s	0.000us	0	75	0.00
	hmac_stress_all	1155.000s	91858.423us	50	50	100.00
stress_all				50	50	100.00
	hmac_stress_all	1155.000s	91858.423us	50	50	100.00
alert_test				0	10	0.00
	hmac_alert_test	0.859s	0.000us	0	10	0.00
intr_test				0	10	0.00
	hmac_intr_test	0.880s	0.000us	0	10	0.00
tl_d_oob_addr_access				0	25	0.00
	hmac_tl_errors	1.539s	0.000us	0	25	0.00
tl_d_illegal_access				0	25	0.00
	hmac_tl_errors	1.539s	0.000us	0	25	0.00
tl_d_outstanding_access				0	12	0.00
	hmac_csr_hw_reset	0.686s	0.000us	0	1	0.00
	hmac_csr_rw	0.848s	0.000us	0	5	0.00
	hmac_csr_aliasing	0.826s	0.000us	0	1	0.00
	hmac_same_csr_outstanding	0.844s	0.000us	0	5	0.00
tl_d_partial_access				0	12	0.00
	hmac_csr_hw_reset	0.686s	0.000us	0	1	0.00
	hmac_csr_rw	0.848s	0.000us	0	5	0.00
	hmac_csr_aliasing	0.826s	0.000us	0	1	0.00
	hmac_same_csr_outstanding	0.844s	0.000us	0	5	0.00

V2S

0/30 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
tl_intg_err				30
	hmac_sec_cm	0.813s	0.000us	5
	hmac_tl_intg_err	1.508s	0.000us	25
sec_cm_bus_integrity				25
	hmac_tl_intg_err	1.508s	0.000us	25

0/70 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
write_config_and_secret_key_during_msg_wr				10
	hmac_smoke	1.485s	0.000us	10
stress_reset				25
	hmac_stress_reset	1.477s	0.000us	25
stress_all_with_rand_reset				35
	hmac_stress_all_with_rand_reset	1.522s	0.000us	35

unmapped

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				0	1	0.00
	hmac_directed	0.666s	0.000us	0	1	0.00

Error Messages

	Test	seed	line	log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				644 test runs
	hmac_smoke	68163815580680943867747436825357391129801289670543678306757258943765157012269	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/default/xcelium.d -r tb +SVSEED=2532336429 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/default/0.hmac_smoke.2532336429 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope default -covtest 0.hmac_smoke.2532336429 -covoverwrite' seed=68163815580680943867747436825357391129801289670543678306757258943765157012269 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68163815580680943867747436825357391129801289670543678306757258943765157012269 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_smoke_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_long_msg	23245407421478180631103066523296895914227840563798592996837817124118761665388	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_long_msg/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/default/xcelium.d -r tb +SVSEED=883258220 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/default/0.hmac_long_msg.883258220 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope default -covtest 0.hmac_long_msg.883258220 -covoverwrite' seed=23245407421478180631103066523296895914227840563798592996837817124118761665388 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23245407421478180631103066523296895914227840563798592996837817124118761665388 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_long_msg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_long_msg_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_stress_reset	84908996382163434958968441814977487611865583752555837446537743514592509013518	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_stress_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/default/xcelium.d -r tb +SVSEED=2085989902 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/default/0.hmac_stress_reset.2085989902 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope default -covtest 0.hmac_stress_reset.2085989902 -covoverwrite' seed=84908996382163434958968441814977487611865583752555837446537743514592509013518 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84908996382163434958968441814977487611865583752555837446537743514592509013518 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_stress_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_stress_reset_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_back_pressure	113475339292477195366009503233536161271607395841363593033192539968089532946136	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_back_pressure/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/default/xcelium.d -r tb +SVSEED=1028151000 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/default/0.hmac_back_pressure.1028151000 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope default -covtest 0.hmac_back_pressure.1028151000 -covoverwrite' seed=113475339292477195366009503233536161271607395841363593033192539968089532946136 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113475339292477195366009503233536161271607395841363593033192539968089532946136 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_back_pressure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_back_pressure_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_datapath_stress	15005608285170479256712494032582663638823958942147574588881231697184360035049	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_datapath_stress/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/default/xcelium.d -r tb +SVSEED=2917200617 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/default/0.hmac_datapath_stress.2917200617 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope default -covtest 0.hmac_datapath_stress.2917200617 -covoverwrite' seed=15005608285170479256712494032582663638823958942147574588881231697184360035049 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15005608285170479256712494032582663638823958942147574588881231697184360035049 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_datapath_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_datapath_stress_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_burst_wr	74699632631806994830659245624366298758232096832177606509407481778488755357471	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_burst_wr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/default/xcelium.d -r tb +SVSEED=3972794143 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/default/0.hmac_burst_wr.3972794143 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope default -covtest 0.hmac_burst_wr.3972794143 -covoverwrite' seed=74699632631806994830659245624366298758232096832177606509407481778488755357471 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74699632631806994830659245624366298758232096832177606509407481778488755357471 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_burst_wr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_burst_wr_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_error	114656525952730582628664167261459939835767796572531731717207572111600774041839	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_error/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/default/xcelium.d -r tb +SVSEED=318787823 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/default/0.hmac_error.318787823 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope default -covtest 0.hmac_error.318787823 -covoverwrite' seed=114656525952730582628664167261459939835767796572531731717207572111600774041839 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114656525952730582628664167261459939835767796572531731717207572111600774041839 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_error_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_wipe_secret	35115467744237881212595567298222018371323020931997644330244648805826530765929	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_wipe_secret/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/default/xcelium.d -r tb +SVSEED=69332073 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/default/0.hmac_wipe_secret.69332073 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope default -covtest 0.hmac_wipe_secret.69332073 -covoverwrite' seed=35115467744237881212595567298222018371323020931997644330244648805826530765929 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35115467744237881212595567298222018371323020931997644330244648805826530765929 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_wipe_secret/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_wipe_secret_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_test_sha256_vectors	113727117471387621055023568547076710715705891856400054846803845374302226564755	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_test_sha256_vectors/latest run_opts='+is_nist_test=1 +test_vectors_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=500_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/default/xcelium.d -r tb +SVSEED=601966227 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/default/0.hmac_test_sha256_vectors.601966227 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope default -covtest 0.hmac_test_sha256_vectors.601966227 -covoverwrite' seed=113727117471387621055023568547076710715705891856400054846803845374302226564755 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113727117471387621055023568547076710715705891856400054846803845374302226564755 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_test_sha256_vectors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_test_vectors_sha_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_test_sha384_vectors	29195930187413095842028311413812168008476751583766025974601169488345855144571	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_test_sha384_vectors/latest run_opts='+is_nist_test=1 +test_vectors_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=750_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/default/xcelium.d -r tb +SVSEED=1338487419 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/default/0.hmac_test_sha384_vectors.1338487419 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope default -covtest 0.hmac_test_sha384_vectors.1338487419 -covoverwrite' seed=29195930187413095842028311413812168008476751583766025974601169488345855144571 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29195930187413095842028311413812168008476751583766025974601169488345855144571 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_test_sha384_vectors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_test_vectors_sha_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_test_sha512_vectors	6205140186354263980594793521793328098669570897384977723911037183573052182839	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_test_sha512_vectors/latest run_opts='+is_nist_test=1 +test_vectors_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=750_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/default/xcelium.d -r tb +SVSEED=1526550839 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/default/0.hmac_test_sha512_vectors.1526550839 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope default -covtest 0.hmac_test_sha512_vectors.1526550839 -covoverwrite' seed=6205140186354263980594793521793328098669570897384977723911037183573052182839 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6205140186354263980594793521793328098669570897384977723911037183573052182839 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_test_sha512_vectors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_test_vectors_sha_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_test_hmac256_vectors	31110427400178678930179586983463983271700833346138506184166977303451999245809	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_test_hmac256_vectors/latest run_opts='+is_nist_test=1 +test_vectors_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=500_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/default/xcelium.d -r tb +SVSEED=503682545 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/default/0.hmac_test_hmac256_vectors.503682545 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope default -covtest 0.hmac_test_hmac256_vectors.503682545 -covoverwrite' seed=31110427400178678930179586983463983271700833346138506184166977303451999245809 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31110427400178678930179586983463983271700833346138506184166977303451999245809 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_test_hmac256_vectors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_test_vectors_hmac_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_test_hmac384_vectors	91943390503155693279924773013307571466382670207971273645070757502283067219290	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_test_hmac384_vectors/latest run_opts='+is_nist_test=1 +test_vectors_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=750_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/default/xcelium.d -r tb +SVSEED=977067354 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/default/0.hmac_test_hmac384_vectors.977067354 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope default -covtest 0.hmac_test_hmac384_vectors.977067354 -covoverwrite' seed=91943390503155693279924773013307571466382670207971273645070757502283067219290 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91943390503155693279924773013307571466382670207971273645070757502283067219290 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_test_hmac384_vectors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_test_vectors_hmac_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_test_hmac512_vectors	107719070270970646080741110038470122516531575862505839537294894153075497804080	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_test_hmac512_vectors/latest run_opts='+is_nist_test=1 +test_vectors_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=750_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/default/xcelium.d -r tb +SVSEED=559325488 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/default/0.hmac_test_hmac512_vectors.559325488 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope default -covtest 0.hmac_test_hmac512_vectors.559325488 -covoverwrite' seed=107719070270970646080741110038470122516531575862505839537294894153075497804080 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107719070270970646080741110038470122516531575862505839537294894153075497804080 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_test_hmac512_vectors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_test_vectors_hmac_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_stress_all_with_rand_reset	119455751148427468806692197282914187081047160490552982001865339635201090095	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=hmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/default/xcelium.d -r tb +SVSEED=392045103 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/default/0.hmac_stress_all_with_rand_reset.392045103 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope default -covtest 0.hmac_stress_all_with_rand_reset.392045103 -covoverwrite' seed=119455751148427468806692197282914187081047160490552982001865339635201090095 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=119455751148427468806692197282914187081047160490552982001865339635201090095 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_directed	86557302669834672794018741699291281671969623412499876868560969110283397039362	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_directed/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/default/xcelium.d -r tb +SVSEED=860816642 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_directed_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/default/0.hmac_directed.860816642 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope default -covtest 0.hmac_directed.860816642 -covoverwrite' seed=86557302669834672794018741699291281671969623412499876868560969110283397039362 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86557302669834672794018741699291281671969623412499876868560969110283397039362 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_directed/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_directed_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_sec_cm	33916142959253179789254256427687934896346014525211269110750458270031225587194	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/default/xcelium.d -r tb +SVSEED=186680826 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/default/0.hmac_sec_cm.186680826 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope default -covtest 0.hmac_sec_cm.186680826 -covoverwrite' seed=33916142959253179789254256427687934896346014525211269110750458270031225587194 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33916142959253179789254256427687934896346014525211269110750458270031225587194 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_tl_errors	35843025744127874481708224149567945475470123880008665212562561235206546680958	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2964352126 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/cover_reg_top/0.hmac_tl_errors.2964352126 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.hmac_tl_errors.2964352126 -covoverwrite' seed=35843025744127874481708224149567945475470123880008665212562561235206546680958 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35843025744127874481708224149567945475470123880008665212562561235206546680958 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_tl_intg_err	67686502016096218332859496129603363261513046034425314659730845510179028557851	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3187761179 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/cover_reg_top/0.hmac_tl_intg_err.3187761179 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.hmac_tl_intg_err.3187761179 -covoverwrite' seed=67686502016096218332859496129603363261513046034425314659730845510179028557851 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67686502016096218332859496129603363261513046034425314659730845510179028557851 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_intr_test	79892614507608921120606095703454884145932618394943857430619085442496800811141	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1192552581 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/cover_reg_top/0.hmac_intr_test.1192552581 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.hmac_intr_test.1192552581 -covoverwrite' seed=79892614507608921120606095703454884145932618394943857430619085442496800811141 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79892614507608921120606095703454884145932618394943857430619085442496800811141 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_alert_test	12385648876597339016563119120735677044902508495710839677532048713601284916031	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/default/xcelium.d -r tb +SVSEED=2487305023 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/default/0.hmac_alert_test.2487305023 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope default -covtest 0.hmac_alert_test.2487305023 -covoverwrite' seed=12385648876597339016563119120735677044902508495710839677532048713601284916031 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12385648876597339016563119120735677044902508495710839677532048713601284916031 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_csr_hw_reset	25286509143868353816852683601528569308113057897051545062609510450523662691686	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_csr_hw_reset/latest run_opts='+csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1391963494 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/cover_reg_top/0.hmac_csr_hw_reset.1391963494 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.hmac_csr_hw_reset.1391963494 -covoverwrite' seed=25286509143868353816852683601528569308113057897051545062609510450523662691686 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25286509143868353816852683601528569308113057897051545062609510450523662691686 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_csr_rw	17936759567615289846239952198668204111729779130720695696234051238608091554959	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1971135631 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/cover_reg_top/0.hmac_csr_rw.1971135631 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.hmac_csr_rw.1971135631 -covoverwrite' seed=17936759567615289846239952198668204111729779130720695696234051238608091554959 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17936759567615289846239952198668204111729779130720695696234051238608091554959 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_csr_bit_bash	54492038229965085797669919365906499038051077070440556303565231687060689033845	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_csr_bit_bash/latest run_opts='+csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1384159861 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/cover_reg_top/0.hmac_csr_bit_bash.1384159861 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.hmac_csr_bit_bash.1384159861 -covoverwrite' seed=54492038229965085797669919365906499038051077070440556303565231687060689033845 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54492038229965085797669919365906499038051077070440556303565231687060689033845 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_csr_aliasing	37337852757878723445814029647413124111652524533586960148168941535589758374676	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_csr_aliasing/latest run_opts='+csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=17797908 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/cover_reg_top/0.hmac_csr_aliasing.17797908 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.hmac_csr_aliasing.17797908 -covoverwrite' seed=37337852757878723445814029647413124111652524533586960148168941535589758374676 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37337852757878723445814029647413124111652524533586960148168941535589758374676 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_same_csr_outstanding	43610186327203449599999727771442860549059325010330978636654004910397055142622	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1092979422 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/cover_reg_top/0.hmac_same_csr_outstanding.1092979422 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.hmac_same_csr_outstanding.1092979422 -covoverwrite' seed=43610186327203449599999727771442860549059325010330978636654004910397055142622 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43610186327203449599999727771442860549059325010330978636654004910397055142622 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_csr_mem_rw_with_rand_reset	104507696163835640814039934252680445043816263140674189339175065940507662109939	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3216919795 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/cover_reg_top/0.hmac_csr_mem_rw_with_rand_reset.3216919795 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.hmac_csr_mem_rw_with_rand_reset.3216919795 -covoverwrite' seed=104507696163835640814039934252680445043816263140674189339175065940507662109939 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104507696163835640814039934252680445043816263140674189339175065940507662109939 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/0.hmac_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_smoke	31746630611472526400131358196475972570994858972300434630160377982853576631940	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/1.hmac_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/default/xcelium.d -r tb +SVSEED=1692378756 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/default/1.hmac_smoke.1692378756 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope default -covtest 1.hmac_smoke.1692378756 -covoverwrite' seed=31746630611472526400131358196475972570994858972300434630160377982853576631940 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31746630611472526400131358196475972570994858972300434630160377982853576631940 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/1.hmac_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_smoke_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_long_msg	47510180529630650884350668177272642249449845447020619571907007140123006081922	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/1.hmac_long_msg/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/default/xcelium.d -r tb +SVSEED=949623682 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_long_msg_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/default/1.hmac_long_msg.949623682 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope default -covtest 1.hmac_long_msg.949623682 -covoverwrite' seed=47510180529630650884350668177272642249449845447020619571907007140123006081922 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47510180529630650884350668177272642249449845447020619571907007140123006081922 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/1.hmac_long_msg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_long_msg_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_stress_reset	14790549034781144528456532032354746480566955040425578195939598824691721376240	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/1.hmac_stress_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/default/xcelium.d -r tb +SVSEED=2725581296 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_stress_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/default/1.hmac_stress_reset.2725581296 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope default -covtest 1.hmac_stress_reset.2725581296 -covoverwrite' seed=14790549034781144528456532032354746480566955040425578195939598824691721376240 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=14790549034781144528456532032354746480566955040425578195939598824691721376240 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/1.hmac_stress_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_stress_reset_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_back_pressure	70029638832837749932148850753477113854007461035686425809908992623675780888212	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/1.hmac_back_pressure/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/default/xcelium.d -r tb +SVSEED=1306523284 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_back_pressure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/default/1.hmac_back_pressure.1306523284 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope default -covtest 1.hmac_back_pressure.1306523284 -covoverwrite' seed=70029638832837749932148850753477113854007461035686425809908992623675780888212 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70029638832837749932148850753477113854007461035686425809908992623675780888212 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/1.hmac_back_pressure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_back_pressure_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_datapath_stress	95383875768055158793921040567123738431929127956920268049227292257719527445266	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/1.hmac_datapath_stress/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/default/xcelium.d -r tb +SVSEED=1234735890 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_datapath_stress_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/default/1.hmac_datapath_stress.1234735890 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope default -covtest 1.hmac_datapath_stress.1234735890 -covoverwrite' seed=95383875768055158793921040567123738431929127956920268049227292257719527445266 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95383875768055158793921040567123738431929127956920268049227292257719527445266 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/1.hmac_datapath_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_datapath_stress_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_burst_wr	112508278463763702418038116985292718214394555215182755031965361179791589086986	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/1.hmac_burst_wr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/default/xcelium.d -r tb +SVSEED=3456866058 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_burst_wr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/default/1.hmac_burst_wr.3456866058 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope default -covtest 1.hmac_burst_wr.3456866058 -covoverwrite' seed=112508278463763702418038116985292718214394555215182755031965361179791589086986 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112508278463763702418038116985292718214394555215182755031965361179791589086986 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/1.hmac_burst_wr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_burst_wr_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_error	47392947971486550830244204893517402077042015141551440950029529624173771509105	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/1.hmac_error/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/default/xcelium.d -r tb +SVSEED=2989510001 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_error_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/default/1.hmac_error.2989510001 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope default -covtest 1.hmac_error.2989510001 -covoverwrite' seed=47392947971486550830244204893517402077042015141551440950029529624173771509105 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47392947971486550830244204893517402077042015141551440950029529624173771509105 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/1.hmac_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_error_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_wipe_secret	6955217937586348992610506789944421625734220502228282939153352167582598770750	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/1.hmac_wipe_secret/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/default/xcelium.d -r tb +SVSEED=131674174 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_wipe_secret_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/default/1.hmac_wipe_secret.131674174 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope default -covtest 1.hmac_wipe_secret.131674174 -covoverwrite' seed=6955217937586348992610506789944421625734220502228282939153352167582598770750 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6955217937586348992610506789944421625734220502228282939153352167582598770750 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/1.hmac_wipe_secret/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_wipe_secret_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_test_sha256_vectors	4316371737667104782155179487473048509085526144917873881250049956809202734934	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/1.hmac_test_sha256_vectors/latest run_opts='+is_nist_test=1 +test_vectors_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=500_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/default/xcelium.d -r tb +SVSEED=3085702998 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/default/1.hmac_test_sha256_vectors.3085702998 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope default -covtest 1.hmac_test_sha256_vectors.3085702998 -covoverwrite' seed=4316371737667104782155179487473048509085526144917873881250049956809202734934 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4316371737667104782155179487473048509085526144917873881250049956809202734934 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/1.hmac_test_sha256_vectors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_test_vectors_sha_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_test_sha384_vectors	96894705950699353680566475864080434693219322523375933486302772610618887666783	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/1.hmac_test_sha384_vectors/latest run_opts='+is_nist_test=1 +test_vectors_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=750_000_000 +sha2_digest_size=SHA2_384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/default/xcelium.d -r tb +SVSEED=691436639 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/default/1.hmac_test_sha384_vectors.691436639 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope default -covtest 1.hmac_test_sha384_vectors.691436639 -covoverwrite' seed=96894705950699353680566475864080434693219322523375933486302772610618887666783 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96894705950699353680566475864080434693219322523375933486302772610618887666783 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/1.hmac_test_sha384_vectors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_test_vectors_sha_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_test_sha512_vectors	76387827593231017478358448034181012124571293886162014827682996470077378875687	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/1.hmac_test_sha512_vectors/latest run_opts='+is_nist_test=1 +test_vectors_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=750_000_000 +sha2_digest_size=SHA2_512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/default/xcelium.d -r tb +SVSEED=3166785831 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_sha_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/default/1.hmac_test_sha512_vectors.3166785831 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope default -covtest 1.hmac_test_sha512_vectors.3166785831 -covoverwrite' seed=76387827593231017478358448034181012124571293886162014827682996470077378875687 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76387827593231017478358448034181012124571293886162014827682996470077378875687 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/1.hmac_test_sha512_vectors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_test_vectors_sha_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	hmac_test_hmac256_vectors	89592780301005545918167120091099157243891923987641496096748399126081027088079	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/1.hmac_test_hmac256_vectors/latest run_opts='+is_nist_test=1 +test_vectors_dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=500_000_000 +sha2_digest_size=SHA2_256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/hmac-sim-xcelium/default/xcelium.d -r tb +SVSEED=2221317839 +UVM_TESTNAME=hmac_base_test +UVM_TEST_SEQ=hmac_test_vectors_hmac_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage/default/1.hmac_test_hmac256_vectors.2221317839 -covworkdir /nightly/current_run/scratch/master/hmac-sim-xcelium/coverage -covscope default -covtest 1.hmac_test_hmac256_vectors.2221317839 -covoverwrite' seed=89592780301005545918167120091099157243891923987641496096748399126081027088079 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89592780301005545918167120091099157243891923987641496096748399126081027088079 --run-dir=/nightly/current_run/scratch/master/hmac-sim-xcelium/1.hmac_test_hmac256_vectors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=hmac_base_test uvm_test_seq=hmac_test_vectors_hmac_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126