Simulation Results: i2c

 
28/08/2026 21:54:34 DVSim: v1.49.0 sha: a099412 json Branch: master Tool: xcelium [unknown]
Validation stages
V1
0.00%
V2
0.00%
V2S
0.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
host_smoke 0 5 0.00
i2c_host_smoke 0.819s 0.000us 0 5 0.00
target_smoke 0 5 0.00
i2c_target_smoke 1.500s 0.000us 0 5 0.00
csr_hw_reset 0 1 0.00
i2c_csr_hw_reset 0.846s 0.000us 0 1 0.00
csr_rw 0 5 0.00
i2c_csr_rw 0.844s 0.000us 0 5 0.00
csr_bit_bash 0 1 0.00
i2c_csr_bit_bash 0.801s 0.000us 0 1 0.00
csr_aliasing 0 1 0.00
i2c_csr_aliasing 0.827s 0.000us 0 1 0.00
csr_mem_rw_with_rand_reset 0 5 0.00
i2c_csr_mem_rw_with_rand_reset 1.531s 0.000us 0 5 0.00
regwen_csr_and_corresponding_lockable_csr 0 6 0.00
i2c_csr_rw 0.844s 0.000us 0 5 0.00
i2c_csr_aliasing 0.827s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_error_intr 0 50 0.00
i2c_host_error_intr 1.918s 0.000us 0 50 0.00
host_stress_all 0 30 0.00
i2c_host_stress_all 1.540s 0.000us 0 30 0.00
host_maxperf 0 5 0.00
i2c_host_perf 0.841s 0.000us 0 5 0.00
host_override 0 50 0.00
i2c_host_override 1.455s 0.000us 0 50 0.00
host_fifo_watermark 0 5 0.00
i2c_host_fifo_watermark 0.972s 0.000us 0 5 0.00
host_fifo_overflow 0 5 0.00
i2c_host_fifo_overflow 0.846s 0.000us 0 5 0.00
host_fifo_reset 0 35 0.00
i2c_host_fifo_reset_fmt 1.863s 0.000us 0 25 0.00
i2c_host_fifo_fmt_empty 0.878s 0.000us 0 5 0.00
i2c_host_fifo_reset_rx 1.482s 0.000us 0 5 0.00
host_fifo_full 0 5 0.00
i2c_host_fifo_full 0.816s 0.000us 0 5 0.00
host_timeout 0 5 0.00
i2c_host_stretch_timeout 0.825s 0.000us 0 5 0.00
i2c_host_mode_toggle 0 50 0.00
i2c_host_mode_toggle 1.613s 0.000us 0 50 0.00
target_glitch 0 2 0.00
i2c_target_glitch 0.868s 0.000us 0 2 0.00
target_stress_all 0 30 0.00
i2c_target_stress_all 1.494s 0.000us 0 30 0.00
target_maxperf 0 5 0.00
i2c_target_perf 1.347s 0.000us 0 5 0.00
target_fifo_empty 0 10 0.00
i2c_target_stress_rd 1.552s 0.000us 0 5 0.00
i2c_target_intr_smoke 0.826s 0.000us 0 5 0.00
target_fifo_reset 0 55 0.00
i2c_target_fifo_reset_acq 1.070s 0.000us 0 5 0.00
i2c_target_fifo_reset_tx 1.474s 0.000us 0 50 0.00
target_fifo_full 0 15 0.00
i2c_target_stress_wr 1.500s 0.000us 0 5 0.00
i2c_target_stress_rd 1.552s 0.000us 0 5 0.00
i2c_target_intr_stress_wr 0.876s 0.000us 0 5 0.00
target_timeout 0 5 0.00
i2c_target_timeout 1.133s 0.000us 0 5 0.00
target_clock_stretch 0 5 0.00
i2c_target_stretch 1.378s 0.000us 0 5 0.00
bad_address 0 5 0.00
i2c_target_bad_addr 0.837s 0.000us 0 5 0.00
target_mode_glitch 0 50 0.00
i2c_target_hrst 1.855s 0.000us 0 50 0.00
target_fifo_watermark 0 10 0.00
i2c_target_fifo_watermarks_acq 0.841s 0.000us 0 5 0.00
i2c_target_fifo_watermarks_tx 1.345s 0.000us 0 5 0.00
host_mode_config_perf 0 10 0.00
i2c_host_perf 0.841s 0.000us 0 5 0.00
i2c_host_perf_precise 0.841s 0.000us 0 5 0.00
host_mode_clock_stretching 0 5 0.00
i2c_host_stretch_timeout 0.825s 0.000us 0 5 0.00
target_mode_tx_stretch_ctrl 0 5 0.00
i2c_target_tx_stretch_ctrl 0.839s 0.000us 0 5 0.00
target_mode_nack_generation 0 130 0.00
i2c_target_nack_acqfull 1.372s 0.000us 0 50 0.00
i2c_target_nack_acqfull_addr 1.519s 0.000us 0 50 0.00
i2c_target_nack_txstretch 1.348s 0.000us 0 30 0.00
host_mode_halt_on_nak 0 50 0.00
i2c_host_may_nack 1.502s 0.000us 0 50 0.00
target_mode_smbus_maxlen 0 5 0.00
i2c_target_smbus_maxlen 0.838s 0.000us 0 5 0.00
alert_test 0 10 0.00
i2c_alert_test 0.851s 0.000us 0 10 0.00
intr_test 0 10 0.00
i2c_intr_test 1.100s 0.000us 0 10 0.00
tl_d_oob_addr_access 0 25 0.00
i2c_tl_errors 1.513s 0.000us 0 25 0.00
tl_d_illegal_access 0 25 0.00
i2c_tl_errors 1.513s 0.000us 0 25 0.00
tl_d_outstanding_access 0 12 0.00
i2c_csr_hw_reset 0.846s 0.000us 0 1 0.00
i2c_csr_rw 0.844s 0.000us 0 5 0.00
i2c_csr_aliasing 0.827s 0.000us 0 1 0.00
i2c_same_csr_outstanding 1.362s 0.000us 0 5 0.00
tl_d_partial_access 0 12 0.00
i2c_csr_hw_reset 0.846s 0.000us 0 1 0.00
i2c_csr_rw 0.844s 0.000us 0 5 0.00
i2c_csr_aliasing 0.827s 0.000us 0 1 0.00
i2c_same_csr_outstanding 1.362s 0.000us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 30 0.00
i2c_tl_intg_err 0.955s 0.000us 0 25 0.00
i2c_sec_cm 1.512s 0.000us 0 5 0.00
sec_cm_bus_integrity 0 25 0.00
i2c_tl_intg_err 0.955s 0.000us 0 25 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
host_stress_all_with_rand_reset 0 10 0.00
i2c_host_stress_all_with_rand_reset 1.588s 0.000us 0 10 0.00
target_error_intr 0 10 0.00
i2c_target_unexp_stop 0.892s 0.000us 0 10 0.00
target_stress_all_with_rand_reset 0 10 0.00
i2c_target_stress_all_with_rand_reset 0.902s 0.000us 0 10 0.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 755 test runs
i2c_host_smoke 1175367695251945334132065980940609039236757504649227161878429637707913437745 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=417538609 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_host_smoke.417538609 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_host_smoke.417538609 -covoverwrite' seed=1175367695251945334132065980940609039236757504649227161878429637707913437745 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1175367695251945334132065980940609039236757504649227161878429637707913437745 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 82882446440006931461214186899359555819284333645637795738369471699497973975383 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1289488727 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_host_override.1289488727 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_host_override.1289488727 -covoverwrite' seed=82882446440006931461214186899359555819284333645637795738369471699497973975383 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82882446440006931461214186899359555819284333645637795738369471699497973975383 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_watermark 75592379008544091705826551643058499463542534299325181414249589077151304181677 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_fifo_watermark/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1087170477 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_host_fifo_watermark.1087170477 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_host_fifo_watermark.1087170477 -covoverwrite' seed=75592379008544091705826551643058499463542534299325181414249589077151304181677 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75592379008544091705826551643058499463542534299325181414249589077151304181677 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_fifo_watermark/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_watermark_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_overflow 62054448336155380441943182466382591795413830852685317512989610428731478070905 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_fifo_overflow/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2261079673 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_host_fifo_overflow.2261079673 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_host_fifo_overflow.2261079673 -covoverwrite' seed=62054448336155380441943182466382591795413830852685317512989610428731478070905 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62054448336155380441943182466382591795413830852685317512989610428731478070905 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_fifo_overflow/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_overflow_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_reset_fmt 107491724270858551543968846517451522151643861675784949747287667826901896031853 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_fifo_reset_fmt/latest run_opts='+test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3320999533 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_host_fifo_reset_fmt.3320999533 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_host_fifo_reset_fmt.3320999533 -covoverwrite' seed=107491724270858551543968846517451522151643861675784949747287667826901896031853 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107491724270858551543968846517451522151643861675784949747287667826901896031853 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_fifo_reset_fmt/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_reset_fmt_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_fmt_empty 79027290377146340607508142749580771370301797497036309353935461377400532454109 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_fifo_fmt_empty/latest run_opts='+test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2952612573 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_host_fifo_fmt_empty.2952612573 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_host_fifo_fmt_empty.2952612573 -covoverwrite' seed=79027290377146340607508142749580771370301797497036309353935461377400532454109 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79027290377146340607508142749580771370301797497036309353935461377400532454109 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_fifo_fmt_empty/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_fmt_empty_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_reset_rx 96784847506428490733979162440060921807833715569285004402778289842455587036252 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_fifo_reset_rx/latest run_opts='+test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3611270236 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_host_fifo_reset_rx.3611270236 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_host_fifo_reset_rx.3611270236 -covoverwrite' seed=96784847506428490733979162440060921807833715569285004402778289842455587036252 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96784847506428490733979162440060921807833715569285004402778289842455587036252 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_fifo_reset_rx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_reset_rx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_full 52499711737747561098914732060451938058247925969930390521192455600369380330081 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_fifo_full/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=890473057 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_host_fifo_full.890473057 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_host_fifo_full.890473057 -covoverwrite' seed=52499711737747561098914732060451938058247925969930390521192455600369380330081 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=52499711737747561098914732060451938058247925969930390521192455600369380330081 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_fifo_full/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_full_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_perf 58572188086885627114790060964770892796992876258089680902694057917095776208153 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_perf/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2969683225 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_host_perf.2969683225 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_host_perf.2969683225 -covoverwrite' seed=58572188086885627114790060964770892796992876258089680902694057917095776208153 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58572188086885627114790060964770892796992876258089680902694057917095776208153 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_perf/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_perf_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_perf_precise 33779350154726756258904177502518147078582861673358384418518894176803940902857 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_perf_precise/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=853714889 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_host_perf_precise.853714889 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_host_perf_precise.853714889 -covoverwrite' seed=33779350154726756258904177502518147078582861673358384418518894176803940902857 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33779350154726756258904177502518147078582861673358384418518894176803940902857 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_perf_precise/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_perf_precise_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stretch_timeout 20086566002417639262587891557259356386211840908892903456130328523076289051717 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_stretch_timeout/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=595737669 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_host_stretch_timeout.595737669 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_host_stretch_timeout.595737669 -covoverwrite' seed=20086566002417639262587891557259356386211840908892903456130328523076289051717 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20086566002417639262587891557259356386211840908892903456130328523076289051717 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_stretch_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_stretch_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 102162279787282961070560038803714361293233965176294515130389502943644084475515 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=451286651 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_host_error_intr.451286651 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_host_error_intr.451286651 -covoverwrite' seed=102162279787282961070560038803714361293233965176294515130389502943644084475515 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102162279787282961070560038803714361293233965176294515130389502943644084475515 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all 108630567119818275585031411908009879336072153777390824019257147206080132997159 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3697205287 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_host_stress_all.3697205287 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_host_stress_all.3697205287 -covoverwrite' seed=108630567119818275585031411908009879336072153777390824019257147206080132997159 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108630567119818275585031411908009879336072153777390824019257147206080132997159 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_glitch 60974876129501939166494098175159237105608194102882648238792012891973734751915 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_glitch/latest run_opts='+i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3104431787 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_target_glitch.3104431787 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_target_glitch.3104431787 -covoverwrite' seed=60974876129501939166494098175159237105608194102882648238792012891973734751915 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60974876129501939166494098175159237105608194102882648238792012891973734751915 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_glitch/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_glitch_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_smoke 23026538903791371682816741862236086831286611476149774926788897058086831510445 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_smoke/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=353096621 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_target_smoke.353096621 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_target_smoke.353096621 -covoverwrite' seed=23026538903791371682816741862236086831286611476149774926788897058086831510445 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23026538903791371682816741862236086831286611476149774926788897058086831510445 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_wr 53365205166666864155408734515177995686530411677260048381327255413049979024254 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_stress_wr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=131838846 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_target_stress_wr.131838846 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_target_stress_wr.131838846 -covoverwrite' seed=53365205166666864155408734515177995686530411677260048381327255413049979024254 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53365205166666864155408734515177995686530411677260048381327255413049979024254 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_stress_wr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_wr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_rd 43030799630528804980199269763438870175241137716993263470650934923690344978394 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_stress_rd/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2747537370 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_target_stress_rd.2747537370 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_target_stress_rd.2747537370 -covoverwrite' seed=43030799630528804980199269763438870175241137716993263470650934923690344978394 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43030799630528804980199269763438870175241137716993263470650934923690344978394 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_stress_rd/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_rd_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stretch 83580217584093067046292713074916299243392698958432549914365092094244442953924 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_stretch/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4222965956 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_target_stretch.4222965956 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_target_stretch.4222965956 -covoverwrite' seed=83580217584093067046292713074916299243392698958432549914365092094244442953924 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83580217584093067046292713074916299243392698958432549914365092094244442953924 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_stretch/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stretch_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_intr_smoke 78992404302880901011900796874781033009270472894977742824333766492791260582038 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_intr_smoke/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3490713750 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_target_intr_smoke.3490713750 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_target_intr_smoke.3490713750 -covoverwrite' seed=78992404302880901011900796874781033009270472894977742824333766492791260582038 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78992404302880901011900796874781033009270472894977742824333766492791260582038 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_intr_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_intr_stress_wr 80914510802342663031879638007311123096941209484803582423323816278287351101216 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_intr_stress_wr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3606656800 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_target_intr_stress_wr.3606656800 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_target_intr_stress_wr.3606656800 -covoverwrite' seed=80914510802342663031879638007311123096941209484803582423323816278287351101216 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80914510802342663031879638007311123096941209484803582423323816278287351101216 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_intr_stress_wr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_wr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_timeout 58402408334243556723783010959600519522411723791912594761630402102393503755700 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_timeout/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2748853684 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_target_timeout.2748853684 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_target_timeout.2748853684 -covoverwrite' seed=58402408334243556723783010959600519522411723791912594761630402102393503755700 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58402408334243556723783010959600519522411723791912594761630402102393503755700 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_unexp_stop 29286824608050462140277478771344684806776389011258488247677555459682210559974 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_unexp_stop/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1158297574 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_target_unexp_stop.1158297574 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_target_unexp_stop.1158297574 -covoverwrite' seed=29286824608050462140277478771344684806776389011258488247677555459682210559974 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29286824608050462140277478771344684806776389011258488247677555459682210559974 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_unexp_stop/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_ack_stop_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_acq 81044240437412827227517343768272182982394922169181019552340146825761478185263 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_fifo_reset_acq/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=563646767 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_target_fifo_reset_acq.563646767 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_target_fifo_reset_acq.563646767 -covoverwrite' seed=81044240437412827227517343768272182982394922169181019552340146825761478185263 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81044240437412827227517343768272182982394922169181019552340146825761478185263 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_fifo_reset_acq/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_acq_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 73908010249154819906062360722575420608011441084729554644085537825322405461964 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2917400524 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_target_fifo_reset_tx.2917400524 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_target_fifo_reset_tx.2917400524 -covoverwrite' seed=73908010249154819906062360722575420608011441084729554644085537825322405461964 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73908010249154819906062360722575420608011441084729554644085537825322405461964 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_perf 45284646580471431755088090347361774162809118606019483190604021600713221153546 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_perf/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2619417354 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_target_perf.2619417354 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_target_perf.2619417354 -covoverwrite' seed=45284646580471431755088090347361774162809118606019483190604021600713221153546 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45284646580471431755088090347361774162809118606019483190604021600713221153546 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_perf/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_perf_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all 62420392976957513581676251506934518945130600038954611215974667096174629581758 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_stress_all/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3785978814 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_target_stress_all.3785978814 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_target_stress_all.3785978814 -covoverwrite' seed=62420392976957513581676251506934518945130600038954611215974667096174629581758 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62420392976957513581676251506934518945130600038954611215974667096174629581758 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_bad_addr 13369089529110262328948879759458706758826487085429074440757743638079274927091 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_bad_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3562456051 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_target_bad_addr.3562456051 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_target_bad_addr.3562456051 -covoverwrite' seed=13369089529110262328948879759458706758826487085429074440757743638079274927091 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13369089529110262328948879759458706758826487085429074440757743638079274927091 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_bad_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 6369661126619282769350343829284274755417361078102969123406640379735480322776 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3340880600 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_target_hrst.3340880600 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_target_hrst.3340880600 -covoverwrite' seed=6369661126619282769350343829284274755417361078102969123406640379735480322776 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6369661126619282769350343829284274755417361078102969123406640379735480322776 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all_with_rand_reset 22719445561705460797537718429719003994601386600296744471713344957579950634709 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +stress_seq=i2c_host_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1433220821 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_host_stress_all_with_rand_reset.1433220821 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_host_stress_all_with_rand_reset.1433220821 -covoverwrite' seed=22719445561705460797537718429719003994601386600296744471713344957579950634709 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22719445561705460797537718429719003994601386600296744471713344957579950634709 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all_with_rand_reset 87660949132139913527805729211705101173163650700005930587254093681353408064566 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_stress_all_with_rand_reset/latest run_opts='+i2c_agent_mode=Host +run_stress_all_with_rand_reset +stress_seq=i2c_target_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3356437558 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_target_stress_all_with_rand_reset.3356437558 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_target_stress_all_with_rand_reset.3356437558 -covoverwrite' seed=87660949132139913527805729211705101173163650700005930587254093681353408064566 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87660949132139913527805729211705101173163650700005930587254093681353408064566 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 21398994559513224896414914616821446291313662430616319681050299835707777380988 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=489976444 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_host_mode_toggle.489976444 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_host_mode_toggle.489976444 -covoverwrite' seed=21398994559513224896414914616821446291313662430616319681050299835707777380988 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21398994559513224896414914616821446291313662430616319681050299835707777380988 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 12617684282865004580721912340987315254157791950851588767325268554659591589068 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1192201420 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_host_may_nack.1192201420 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_host_may_nack.1192201420 -covoverwrite' seed=12617684282865004580721912340987315254157791950851588767325268554659591589068 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12617684282865004580721912340987315254157791950851588767325268554659591589068 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_watermarks_acq 113717783549893965418797594080556790459824947126996500386269374650554512273631 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_fifo_watermarks_acq/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3857674463 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_target_fifo_watermarks_acq.3857674463 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_target_fifo_watermarks_acq.3857674463 -covoverwrite' seed=113717783549893965418797594080556790459824947126996500386269374650554512273631 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113717783549893965418797594080556790459824947126996500386269374650554512273631 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_fifo_watermarks_acq/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_watermarks_acq_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_watermarks_tx 10788061313318927642183966106971353860958190205505152107163929605769086987208 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_fifo_watermarks_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2971757512 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_target_fifo_watermarks_tx.2971757512 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_target_fifo_watermarks_tx.2971757512 -covoverwrite' seed=10788061313318927642183966106971353860958190205505152107163929605769086987208 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10788061313318927642183966106971353860958190205505152107163929605769086987208 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_fifo_watermarks_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_watermarks_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_tx_stretch_ctrl 47826873090927418691301503836502333066430338540015806201985445006272727828458 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_tx_stretch_ctrl/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1109870570 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_target_tx_stretch_ctrl.1109870570 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_target_tx_stretch_ctrl.1109870570 -covoverwrite' seed=47826873090927418691301503836502333066430338540015806201985445006272727828458 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47826873090927418691301503836502333066430338540015806201985445006272727828458 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_tx_stretch_ctrl/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_tx_stretch_ctrl_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_smbus_maxlen 11730103292076283076698877898173569094678565774809627472335849432646203310826 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_smbus_maxlen/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1064141546 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_target_smbus_maxlen.1064141546 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_target_smbus_maxlen.1064141546 -covoverwrite' seed=11730103292076283076698877898173569094678565774809627472335849432646203310826 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11730103292076283076698877898173569094678565774809627472335849432646203310826 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_smbus_maxlen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_smbus_maxlen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 114707258657871451708456861057944411264826730172173137679450744124204385704735 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=542513951 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_target_nack_acqfull.542513951 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_target_nack_acqfull.542513951 -covoverwrite' seed=114707258657871451708456861057944411264826730172173137679450744124204385704735 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114707258657871451708456861057944411264826730172173137679450744124204385704735 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 109767905145064149464483129741912351564429336866607643261456220910986801937045 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1569684117 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_target_nack_acqfull_addr.1569684117 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_target_nack_acqfull_addr.1569684117 -covoverwrite' seed=109767905145064149464483129741912351564429336866607643261456220910986801937045 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109767905145064149464483129741912351564429336866607643261456220910986801937045 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_txstretch 5776207340347427606180893328320877349428701018329762823904507447163546630523 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_nack_txstretch/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1694103931 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_target_nack_txstretch.1694103931 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_target_nack_txstretch.1694103931 -covoverwrite' seed=5776207340347427606180893328320877349428701018329762823904507447163546630523 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5776207340347427606180893328320877349428701018329762823904507447163546630523 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_target_nack_txstretch/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_txstretch_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_errors 20291617729978180635397364159302843957229836217291422625366635418549601377027 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=407313155 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/0.i2c_tl_errors.407313155 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.i2c_tl_errors.407313155 -covoverwrite' seed=20291617729978180635397364159302843957229836217291422625366635418549601377027 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20291617729978180635397364159302843957229836217291422625366635418549601377027 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_intg_err 1382272682143133711737439083684434598221520199097564484127495724792897515784 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3894325512 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/0.i2c_tl_intg_err.3894325512 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.i2c_tl_intg_err.3894325512 -covoverwrite' seed=1382272682143133711737439083684434598221520199097564484127495724792897515784 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1382272682143133711737439083684434598221520199097564484127495724792897515784 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_sec_cm 35509811872541580585986495465335763348227417992466467308519427707827182698349 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3927768941 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_sec_cm.3927768941 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_sec_cm.3927768941 -covoverwrite' seed=35509811872541580585986495465335763348227417992466467308519427707827182698349 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35509811872541580585986495465335763348227417992466467308519427707827182698349 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_intr_test 103295960496074234949029391959689859385114553820689094766368611678720085322706 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1675226066 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/0.i2c_intr_test.1675226066 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.i2c_intr_test.1675226066 -covoverwrite' seed=103295960496074234949029391959689859385114553820689094766368611678720085322706 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103295960496074234949029391959689859385114553820689094766368611678720085322706 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_alert_test 57261198840420664760974659688379411810757311316949973287526697278922136189095 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3106109607 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/0.i2c_alert_test.3106109607 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 0.i2c_alert_test.3106109607 -covoverwrite' seed=57261198840420664760974659688379411810757311316949973287526697278922136189095 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57261198840420664760974659688379411810757311316949973287526697278922136189095 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_csr_hw_reset 51151772734803748038491117692558276765701517031941674882925727662404393200325 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_csr_hw_reset/latest run_opts='+csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1003973317 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/0.i2c_csr_hw_reset.1003973317 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.i2c_csr_hw_reset.1003973317 -covoverwrite' seed=51151772734803748038491117692558276765701517031941674882925727662404393200325 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51151772734803748038491117692558276765701517031941674882925727662404393200325 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_csr_rw 100712628678333927525597668453945496664119249183429153431534183613207951023517 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=519413149 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/0.i2c_csr_rw.519413149 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.i2c_csr_rw.519413149 -covoverwrite' seed=100712628678333927525597668453945496664119249183429153431534183613207951023517 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100712628678333927525597668453945496664119249183429153431534183613207951023517 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_csr_bit_bash 72390981791881372453784339383717669018907425364907966367110308235407952141468 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_csr_bit_bash/latest run_opts='+csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=8871068 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/0.i2c_csr_bit_bash.8871068 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.i2c_csr_bit_bash.8871068 -covoverwrite' seed=72390981791881372453784339383717669018907425364907966367110308235407952141468 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72390981791881372453784339383717669018907425364907966367110308235407952141468 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_csr_aliasing 20285469328539447859342054128991858463622059128703828025850030428309055002374 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_csr_aliasing/latest run_opts='+csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=603903750 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/0.i2c_csr_aliasing.603903750 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.i2c_csr_aliasing.603903750 -covoverwrite' seed=20285469328539447859342054128991858463622059128703828025850030428309055002374 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20285469328539447859342054128991858463622059128703828025850030428309055002374 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_same_csr_outstanding 107671427899443266544386516887410931316729713265252667907504080520746176571683 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2443667747 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/0.i2c_same_csr_outstanding.2443667747 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.i2c_same_csr_outstanding.2443667747 -covoverwrite' seed=107671427899443266544386516887410931316729713265252667907504080520746176571683 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107671427899443266544386516887410931316729713265252667907504080520746176571683 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_csr_mem_rw_with_rand_reset 61304423749150750226713822888682766164234554378929232303722918183474237656099 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=872008739 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/0.i2c_csr_mem_rw_with_rand_reset.872008739 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.i2c_csr_mem_rw_with_rand_reset.872008739 -covoverwrite' seed=61304423749150750226713822888682766164234554378929232303722918183474237656099 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61304423749150750226713822888682766164234554378929232303722918183474237656099 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/0.i2c_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_smoke 28001115234725589864380833987243024680944659078905051117654067715907584649293 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_host_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1959913549 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_host_smoke.1959913549 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_host_smoke.1959913549 -covoverwrite' seed=28001115234725589864380833987243024680944659078905051117654067715907584649293 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28001115234725589864380833987243024680944659078905051117654067715907584649293 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_host_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 74000776838133510457863829085075450751210152394308457317780529473179144496166 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3536921638 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_host_override.3536921638 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_host_override.3536921638 -covoverwrite' seed=74000776838133510457863829085075450751210152394308457317780529473179144496166 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74000776838133510457863829085075450751210152394308457317780529473179144496166 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_watermark 107199322696360967941729937374727773347087286907122503661350421113632282418251 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_host_fifo_watermark/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1662819403 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_host_fifo_watermark.1662819403 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_host_fifo_watermark.1662819403 -covoverwrite' seed=107199322696360967941729937374727773347087286907122503661350421113632282418251 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107199322696360967941729937374727773347087286907122503661350421113632282418251 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_host_fifo_watermark/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_watermark_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_overflow 85117092301585376205117423673035050664932769712837116772700111044628994710993 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_host_fifo_overflow/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4251049425 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_host_fifo_overflow.4251049425 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_host_fifo_overflow.4251049425 -covoverwrite' seed=85117092301585376205117423673035050664932769712837116772700111044628994710993 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85117092301585376205117423673035050664932769712837116772700111044628994710993 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_host_fifo_overflow/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_overflow_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_reset_fmt 81196261440719934384836911876971856029637560063263175650252614661607341897782 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_host_fifo_reset_fmt/latest run_opts='+test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3663673398 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_host_fifo_reset_fmt.3663673398 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_host_fifo_reset_fmt.3663673398 -covoverwrite' seed=81196261440719934384836911876971856029637560063263175650252614661607341897782 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81196261440719934384836911876971856029637560063263175650252614661607341897782 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_host_fifo_reset_fmt/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_reset_fmt_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_fmt_empty 110714971142157809253938587733373564604067446114205093574886382665357494684317 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_host_fifo_fmt_empty/latest run_opts='+test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3240725149 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_host_fifo_fmt_empty.3240725149 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_host_fifo_fmt_empty.3240725149 -covoverwrite' seed=110714971142157809253938587733373564604067446114205093574886382665357494684317 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110714971142157809253938587733373564604067446114205093574886382665357494684317 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_host_fifo_fmt_empty/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_fmt_empty_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_reset_rx 101183359415377553871400428554193915800592934274110882514859014655810134005264 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_host_fifo_reset_rx/latest run_opts='+test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1085986320 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_host_fifo_reset_rx.1085986320 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_host_fifo_reset_rx.1085986320 -covoverwrite' seed=101183359415377553871400428554193915800592934274110882514859014655810134005264 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101183359415377553871400428554193915800592934274110882514859014655810134005264 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_host_fifo_reset_rx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_reset_rx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_full 84698779165895817749071936130514397949957229150603099956469886144738881617796 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_host_fifo_full/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=793952132 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_host_fifo_full.793952132 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_host_fifo_full.793952132 -covoverwrite' seed=84698779165895817749071936130514397949957229150603099956469886144738881617796 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84698779165895817749071936130514397949957229150603099956469886144738881617796 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_host_fifo_full/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_full_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_perf 25051743830209005852000753646694527263930544451071666775076794006629247882571 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_host_perf/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=665851211 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_host_perf.665851211 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_host_perf.665851211 -covoverwrite' seed=25051743830209005852000753646694527263930544451071666775076794006629247882571 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25051743830209005852000753646694527263930544451071666775076794006629247882571 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_host_perf/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_perf_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_perf_precise 61075244435688240439468288531236446510562673996873783954730117952742332040215 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_host_perf_precise/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1969488919 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_host_perf_precise.1969488919 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_host_perf_precise.1969488919 -covoverwrite' seed=61075244435688240439468288531236446510562673996873783954730117952742332040215 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61075244435688240439468288531236446510562673996873783954730117952742332040215 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_host_perf_precise/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_perf_precise_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stretch_timeout 30690652154237359994714053601793056720260006597202096290726862359190945155594 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_host_stretch_timeout/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=334252554 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_host_stretch_timeout.334252554 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_host_stretch_timeout.334252554 -covoverwrite' seed=30690652154237359994714053601793056720260006597202096290726862359190945155594 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30690652154237359994714053601793056720260006597202096290726862359190945155594 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_host_stretch_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_stretch_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 5971660005318522715819001360946026474842263949624970903513476031009516201868 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3624707980 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_host_error_intr.3624707980 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_host_error_intr.3624707980 -covoverwrite' seed=5971660005318522715819001360946026474842263949624970903513476031009516201868 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5971660005318522715819001360946026474842263949624970903513476031009516201868 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all 10025395861158842188497152481844936749997506920859152051517517558755529532298 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_host_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2760844170 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_host_stress_all.2760844170 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_host_stress_all.2760844170 -covoverwrite' seed=10025395861158842188497152481844936749997506920859152051517517558755529532298 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10025395861158842188497152481844936749997506920859152051517517558755529532298 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_glitch 73241204040967691312294066968476355565266271067910881176328605771213239845300 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_glitch/latest run_opts='+i2c_agent_mode=Host +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2205254068 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_glitch_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_target_glitch.2205254068 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_target_glitch.2205254068 -covoverwrite' seed=73241204040967691312294066968476355565266271067910881176328605771213239845300 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73241204040967691312294066968476355565266271067910881176328605771213239845300 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_glitch/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_glitch_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_smoke 30995796695360126616320666965688133326797953665756031578331441097679862100318 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_smoke/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2851729758 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_target_smoke.2851729758 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_target_smoke.2851729758 -covoverwrite' seed=30995796695360126616320666965688133326797953665756031578331441097679862100318 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30995796695360126616320666965688133326797953665756031578331441097679862100318 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_wr 53755293910439749529249630216906167833307140783574822408227446329833700042286 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_stress_wr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2567284270 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_target_stress_wr.2567284270 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_target_stress_wr.2567284270 -covoverwrite' seed=53755293910439749529249630216906167833307140783574822408227446329833700042286 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53755293910439749529249630216906167833307140783574822408227446329833700042286 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_stress_wr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_wr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_rd 70069561664967587404903058596198688752615414348767971660964772471026877101114 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_stress_rd/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1884976186 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_target_stress_rd.1884976186 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_target_stress_rd.1884976186 -covoverwrite' seed=70069561664967587404903058596198688752615414348767971660964772471026877101114 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70069561664967587404903058596198688752615414348767971660964772471026877101114 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_stress_rd/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_rd_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stretch 15128220853846765647832308825116276050397416739501921925907909882622151584147 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_stretch/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=152136083 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_target_stretch.152136083 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_target_stretch.152136083 -covoverwrite' seed=15128220853846765647832308825116276050397416739501921925907909882622151584147 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15128220853846765647832308825116276050397416739501921925907909882622151584147 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_stretch/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stretch_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_intr_smoke 5966523041816189864347409569504795284881193359882236867677766612614263774574 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_intr_smoke/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2296028526 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_target_intr_smoke.2296028526 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_target_intr_smoke.2296028526 -covoverwrite' seed=5966523041816189864347409569504795284881193359882236867677766612614263774574 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5966523041816189864347409569504795284881193359882236867677766612614263774574 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_intr_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_intr_stress_wr 50155679880577634008224272828550487980215724014469353652574164960715282640870 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_intr_stress_wr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1594421222 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_target_intr_stress_wr.1594421222 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_target_intr_stress_wr.1594421222 -covoverwrite' seed=50155679880577634008224272828550487980215724014469353652574164960715282640870 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50155679880577634008224272828550487980215724014469353652574164960715282640870 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_intr_stress_wr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_wr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_timeout 90049063135517381173618784984903905829161379523471424534278262974288298597056 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_timeout/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=930175680 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_target_timeout.930175680 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_target_timeout.930175680 -covoverwrite' seed=90049063135517381173618784984903905829161379523471424534278262974288298597056 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90049063135517381173618784984903905829161379523471424534278262974288298597056 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_unexp_stop 40840146158727811004045315137971729369375574930170070647306354999780120980416 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_unexp_stop/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2673601472 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_target_unexp_stop.2673601472 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_target_unexp_stop.2673601472 -covoverwrite' seed=40840146158727811004045315137971729369375574930170070647306354999780120980416 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40840146158727811004045315137971729369375574930170070647306354999780120980416 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_unexp_stop/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_ack_stop_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_acq 110009530882467119793787721456112674592580311771607717704170896178759601940290 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_fifo_reset_acq/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2461722434 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_target_fifo_reset_acq.2461722434 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_target_fifo_reset_acq.2461722434 -covoverwrite' seed=110009530882467119793787721456112674592580311771607717704170896178759601940290 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110009530882467119793787721456112674592580311771607717704170896178759601940290 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_fifo_reset_acq/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_acq_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 6346150095742773739935428444322619182775639180835380492397134584865272630474 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4098624714 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_target_fifo_reset_tx.4098624714 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_target_fifo_reset_tx.4098624714 -covoverwrite' seed=6346150095742773739935428444322619182775639180835380492397134584865272630474 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6346150095742773739935428444322619182775639180835380492397134584865272630474 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_perf 109108847831318167507677899861292543899933264620001267889094786748920214870198 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_perf/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3761002678 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_target_perf.3761002678 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_target_perf.3761002678 -covoverwrite' seed=109108847831318167507677899861292543899933264620001267889094786748920214870198 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109108847831318167507677899861292543899933264620001267889094786748920214870198 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_perf/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_perf_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all 62625601679296757124048786719308820268944281053088900385591671808893681430864 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_stress_all/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1666216272 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_target_stress_all.1666216272 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_target_stress_all.1666216272 -covoverwrite' seed=62625601679296757124048786719308820268944281053088900385591671808893681430864 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62625601679296757124048786719308820268944281053088900385591671808893681430864 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_bad_addr 13248393469700258965966351254318792402566254761018563661559354491978001496300 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_bad_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1643985132 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_target_bad_addr.1643985132 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_target_bad_addr.1643985132 -covoverwrite' seed=13248393469700258965966351254318792402566254761018563661559354491978001496300 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13248393469700258965966351254318792402566254761018563661559354491978001496300 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_bad_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 77959742046701701157916336686546358971621205867945530080131228737015172212692 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=746498004 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_target_hrst.746498004 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_target_hrst.746498004 -covoverwrite' seed=77959742046701701157916336686546358971621205867945530080131228737015172212692 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77959742046701701157916336686546358971621205867945530080131228737015172212692 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all_with_rand_reset 49935898702838673182972324853440636370149817878923566863660440596057786035417 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_host_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +stress_seq=i2c_host_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3002477785 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_host_stress_all_with_rand_reset.3002477785 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_host_stress_all_with_rand_reset.3002477785 -covoverwrite' seed=49935898702838673182972324853440636370149817878923566863660440596057786035417 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49935898702838673182972324853440636370149817878923566863660440596057786035417 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_host_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all_with_rand_reset 24376827741166789724013643470368146797020264138329646502927862710600436313271 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_stress_all_with_rand_reset/latest run_opts='+i2c_agent_mode=Host +run_stress_all_with_rand_reset +stress_seq=i2c_target_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=30698679 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_target_stress_all_with_rand_reset.30698679 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_target_stress_all_with_rand_reset.30698679 -covoverwrite' seed=24376827741166789724013643470368146797020264138329646502927862710600436313271 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24376827741166789724013643470368146797020264138329646502927862710600436313271 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 112829339071542501185925484498422708106370835754453553424274382904374193234521 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2579702361 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_host_mode_toggle.2579702361 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_host_mode_toggle.2579702361 -covoverwrite' seed=112829339071542501185925484498422708106370835754453553424274382904374193234521 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112829339071542501185925484498422708106370835754453553424274382904374193234521 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 115670959302101191966238497162758646593022650799741773055524305473847211231622 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1497532806 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_host_may_nack.1497532806 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_host_may_nack.1497532806 -covoverwrite' seed=115670959302101191966238497162758646593022650799741773055524305473847211231622 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115670959302101191966238497162758646593022650799741773055524305473847211231622 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_watermarks_acq 80514711105206720618847825444942910821299449909796954634190416519522592868437 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_fifo_watermarks_acq/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3097610325 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_target_fifo_watermarks_acq.3097610325 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_target_fifo_watermarks_acq.3097610325 -covoverwrite' seed=80514711105206720618847825444942910821299449909796954634190416519522592868437 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80514711105206720618847825444942910821299449909796954634190416519522592868437 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_fifo_watermarks_acq/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_watermarks_acq_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_watermarks_tx 58707455257791282668333096940448403362412083682107483542007160614932986198522 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_fifo_watermarks_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1606416890 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_target_fifo_watermarks_tx.1606416890 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_target_fifo_watermarks_tx.1606416890 -covoverwrite' seed=58707455257791282668333096940448403362412083682107483542007160614932986198522 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58707455257791282668333096940448403362412083682107483542007160614932986198522 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_fifo_watermarks_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_watermarks_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_tx_stretch_ctrl 52123801319314874564901117466769326943911218854830962503290711694187273538272 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_tx_stretch_ctrl/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1926122208 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_target_tx_stretch_ctrl.1926122208 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_target_tx_stretch_ctrl.1926122208 -covoverwrite' seed=52123801319314874564901117466769326943911218854830962503290711694187273538272 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=52123801319314874564901117466769326943911218854830962503290711694187273538272 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_tx_stretch_ctrl/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_tx_stretch_ctrl_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_smbus_maxlen 87871478265204600909542276288902242441846947726882408148873475085125620781164 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_smbus_maxlen/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2268516460 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_target_smbus_maxlen.2268516460 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_target_smbus_maxlen.2268516460 -covoverwrite' seed=87871478265204600909542276288902242441846947726882408148873475085125620781164 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87871478265204600909542276288902242441846947726882408148873475085125620781164 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_smbus_maxlen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_smbus_maxlen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 102423040467596468754962286092623151524919975504043529761583777810251515277819 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=664121851 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_target_nack_acqfull.664121851 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_target_nack_acqfull.664121851 -covoverwrite' seed=102423040467596468754962286092623151524919975504043529761583777810251515277819 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102423040467596468754962286092623151524919975504043529761583777810251515277819 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 2915845572768564506714094226547840210372036504044338312577540902272866720133 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1708136837 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_target_nack_acqfull_addr.1708136837 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_target_nack_acqfull_addr.1708136837 -covoverwrite' seed=2915845572768564506714094226547840210372036504044338312577540902272866720133 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2915845572768564506714094226547840210372036504044338312577540902272866720133 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_txstretch 100010290044056799775331120511417799195192037944917023581495012040480548496250 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_nack_txstretch/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1082172282 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_target_nack_txstretch.1082172282 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_target_nack_txstretch.1082172282 -covoverwrite' seed=100010290044056799775331120511417799195192037944917023581495012040480548496250 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100010290044056799775331120511417799195192037944917023581495012040480548496250 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_target_nack_txstretch/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_txstretch_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_errors 66995565179937736627230119609495973124450457280770640184766218815337189380974 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4241265518 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/1.i2c_tl_errors.4241265518 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.i2c_tl_errors.4241265518 -covoverwrite' seed=66995565179937736627230119609495973124450457280770640184766218815337189380974 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66995565179937736627230119609495973124450457280770640184766218815337189380974 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_intg_err 46480526739244262947324441213795034020095710987273043785771586167001454492458 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=982268714 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/1.i2c_tl_intg_err.982268714 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.i2c_tl_intg_err.982268714 -covoverwrite' seed=46480526739244262947324441213795034020095710987273043785771586167001454492458 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46480526739244262947324441213795034020095710987273043785771586167001454492458 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_sec_cm 40183849535548904852353093036125920830510557431340646849578266761978540416910 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2430820238 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_sec_cm.2430820238 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_sec_cm.2430820238 -covoverwrite' seed=40183849535548904852353093036125920830510557431340646849578266761978540416910 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40183849535548904852353093036125920830510557431340646849578266761978540416910 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_intr_test 40852671733877133630581795067903678306363544011062577945037095689292030276015 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1129968047 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/1.i2c_intr_test.1129968047 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.i2c_intr_test.1129968047 -covoverwrite' seed=40852671733877133630581795067903678306363544011062577945037095689292030276015 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40852671733877133630581795067903678306363544011062577945037095689292030276015 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_alert_test 3683740241134984078890613590845815038319865392861825956856408851270743019295 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3145387807 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/1.i2c_alert_test.3145387807 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 1.i2c_alert_test.3145387807 -covoverwrite' seed=3683740241134984078890613590845815038319865392861825956856408851270743019295 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3683740241134984078890613590845815038319865392861825956856408851270743019295 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_csr_rw 93893081616583505689100692984946538438032762036787455470278950537732661002893 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4231348877 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/1.i2c_csr_rw.4231348877 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.i2c_csr_rw.4231348877 -covoverwrite' seed=93893081616583505689100692984946538438032762036787455470278950537732661002893 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93893081616583505689100692984946538438032762036787455470278950537732661002893 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_same_csr_outstanding 65552031868766485712921913881200944672751628062546966074340630301796925781010 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2484941842 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/1.i2c_same_csr_outstanding.2484941842 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.i2c_same_csr_outstanding.2484941842 -covoverwrite' seed=65552031868766485712921913881200944672751628062546966074340630301796925781010 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65552031868766485712921913881200944672751628062546966074340630301796925781010 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_csr_mem_rw_with_rand_reset 30507481530100249465653340508601667155117835344783782978413159031712678085821 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4157015229 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/1.i2c_csr_mem_rw_with_rand_reset.4157015229 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.i2c_csr_mem_rw_with_rand_reset.4157015229 -covoverwrite' seed=30507481530100249465653340508601667155117835344783782978413159031712678085821 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30507481530100249465653340508601667155117835344783782978413159031712678085821 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/1.i2c_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_smoke 35488893709644404902013121285037805272458040811468735793601123717444473579740 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_host_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4039239900 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_host_smoke.4039239900 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_host_smoke.4039239900 -covoverwrite' seed=35488893709644404902013121285037805272458040811468735793601123717444473579740 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35488893709644404902013121285037805272458040811468735793601123717444473579740 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_host_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 110191581135493734775911121664107909436880097993124246794177975869179979254037 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3662563605 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_host_override.3662563605 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_host_override.3662563605 -covoverwrite' seed=110191581135493734775911121664107909436880097993124246794177975869179979254037 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110191581135493734775911121664107909436880097993124246794177975869179979254037 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_watermark 37053832644486121460947489828046473977618928680202586370208834885300858366689 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_host_fifo_watermark/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1482402529 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_host_fifo_watermark.1482402529 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_host_fifo_watermark.1482402529 -covoverwrite' seed=37053832644486121460947489828046473977618928680202586370208834885300858366689 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37053832644486121460947489828046473977618928680202586370208834885300858366689 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_host_fifo_watermark/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_watermark_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_overflow 42807491901385094935392869176841315343998031414714078206766592992642354986339 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_host_fifo_overflow/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=972373347 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_host_fifo_overflow.972373347 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_host_fifo_overflow.972373347 -covoverwrite' seed=42807491901385094935392869176841315343998031414714078206766592992642354986339 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42807491901385094935392869176841315343998031414714078206766592992642354986339 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_host_fifo_overflow/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_overflow_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_reset_fmt 37080621711571674341513717389404847475203695803245630723964527254478276172902 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_host_fifo_reset_fmt/latest run_opts='+test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2622659686 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_host_fifo_reset_fmt.2622659686 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_host_fifo_reset_fmt.2622659686 -covoverwrite' seed=37080621711571674341513717389404847475203695803245630723964527254478276172902 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37080621711571674341513717389404847475203695803245630723964527254478276172902 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_host_fifo_reset_fmt/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_reset_fmt_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_fmt_empty 25809066748304237197071561362873589553661006472617643421083848948606886607854 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_host_fifo_fmt_empty/latest run_opts='+test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2140535790 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_host_fifo_fmt_empty.2140535790 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_host_fifo_fmt_empty.2140535790 -covoverwrite' seed=25809066748304237197071561362873589553661006472617643421083848948606886607854 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25809066748304237197071561362873589553661006472617643421083848948606886607854 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_host_fifo_fmt_empty/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_fmt_empty_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_reset_rx 107053969541343371730459277303922668876559083710757845302143669896191184932497 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_host_fifo_reset_rx/latest run_opts='+test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1989349009 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_host_fifo_reset_rx.1989349009 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_host_fifo_reset_rx.1989349009 -covoverwrite' seed=107053969541343371730459277303922668876559083710757845302143669896191184932497 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107053969541343371730459277303922668876559083710757845302143669896191184932497 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_host_fifo_reset_rx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_reset_rx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_full 81002413299068013408526014419443767500781070697373754873181835853648404560990 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_host_fifo_full/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4172430430 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_host_fifo_full.4172430430 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_host_fifo_full.4172430430 -covoverwrite' seed=81002413299068013408526014419443767500781070697373754873181835853648404560990 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81002413299068013408526014419443767500781070697373754873181835853648404560990 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_host_fifo_full/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_full_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_perf 78689224656275093379466411430079550814619664120179822328923493111844032471388 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_host_perf/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4205044060 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_host_perf.4205044060 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_host_perf.4205044060 -covoverwrite' seed=78689224656275093379466411430079550814619664120179822328923493111844032471388 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78689224656275093379466411430079550814619664120179822328923493111844032471388 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_host_perf/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_perf_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_perf_precise 43054325846623470409233415058255637345419978219871010877136084044081252897027 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_host_perf_precise/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2177732867 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_host_perf_precise.2177732867 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_host_perf_precise.2177732867 -covoverwrite' seed=43054325846623470409233415058255637345419978219871010877136084044081252897027 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43054325846623470409233415058255637345419978219871010877136084044081252897027 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_host_perf_precise/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_perf_precise_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stretch_timeout 68347049454921088342429715018190123290378144505730946240859809352215045072712 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_host_stretch_timeout/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1350297416 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_host_stretch_timeout.1350297416 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_host_stretch_timeout.1350297416 -covoverwrite' seed=68347049454921088342429715018190123290378144505730946240859809352215045072712 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68347049454921088342429715018190123290378144505730946240859809352215045072712 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_host_stretch_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_stretch_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 24597637381200046808243116791132259702037388235775071530208383543782869707172 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2101488036 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_host_error_intr.2101488036 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_host_error_intr.2101488036 -covoverwrite' seed=24597637381200046808243116791132259702037388235775071530208383543782869707172 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24597637381200046808243116791132259702037388235775071530208383543782869707172 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all 78718032878621765518088879116898764613150153456814759741997712288945021975523 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_host_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3725392867 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_host_stress_all.3725392867 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_host_stress_all.3725392867 -covoverwrite' seed=78718032878621765518088879116898764613150153456814759741997712288945021975523 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78718032878621765518088879116898764613150153456814759741997712288945021975523 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_smoke 24646672448139312207550002090314552402636350775623133729227352129389342033642 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_smoke/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3204515562 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_target_smoke.3204515562 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_target_smoke.3204515562 -covoverwrite' seed=24646672448139312207550002090314552402636350775623133729227352129389342033642 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24646672448139312207550002090314552402636350775623133729227352129389342033642 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_wr 36860900187512966820218277499833103561425039915682509190416552032779190126686 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_stress_wr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1983891550 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_target_stress_wr.1983891550 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_target_stress_wr.1983891550 -covoverwrite' seed=36860900187512966820218277499833103561425039915682509190416552032779190126686 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36860900187512966820218277499833103561425039915682509190416552032779190126686 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_stress_wr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_wr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_rd 8237671444789372006377869210620461861212633519786695565110393948650794211024 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_stress_rd/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1500337872 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_target_stress_rd.1500337872 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_target_stress_rd.1500337872 -covoverwrite' seed=8237671444789372006377869210620461861212633519786695565110393948650794211024 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8237671444789372006377869210620461861212633519786695565110393948650794211024 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_stress_rd/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_rd_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stretch 6977096866304947167869168608391297995591962156780531461345694219995248695610 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_stretch/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2745801018 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_target_stretch.2745801018 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_target_stretch.2745801018 -covoverwrite' seed=6977096866304947167869168608391297995591962156780531461345694219995248695610 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6977096866304947167869168608391297995591962156780531461345694219995248695610 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_stretch/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stretch_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_intr_smoke 32702632465094527269514323944220830902006914820554032121886724846503879975584 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_intr_smoke/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3391824544 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_target_intr_smoke.3391824544 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_target_intr_smoke.3391824544 -covoverwrite' seed=32702632465094527269514323944220830902006914820554032121886724846503879975584 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32702632465094527269514323944220830902006914820554032121886724846503879975584 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_intr_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_intr_stress_wr 58333589786339724285758709601329986365112088165634194272911054532318108013574 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_intr_stress_wr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3262600198 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_target_intr_stress_wr.3262600198 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_target_intr_stress_wr.3262600198 -covoverwrite' seed=58333589786339724285758709601329986365112088165634194272911054532318108013574 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58333589786339724285758709601329986365112088165634194272911054532318108013574 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_intr_stress_wr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_wr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_timeout 102687576917967078831926763191946889158436989325750700197687193954873084696933 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_timeout/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2737264997 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_target_timeout.2737264997 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_target_timeout.2737264997 -covoverwrite' seed=102687576917967078831926763191946889158436989325750700197687193954873084696933 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102687576917967078831926763191946889158436989325750700197687193954873084696933 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_unexp_stop 60070089929160017983401202554618701869294513643328087104561685510767130353174 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_unexp_stop/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=514235926 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_target_unexp_stop.514235926 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_target_unexp_stop.514235926 -covoverwrite' seed=60070089929160017983401202554618701869294513643328087104561685510767130353174 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60070089929160017983401202554618701869294513643328087104561685510767130353174 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_unexp_stop/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_ack_stop_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_acq 4699255975715669693626889934006312061828131776546949569878216205389172056022 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_fifo_reset_acq/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2075664342 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_target_fifo_reset_acq.2075664342 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_target_fifo_reset_acq.2075664342 -covoverwrite' seed=4699255975715669693626889934006312061828131776546949569878216205389172056022 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4699255975715669693626889934006312061828131776546949569878216205389172056022 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_fifo_reset_acq/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_acq_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 106772093303436646326353766627899373673983564696106173527474715114292815805309 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=748632957 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_target_fifo_reset_tx.748632957 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_target_fifo_reset_tx.748632957 -covoverwrite' seed=106772093303436646326353766627899373673983564696106173527474715114292815805309 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106772093303436646326353766627899373673983564696106173527474715114292815805309 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_perf 17688562165769941059894249463678136913235795008855249417858705677371773301317 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_perf/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3344708165 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_target_perf.3344708165 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_target_perf.3344708165 -covoverwrite' seed=17688562165769941059894249463678136913235795008855249417858705677371773301317 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17688562165769941059894249463678136913235795008855249417858705677371773301317 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_perf/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_perf_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all 30095122791031848880273707445522978095867107456859475441724160309926830380278 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_stress_all/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2384565494 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_target_stress_all.2384565494 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_target_stress_all.2384565494 -covoverwrite' seed=30095122791031848880273707445522978095867107456859475441724160309926830380278 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30095122791031848880273707445522978095867107456859475441724160309926830380278 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_bad_addr 17404755696825643308073524156297483880577965923067202801467680368960918526688 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_bad_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2278300384 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_target_bad_addr.2278300384 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_target_bad_addr.2278300384 -covoverwrite' seed=17404755696825643308073524156297483880577965923067202801467680368960918526688 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17404755696825643308073524156297483880577965923067202801467680368960918526688 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_bad_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 99276823367429971059279389487164755256847964087032143407802539865851143723039 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2725320735 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_target_hrst.2725320735 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_target_hrst.2725320735 -covoverwrite' seed=99276823367429971059279389487164755256847964087032143407802539865851143723039 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99276823367429971059279389487164755256847964087032143407802539865851143723039 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all_with_rand_reset 61790943624204016020454000237826997659661804224543215062945667412621085171462 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_host_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +stress_seq=i2c_host_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1212735238 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_host_stress_all_with_rand_reset.1212735238 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_host_stress_all_with_rand_reset.1212735238 -covoverwrite' seed=61790943624204016020454000237826997659661804224543215062945667412621085171462 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61790943624204016020454000237826997659661804224543215062945667412621085171462 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_host_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all_with_rand_reset 31922470144931671098584741533893345329085973628319889613780177167469253324926 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_stress_all_with_rand_reset/latest run_opts='+i2c_agent_mode=Host +run_stress_all_with_rand_reset +stress_seq=i2c_target_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=828993662 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_target_stress_all_with_rand_reset.828993662 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_target_stress_all_with_rand_reset.828993662 -covoverwrite' seed=31922470144931671098584741533893345329085973628319889613780177167469253324926 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31922470144931671098584741533893345329085973628319889613780177167469253324926 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 25630761471462562953904833696384803904539806358288298787375768109278889527554 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1346390274 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_host_mode_toggle.1346390274 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_host_mode_toggle.1346390274 -covoverwrite' seed=25630761471462562953904833696384803904539806358288298787375768109278889527554 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25630761471462562953904833696384803904539806358288298787375768109278889527554 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 31266740014736473683987193245734921902304136071223273202263355433476606632579 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1298637443 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_host_may_nack.1298637443 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_host_may_nack.1298637443 -covoverwrite' seed=31266740014736473683987193245734921902304136071223273202263355433476606632579 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31266740014736473683987193245734921902304136071223273202263355433476606632579 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_watermarks_acq 95611886837304651198166099982593283167230767031977044771410900766518745466329 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_fifo_watermarks_acq/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3177940441 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_target_fifo_watermarks_acq.3177940441 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_target_fifo_watermarks_acq.3177940441 -covoverwrite' seed=95611886837304651198166099982593283167230767031977044771410900766518745466329 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95611886837304651198166099982593283167230767031977044771410900766518745466329 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_fifo_watermarks_acq/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_watermarks_acq_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_watermarks_tx 56566679989304145628502105928656526085723116101558019856190590465642826092682 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_fifo_watermarks_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=854642826 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_target_fifo_watermarks_tx.854642826 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_target_fifo_watermarks_tx.854642826 -covoverwrite' seed=56566679989304145628502105928656526085723116101558019856190590465642826092682 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56566679989304145628502105928656526085723116101558019856190590465642826092682 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_fifo_watermarks_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_watermarks_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_tx_stretch_ctrl 61324133415487237986256025728205504683362768371770548863905005468799572525028 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_tx_stretch_ctrl/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2445426660 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_target_tx_stretch_ctrl.2445426660 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_target_tx_stretch_ctrl.2445426660 -covoverwrite' seed=61324133415487237986256025728205504683362768371770548863905005468799572525028 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61324133415487237986256025728205504683362768371770548863905005468799572525028 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_tx_stretch_ctrl/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_tx_stretch_ctrl_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_smbus_maxlen 113638846240342082181895980669280240673418778182689193038487008879441717128898 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_smbus_maxlen/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3847646914 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_target_smbus_maxlen.3847646914 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_target_smbus_maxlen.3847646914 -covoverwrite' seed=113638846240342082181895980669280240673418778182689193038487008879441717128898 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113638846240342082181895980669280240673418778182689193038487008879441717128898 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_smbus_maxlen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_smbus_maxlen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 36510308470110919463379528844139054024484356100299644588095729150485144430137 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=947021369 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_target_nack_acqfull.947021369 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_target_nack_acqfull.947021369 -covoverwrite' seed=36510308470110919463379528844139054024484356100299644588095729150485144430137 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36510308470110919463379528844139054024484356100299644588095729150485144430137 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 66128578637668988921795079373129018412019464156219993099124896204249554494233 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1781801753 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_target_nack_acqfull_addr.1781801753 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_target_nack_acqfull_addr.1781801753 -covoverwrite' seed=66128578637668988921795079373129018412019464156219993099124896204249554494233 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66128578637668988921795079373129018412019464156219993099124896204249554494233 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_txstretch 17383540948046811967699150706996704315215834337793018246325940149130582450997 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_nack_txstretch/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3723911989 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_target_nack_txstretch.3723911989 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_target_nack_txstretch.3723911989 -covoverwrite' seed=17383540948046811967699150706996704315215834337793018246325940149130582450997 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17383540948046811967699150706996704315215834337793018246325940149130582450997 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_target_nack_txstretch/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_txstretch_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_errors 85812836811774407301404318351720428826580037486887306816076188067754875308674 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2226932354 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/2.i2c_tl_errors.2226932354 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.i2c_tl_errors.2226932354 -covoverwrite' seed=85812836811774407301404318351720428826580037486887306816076188067754875308674 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85812836811774407301404318351720428826580037486887306816076188067754875308674 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_intg_err 19603586036084431798607054904837829054128435411478774567610832755904848955176 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4224288552 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/2.i2c_tl_intg_err.4224288552 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.i2c_tl_intg_err.4224288552 -covoverwrite' seed=19603586036084431798607054904837829054128435411478774567610832755904848955176 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19603586036084431798607054904837829054128435411478774567610832755904848955176 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_sec_cm 83571118811403751846165699885609814085626146310253257400766285599086595300263 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1223187367 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_sec_cm.1223187367 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_sec_cm.1223187367 -covoverwrite' seed=83571118811403751846165699885609814085626146310253257400766285599086595300263 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83571118811403751846165699885609814085626146310253257400766285599086595300263 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_intr_test 113726592846776541433503788938859284527565701634994169436076269959804022591741 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1637257469 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/2.i2c_intr_test.1637257469 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.i2c_intr_test.1637257469 -covoverwrite' seed=113726592846776541433503788938859284527565701634994169436076269959804022591741 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113726592846776541433503788938859284527565701634994169436076269959804022591741 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_alert_test 76209600062700421120957424933057185068906318340405668573301956414276083090733 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3233776941 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/2.i2c_alert_test.3233776941 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 2.i2c_alert_test.3233776941 -covoverwrite' seed=76209600062700421120957424933057185068906318340405668573301956414276083090733 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76209600062700421120957424933057185068906318340405668573301956414276083090733 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_csr_rw 81379023068265946777951465163716140258458562520061366737491059797224317537215 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2808892351 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/2.i2c_csr_rw.2808892351 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.i2c_csr_rw.2808892351 -covoverwrite' seed=81379023068265946777951465163716140258458562520061366737491059797224317537215 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81379023068265946777951465163716140258458562520061366737491059797224317537215 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_same_csr_outstanding 55718648092622049216187795948639143782085318110869318433018706931168572545408 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1460869504 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/2.i2c_same_csr_outstanding.1460869504 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.i2c_same_csr_outstanding.1460869504 -covoverwrite' seed=55718648092622049216187795948639143782085318110869318433018706931168572545408 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55718648092622049216187795948639143782085318110869318433018706931168572545408 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_csr_mem_rw_with_rand_reset 70908234364755254175807330597077527944825985652714941877756546302194694684215 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2033909303 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/2.i2c_csr_mem_rw_with_rand_reset.2033909303 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.i2c_csr_mem_rw_with_rand_reset.2033909303 -covoverwrite' seed=70908234364755254175807330597077527944825985652714941877756546302194694684215 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70908234364755254175807330597077527944825985652714941877756546302194694684215 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/2.i2c_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_smoke 49318530378870010785083586109041950357559919486248069306663836718457457501541 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_host_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1174431077 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_host_smoke.1174431077 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_host_smoke.1174431077 -covoverwrite' seed=49318530378870010785083586109041950357559919486248069306663836718457457501541 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49318530378870010785083586109041950357559919486248069306663836718457457501541 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_host_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 70845452879821985311499094412455301066147637981061621837355126077477655721825 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1537521505 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_host_override.1537521505 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_host_override.1537521505 -covoverwrite' seed=70845452879821985311499094412455301066147637981061621837355126077477655721825 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70845452879821985311499094412455301066147637981061621837355126077477655721825 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_watermark 113615812611149003002605876340112184290972193485720992381925124496504333554979 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_host_fifo_watermark/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=84432163 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_host_fifo_watermark.84432163 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_host_fifo_watermark.84432163 -covoverwrite' seed=113615812611149003002605876340112184290972193485720992381925124496504333554979 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113615812611149003002605876340112184290972193485720992381925124496504333554979 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_host_fifo_watermark/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_watermark_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_overflow 90325401496099474845790874907223708880599238578366069081179393778440357249573 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_host_fifo_overflow/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3393159717 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_host_fifo_overflow.3393159717 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_host_fifo_overflow.3393159717 -covoverwrite' seed=90325401496099474845790874907223708880599238578366069081179393778440357249573 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90325401496099474845790874907223708880599238578366069081179393778440357249573 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_host_fifo_overflow/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_overflow_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_reset_fmt 77684436857934565535397201233733512540718376697140350838076653350540722933813 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_host_fifo_reset_fmt/latest run_opts='+test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2634649653 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_host_fifo_reset_fmt.2634649653 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_host_fifo_reset_fmt.2634649653 -covoverwrite' seed=77684436857934565535397201233733512540718376697140350838076653350540722933813 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77684436857934565535397201233733512540718376697140350838076653350540722933813 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_host_fifo_reset_fmt/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_reset_fmt_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_fmt_empty 38969106997487323169666755845659907721960618585155245981256499205017108338827 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_host_fifo_fmt_empty/latest run_opts='+test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3203782795 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_host_fifo_fmt_empty.3203782795 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_host_fifo_fmt_empty.3203782795 -covoverwrite' seed=38969106997487323169666755845659907721960618585155245981256499205017108338827 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38969106997487323169666755845659907721960618585155245981256499205017108338827 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_host_fifo_fmt_empty/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_fmt_empty_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_reset_rx 58738307064277185110905223889522604515977007823835045750614434331283899733366 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_host_fifo_reset_rx/latest run_opts='+test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3678852470 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_host_fifo_reset_rx.3678852470 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_host_fifo_reset_rx.3678852470 -covoverwrite' seed=58738307064277185110905223889522604515977007823835045750614434331283899733366 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58738307064277185110905223889522604515977007823835045750614434331283899733366 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_host_fifo_reset_rx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_reset_rx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_full 50812087685922890534098609357358438708852797494438626213824592346833171312823 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_host_fifo_full/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2516644023 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_host_fifo_full.2516644023 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_host_fifo_full.2516644023 -covoverwrite' seed=50812087685922890534098609357358438708852797494438626213824592346833171312823 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50812087685922890534098609357358438708852797494438626213824592346833171312823 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_host_fifo_full/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_full_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_perf 65918134974656514296731347574260278083402316428667812932333804309351843337856 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_host_perf/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1975096960 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_host_perf.1975096960 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_host_perf.1975096960 -covoverwrite' seed=65918134974656514296731347574260278083402316428667812932333804309351843337856 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65918134974656514296731347574260278083402316428667812932333804309351843337856 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_host_perf/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_perf_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_perf_precise 44728503204889653454067405679756368531104016815219825493811921858548570203472 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_host_perf_precise/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1302013264 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_host_perf_precise.1302013264 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_host_perf_precise.1302013264 -covoverwrite' seed=44728503204889653454067405679756368531104016815219825493811921858548570203472 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44728503204889653454067405679756368531104016815219825493811921858548570203472 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_host_perf_precise/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_perf_precise_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stretch_timeout 13154094288542436046505236053942622490098931878987318286194762126888735161563 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_host_stretch_timeout/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2472361179 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_host_stretch_timeout.2472361179 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_host_stretch_timeout.2472361179 -covoverwrite' seed=13154094288542436046505236053942622490098931878987318286194762126888735161563 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13154094288542436046505236053942622490098931878987318286194762126888735161563 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_host_stretch_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_stretch_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 44970947597106298332324807518100216246779413136768031444930929943917856295794 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2862877554 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_host_error_intr.2862877554 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_host_error_intr.2862877554 -covoverwrite' seed=44970947597106298332324807518100216246779413136768031444930929943917856295794 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44970947597106298332324807518100216246779413136768031444930929943917856295794 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all 61192819467726488837998948243171845579786698268987138295210605045023947349049 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_host_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2045238329 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_host_stress_all.2045238329 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_host_stress_all.2045238329 -covoverwrite' seed=61192819467726488837998948243171845579786698268987138295210605045023947349049 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61192819467726488837998948243171845579786698268987138295210605045023947349049 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_smoke 31367604158914610708960252973539109953001692100159303175697988919993865069988 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_smoke/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1195369892 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_target_smoke.1195369892 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_target_smoke.1195369892 -covoverwrite' seed=31367604158914610708960252973539109953001692100159303175697988919993865069988 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31367604158914610708960252973539109953001692100159303175697988919993865069988 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_wr 71794554760203609311625899312679830331710737390206441026829741194356422478920 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_stress_wr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1210715208 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_target_stress_wr.1210715208 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_target_stress_wr.1210715208 -covoverwrite' seed=71794554760203609311625899312679830331710737390206441026829741194356422478920 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71794554760203609311625899312679830331710737390206441026829741194356422478920 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_stress_wr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_wr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_rd 20590168651739196902549683130598882072900354976233870526692024959091249407661 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_stress_rd/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2095474349 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_target_stress_rd.2095474349 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_target_stress_rd.2095474349 -covoverwrite' seed=20590168651739196902549683130598882072900354976233870526692024959091249407661 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20590168651739196902549683130598882072900354976233870526692024959091249407661 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_stress_rd/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_rd_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stretch 86841308755410473758296302191780940632456221671078740690622222172044059367963 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_stretch/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2573621787 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_target_stretch.2573621787 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_target_stretch.2573621787 -covoverwrite' seed=86841308755410473758296302191780940632456221671078740690622222172044059367963 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86841308755410473758296302191780940632456221671078740690622222172044059367963 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_stretch/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stretch_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_intr_smoke 113661289271393449140301572469898065257424520243348286541083460758176620911327 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_intr_smoke/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2422512351 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_target_intr_smoke.2422512351 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_target_intr_smoke.2422512351 -covoverwrite' seed=113661289271393449140301572469898065257424520243348286541083460758176620911327 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113661289271393449140301572469898065257424520243348286541083460758176620911327 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_intr_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_intr_stress_wr 103278579862652400126112235969927717006033643293790794595912299466993543488957 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_intr_stress_wr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=675095997 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_target_intr_stress_wr.675095997 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_target_intr_stress_wr.675095997 -covoverwrite' seed=103278579862652400126112235969927717006033643293790794595912299466993543488957 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103278579862652400126112235969927717006033643293790794595912299466993543488957 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_intr_stress_wr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_wr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_timeout 3059652696629263635793293099572701339612785560543267575203739169322955340630 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_timeout/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=71990102 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_target_timeout.71990102 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_target_timeout.71990102 -covoverwrite' seed=3059652696629263635793293099572701339612785560543267575203739169322955340630 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3059652696629263635793293099572701339612785560543267575203739169322955340630 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_unexp_stop 58436818894827026798939483524441700071388993774974871201198615399186908756745 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_unexp_stop/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=79346441 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_target_unexp_stop.79346441 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_target_unexp_stop.79346441 -covoverwrite' seed=58436818894827026798939483524441700071388993774974871201198615399186908756745 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58436818894827026798939483524441700071388993774974871201198615399186908756745 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_unexp_stop/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_ack_stop_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_acq 70317022779503892619234509033611421177406198854347422789307216677372541475198 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_fifo_reset_acq/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1530861950 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_target_fifo_reset_acq.1530861950 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_target_fifo_reset_acq.1530861950 -covoverwrite' seed=70317022779503892619234509033611421177406198854347422789307216677372541475198 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70317022779503892619234509033611421177406198854347422789307216677372541475198 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_fifo_reset_acq/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_acq_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 44418125759667015848333284489395449729117132994840892987986469579365433817431 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2895198551 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_target_fifo_reset_tx.2895198551 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_target_fifo_reset_tx.2895198551 -covoverwrite' seed=44418125759667015848333284489395449729117132994840892987986469579365433817431 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44418125759667015848333284489395449729117132994840892987986469579365433817431 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_perf 26252382109155164814608929782123936036032967308573724232802879869191867127485 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_perf/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=173332157 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_target_perf.173332157 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_target_perf.173332157 -covoverwrite' seed=26252382109155164814608929782123936036032967308573724232802879869191867127485 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26252382109155164814608929782123936036032967308573724232802879869191867127485 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_perf/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_perf_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all 114337593842442454403548759168464284313544638581447411107927158995330070415030 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_stress_all/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=214369974 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_target_stress_all.214369974 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_target_stress_all.214369974 -covoverwrite' seed=114337593842442454403548759168464284313544638581447411107927158995330070415030 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114337593842442454403548759168464284313544638581447411107927158995330070415030 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_bad_addr 42069083378870770769727995821109800562128037296032180732271224224221301678968 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_bad_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3172311928 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_target_bad_addr.3172311928 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_target_bad_addr.3172311928 -covoverwrite' seed=42069083378870770769727995821109800562128037296032180732271224224221301678968 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42069083378870770769727995821109800562128037296032180732271224224221301678968 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_bad_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 42167419814905585245363336170561151006004596444757542108744947390663101249606 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=768342086 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_target_hrst.768342086 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_target_hrst.768342086 -covoverwrite' seed=42167419814905585245363336170561151006004596444757542108744947390663101249606 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42167419814905585245363336170561151006004596444757542108744947390663101249606 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all_with_rand_reset 92897864732186108903874461617249040919061905239792451365777378757416465401185 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_host_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +stress_seq=i2c_host_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2887452001 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_host_stress_all_with_rand_reset.2887452001 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_host_stress_all_with_rand_reset.2887452001 -covoverwrite' seed=92897864732186108903874461617249040919061905239792451365777378757416465401185 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92897864732186108903874461617249040919061905239792451365777378757416465401185 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_host_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all_with_rand_reset 112136896937923603347746154112967912252231058868854008409462159686795321301025 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_stress_all_with_rand_reset/latest run_opts='+i2c_agent_mode=Host +run_stress_all_with_rand_reset +stress_seq=i2c_target_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=311056417 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_target_stress_all_with_rand_reset.311056417 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_target_stress_all_with_rand_reset.311056417 -covoverwrite' seed=112136896937923603347746154112967912252231058868854008409462159686795321301025 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112136896937923603347746154112967912252231058868854008409462159686795321301025 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 105153200875499554075502212232302697235626004162145972532779214375093318155929 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=733445785 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_host_mode_toggle.733445785 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_host_mode_toggle.733445785 -covoverwrite' seed=105153200875499554075502212232302697235626004162145972532779214375093318155929 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105153200875499554075502212232302697235626004162145972532779214375093318155929 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 57565015185478751581924912942074330597725742357038626104028749437746910446015 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=533578175 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_host_may_nack.533578175 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_host_may_nack.533578175 -covoverwrite' seed=57565015185478751581924912942074330597725742357038626104028749437746910446015 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57565015185478751581924912942074330597725742357038626104028749437746910446015 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_watermarks_acq 49312956732225194950067757961362422713504970056289316142451310149116476226517 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_fifo_watermarks_acq/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1893956565 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_target_fifo_watermarks_acq.1893956565 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_target_fifo_watermarks_acq.1893956565 -covoverwrite' seed=49312956732225194950067757961362422713504970056289316142451310149116476226517 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49312956732225194950067757961362422713504970056289316142451310149116476226517 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_fifo_watermarks_acq/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_watermarks_acq_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_watermarks_tx 71461732433045724904543563923285162900490118166634901308835745678842155013186 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_fifo_watermarks_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1339593794 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_target_fifo_watermarks_tx.1339593794 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_target_fifo_watermarks_tx.1339593794 -covoverwrite' seed=71461732433045724904543563923285162900490118166634901308835745678842155013186 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71461732433045724904543563923285162900490118166634901308835745678842155013186 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_fifo_watermarks_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_watermarks_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_tx_stretch_ctrl 65015403622794731300462149441316020264974165327012825550910433598032742079812 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_tx_stretch_ctrl/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3609091396 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_target_tx_stretch_ctrl.3609091396 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_target_tx_stretch_ctrl.3609091396 -covoverwrite' seed=65015403622794731300462149441316020264974165327012825550910433598032742079812 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65015403622794731300462149441316020264974165327012825550910433598032742079812 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_tx_stretch_ctrl/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_tx_stretch_ctrl_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_smbus_maxlen 104821904864315623674164157251023596970841469939334151028159408457809306903433 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_smbus_maxlen/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1561650057 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_target_smbus_maxlen.1561650057 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_target_smbus_maxlen.1561650057 -covoverwrite' seed=104821904864315623674164157251023596970841469939334151028159408457809306903433 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104821904864315623674164157251023596970841469939334151028159408457809306903433 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_smbus_maxlen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_smbus_maxlen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 2151156215853727893137371259711103187405452000498935263572987377702183310233 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4271313817 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_target_nack_acqfull.4271313817 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_target_nack_acqfull.4271313817 -covoverwrite' seed=2151156215853727893137371259711103187405452000498935263572987377702183310233 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2151156215853727893137371259711103187405452000498935263572987377702183310233 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 112071980925677612671040730150768205761966793633006491278226235619797865125666 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=886363938 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_target_nack_acqfull_addr.886363938 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_target_nack_acqfull_addr.886363938 -covoverwrite' seed=112071980925677612671040730150768205761966793633006491278226235619797865125666 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112071980925677612671040730150768205761966793633006491278226235619797865125666 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_txstretch 43763565641357586756924475153645898919858638295616892640606262223316533449055 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_nack_txstretch/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1552224607 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_target_nack_txstretch.1552224607 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_target_nack_txstretch.1552224607 -covoverwrite' seed=43763565641357586756924475153645898919858638295616892640606262223316533449055 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43763565641357586756924475153645898919858638295616892640606262223316533449055 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_target_nack_txstretch/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_txstretch_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_errors 20246260010825111492773991622270411174695563015095059823484301345264099837948 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3990538236 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/3.i2c_tl_errors.3990538236 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.i2c_tl_errors.3990538236 -covoverwrite' seed=20246260010825111492773991622270411174695563015095059823484301345264099837948 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20246260010825111492773991622270411174695563015095059823484301345264099837948 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_intg_err 3685969052049728919387421967328945783680803309425255648840790199869032765523 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2875332691 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/3.i2c_tl_intg_err.2875332691 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.i2c_tl_intg_err.2875332691 -covoverwrite' seed=3685969052049728919387421967328945783680803309425255648840790199869032765523 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3685969052049728919387421967328945783680803309425255648840790199869032765523 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_sec_cm 49505479832875248583147755922327856118714098855768562101077737195563753793703 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4223527079 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_sec_cm.4223527079 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_sec_cm.4223527079 -covoverwrite' seed=49505479832875248583147755922327856118714098855768562101077737195563753793703 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49505479832875248583147755922327856118714098855768562101077737195563753793703 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_intr_test 93587372610686089530268793243831481260082691004706706271739319517803688610743 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2538720183 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/3.i2c_intr_test.2538720183 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.i2c_intr_test.2538720183 -covoverwrite' seed=93587372610686089530268793243831481260082691004706706271739319517803688610743 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93587372610686089530268793243831481260082691004706706271739319517803688610743 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_alert_test 83944214968078365147559159959667652015783713485075751200283091054020441502796 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2941613132 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/3.i2c_alert_test.2941613132 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 3.i2c_alert_test.2941613132 -covoverwrite' seed=83944214968078365147559159959667652015783713485075751200283091054020441502796 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83944214968078365147559159959667652015783713485075751200283091054020441502796 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_csr_rw 24886756193477166264153491911062489616349538835463916276269801959891195226819 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4217465539 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/3.i2c_csr_rw.4217465539 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.i2c_csr_rw.4217465539 -covoverwrite' seed=24886756193477166264153491911062489616349538835463916276269801959891195226819 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24886756193477166264153491911062489616349538835463916276269801959891195226819 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_same_csr_outstanding 71912666945954797920522154621265162659063848725295945225488866105892043430823 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4217314215 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/3.i2c_same_csr_outstanding.4217314215 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.i2c_same_csr_outstanding.4217314215 -covoverwrite' seed=71912666945954797920522154621265162659063848725295945225488866105892043430823 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71912666945954797920522154621265162659063848725295945225488866105892043430823 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_csr_mem_rw_with_rand_reset 76668453099687344115210178126042113222799765518672665410366373690272597334093 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1214699597 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/3.i2c_csr_mem_rw_with_rand_reset.1214699597 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.i2c_csr_mem_rw_with_rand_reset.1214699597 -covoverwrite' seed=76668453099687344115210178126042113222799765518672665410366373690272597334093 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76668453099687344115210178126042113222799765518672665410366373690272597334093 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/3.i2c_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_smoke 26573749662905350314129413197149689929429405807096171389832429948175154222710 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_host_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4110751350 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_host_smoke.4110751350 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_host_smoke.4110751350 -covoverwrite' seed=26573749662905350314129413197149689929429405807096171389832429948175154222710 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26573749662905350314129413197149689929429405807096171389832429948175154222710 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_host_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 47122183169310758771634268784490031085335743501019221654217782334955267697797 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1167993989 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_host_override.1167993989 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_host_override.1167993989 -covoverwrite' seed=47122183169310758771634268784490031085335743501019221654217782334955267697797 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47122183169310758771634268784490031085335743501019221654217782334955267697797 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_watermark 61414052298686604152681200526860184546236808402093242628280802985139045127992 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_host_fifo_watermark/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4103329592 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_watermark_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_host_fifo_watermark.4103329592 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_host_fifo_watermark.4103329592 -covoverwrite' seed=61414052298686604152681200526860184546236808402093242628280802985139045127992 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61414052298686604152681200526860184546236808402093242628280802985139045127992 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_host_fifo_watermark/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_watermark_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_overflow 111793005203459466261232095105006798986825938233153413224784975373572131866689 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_host_fifo_overflow/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2910406721 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_overflow_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_host_fifo_overflow.2910406721 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_host_fifo_overflow.2910406721 -covoverwrite' seed=111793005203459466261232095105006798986825938233153413224784975373572131866689 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111793005203459466261232095105006798986825938233153413224784975373572131866689 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_host_fifo_overflow/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_overflow_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_reset_fmt 72521589176099916526404132694784779148825115270287378028872619253003048452310 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_host_fifo_reset_fmt/latest run_opts='+test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=552337622 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_host_fifo_reset_fmt.552337622 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_host_fifo_reset_fmt.552337622 -covoverwrite' seed=72521589176099916526404132694784779148825115270287378028872619253003048452310 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72521589176099916526404132694784779148825115270287378028872619253003048452310 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_host_fifo_reset_fmt/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_reset_fmt_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_fmt_empty 29254208359544571997297170215251752277258392528031039251189672814301902918073 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_host_fifo_fmt_empty/latest run_opts='+test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1936576953 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_fmt_empty_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_host_fifo_fmt_empty.1936576953 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_host_fifo_fmt_empty.1936576953 -covoverwrite' seed=29254208359544571997297170215251752277258392528031039251189672814301902918073 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29254208359544571997297170215251752277258392528031039251189672814301902918073 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_host_fifo_fmt_empty/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_fmt_empty_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_reset_rx 38526745960684841390889548993280458426958855337782589619676194895808259155709 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_host_fifo_reset_rx/latest run_opts='+test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=695199485 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_rx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_host_fifo_reset_rx.695199485 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_host_fifo_reset_rx.695199485 -covoverwrite' seed=38526745960684841390889548993280458426958855337782589619676194895808259155709 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38526745960684841390889548993280458426958855337782589619676194895808259155709 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_host_fifo_reset_rx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_reset_rx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_full 30237758435067475775039585138956407361590176879683046119154221451929328717849 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_host_fifo_full/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=318672921 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_full_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_host_fifo_full.318672921 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_host_fifo_full.318672921 -covoverwrite' seed=30237758435067475775039585138956407361590176879683046119154221451929328717849 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30237758435067475775039585138956407361590176879683046119154221451929328717849 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_host_fifo_full/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_full_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_perf 59468368826166210491517913415855459343663159694300344160557372948306135936873 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_host_perf/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=996470633 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_host_perf.996470633 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_host_perf.996470633 -covoverwrite' seed=59468368826166210491517913415855459343663159694300344160557372948306135936873 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=59468368826166210491517913415855459343663159694300344160557372948306135936873 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_host_perf/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_perf_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_perf_precise 15938634264568331938418337349306230969250567279251195814359273214727897607528 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_host_perf_precise/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1824124264 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_perf_precise_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_host_perf_precise.1824124264 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_host_perf_precise.1824124264 -covoverwrite' seed=15938634264568331938418337349306230969250567279251195814359273214727897607528 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15938634264568331938418337349306230969250567279251195814359273214727897607528 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_host_perf_precise/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_perf_precise_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stretch_timeout 103070152110953565006848762302975696519964052728923368883545754071329990697919 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_host_stretch_timeout/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1160438719 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stretch_timeout_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_host_stretch_timeout.1160438719 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_host_stretch_timeout.1160438719 -covoverwrite' seed=103070152110953565006848762302975696519964052728923368883545754071329990697919 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103070152110953565006848762302975696519964052728923368883545754071329990697919 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_host_stretch_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_stretch_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 5847846452394723709335583411481001544512093967595321213586363580973252227433 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1154625897 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_host_error_intr.1154625897 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_host_error_intr.1154625897 -covoverwrite' seed=5847846452394723709335583411481001544512093967595321213586363580973252227433 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5847846452394723709335583411481001544512093967595321213586363580973252227433 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all 3490911460245762218639326330706657275654115029538420259254260662094961391981 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_host_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2645375341 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_host_stress_all.2645375341 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_host_stress_all.2645375341 -covoverwrite' seed=3490911460245762218639326330706657275654115029538420259254260662094961391981 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3490911460245762218639326330706657275654115029538420259254260662094961391981 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_smoke 5306392575793570269176106644516974415381254802051957918132008833455442303747 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_smoke/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1410800387 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_target_smoke.1410800387 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_target_smoke.1410800387 -covoverwrite' seed=5306392575793570269176106644516974415381254802051957918132008833455442303747 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5306392575793570269176106644516974415381254802051957918132008833455442303747 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_wr 6762461810187988372829386105218018638816721742016903311230105310445679141997 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_stress_wr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=600_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2567955565 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_target_stress_wr.2567955565 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_target_stress_wr.2567955565 -covoverwrite' seed=6762461810187988372829386105218018638816721742016903311230105310445679141997 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6762461810187988372829386105218018638816721742016903311230105310445679141997 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_stress_wr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_wr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_rd 35260195226901000383708473447751986767109200494612095755778689671259985604854 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_stress_rd/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=100_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2248470774 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_rd_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_target_stress_rd.2248470774 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_target_stress_rd.2248470774 -covoverwrite' seed=35260195226901000383708473447751986767109200494612095755778689671259985604854 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35260195226901000383708473447751986767109200494612095755778689671259985604854 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_stress_rd/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_rd_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stretch 79821714920090147623980648093972397025993290035850752519621251529327941327324 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_stretch/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=400_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3061651932 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stretch_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_target_stretch.3061651932 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_target_stretch.3061651932 -covoverwrite' seed=79821714920090147623980648093972397025993290035850752519621251529327941327324 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79821714920090147623980648093972397025993290035850752519621251529327941327324 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_stretch/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stretch_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_intr_smoke 3961258365163479444710132312536477169026525726753928018296135350237630429719 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_intr_smoke/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=200_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2904160791 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_target_intr_smoke.2904160791 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_target_intr_smoke.2904160791 -covoverwrite' seed=3961258365163479444710132312536477169026525726753928018296135350237630429719 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3961258365163479444710132312536477169026525726753928018296135350237630429719 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_intr_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_intr_stress_wr 17319546320382363146485213095466758341277110543217562909297283691025355191925 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_intr_stress_wr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=600_000_000 +use_intr_handler=1 +slow_acq=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2473014901 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_wr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_target_intr_stress_wr.2473014901 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_target_intr_stress_wr.2473014901 -covoverwrite' seed=17319546320382363146485213095466758341277110543217562909297283691025355191925 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17319546320382363146485213095466758341277110543217562909297283691025355191925 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_intr_stress_wr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_wr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_timeout 70261413950004960654404061628144764466158458957064741856868598810229068574864 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_timeout/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1250996368 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_timeout_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_target_timeout.1250996368 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_target_timeout.1250996368 -covoverwrite' seed=70261413950004960654404061628144764466158458957064741856868598810229068574864 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70261413950004960654404061628144764466158458957064741856868598810229068574864 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_timeout/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_timeout_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_unexp_stop 53185546990389709971299954873011353668479491441988104791431400163978421296788 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_unexp_stop/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1668374164 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_target_unexp_stop.1668374164 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_target_unexp_stop.1668374164 -covoverwrite' seed=53185546990389709971299954873011353668479491441988104791431400163978421296788 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53185546990389709971299954873011353668479491441988104791431400163978421296788 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_unexp_stop/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_ack_stop_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_acq 63201897387023433905935405748318416712688817667217819378095440229978191903598 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_fifo_reset_acq/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2130131822 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_acq_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_target_fifo_reset_acq.2130131822 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_target_fifo_reset_acq.2130131822 -covoverwrite' seed=63201897387023433905935405748318416712688817667217819378095440229978191903598 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63201897387023433905935405748318416712688817667217819378095440229978191903598 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_fifo_reset_acq/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_acq_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 46652408469863670488948171852877237923063673451003319721153415249055632005376 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=145168640 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_target_fifo_reset_tx.145168640 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_target_fifo_reset_tx.145168640 -covoverwrite' seed=46652408469863670488948171852877237923063673451003319721153415249055632005376 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46652408469863670488948171852877237923063673451003319721153415249055632005376 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_perf 111416879444983716950572562637437924816826175748147876666535176332305371331553 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_perf/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1246854113 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_perf_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_target_perf.1246854113 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_target_perf.1246854113 -covoverwrite' seed=111416879444983716950572562637437924816826175748147876666535176332305371331553 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111416879444983716950572562637437924816826175748147876666535176332305371331553 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_perf/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_perf_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all 100632674129235822086129537078039105456979586867114181843149066656652164545320 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_stress_all/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2772646696 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_target_stress_all.2772646696 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_target_stress_all.2772646696 -covoverwrite' seed=100632674129235822086129537078039105456979586867114181843149066656652164545320 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100632674129235822086129537078039105456979586867114181843149066656652164545320 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_bad_addr 79567120081297478024048152654868115203523091164922646592912261313642568160646 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_bad_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +i2c_bad_addr_pct=50 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2491225478 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_target_bad_addr.2491225478 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_target_bad_addr.2491225478 -covoverwrite' seed=79567120081297478024048152654868115203523091164922646592912261313642568160646 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79567120081297478024048152654868115203523091164922646592912261313642568160646 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_bad_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 17253369535946970831551929532634709591155146472577824132419385129415951609955 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2978312291 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_target_hrst.2978312291 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_target_hrst.2978312291 -covoverwrite' seed=17253369535946970831551929532634709591155146472577824132419385129415951609955 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17253369535946970831551929532634709591155146472577824132419385129415951609955 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all_with_rand_reset 48021840191674615542035123298471494412298142420529009347949152244107330763448 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_host_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +stress_seq=i2c_host_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3660364472 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_host_stress_all_with_rand_reset.3660364472 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_host_stress_all_with_rand_reset.3660364472 -covoverwrite' seed=48021840191674615542035123298471494412298142420529009347949152244107330763448 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48021840191674615542035123298471494412298142420529009347949152244107330763448 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_host_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all_with_rand_reset 12994737806665750994294303477075762840207753671032813703224071966647800846603 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_stress_all_with_rand_reset/latest run_opts='+i2c_agent_mode=Host +run_stress_all_with_rand_reset +stress_seq=i2c_target_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3417856267 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_target_stress_all_with_rand_reset.3417856267 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_target_stress_all_with_rand_reset.3417856267 -covoverwrite' seed=12994737806665750994294303477075762840207753671032813703224071966647800846603 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12994737806665750994294303477075762840207753671032813703224071966647800846603 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 47785136915076040463132794441490322733142715504691666649733040518653660717052 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4113391612 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_host_mode_toggle.4113391612 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_host_mode_toggle.4113391612 -covoverwrite' seed=47785136915076040463132794441490322733142715504691666649733040518653660717052 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47785136915076040463132794441490322733142715504691666649733040518653660717052 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 95920547998964591981733145452575801449195539498062411415516533982380004864025 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2993811481 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_host_may_nack.2993811481 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_host_may_nack.2993811481 -covoverwrite' seed=95920547998964591981733145452575801449195539498062411415516533982380004864025 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95920547998964591981733145452575801449195539498062411415516533982380004864025 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_watermarks_acq 19125837631221721062649990202348904842907112172510489889151342350336220341609 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_fifo_watermarks_acq/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2982290793 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_acq_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_target_fifo_watermarks_acq.2982290793 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_target_fifo_watermarks_acq.2982290793 -covoverwrite' seed=19125837631221721062649990202348904842907112172510489889151342350336220341609 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19125837631221721062649990202348904842907112172510489889151342350336220341609 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_fifo_watermarks_acq/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_watermarks_acq_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_watermarks_tx 76666223941821389851757973091093353102488907534047653436070767045978758882460 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_fifo_watermarks_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2770904220 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_watermarks_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_target_fifo_watermarks_tx.2770904220 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_target_fifo_watermarks_tx.2770904220 -covoverwrite' seed=76666223941821389851757973091093353102488907534047653436070767045978758882460 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76666223941821389851757973091093353102488907534047653436070767045978758882460 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_fifo_watermarks_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_watermarks_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_tx_stretch_ctrl 60922167727571737244452471720057549660142970657304857453855029161915426596556 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_tx_stretch_ctrl/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1125443276 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_tx_stretch_ctrl_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_target_tx_stretch_ctrl.1125443276 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_target_tx_stretch_ctrl.1125443276 -covoverwrite' seed=60922167727571737244452471720057549660142970657304857453855029161915426596556 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60922167727571737244452471720057549660142970657304857453855029161915426596556 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_tx_stretch_ctrl/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_tx_stretch_ctrl_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_smbus_maxlen 87357773422615295621193073476812277257277565690752080799935096433867465760585 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_smbus_maxlen/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4063829833 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_smbus_maxlen_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_target_smbus_maxlen.4063829833 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_target_smbus_maxlen.4063829833 -covoverwrite' seed=87357773422615295621193073476812277257277565690752080799935096433867465760585 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87357773422615295621193073476812277257277565690752080799935096433867465760585 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_smbus_maxlen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_smbus_maxlen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 53869756224333189876512934503953778045536088258585480096923416016470839405091 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=916728355 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_target_nack_acqfull.916728355 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_target_nack_acqfull.916728355 -covoverwrite' seed=53869756224333189876512934503953778045536088258585480096923416016470839405091 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53869756224333189876512934503953778045536088258585480096923416016470839405091 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 101083344549914179426091916679826905570274571342481391841454266749039519175041 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=380604801 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_target_nack_acqfull_addr.380604801 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_target_nack_acqfull_addr.380604801 -covoverwrite' seed=101083344549914179426091916679826905570274571342481391841454266749039519175041 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101083344549914179426091916679826905570274571342481391841454266749039519175041 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_txstretch 42019558973607464510793965271740203740246357052525441634655309783917155434796 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_nack_txstretch/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2504638764 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_target_nack_txstretch.2504638764 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_target_nack_txstretch.2504638764 -covoverwrite' seed=42019558973607464510793965271740203740246357052525441634655309783917155434796 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42019558973607464510793965271740203740246357052525441634655309783917155434796 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_target_nack_txstretch/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_txstretch_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_errors 4525215205279314884782911796276302209865796877272233507397129135587703503466 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3336682090 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/4.i2c_tl_errors.3336682090 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.i2c_tl_errors.3336682090 -covoverwrite' seed=4525215205279314884782911796276302209865796877272233507397129135587703503466 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4525215205279314884782911796276302209865796877272233507397129135587703503466 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_intg_err 31939886167199120944634447313016772866113790965261723381261819387405579413792 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2198956320 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/4.i2c_tl_intg_err.2198956320 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.i2c_tl_intg_err.2198956320 -covoverwrite' seed=31939886167199120944634447313016772866113790965261723381261819387405579413792 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31939886167199120944634447313016772866113790965261723381261819387405579413792 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_sec_cm 4785297943572023948480913966819789209707623679591101498090122600517088640962 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=398524354 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_sec_cm.398524354 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_sec_cm.398524354 -covoverwrite' seed=4785297943572023948480913966819789209707623679591101498090122600517088640962 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4785297943572023948480913966819789209707623679591101498090122600517088640962 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_intr_test 28633814785722062850033982288071490163942435034698198221840619375011486368651 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2628125579 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/4.i2c_intr_test.2628125579 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.i2c_intr_test.2628125579 -covoverwrite' seed=28633814785722062850033982288071490163942435034698198221840619375011486368651 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28633814785722062850033982288071490163942435034698198221840619375011486368651 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_alert_test 42311805986307422588517574898721911910216095382778539424200009410504675678931 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3866745555 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/4.i2c_alert_test.3866745555 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 4.i2c_alert_test.3866745555 -covoverwrite' seed=42311805986307422588517574898721911910216095382778539424200009410504675678931 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42311805986307422588517574898721911910216095382778539424200009410504675678931 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_csr_rw 80240963179087381624944591872740682911645890142695256923306053659356636718251 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2744984747 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/4.i2c_csr_rw.2744984747 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.i2c_csr_rw.2744984747 -covoverwrite' seed=80240963179087381624944591872740682911645890142695256923306053659356636718251 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80240963179087381624944591872740682911645890142695256923306053659356636718251 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_same_csr_outstanding 47278398993457766627492710964853876006369937136385457202019858010901998938451 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4206569811 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/4.i2c_same_csr_outstanding.4206569811 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.i2c_same_csr_outstanding.4206569811 -covoverwrite' seed=47278398993457766627492710964853876006369937136385457202019858010901998938451 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47278398993457766627492710964853876006369937136385457202019858010901998938451 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_csr_mem_rw_with_rand_reset 46160331412476735018571966174441193240277604228612441651411158478159643816204 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3248894220 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/4.i2c_csr_mem_rw_with_rand_reset.3248894220 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.i2c_csr_mem_rw_with_rand_reset.3248894220 -covoverwrite' seed=46160331412476735018571966174441193240277604228612441651411158478159643816204 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46160331412476735018571966174441193240277604228612441651411158478159643816204 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/4.i2c_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 30963383231639005339387657852203771234884901221548201264773775846532141822595 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3279696515 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/5.i2c_host_override.3279696515 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 5.i2c_host_override.3279696515 -covoverwrite' seed=30963383231639005339387657852203771234884901221548201264773775846532141822595 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30963383231639005339387657852203771234884901221548201264773775846532141822595 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_reset_fmt 9870807066055671620219851019681737319867076066933652637654742164795156617952 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_host_fifo_reset_fmt/latest run_opts='+test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2645842656 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/5.i2c_host_fifo_reset_fmt.2645842656 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 5.i2c_host_fifo_reset_fmt.2645842656 -covoverwrite' seed=9870807066055671620219851019681737319867076066933652637654742164795156617952 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9870807066055671620219851019681737319867076066933652637654742164795156617952 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_host_fifo_reset_fmt/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_reset_fmt_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 59516744389940543486792793775106939715207564309298187961357318296638498540112 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1190922832 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/5.i2c_host_error_intr.1190922832 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 5.i2c_host_error_intr.1190922832 -covoverwrite' seed=59516744389940543486792793775106939715207564309298187961357318296638498540112 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=59516744389940543486792793775106939715207564309298187961357318296638498540112 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all 83172741996339102929103160978689160315324745795005590033901289207849268325518 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_host_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3715673230 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/5.i2c_host_stress_all.3715673230 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 5.i2c_host_stress_all.3715673230 -covoverwrite' seed=83172741996339102929103160978689160315324745795005590033901289207849268325518 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83172741996339102929103160978689160315324745795005590033901289207849268325518 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_unexp_stop 28258286530890208415791886703267634780525843238535881232916659549278670878261 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_target_unexp_stop/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=786101813 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/5.i2c_target_unexp_stop.786101813 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 5.i2c_target_unexp_stop.786101813 -covoverwrite' seed=28258286530890208415791886703267634780525843238535881232916659549278670878261 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28258286530890208415791886703267634780525843238535881232916659549278670878261 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_target_unexp_stop/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_ack_stop_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 112865990928779989579733781421544939081331288811231110964435749621740845838562 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1920119010 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/5.i2c_target_fifo_reset_tx.1920119010 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 5.i2c_target_fifo_reset_tx.1920119010 -covoverwrite' seed=112865990928779989579733781421544939081331288811231110964435749621740845838562 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112865990928779989579733781421544939081331288811231110964435749621740845838562 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all 107634339696610261382284101995724463398587689189693445358060287097448987095788 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_target_stress_all/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2331767532 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/5.i2c_target_stress_all.2331767532 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 5.i2c_target_stress_all.2331767532 -covoverwrite' seed=107634339696610261382284101995724463398587689189693445358060287097448987095788 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107634339696610261382284101995724463398587689189693445358060287097448987095788 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_target_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 80785717777794931504811337944015903220779315905518729380024466140864454978137 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3506563673 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/5.i2c_target_hrst.3506563673 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 5.i2c_target_hrst.3506563673 -covoverwrite' seed=80785717777794931504811337944015903220779315905518729380024466140864454978137 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80785717777794931504811337944015903220779315905518729380024466140864454978137 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all_with_rand_reset 39636785620720056254568740416787959962473875468958702268797465772347468353544 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_host_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +stress_seq=i2c_host_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1424035848 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/5.i2c_host_stress_all_with_rand_reset.1424035848 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 5.i2c_host_stress_all_with_rand_reset.1424035848 -covoverwrite' seed=39636785620720056254568740416787959962473875468958702268797465772347468353544 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39636785620720056254568740416787959962473875468958702268797465772347468353544 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_host_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all_with_rand_reset 14067895454112596762358708572669385274009237920653172554798574388515164793863 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_target_stress_all_with_rand_reset/latest run_opts='+i2c_agent_mode=Host +run_stress_all_with_rand_reset +stress_seq=i2c_target_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=896412679 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/5.i2c_target_stress_all_with_rand_reset.896412679 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 5.i2c_target_stress_all_with_rand_reset.896412679 -covoverwrite' seed=14067895454112596762358708572669385274009237920653172554798574388515164793863 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=14067895454112596762358708572669385274009237920653172554798574388515164793863 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_target_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 75023035630175373265894517917368400934242371258969452808799256811347140140567 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1185930775 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/5.i2c_host_mode_toggle.1185930775 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 5.i2c_host_mode_toggle.1185930775 -covoverwrite' seed=75023035630175373265894517917368400934242371258969452808799256811347140140567 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75023035630175373265894517917368400934242371258969452808799256811347140140567 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 5333487243888742516110810712380930807647857383510135238679054646061408864187 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1889683387 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/5.i2c_host_may_nack.1889683387 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 5.i2c_host_may_nack.1889683387 -covoverwrite' seed=5333487243888742516110810712380930807647857383510135238679054646061408864187 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5333487243888742516110810712380930807647857383510135238679054646061408864187 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 26764724821500066209191881285395821766353481513414177380336967864298541276441 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2199248153 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/5.i2c_target_nack_acqfull.2199248153 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 5.i2c_target_nack_acqfull.2199248153 -covoverwrite' seed=26764724821500066209191881285395821766353481513414177380336967864298541276441 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26764724821500066209191881285395821766353481513414177380336967864298541276441 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 43572208348209264333084754522525215683618269914471386083168218964134591806196 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2254781172 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/5.i2c_target_nack_acqfull_addr.2254781172 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 5.i2c_target_nack_acqfull_addr.2254781172 -covoverwrite' seed=43572208348209264333084754522525215683618269914471386083168218964134591806196 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43572208348209264333084754522525215683618269914471386083168218964134591806196 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_txstretch 32825786823516170194598636819001228082615221557444329909133581423399722700912 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_target_nack_txstretch/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1655066736 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/5.i2c_target_nack_txstretch.1655066736 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 5.i2c_target_nack_txstretch.1655066736 -covoverwrite' seed=32825786823516170194598636819001228082615221557444329909133581423399722700912 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32825786823516170194598636819001228082615221557444329909133581423399722700912 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_target_nack_txstretch/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_txstretch_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_errors 107504258244444441563419676270939673404149177743844314727812734948494450103680 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1199052160 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/5.i2c_tl_errors.1199052160 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.i2c_tl_errors.1199052160 -covoverwrite' seed=107504258244444441563419676270939673404149177743844314727812734948494450103680 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107504258244444441563419676270939673404149177743844314727812734948494450103680 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_intg_err 73290413286254163661602120827379227725951096136669580720031147523788320108145 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=165244529 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/5.i2c_tl_intg_err.165244529 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.i2c_tl_intg_err.165244529 -covoverwrite' seed=73290413286254163661602120827379227725951096136669580720031147523788320108145 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73290413286254163661602120827379227725951096136669580720031147523788320108145 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_intr_test 7821093846262275645086749974780771354194652142576710801130921278406921552112 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=288620784 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/5.i2c_intr_test.288620784 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.i2c_intr_test.288620784 -covoverwrite' seed=7821093846262275645086749974780771354194652142576710801130921278406921552112 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7821093846262275645086749974780771354194652142576710801130921278406921552112 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_alert_test 108139778789625306008009251862932589499350547938950007095798188627822427009184 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2359062688 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/5.i2c_alert_test.2359062688 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 5.i2c_alert_test.2359062688 -covoverwrite' seed=108139778789625306008009251862932589499350547938950007095798188627822427009184 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108139778789625306008009251862932589499350547938950007095798188627822427009184 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/5.i2c_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 38094586307366533350532945741121092510810410051213616759245352991722548550766 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1715264622 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/6.i2c_host_override.1715264622 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 6.i2c_host_override.1715264622 -covoverwrite' seed=38094586307366533350532945741121092510810410051213616759245352991722548550766 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38094586307366533350532945741121092510810410051213616759245352991722548550766 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_reset_fmt 26589443978343737670822925944445617784296570086583743466166180265108355122360 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_host_fifo_reset_fmt/latest run_opts='+test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=503284920 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/6.i2c_host_fifo_reset_fmt.503284920 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 6.i2c_host_fifo_reset_fmt.503284920 -covoverwrite' seed=26589443978343737670822925944445617784296570086583743466166180265108355122360 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26589443978343737670822925944445617784296570086583743466166180265108355122360 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_host_fifo_reset_fmt/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_reset_fmt_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 48517307202015558815451238612263948203790687501354024153113520418727698490344 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1873929192 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/6.i2c_host_error_intr.1873929192 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 6.i2c_host_error_intr.1873929192 -covoverwrite' seed=48517307202015558815451238612263948203790687501354024153113520418727698490344 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48517307202015558815451238612263948203790687501354024153113520418727698490344 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all 45750116114286753082096657693954655061270119305227893167180806354329960625482 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_host_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=706131274 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/6.i2c_host_stress_all.706131274 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 6.i2c_host_stress_all.706131274 -covoverwrite' seed=45750116114286753082096657693954655061270119305227893167180806354329960625482 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45750116114286753082096657693954655061270119305227893167180806354329960625482 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_unexp_stop 104871198939428367771713610357124420125564129109472998306910029677634133901830 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_target_unexp_stop/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1863008774 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/6.i2c_target_unexp_stop.1863008774 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 6.i2c_target_unexp_stop.1863008774 -covoverwrite' seed=104871198939428367771713610357124420125564129109472998306910029677634133901830 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104871198939428367771713610357124420125564129109472998306910029677634133901830 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_target_unexp_stop/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_ack_stop_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 20113046248535369370900695735162026901789975303258075418332856423204592378972 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1225876572 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/6.i2c_target_fifo_reset_tx.1225876572 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 6.i2c_target_fifo_reset_tx.1225876572 -covoverwrite' seed=20113046248535369370900695735162026901789975303258075418332856423204592378972 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20113046248535369370900695735162026901789975303258075418332856423204592378972 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all 112277638883873354664437107103244226600115823689236829454514140628629498694416 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_target_stress_all/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3054308112 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/6.i2c_target_stress_all.3054308112 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 6.i2c_target_stress_all.3054308112 -covoverwrite' seed=112277638883873354664437107103244226600115823689236829454514140628629498694416 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112277638883873354664437107103244226600115823689236829454514140628629498694416 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_target_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 2039597696411738930204673228895882561512068455584270245679436422646147429008 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1927918224 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/6.i2c_target_hrst.1927918224 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 6.i2c_target_hrst.1927918224 -covoverwrite' seed=2039597696411738930204673228895882561512068455584270245679436422646147429008 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2039597696411738930204673228895882561512068455584270245679436422646147429008 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all_with_rand_reset 23249368870183657831736031269369991752054770017472414753575051608345220541969 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_host_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +stress_seq=i2c_host_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1754066449 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/6.i2c_host_stress_all_with_rand_reset.1754066449 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 6.i2c_host_stress_all_with_rand_reset.1754066449 -covoverwrite' seed=23249368870183657831736031269369991752054770017472414753575051608345220541969 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23249368870183657831736031269369991752054770017472414753575051608345220541969 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_host_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all_with_rand_reset 3974164289847739790618183473051128330687156918489043892197287871284208652086 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_target_stress_all_with_rand_reset/latest run_opts='+i2c_agent_mode=Host +run_stress_all_with_rand_reset +stress_seq=i2c_target_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2629750582 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/6.i2c_target_stress_all_with_rand_reset.2629750582 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 6.i2c_target_stress_all_with_rand_reset.2629750582 -covoverwrite' seed=3974164289847739790618183473051128330687156918489043892197287871284208652086 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3974164289847739790618183473051128330687156918489043892197287871284208652086 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_target_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 60031219743511320424136223027084608037091614806102812236482132589548598888482 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4075980834 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/6.i2c_host_mode_toggle.4075980834 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 6.i2c_host_mode_toggle.4075980834 -covoverwrite' seed=60031219743511320424136223027084608037091614806102812236482132589548598888482 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60031219743511320424136223027084608037091614806102812236482132589548598888482 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 58281129238027580224266973707505638489061845112446331128539225004837108358014 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=656579454 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/6.i2c_host_may_nack.656579454 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 6.i2c_host_may_nack.656579454 -covoverwrite' seed=58281129238027580224266973707505638489061845112446331128539225004837108358014 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58281129238027580224266973707505638489061845112446331128539225004837108358014 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 39953815337888793437615549508322095663367563285268951520604009877866304125268 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1411529044 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/6.i2c_target_nack_acqfull.1411529044 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 6.i2c_target_nack_acqfull.1411529044 -covoverwrite' seed=39953815337888793437615549508322095663367563285268951520604009877866304125268 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39953815337888793437615549508322095663367563285268951520604009877866304125268 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 61312453762187647488799542619738090170820125595020171015201019787865320579488 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1328538016 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/6.i2c_target_nack_acqfull_addr.1328538016 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 6.i2c_target_nack_acqfull_addr.1328538016 -covoverwrite' seed=61312453762187647488799542619738090170820125595020171015201019787865320579488 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61312453762187647488799542619738090170820125595020171015201019787865320579488 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_txstretch 63893469858367546936078010895868884792351075080824910146166240682276496774222 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_target_nack_txstretch/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3932853326 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/6.i2c_target_nack_txstretch.3932853326 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 6.i2c_target_nack_txstretch.3932853326 -covoverwrite' seed=63893469858367546936078010895868884792351075080824910146166240682276496774222 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63893469858367546936078010895868884792351075080824910146166240682276496774222 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_target_nack_txstretch/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_txstretch_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_errors 44874260406741997304783013023068879601142061404697387726009653402439410299923 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3484464147 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/6.i2c_tl_errors.3484464147 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.i2c_tl_errors.3484464147 -covoverwrite' seed=44874260406741997304783013023068879601142061404697387726009653402439410299923 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44874260406741997304783013023068879601142061404697387726009653402439410299923 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_intg_err 64929345049077520545033542241851878384241359279026618570324363355723790599451 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2423571739 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/6.i2c_tl_intg_err.2423571739 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.i2c_tl_intg_err.2423571739 -covoverwrite' seed=64929345049077520545033542241851878384241359279026618570324363355723790599451 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64929345049077520545033542241851878384241359279026618570324363355723790599451 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_intr_test 15941177325614956731849937451161204008719231169551132238975131772512656431682 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=178788930 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/6.i2c_intr_test.178788930 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.i2c_intr_test.178788930 -covoverwrite' seed=15941177325614956731849937451161204008719231169551132238975131772512656431682 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15941177325614956731849937451161204008719231169551132238975131772512656431682 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_alert_test 55970697196347184483921758886382902931765593121208271882174766747469605052207 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3597999919 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/6.i2c_alert_test.3597999919 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 6.i2c_alert_test.3597999919 -covoverwrite' seed=55970697196347184483921758886382902931765593121208271882174766747469605052207 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55970697196347184483921758886382902931765593121208271882174766747469605052207 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/6.i2c_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 96538012925320258621955307738669711998375338083541461207056575685273440705219 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1478187715 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/7.i2c_host_override.1478187715 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 7.i2c_host_override.1478187715 -covoverwrite' seed=96538012925320258621955307738669711998375338083541461207056575685273440705219 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96538012925320258621955307738669711998375338083541461207056575685273440705219 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_reset_fmt 87382153545594049329491428991683180715251958085534789746703136854550871779382 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_host_fifo_reset_fmt/latest run_opts='+test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4185368630 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/7.i2c_host_fifo_reset_fmt.4185368630 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 7.i2c_host_fifo_reset_fmt.4185368630 -covoverwrite' seed=87382153545594049329491428991683180715251958085534789746703136854550871779382 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87382153545594049329491428991683180715251958085534789746703136854550871779382 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_host_fifo_reset_fmt/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_reset_fmt_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 15273325680685488135033369559627734862107215859197269631806482895526437043759 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1931460143 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/7.i2c_host_error_intr.1931460143 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 7.i2c_host_error_intr.1931460143 -covoverwrite' seed=15273325680685488135033369559627734862107215859197269631806482895526437043759 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15273325680685488135033369559627734862107215859197269631806482895526437043759 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all 114493837057231345669865506408777842071969901431883744536532160003360911902284 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_host_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1557513804 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/7.i2c_host_stress_all.1557513804 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 7.i2c_host_stress_all.1557513804 -covoverwrite' seed=114493837057231345669865506408777842071969901431883744536532160003360911902284 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114493837057231345669865506408777842071969901431883744536532160003360911902284 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_unexp_stop 100738204502712161159353244449395837827686247536463917432686916339458448347435 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_target_unexp_stop/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1937035563 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/7.i2c_target_unexp_stop.1937035563 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 7.i2c_target_unexp_stop.1937035563 -covoverwrite' seed=100738204502712161159353244449395837827686247536463917432686916339458448347435 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100738204502712161159353244449395837827686247536463917432686916339458448347435 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_target_unexp_stop/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_ack_stop_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 30527859194603027473775333731465851948007847017204136986069872664050332761407 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3263855935 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/7.i2c_target_fifo_reset_tx.3263855935 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 7.i2c_target_fifo_reset_tx.3263855935 -covoverwrite' seed=30527859194603027473775333731465851948007847017204136986069872664050332761407 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30527859194603027473775333731465851948007847017204136986069872664050332761407 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all 113367901267920522488548506690724674277900320240568298065261815377230590826206 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_target_stress_all/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3303200478 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/7.i2c_target_stress_all.3303200478 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 7.i2c_target_stress_all.3303200478 -covoverwrite' seed=113367901267920522488548506690724674277900320240568298065261815377230590826206 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113367901267920522488548506690724674277900320240568298065261815377230590826206 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_target_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 5836353793371456558297518840450262387579697980093932612359026876793948241034 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2612558986 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/7.i2c_target_hrst.2612558986 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 7.i2c_target_hrst.2612558986 -covoverwrite' seed=5836353793371456558297518840450262387579697980093932612359026876793948241034 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5836353793371456558297518840450262387579697980093932612359026876793948241034 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all_with_rand_reset 45438816453588542061665990622643524137370342052549447277441130755713846646518 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_host_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +stress_seq=i2c_host_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3918698230 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/7.i2c_host_stress_all_with_rand_reset.3918698230 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 7.i2c_host_stress_all_with_rand_reset.3918698230 -covoverwrite' seed=45438816453588542061665990622643524137370342052549447277441130755713846646518 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45438816453588542061665990622643524137370342052549447277441130755713846646518 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_host_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all_with_rand_reset 88298192282252648956694298407433106347833113787999019579866361549631639061397 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_target_stress_all_with_rand_reset/latest run_opts='+i2c_agent_mode=Host +run_stress_all_with_rand_reset +stress_seq=i2c_target_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1101857685 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/7.i2c_target_stress_all_with_rand_reset.1101857685 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 7.i2c_target_stress_all_with_rand_reset.1101857685 -covoverwrite' seed=88298192282252648956694298407433106347833113787999019579866361549631639061397 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88298192282252648956694298407433106347833113787999019579866361549631639061397 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_target_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 66745400245751801924639150525628314171634635578224378480757746385963305144844 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3772256780 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/7.i2c_host_mode_toggle.3772256780 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 7.i2c_host_mode_toggle.3772256780 -covoverwrite' seed=66745400245751801924639150525628314171634635578224378480757746385963305144844 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66745400245751801924639150525628314171634635578224378480757746385963305144844 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 63250887155536072124957026346686066658829648668929211342728864252059611249705 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1520909353 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/7.i2c_host_may_nack.1520909353 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 7.i2c_host_may_nack.1520909353 -covoverwrite' seed=63250887155536072124957026346686066658829648668929211342728864252059611249705 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63250887155536072124957026346686066658829648668929211342728864252059611249705 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 85288634589285676814890669279954694593809610062534851164763622839269934979993 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1160731545 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/7.i2c_target_nack_acqfull.1160731545 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 7.i2c_target_nack_acqfull.1160731545 -covoverwrite' seed=85288634589285676814890669279954694593809610062534851164763622839269934979993 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85288634589285676814890669279954694593809610062534851164763622839269934979993 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 103987511049309213348385938759844986063929405497620165827299410880200826026797 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=891681581 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/7.i2c_target_nack_acqfull_addr.891681581 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 7.i2c_target_nack_acqfull_addr.891681581 -covoverwrite' seed=103987511049309213348385938759844986063929405497620165827299410880200826026797 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103987511049309213348385938759844986063929405497620165827299410880200826026797 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_txstretch 109356957932736270258768411757585305238560135532021292115280715251877230466161 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_target_nack_txstretch/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3061896305 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/7.i2c_target_nack_txstretch.3061896305 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 7.i2c_target_nack_txstretch.3061896305 -covoverwrite' seed=109356957932736270258768411757585305238560135532021292115280715251877230466161 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109356957932736270258768411757585305238560135532021292115280715251877230466161 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_target_nack_txstretch/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_txstretch_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_errors 89810842059278939648265443449511860131184096194752927678745933366965803480042 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=647033834 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/7.i2c_tl_errors.647033834 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.i2c_tl_errors.647033834 -covoverwrite' seed=89810842059278939648265443449511860131184096194752927678745933366965803480042 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89810842059278939648265443449511860131184096194752927678745933366965803480042 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_intg_err 75676127468383353205640639939854335934397145255757355017124613586562297073175 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=616271383 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/7.i2c_tl_intg_err.616271383 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.i2c_tl_intg_err.616271383 -covoverwrite' seed=75676127468383353205640639939854335934397145255757355017124613586562297073175 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75676127468383353205640639939854335934397145255757355017124613586562297073175 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_intr_test 3393588903435171521259502909962667343539143535995047067281112169511547265334 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2584437046 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/7.i2c_intr_test.2584437046 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.i2c_intr_test.2584437046 -covoverwrite' seed=3393588903435171521259502909962667343539143535995047067281112169511547265334 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3393588903435171521259502909962667343539143535995047067281112169511547265334 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_alert_test 82680068728652735030373837129960578870699108232312707987244059614685244872209 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3399144977 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/7.i2c_alert_test.3399144977 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 7.i2c_alert_test.3399144977 -covoverwrite' seed=82680068728652735030373837129960578870699108232312707987244059614685244872209 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82680068728652735030373837129960578870699108232312707987244059614685244872209 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/7.i2c_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 31920423684437926478306581568975588150421388526257245844517724726446254648847 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1976233487 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/8.i2c_host_override.1976233487 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 8.i2c_host_override.1976233487 -covoverwrite' seed=31920423684437926478306581568975588150421388526257245844517724726446254648847 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31920423684437926478306581568975588150421388526257245844517724726446254648847 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_reset_fmt 45436553887795599230201199256115785324696127141676662518051127102271838223758 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_host_fifo_reset_fmt/latest run_opts='+test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3384540558 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/8.i2c_host_fifo_reset_fmt.3384540558 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 8.i2c_host_fifo_reset_fmt.3384540558 -covoverwrite' seed=45436553887795599230201199256115785324696127141676662518051127102271838223758 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45436553887795599230201199256115785324696127141676662518051127102271838223758 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_host_fifo_reset_fmt/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_reset_fmt_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 97460911971093301716816411034744104885239776804803654898105746579884739309847 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3046813975 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/8.i2c_host_error_intr.3046813975 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 8.i2c_host_error_intr.3046813975 -covoverwrite' seed=97460911971093301716816411034744104885239776804803654898105746579884739309847 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97460911971093301716816411034744104885239776804803654898105746579884739309847 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all 38808206813709603341822857306872455162647048353313352061941116027872013125705 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_host_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3189180489 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/8.i2c_host_stress_all.3189180489 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 8.i2c_host_stress_all.3189180489 -covoverwrite' seed=38808206813709603341822857306872455162647048353313352061941116027872013125705 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38808206813709603341822857306872455162647048353313352061941116027872013125705 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_unexp_stop 65338396184537845439970695807294120437302236951505332093790073197986461787843 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_target_unexp_stop/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4027328195 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/8.i2c_target_unexp_stop.4027328195 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 8.i2c_target_unexp_stop.4027328195 -covoverwrite' seed=65338396184537845439970695807294120437302236951505332093790073197986461787843 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65338396184537845439970695807294120437302236951505332093790073197986461787843 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_target_unexp_stop/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_ack_stop_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 22687857201641931625126128137140516405333083069033884217135437134409421855155 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=825779 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/8.i2c_target_fifo_reset_tx.825779 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 8.i2c_target_fifo_reset_tx.825779 -covoverwrite' seed=22687857201641931625126128137140516405333083069033884217135437134409421855155 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22687857201641931625126128137140516405333083069033884217135437134409421855155 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all 25477385002349656164215076026239632801432116632787017201106191395067514796958 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_target_stress_all/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3338877854 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/8.i2c_target_stress_all.3338877854 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 8.i2c_target_stress_all.3338877854 -covoverwrite' seed=25477385002349656164215076026239632801432116632787017201106191395067514796958 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25477385002349656164215076026239632801432116632787017201106191395067514796958 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_target_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 29698310116449570689478010040011942161475508129492757215993588899407389995647 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2318348927 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/8.i2c_target_hrst.2318348927 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 8.i2c_target_hrst.2318348927 -covoverwrite' seed=29698310116449570689478010040011942161475508129492757215993588899407389995647 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29698310116449570689478010040011942161475508129492757215993588899407389995647 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all_with_rand_reset 66161164275567505530799951662444939745973853734123190482485046312654811904094 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_host_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +stress_seq=i2c_host_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4200544350 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/8.i2c_host_stress_all_with_rand_reset.4200544350 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 8.i2c_host_stress_all_with_rand_reset.4200544350 -covoverwrite' seed=66161164275567505530799951662444939745973853734123190482485046312654811904094 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66161164275567505530799951662444939745973853734123190482485046312654811904094 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_host_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all_with_rand_reset 38938286926579535848946733012254006021717752110542765308695966395752821386444 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_target_stress_all_with_rand_reset/latest run_opts='+i2c_agent_mode=Host +run_stress_all_with_rand_reset +stress_seq=i2c_target_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1029270732 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/8.i2c_target_stress_all_with_rand_reset.1029270732 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 8.i2c_target_stress_all_with_rand_reset.1029270732 -covoverwrite' seed=38938286926579535848946733012254006021717752110542765308695966395752821386444 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38938286926579535848946733012254006021717752110542765308695966395752821386444 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_target_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 87635799509180792768941483828020550878484358555269876947131306900337178495728 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2969881328 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/8.i2c_host_mode_toggle.2969881328 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 8.i2c_host_mode_toggle.2969881328 -covoverwrite' seed=87635799509180792768941483828020550878484358555269876947131306900337178495728 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87635799509180792768941483828020550878484358555269876947131306900337178495728 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 35484622639887331281275894427215111760739623408318612097909475871710571941895 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2013286407 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/8.i2c_host_may_nack.2013286407 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 8.i2c_host_may_nack.2013286407 -covoverwrite' seed=35484622639887331281275894427215111760739623408318612097909475871710571941895 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35484622639887331281275894427215111760739623408318612097909475871710571941895 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 12226684758246437065332621670002723510356300671463682892293163746346464463408 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3409726000 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/8.i2c_target_nack_acqfull.3409726000 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 8.i2c_target_nack_acqfull.3409726000 -covoverwrite' seed=12226684758246437065332621670002723510356300671463682892293163746346464463408 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12226684758246437065332621670002723510356300671463682892293163746346464463408 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 45286162523280333566501035458853551784097160401321472416049178987401511130698 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3027981898 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/8.i2c_target_nack_acqfull_addr.3027981898 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 8.i2c_target_nack_acqfull_addr.3027981898 -covoverwrite' seed=45286162523280333566501035458853551784097160401321472416049178987401511130698 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45286162523280333566501035458853551784097160401321472416049178987401511130698 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_txstretch 37013542276393091748296045073656649434968146566171864621429038637966996699549 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_target_nack_txstretch/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=509770141 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/8.i2c_target_nack_txstretch.509770141 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 8.i2c_target_nack_txstretch.509770141 -covoverwrite' seed=37013542276393091748296045073656649434968146566171864621429038637966996699549 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37013542276393091748296045073656649434968146566171864621429038637966996699549 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_target_nack_txstretch/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_txstretch_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_errors 36811355073104304520830172016177547245257501364296667434773754610170798086353 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1569003729 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/8.i2c_tl_errors.1569003729 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.i2c_tl_errors.1569003729 -covoverwrite' seed=36811355073104304520830172016177547245257501364296667434773754610170798086353 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36811355073104304520830172016177547245257501364296667434773754610170798086353 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_intg_err 30276136326321760597099687982067643439111499760759425854777522256220912547628 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3934189356 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/8.i2c_tl_intg_err.3934189356 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.i2c_tl_intg_err.3934189356 -covoverwrite' seed=30276136326321760597099687982067643439111499760759425854777522256220912547628 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30276136326321760597099687982067643439111499760759425854777522256220912547628 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_intr_test 59197545244270633779235075064304838750317866141904808968670153442865797905722 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3253452090 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/8.i2c_intr_test.3253452090 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.i2c_intr_test.3253452090 -covoverwrite' seed=59197545244270633779235075064304838750317866141904808968670153442865797905722 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=59197545244270633779235075064304838750317866141904808968670153442865797905722 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_alert_test 83235528612425123231463987268373431168565670411017145721979557537273235543258 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2907346138 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/8.i2c_alert_test.2907346138 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 8.i2c_alert_test.2907346138 -covoverwrite' seed=83235528612425123231463987268373431168565670411017145721979557537273235543258 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83235528612425123231463987268373431168565670411017145721979557537273235543258 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/8.i2c_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 7164245149092378438351978984044930035814001702156737176446323582808473733884 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2713193212 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/9.i2c_host_override.2713193212 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 9.i2c_host_override.2713193212 -covoverwrite' seed=7164245149092378438351978984044930035814001702156737176446323582808473733884 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7164245149092378438351978984044930035814001702156737176446323582808473733884 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_reset_fmt 62307712841735529148185270180319339487544071577635886858940941392488449895188 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_host_fifo_reset_fmt/latest run_opts='+test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3115772692 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/9.i2c_host_fifo_reset_fmt.3115772692 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 9.i2c_host_fifo_reset_fmt.3115772692 -covoverwrite' seed=62307712841735529148185270180319339487544071577635886858940941392488449895188 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62307712841735529148185270180319339487544071577635886858940941392488449895188 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_host_fifo_reset_fmt/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_reset_fmt_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 20480129858033632312863716197097193801992198939721623566004223563818999220245 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2858682389 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/9.i2c_host_error_intr.2858682389 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 9.i2c_host_error_intr.2858682389 -covoverwrite' seed=20480129858033632312863716197097193801992198939721623566004223563818999220245 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20480129858033632312863716197097193801992198939721623566004223563818999220245 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all 3179891776173738572161741213649909267328306032395364540778264300090884758895 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_host_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2058493295 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/9.i2c_host_stress_all.2058493295 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 9.i2c_host_stress_all.2058493295 -covoverwrite' seed=3179891776173738572161741213649909267328306032395364540778264300090884758895 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3179891776173738572161741213649909267328306032395364540778264300090884758895 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_unexp_stop 15082490475848073486632604776847734839631923499238384815296902328547436488570 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_target_unexp_stop/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=50_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3081070458 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_ack_stop_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/9.i2c_target_unexp_stop.3081070458 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 9.i2c_target_unexp_stop.3081070458 -covoverwrite' seed=15082490475848073486632604776847734839631923499238384815296902328547436488570 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15082490475848073486632604776847734839631923499238384815296902328547436488570 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_target_unexp_stop/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_ack_stop_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 99759849152249383936520770430726534487679289123176355444026255728279137450440 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1974106568 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/9.i2c_target_fifo_reset_tx.1974106568 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 9.i2c_target_fifo_reset_tx.1974106568 -covoverwrite' seed=99759849152249383936520770430726534487679289123176355444026255728279137450440 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99759849152249383936520770430726534487679289123176355444026255728279137450440 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all 71175227504243629533937644989210188317264693111985485833511542050378748391158 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_target_stress_all/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2279993078 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/9.i2c_target_stress_all.2279993078 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 9.i2c_target_stress_all.2279993078 -covoverwrite' seed=71175227504243629533937644989210188317264693111985485833511542050378748391158 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71175227504243629533937644989210188317264693111985485833511542050378748391158 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_target_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 97527131121440566175073233678698875917305031538298511585881864219255604457740 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1142894860 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/9.i2c_target_hrst.1142894860 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 9.i2c_target_hrst.1142894860 -covoverwrite' seed=97527131121440566175073233678698875917305031538298511585881864219255604457740 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97527131121440566175073233678698875917305031538298511585881864219255604457740 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all_with_rand_reset 111614953654105310888846893764054836232699575423246385798178469416009667966099 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_host_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +stress_seq=i2c_host_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3614176403 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/9.i2c_host_stress_all_with_rand_reset.3614176403 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 9.i2c_host_stress_all_with_rand_reset.3614176403 -covoverwrite' seed=111614953654105310888846893764054836232699575423246385798178469416009667966099 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111614953654105310888846893764054836232699575423246385798178469416009667966099 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_host_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all_with_rand_reset 90335535380862943897906292056864854692244797011858615158354515493404097156149 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_target_stress_all_with_rand_reset/latest run_opts='+i2c_agent_mode=Host +run_stress_all_with_rand_reset +stress_seq=i2c_target_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=156013621 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/9.i2c_target_stress_all_with_rand_reset.156013621 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 9.i2c_target_stress_all_with_rand_reset.156013621 -covoverwrite' seed=90335535380862943897906292056864854692244797011858615158354515493404097156149 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90335535380862943897906292056864854692244797011858615158354515493404097156149 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_target_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 19142064138967787597801697162695648394477800346131064264576985601677899910202 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3141585978 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/9.i2c_host_mode_toggle.3141585978 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 9.i2c_host_mode_toggle.3141585978 -covoverwrite' seed=19142064138967787597801697162695648394477800346131064264576985601677899910202 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19142064138967787597801697162695648394477800346131064264576985601677899910202 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 106648154150402295911705581524687638785476869796648629386374156087845570542172 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2606037596 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/9.i2c_host_may_nack.2606037596 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 9.i2c_host_may_nack.2606037596 -covoverwrite' seed=106648154150402295911705581524687638785476869796648629386374156087845570542172 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106648154150402295911705581524687638785476869796648629386374156087845570542172 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 112558309809512472769245225656722432160518999591539964621053832419471760771733 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2487175829 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/9.i2c_target_nack_acqfull.2487175829 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 9.i2c_target_nack_acqfull.2487175829 -covoverwrite' seed=112558309809512472769245225656722432160518999591539964621053832419471760771733 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112558309809512472769245225656722432160518999591539964621053832419471760771733 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 81303994741066869560819244877125254743197126923397539020608118950581583362930 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3994696562 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/9.i2c_target_nack_acqfull_addr.3994696562 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 9.i2c_target_nack_acqfull_addr.3994696562 -covoverwrite' seed=81303994741066869560819244877125254743197126923397539020608118950581583362930 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81303994741066869560819244877125254743197126923397539020608118950581583362930 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_txstretch 66701027901718249807516110342986048374899446113520808225277345755218374776125 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_target_nack_txstretch/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2085311805 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/9.i2c_target_nack_txstretch.2085311805 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 9.i2c_target_nack_txstretch.2085311805 -covoverwrite' seed=66701027901718249807516110342986048374899446113520808225277345755218374776125 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66701027901718249807516110342986048374899446113520808225277345755218374776125 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_target_nack_txstretch/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_txstretch_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_errors 91117895756742405023982647714097522544249309865649878883988491986325368261211 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1270663771 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/9.i2c_tl_errors.1270663771 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.i2c_tl_errors.1270663771 -covoverwrite' seed=91117895756742405023982647714097522544249309865649878883988491986325368261211 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91117895756742405023982647714097522544249309865649878883988491986325368261211 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_intg_err 103259754234977301824520710180619650697309641322562889602865078085714291717997 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=612890477 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/9.i2c_tl_intg_err.612890477 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.i2c_tl_intg_err.612890477 -covoverwrite' seed=103259754234977301824520710180619650697309641322562889602865078085714291717997 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103259754234977301824520710180619650697309641322562889602865078085714291717997 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_intr_test 44273040709510954944323780145299805805736459663789894304005055351848895058263 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1140920663 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/9.i2c_intr_test.1140920663 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.i2c_intr_test.1140920663 -covoverwrite' seed=44273040709510954944323780145299805805736459663789894304005055351848895058263 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44273040709510954944323780145299805805736459663789894304005055351848895058263 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_alert_test 12757070362846130853525842524345280684535519066079479560574609749908705905845 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1568017589 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/9.i2c_alert_test.1568017589 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 9.i2c_alert_test.1568017589 -covoverwrite' seed=12757070362846130853525842524345280684535519066079479560574609749908705905845 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12757070362846130853525842524345280684535519066079479560574609749908705905845 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/9.i2c_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 32821684813032747555389629771703872263438661268819289197688378605304420209797 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/10.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3739980933 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/10.i2c_host_override.3739980933 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 10.i2c_host_override.3739980933 -covoverwrite' seed=32821684813032747555389629771703872263438661268819289197688378605304420209797 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32821684813032747555389629771703872263438661268819289197688378605304420209797 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/10.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_reset_fmt 47709808493916999645683531220568645331447113144033577297088721403164857101957 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/10.i2c_host_fifo_reset_fmt/latest run_opts='+test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3492179589 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/10.i2c_host_fifo_reset_fmt.3492179589 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 10.i2c_host_fifo_reset_fmt.3492179589 -covoverwrite' seed=47709808493916999645683531220568645331447113144033577297088721403164857101957 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47709808493916999645683531220568645331447113144033577297088721403164857101957 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/10.i2c_host_fifo_reset_fmt/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_reset_fmt_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 50125080821825398560427088703845753084054013961841632431665961727220801004503 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/10.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1489953751 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/10.i2c_host_error_intr.1489953751 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 10.i2c_host_error_intr.1489953751 -covoverwrite' seed=50125080821825398560427088703845753084054013961841632431665961727220801004503 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50125080821825398560427088703845753084054013961841632431665961727220801004503 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/10.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all 94708057440289954739977210505016455337125373909085908138691547762531258702880 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/10.i2c_host_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3793591328 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/10.i2c_host_stress_all.3793591328 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 10.i2c_host_stress_all.3793591328 -covoverwrite' seed=94708057440289954739977210505016455337125373909085908138691547762531258702880 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94708057440289954739977210505016455337125373909085908138691547762531258702880 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/10.i2c_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 33862611548134363281232871385846631302743114044852027669227580420955427834940 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/10.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4114877500 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/10.i2c_target_fifo_reset_tx.4114877500 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 10.i2c_target_fifo_reset_tx.4114877500 -covoverwrite' seed=33862611548134363281232871385846631302743114044852027669227580420955427834940 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33862611548134363281232871385846631302743114044852027669227580420955427834940 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/10.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all 16213108925606336621409047292049920147020656668344999460883831183974421881979 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/10.i2c_target_stress_all/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=785769595 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/10.i2c_target_stress_all.785769595 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 10.i2c_target_stress_all.785769595 -covoverwrite' seed=16213108925606336621409047292049920147020656668344999460883831183974421881979 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16213108925606336621409047292049920147020656668344999460883831183974421881979 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/10.i2c_target_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 2765959871867085935238604243404652670305707811239347169244947287900057052642 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/10.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2497521122 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/10.i2c_target_hrst.2497521122 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 10.i2c_target_hrst.2497521122 -covoverwrite' seed=2765959871867085935238604243404652670305707811239347169244947287900057052642 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2765959871867085935238604243404652670305707811239347169244947287900057052642 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/10.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 28174025163314159648156405074901247636404064891722138517217419717978483686491 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/10.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1816231003 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/10.i2c_host_mode_toggle.1816231003 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 10.i2c_host_mode_toggle.1816231003 -covoverwrite' seed=28174025163314159648156405074901247636404064891722138517217419717978483686491 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28174025163314159648156405074901247636404064891722138517217419717978483686491 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/10.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 44981566186854269420148749025453026762700351076068006021982091145493109229942 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/10.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2522827126 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/10.i2c_host_may_nack.2522827126 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 10.i2c_host_may_nack.2522827126 -covoverwrite' seed=44981566186854269420148749025453026762700351076068006021982091145493109229942 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44981566186854269420148749025453026762700351076068006021982091145493109229942 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/10.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 60326553548635638662646632738183653112771735308996730693932477445928622408128 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/10.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2821636544 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/10.i2c_target_nack_acqfull.2821636544 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 10.i2c_target_nack_acqfull.2821636544 -covoverwrite' seed=60326553548635638662646632738183653112771735308996730693932477445928622408128 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60326553548635638662646632738183653112771735308996730693932477445928622408128 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/10.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 25623540841016098293623103276380781190853233003669535542173279301933438160037 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/10.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3825028261 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/10.i2c_target_nack_acqfull_addr.3825028261 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 10.i2c_target_nack_acqfull_addr.3825028261 -covoverwrite' seed=25623540841016098293623103276380781190853233003669535542173279301933438160037 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25623540841016098293623103276380781190853233003669535542173279301933438160037 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/10.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_txstretch 103175570972264746694009720780345090281390358657987814994902316814900441428561 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/10.i2c_target_nack_txstretch/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=167031377 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/10.i2c_target_nack_txstretch.167031377 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 10.i2c_target_nack_txstretch.167031377 -covoverwrite' seed=103175570972264746694009720780345090281390358657987814994902316814900441428561 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103175570972264746694009720780345090281390358657987814994902316814900441428561 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/10.i2c_target_nack_txstretch/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_txstretch_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_errors 84127724080949179929655090308163688272354996120244265322205110134099218876629 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/10.i2c_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=250431701 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/10.i2c_tl_errors.250431701 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 10.i2c_tl_errors.250431701 -covoverwrite' seed=84127724080949179929655090308163688272354996120244265322205110134099218876629 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84127724080949179929655090308163688272354996120244265322205110134099218876629 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/10.i2c_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_intg_err 44957583210587709013077964468966036207394411903413524768871485742504727736439 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/10.i2c_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4292276343 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/10.i2c_tl_intg_err.4292276343 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 10.i2c_tl_intg_err.4292276343 -covoverwrite' seed=44957583210587709013077964468966036207394411903413524768871485742504727736439 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44957583210587709013077964468966036207394411903413524768871485742504727736439 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/10.i2c_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 22505493497603213171384133855965494363956908384689613263935795231126656603376 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/11.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=340743408 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/11.i2c_host_override.340743408 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 11.i2c_host_override.340743408 -covoverwrite' seed=22505493497603213171384133855965494363956908384689613263935795231126656603376 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22505493497603213171384133855965494363956908384689613263935795231126656603376 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/11.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_reset_fmt 63246046111374671295960207325200147251275224819215510817919203250993416081251 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/11.i2c_host_fifo_reset_fmt/latest run_opts='+test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1500221283 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/11.i2c_host_fifo_reset_fmt.1500221283 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 11.i2c_host_fifo_reset_fmt.1500221283 -covoverwrite' seed=63246046111374671295960207325200147251275224819215510817919203250993416081251 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63246046111374671295960207325200147251275224819215510817919203250993416081251 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/11.i2c_host_fifo_reset_fmt/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_reset_fmt_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 114995614725994829614098574007012541205949329022375357526393242867219194376202 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/11.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=971960330 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/11.i2c_host_error_intr.971960330 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 11.i2c_host_error_intr.971960330 -covoverwrite' seed=114995614725994829614098574007012541205949329022375357526393242867219194376202 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114995614725994829614098574007012541205949329022375357526393242867219194376202 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/11.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all 13893734910454470558787832118142417928296709592860421269261529301255195453575 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/11.i2c_host_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2871781511 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/11.i2c_host_stress_all.2871781511 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 11.i2c_host_stress_all.2871781511 -covoverwrite' seed=13893734910454470558787832118142417928296709592860421269261529301255195453575 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13893734910454470558787832118142417928296709592860421269261529301255195453575 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/11.i2c_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 53968477642345980239161959344115673951349474510617776588680209012343665923979 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/11.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=721491851 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/11.i2c_target_fifo_reset_tx.721491851 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 11.i2c_target_fifo_reset_tx.721491851 -covoverwrite' seed=53968477642345980239161959344115673951349474510617776588680209012343665923979 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53968477642345980239161959344115673951349474510617776588680209012343665923979 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/11.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all 69734247234668966162735473357916947065441629485604719259739182825366422253583 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/11.i2c_target_stress_all/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4262686735 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/11.i2c_target_stress_all.4262686735 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 11.i2c_target_stress_all.4262686735 -covoverwrite' seed=69734247234668966162735473357916947065441629485604719259739182825366422253583 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69734247234668966162735473357916947065441629485604719259739182825366422253583 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/11.i2c_target_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 79882843459019944747621794070750029572916341619641398987560000710485342181486 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/11.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=907040878 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/11.i2c_target_hrst.907040878 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 11.i2c_target_hrst.907040878 -covoverwrite' seed=79882843459019944747621794070750029572916341619641398987560000710485342181486 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79882843459019944747621794070750029572916341619641398987560000710485342181486 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/11.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 79650231315895685221745523128519911890070502224769193857002877286475042156711 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/11.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2223796391 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/11.i2c_host_mode_toggle.2223796391 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 11.i2c_host_mode_toggle.2223796391 -covoverwrite' seed=79650231315895685221745523128519911890070502224769193857002877286475042156711 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79650231315895685221745523128519911890070502224769193857002877286475042156711 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/11.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 27997015052757090019400283405547636962533483370710575864283911564634935069712 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/11.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2779319312 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/11.i2c_host_may_nack.2779319312 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 11.i2c_host_may_nack.2779319312 -covoverwrite' seed=27997015052757090019400283405547636962533483370710575864283911564634935069712 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27997015052757090019400283405547636962533483370710575864283911564634935069712 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/11.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 35158143525536674447337861682045681804668643145235942412155645657372708881783 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/11.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4093166967 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/11.i2c_target_nack_acqfull.4093166967 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 11.i2c_target_nack_acqfull.4093166967 -covoverwrite' seed=35158143525536674447337861682045681804668643145235942412155645657372708881783 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35158143525536674447337861682045681804668643145235942412155645657372708881783 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/11.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 21302481759725991705800314615433460940616014510769408649018697781307327276434 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/11.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=315516306 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/11.i2c_target_nack_acqfull_addr.315516306 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 11.i2c_target_nack_acqfull_addr.315516306 -covoverwrite' seed=21302481759725991705800314615433460940616014510769408649018697781307327276434 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21302481759725991705800314615433460940616014510769408649018697781307327276434 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/11.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_txstretch 62782733349483781226806544187395096345421478446809286918636669567056167443481 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/11.i2c_target_nack_txstretch/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1549409305 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/11.i2c_target_nack_txstretch.1549409305 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 11.i2c_target_nack_txstretch.1549409305 -covoverwrite' seed=62782733349483781226806544187395096345421478446809286918636669567056167443481 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62782733349483781226806544187395096345421478446809286918636669567056167443481 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/11.i2c_target_nack_txstretch/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_txstretch_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_errors 59706939946389184012152065818827477900206565270456912385360708234573148931741 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/11.i2c_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=158418589 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/11.i2c_tl_errors.158418589 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 11.i2c_tl_errors.158418589 -covoverwrite' seed=59706939946389184012152065818827477900206565270456912385360708234573148931741 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=59706939946389184012152065818827477900206565270456912385360708234573148931741 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/11.i2c_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_intg_err 70929220043522220753900840186552820272128910444427933717612389600238104031069 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/11.i2c_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2731093853 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/11.i2c_tl_intg_err.2731093853 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 11.i2c_tl_intg_err.2731093853 -covoverwrite' seed=70929220043522220753900840186552820272128910444427933717612389600238104031069 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70929220043522220753900840186552820272128910444427933717612389600238104031069 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/11.i2c_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 44181468525199236244608686973624568218487140748319398664257126894022149308666 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/12.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3132653818 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/12.i2c_host_override.3132653818 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 12.i2c_host_override.3132653818 -covoverwrite' seed=44181468525199236244608686973624568218487140748319398664257126894022149308666 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44181468525199236244608686973624568218487140748319398664257126894022149308666 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/12.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_reset_fmt 34272691657185116640655484921097655965974873373404948329507090936472866247399 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/12.i2c_host_fifo_reset_fmt/latest run_opts='+test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3036533479 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/12.i2c_host_fifo_reset_fmt.3036533479 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 12.i2c_host_fifo_reset_fmt.3036533479 -covoverwrite' seed=34272691657185116640655484921097655965974873373404948329507090936472866247399 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34272691657185116640655484921097655965974873373404948329507090936472866247399 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/12.i2c_host_fifo_reset_fmt/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_reset_fmt_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 43785297455087522948705175935031317842838179400778823844601574734169979742392 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/12.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1378871480 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/12.i2c_host_error_intr.1378871480 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 12.i2c_host_error_intr.1378871480 -covoverwrite' seed=43785297455087522948705175935031317842838179400778823844601574734169979742392 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43785297455087522948705175935031317842838179400778823844601574734169979742392 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/12.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all 33182648919898169995180072523966119609907665474834131121402520826493681993968 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/12.i2c_host_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2301561072 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/12.i2c_host_stress_all.2301561072 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 12.i2c_host_stress_all.2301561072 -covoverwrite' seed=33182648919898169995180072523966119609907665474834131121402520826493681993968 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33182648919898169995180072523966119609907665474834131121402520826493681993968 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/12.i2c_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 57111819123515787859331945460261422459123520502727945478852547404503590967435 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/12.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1502419083 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/12.i2c_target_fifo_reset_tx.1502419083 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 12.i2c_target_fifo_reset_tx.1502419083 -covoverwrite' seed=57111819123515787859331945460261422459123520502727945478852547404503590967435 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57111819123515787859331945460261422459123520502727945478852547404503590967435 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/12.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all 62577329343236635099733424740765604976459445990626409936256058000083404188906 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/12.i2c_target_stress_all/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=641723626 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/12.i2c_target_stress_all.641723626 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 12.i2c_target_stress_all.641723626 -covoverwrite' seed=62577329343236635099733424740765604976459445990626409936256058000083404188906 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62577329343236635099733424740765604976459445990626409936256058000083404188906 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/12.i2c_target_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 33763520441728243202607556386431138107888940761323774799767595754745727887843 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/12.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=5843427 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/12.i2c_target_hrst.5843427 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 12.i2c_target_hrst.5843427 -covoverwrite' seed=33763520441728243202607556386431138107888940761323774799767595754745727887843 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33763520441728243202607556386431138107888940761323774799767595754745727887843 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/12.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 9323279218327209935410238353175023400993947217052808120953394360503450068017 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/12.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3755598897 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/12.i2c_host_mode_toggle.3755598897 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 12.i2c_host_mode_toggle.3755598897 -covoverwrite' seed=9323279218327209935410238353175023400993947217052808120953394360503450068017 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9323279218327209935410238353175023400993947217052808120953394360503450068017 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/12.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 46283457083258446351832388027338361996259795092673221686763656239825172169104 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/12.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1067843984 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/12.i2c_host_may_nack.1067843984 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 12.i2c_host_may_nack.1067843984 -covoverwrite' seed=46283457083258446351832388027338361996259795092673221686763656239825172169104 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46283457083258446351832388027338361996259795092673221686763656239825172169104 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/12.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 93931289919102078147012078236677591342888392479382908473892805391204453289881 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/12.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=414814105 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/12.i2c_target_nack_acqfull.414814105 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 12.i2c_target_nack_acqfull.414814105 -covoverwrite' seed=93931289919102078147012078236677591342888392479382908473892805391204453289881 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93931289919102078147012078236677591342888392479382908473892805391204453289881 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/12.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 19799354087520653070480903261861115098323513429137558999915411349441905913479 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/12.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3056037511 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/12.i2c_target_nack_acqfull_addr.3056037511 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 12.i2c_target_nack_acqfull_addr.3056037511 -covoverwrite' seed=19799354087520653070480903261861115098323513429137558999915411349441905913479 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19799354087520653070480903261861115098323513429137558999915411349441905913479 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/12.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_txstretch 101932343459040021364835161255837894651434592524194752265153026718621632773213 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/12.i2c_target_nack_txstretch/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=498285661 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/12.i2c_target_nack_txstretch.498285661 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 12.i2c_target_nack_txstretch.498285661 -covoverwrite' seed=101932343459040021364835161255837894651434592524194752265153026718621632773213 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101932343459040021364835161255837894651434592524194752265153026718621632773213 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/12.i2c_target_nack_txstretch/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_txstretch_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_errors 78355610707582039877259250393357453114709341277612229451792503409110640295238 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/12.i2c_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=917044550 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/12.i2c_tl_errors.917044550 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 12.i2c_tl_errors.917044550 -covoverwrite' seed=78355610707582039877259250393357453114709341277612229451792503409110640295238 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78355610707582039877259250393357453114709341277612229451792503409110640295238 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/12.i2c_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_intg_err 85288232484251312680557514617120388486603629946243474892692412993576866718523 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/12.i2c_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1433969467 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/12.i2c_tl_intg_err.1433969467 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 12.i2c_tl_intg_err.1433969467 -covoverwrite' seed=85288232484251312680557514617120388486603629946243474892692412993576866718523 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85288232484251312680557514617120388486603629946243474892692412993576866718523 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/12.i2c_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 104027774130630111464057518080680268106424704526066699383221350506778081617719 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/13.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1017112375 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/13.i2c_host_override.1017112375 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 13.i2c_host_override.1017112375 -covoverwrite' seed=104027774130630111464057518080680268106424704526066699383221350506778081617719 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104027774130630111464057518080680268106424704526066699383221350506778081617719 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/13.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_reset_fmt 72715934579174130726094800958236657284548773429625077414777692718716424849155 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/13.i2c_host_fifo_reset_fmt/latest run_opts='+test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3356002051 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/13.i2c_host_fifo_reset_fmt.3356002051 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 13.i2c_host_fifo_reset_fmt.3356002051 -covoverwrite' seed=72715934579174130726094800958236657284548773429625077414777692718716424849155 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72715934579174130726094800958236657284548773429625077414777692718716424849155 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/13.i2c_host_fifo_reset_fmt/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_reset_fmt_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 62867611471555058765936765947839511752709568050838488393684418283854444681402 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/13.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3930380474 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/13.i2c_host_error_intr.3930380474 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 13.i2c_host_error_intr.3930380474 -covoverwrite' seed=62867611471555058765936765947839511752709568050838488393684418283854444681402 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62867611471555058765936765947839511752709568050838488393684418283854444681402 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/13.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all 73137376323778410971311319901924942862696879952019432737193483251943770803708 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/13.i2c_host_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=578670076 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/13.i2c_host_stress_all.578670076 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 13.i2c_host_stress_all.578670076 -covoverwrite' seed=73137376323778410971311319901924942862696879952019432737193483251943770803708 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73137376323778410971311319901924942862696879952019432737193483251943770803708 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/13.i2c_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 37291603302828386731360755687133902285908920292753006054492805545762244729751 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/13.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=685448087 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/13.i2c_target_fifo_reset_tx.685448087 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 13.i2c_target_fifo_reset_tx.685448087 -covoverwrite' seed=37291603302828386731360755687133902285908920292753006054492805545762244729751 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37291603302828386731360755687133902285908920292753006054492805545762244729751 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/13.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all 37684930292433739478397916107208492134909564890220623025375805867387204119832 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/13.i2c_target_stress_all/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=377203992 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/13.i2c_target_stress_all.377203992 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 13.i2c_target_stress_all.377203992 -covoverwrite' seed=37684930292433739478397916107208492134909564890220623025375805867387204119832 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37684930292433739478397916107208492134909564890220623025375805867387204119832 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/13.i2c_target_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 53263649218727896662976796511742210738134200192722240434454993527520500292446 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/13.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2627115870 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/13.i2c_target_hrst.2627115870 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 13.i2c_target_hrst.2627115870 -covoverwrite' seed=53263649218727896662976796511742210738134200192722240434454993527520500292446 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53263649218727896662976796511742210738134200192722240434454993527520500292446 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/13.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 20576075558206094710099535139711814775618077018102397777247573901542515639516 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/13.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1540195548 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/13.i2c_host_mode_toggle.1540195548 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 13.i2c_host_mode_toggle.1540195548 -covoverwrite' seed=20576075558206094710099535139711814775618077018102397777247573901542515639516 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20576075558206094710099535139711814775618077018102397777247573901542515639516 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/13.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 110106508678162416902892183808116218299122823035073165233075456353739401301251 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/13.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=937135363 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/13.i2c_host_may_nack.937135363 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 13.i2c_host_may_nack.937135363 -covoverwrite' seed=110106508678162416902892183808116218299122823035073165233075456353739401301251 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110106508678162416902892183808116218299122823035073165233075456353739401301251 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/13.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 97924865486207331629230318472043907939085080721759315663502199365669620846298 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/13.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=799051482 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/13.i2c_target_nack_acqfull.799051482 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 13.i2c_target_nack_acqfull.799051482 -covoverwrite' seed=97924865486207331629230318472043907939085080721759315663502199365669620846298 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97924865486207331629230318472043907939085080721759315663502199365669620846298 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/13.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 77578190663690332054103800824005626917665902798486835531347169482359810080123 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/13.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2845359483 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/13.i2c_target_nack_acqfull_addr.2845359483 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 13.i2c_target_nack_acqfull_addr.2845359483 -covoverwrite' seed=77578190663690332054103800824005626917665902798486835531347169482359810080123 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77578190663690332054103800824005626917665902798486835531347169482359810080123 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/13.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_txstretch 87052267439329338694533011331994239030878957884512726644585484661218452831467 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/13.i2c_target_nack_txstretch/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2521693419 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/13.i2c_target_nack_txstretch.2521693419 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 13.i2c_target_nack_txstretch.2521693419 -covoverwrite' seed=87052267439329338694533011331994239030878957884512726644585484661218452831467 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87052267439329338694533011331994239030878957884512726644585484661218452831467 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/13.i2c_target_nack_txstretch/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_txstretch_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_errors 49639380561664118420051292477104114004233619172683441230903322109027875939982 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/13.i2c_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=268035726 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/13.i2c_tl_errors.268035726 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 13.i2c_tl_errors.268035726 -covoverwrite' seed=49639380561664118420051292477104114004233619172683441230903322109027875939982 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49639380561664118420051292477104114004233619172683441230903322109027875939982 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/13.i2c_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_intg_err 11451166874359472824645403820774902924144772873048446246134271554963713336884 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/13.i2c_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3342378548 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/13.i2c_tl_intg_err.3342378548 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 13.i2c_tl_intg_err.3342378548 -covoverwrite' seed=11451166874359472824645403820774902924144772873048446246134271554963713336884 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11451166874359472824645403820774902924144772873048446246134271554963713336884 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/13.i2c_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 79305507693317960524157999531871336120117986111888609135565945753050822725372 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/14.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3868970748 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/14.i2c_host_override.3868970748 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 14.i2c_host_override.3868970748 -covoverwrite' seed=79305507693317960524157999531871336120117986111888609135565945753050822725372 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79305507693317960524157999531871336120117986111888609135565945753050822725372 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/14.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_reset_fmt 93343807966546959711598650388851629951505051016834457042004569380654100703743 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/14.i2c_host_fifo_reset_fmt/latest run_opts='+test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2323048959 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/14.i2c_host_fifo_reset_fmt.2323048959 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 14.i2c_host_fifo_reset_fmt.2323048959 -covoverwrite' seed=93343807966546959711598650388851629951505051016834457042004569380654100703743 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93343807966546959711598650388851629951505051016834457042004569380654100703743 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/14.i2c_host_fifo_reset_fmt/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_reset_fmt_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 94804059486117438255427606833137997489732045924835230037522840286615925922988 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/14.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2161089708 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/14.i2c_host_error_intr.2161089708 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 14.i2c_host_error_intr.2161089708 -covoverwrite' seed=94804059486117438255427606833137997489732045924835230037522840286615925922988 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94804059486117438255427606833137997489732045924835230037522840286615925922988 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/14.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all 82286630332351270816528706833115166369798480348828953930421224759722758091665 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/14.i2c_host_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2894312337 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/14.i2c_host_stress_all.2894312337 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 14.i2c_host_stress_all.2894312337 -covoverwrite' seed=82286630332351270816528706833115166369798480348828953930421224759722758091665 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82286630332351270816528706833115166369798480348828953930421224759722758091665 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/14.i2c_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 98313216755247955126102666698654677939929468742655588178150384039359975897467 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/14.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=586791291 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/14.i2c_target_fifo_reset_tx.586791291 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 14.i2c_target_fifo_reset_tx.586791291 -covoverwrite' seed=98313216755247955126102666698654677939929468742655588178150384039359975897467 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98313216755247955126102666698654677939929468742655588178150384039359975897467 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/14.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all 26186203793808820739132670857366147208538269482815571326141462039117082247362 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/14.i2c_target_stress_all/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3940139202 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/14.i2c_target_stress_all.3940139202 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 14.i2c_target_stress_all.3940139202 -covoverwrite' seed=26186203793808820739132670857366147208538269482815571326141462039117082247362 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26186203793808820739132670857366147208538269482815571326141462039117082247362 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/14.i2c_target_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 52880404410210870329275179466301668520070570755533098634030779700013501561294 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/14.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1612233166 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/14.i2c_target_hrst.1612233166 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 14.i2c_target_hrst.1612233166 -covoverwrite' seed=52880404410210870329275179466301668520070570755533098634030779700013501561294 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=52880404410210870329275179466301668520070570755533098634030779700013501561294 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/14.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 55732533458343403930543756326779528632705780367181713944656499617341060298477 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/14.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=684078829 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/14.i2c_host_mode_toggle.684078829 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 14.i2c_host_mode_toggle.684078829 -covoverwrite' seed=55732533458343403930543756326779528632705780367181713944656499617341060298477 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55732533458343403930543756326779528632705780367181713944656499617341060298477 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/14.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 1522631166182677595322629525391948865720833569224968655795072496624185749667 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/14.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=586002595 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/14.i2c_host_may_nack.586002595 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 14.i2c_host_may_nack.586002595 -covoverwrite' seed=1522631166182677595322629525391948865720833569224968655795072496624185749667 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1522631166182677595322629525391948865720833569224968655795072496624185749667 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/14.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 3693303274164125787553331636577200455385924826355102810790576156574763083546 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/14.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2023384858 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/14.i2c_target_nack_acqfull.2023384858 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 14.i2c_target_nack_acqfull.2023384858 -covoverwrite' seed=3693303274164125787553331636577200455385924826355102810790576156574763083546 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3693303274164125787553331636577200455385924826355102810790576156574763083546 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/14.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 59678655731969118173356378181498335632460147220160039553952204605304700836257 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/14.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3025836449 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/14.i2c_target_nack_acqfull_addr.3025836449 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 14.i2c_target_nack_acqfull_addr.3025836449 -covoverwrite' seed=59678655731969118173356378181498335632460147220160039553952204605304700836257 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=59678655731969118173356378181498335632460147220160039553952204605304700836257 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/14.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_txstretch 45872009774632047326924993138062844673548503783383808611676348898190522841960 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/14.i2c_target_nack_txstretch/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2698247016 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/14.i2c_target_nack_txstretch.2698247016 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 14.i2c_target_nack_txstretch.2698247016 -covoverwrite' seed=45872009774632047326924993138062844673548503783383808611676348898190522841960 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45872009774632047326924993138062844673548503783383808611676348898190522841960 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/14.i2c_target_nack_txstretch/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_txstretch_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_errors 5013356504074022077105940357771809090496465667167052411035130097225309524336 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/14.i2c_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3462566256 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/14.i2c_tl_errors.3462566256 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 14.i2c_tl_errors.3462566256 -covoverwrite' seed=5013356504074022077105940357771809090496465667167052411035130097225309524336 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5013356504074022077105940357771809090496465667167052411035130097225309524336 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/14.i2c_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_intg_err 110701278795055816622834149383898082375606567837090398080610109444674005953548 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/14.i2c_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1895230476 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/14.i2c_tl_intg_err.1895230476 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 14.i2c_tl_intg_err.1895230476 -covoverwrite' seed=110701278795055816622834149383898082375606567837090398080610109444674005953548 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110701278795055816622834149383898082375606567837090398080610109444674005953548 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/14.i2c_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 10833178012853699345920784266928355031316895199997267552276017151007833131456 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/15.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3846113728 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/15.i2c_host_override.3846113728 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 15.i2c_host_override.3846113728 -covoverwrite' seed=10833178012853699345920784266928355031316895199997267552276017151007833131456 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10833178012853699345920784266928355031316895199997267552276017151007833131456 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/15.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_reset_fmt 2050892169693599902755805732339411764313603174984101222372225596511847355572 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/15.i2c_host_fifo_reset_fmt/latest run_opts='+test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=541758644 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/15.i2c_host_fifo_reset_fmt.541758644 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 15.i2c_host_fifo_reset_fmt.541758644 -covoverwrite' seed=2050892169693599902755805732339411764313603174984101222372225596511847355572 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2050892169693599902755805732339411764313603174984101222372225596511847355572 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/15.i2c_host_fifo_reset_fmt/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_reset_fmt_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 97026145707052820564204242635661111469957291922042811622866060923455536903522 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/15.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=567031138 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/15.i2c_host_error_intr.567031138 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 15.i2c_host_error_intr.567031138 -covoverwrite' seed=97026145707052820564204242635661111469957291922042811622866060923455536903522 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97026145707052820564204242635661111469957291922042811622866060923455536903522 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/15.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all 38253422754379870964365125386482582261727664499167759697701090431278138374481 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/15.i2c_host_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2675554641 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/15.i2c_host_stress_all.2675554641 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 15.i2c_host_stress_all.2675554641 -covoverwrite' seed=38253422754379870964365125386482582261727664499167759697701090431278138374481 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38253422754379870964365125386482582261727664499167759697701090431278138374481 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/15.i2c_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 1396477049303243494499400259015353086210776859600463053468748730621803230615 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/15.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1643771287 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/15.i2c_target_fifo_reset_tx.1643771287 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 15.i2c_target_fifo_reset_tx.1643771287 -covoverwrite' seed=1396477049303243494499400259015353086210776859600463053468748730621803230615 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1396477049303243494499400259015353086210776859600463053468748730621803230615 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/15.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all 111381736945416255493965992124399018191129579094673934803097819317525779429701 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/15.i2c_target_stress_all/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1830402373 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/15.i2c_target_stress_all.1830402373 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 15.i2c_target_stress_all.1830402373 -covoverwrite' seed=111381736945416255493965992124399018191129579094673934803097819317525779429701 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111381736945416255493965992124399018191129579094673934803097819317525779429701 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/15.i2c_target_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 82874923469785707800289442113212168696025113756405873878739919574248877484828 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/15.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=274492188 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/15.i2c_target_hrst.274492188 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 15.i2c_target_hrst.274492188 -covoverwrite' seed=82874923469785707800289442113212168696025113756405873878739919574248877484828 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82874923469785707800289442113212168696025113756405873878739919574248877484828 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/15.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 110512481115157153904837909174342908107601864549187263806254211000950376148832 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/15.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=912830304 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/15.i2c_host_mode_toggle.912830304 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 15.i2c_host_mode_toggle.912830304 -covoverwrite' seed=110512481115157153904837909174342908107601864549187263806254211000950376148832 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110512481115157153904837909174342908107601864549187263806254211000950376148832 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/15.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 26355461404772049813948006037900220417086971273822480710346841845296842125414 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/15.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=251900006 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/15.i2c_host_may_nack.251900006 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 15.i2c_host_may_nack.251900006 -covoverwrite' seed=26355461404772049813948006037900220417086971273822480710346841845296842125414 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26355461404772049813948006037900220417086971273822480710346841845296842125414 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/15.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 42480389069372963588870212085313099077568202715346625598633166023602259583968 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/15.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2114413536 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/15.i2c_target_nack_acqfull.2114413536 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 15.i2c_target_nack_acqfull.2114413536 -covoverwrite' seed=42480389069372963588870212085313099077568202715346625598633166023602259583968 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42480389069372963588870212085313099077568202715346625598633166023602259583968 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/15.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 99034983269178839932766664945292808283189134294403440038716965835792633595535 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/15.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3937961615 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/15.i2c_target_nack_acqfull_addr.3937961615 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 15.i2c_target_nack_acqfull_addr.3937961615 -covoverwrite' seed=99034983269178839932766664945292808283189134294403440038716965835792633595535 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99034983269178839932766664945292808283189134294403440038716965835792633595535 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/15.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_txstretch 22158842456320584756290225224871987104991196194500858792112216122983676666824 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/15.i2c_target_nack_txstretch/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2593678280 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/15.i2c_target_nack_txstretch.2593678280 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 15.i2c_target_nack_txstretch.2593678280 -covoverwrite' seed=22158842456320584756290225224871987104991196194500858792112216122983676666824 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22158842456320584756290225224871987104991196194500858792112216122983676666824 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/15.i2c_target_nack_txstretch/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_txstretch_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_errors 60215383033913604913787496167664196003606376286116650656285302287400848473145 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/15.i2c_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1509571641 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/15.i2c_tl_errors.1509571641 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 15.i2c_tl_errors.1509571641 -covoverwrite' seed=60215383033913604913787496167664196003606376286116650656285302287400848473145 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60215383033913604913787496167664196003606376286116650656285302287400848473145 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/15.i2c_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_intg_err 53257388707173742332139257795422154405050696637260321850657860943132562856893 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/15.i2c_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1008507837 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/15.i2c_tl_intg_err.1008507837 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 15.i2c_tl_intg_err.1008507837 -covoverwrite' seed=53257388707173742332139257795422154405050696637260321850657860943132562856893 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53257388707173742332139257795422154405050696637260321850657860943132562856893 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/15.i2c_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 61494232458378468969536249807609996187315380353703656886002777179132925647972 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/16.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1969822820 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/16.i2c_host_override.1969822820 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 16.i2c_host_override.1969822820 -covoverwrite' seed=61494232458378468969536249807609996187315380353703656886002777179132925647972 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61494232458378468969536249807609996187315380353703656886002777179132925647972 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/16.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_reset_fmt 55448495835499788224464727070216201796112673987540461721626047045269970169528 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/16.i2c_host_fifo_reset_fmt/latest run_opts='+test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3709284024 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/16.i2c_host_fifo_reset_fmt.3709284024 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 16.i2c_host_fifo_reset_fmt.3709284024 -covoverwrite' seed=55448495835499788224464727070216201796112673987540461721626047045269970169528 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55448495835499788224464727070216201796112673987540461721626047045269970169528 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/16.i2c_host_fifo_reset_fmt/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_reset_fmt_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 26987224442957420915738916575730095876073365674364544659310912552319502882048 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/16.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=870683904 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/16.i2c_host_error_intr.870683904 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 16.i2c_host_error_intr.870683904 -covoverwrite' seed=26987224442957420915738916575730095876073365674364544659310912552319502882048 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26987224442957420915738916575730095876073365674364544659310912552319502882048 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/16.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all 39627288145666691112570659106636980378263077165289584167853515450229194752080 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/16.i2c_host_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=220201040 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/16.i2c_host_stress_all.220201040 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 16.i2c_host_stress_all.220201040 -covoverwrite' seed=39627288145666691112570659106636980378263077165289584167853515450229194752080 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39627288145666691112570659106636980378263077165289584167853515450229194752080 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/16.i2c_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 3104101392221636281242066217975788374011653841138409104499765967260404521213 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/16.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2213124349 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/16.i2c_target_fifo_reset_tx.2213124349 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 16.i2c_target_fifo_reset_tx.2213124349 -covoverwrite' seed=3104101392221636281242066217975788374011653841138409104499765967260404521213 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3104101392221636281242066217975788374011653841138409104499765967260404521213 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/16.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all 8311604422046111529357213875721048966520852876967303252792740183355603617400 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/16.i2c_target_stress_all/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=88671864 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/16.i2c_target_stress_all.88671864 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 16.i2c_target_stress_all.88671864 -covoverwrite' seed=8311604422046111529357213875721048966520852876967303252792740183355603617400 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8311604422046111529357213875721048966520852876967303252792740183355603617400 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/16.i2c_target_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 73846045110619415782335851666596391590676033636242413853359761230568513783509 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/16.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3519727317 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/16.i2c_target_hrst.3519727317 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 16.i2c_target_hrst.3519727317 -covoverwrite' seed=73846045110619415782335851666596391590676033636242413853359761230568513783509 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73846045110619415782335851666596391590676033636242413853359761230568513783509 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/16.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 34458864170099579298885945307578634114401268578994674069443110854874699417874 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/16.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2973780242 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/16.i2c_host_mode_toggle.2973780242 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 16.i2c_host_mode_toggle.2973780242 -covoverwrite' seed=34458864170099579298885945307578634114401268578994674069443110854874699417874 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34458864170099579298885945307578634114401268578994674069443110854874699417874 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/16.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 71405391018482425684699586398411700526264571197671498507716693578025315876367 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/16.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2877832719 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/16.i2c_host_may_nack.2877832719 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 16.i2c_host_may_nack.2877832719 -covoverwrite' seed=71405391018482425684699586398411700526264571197671498507716693578025315876367 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71405391018482425684699586398411700526264571197671498507716693578025315876367 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/16.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 2063092726558982878520474094346353217879351273786442805899759024872666562343 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/16.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=306577191 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/16.i2c_target_nack_acqfull.306577191 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 16.i2c_target_nack_acqfull.306577191 -covoverwrite' seed=2063092726558982878520474094346353217879351273786442805899759024872666562343 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2063092726558982878520474094346353217879351273786442805899759024872666562343 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/16.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 73848323751444946609193666907347226796125381555188380361239414741823069142653 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/16.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4018454141 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/16.i2c_target_nack_acqfull_addr.4018454141 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 16.i2c_target_nack_acqfull_addr.4018454141 -covoverwrite' seed=73848323751444946609193666907347226796125381555188380361239414741823069142653 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73848323751444946609193666907347226796125381555188380361239414741823069142653 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/16.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_txstretch 46430446468057645294293545749321560444391891525883856689395587961432331971135 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/16.i2c_target_nack_txstretch/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4289915455 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/16.i2c_target_nack_txstretch.4289915455 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 16.i2c_target_nack_txstretch.4289915455 -covoverwrite' seed=46430446468057645294293545749321560444391891525883856689395587961432331971135 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46430446468057645294293545749321560444391891525883856689395587961432331971135 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/16.i2c_target_nack_txstretch/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_txstretch_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_errors 85392115477441747003880510830952927476248039713396324794877460034605293782678 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/16.i2c_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=314590870 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/16.i2c_tl_errors.314590870 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 16.i2c_tl_errors.314590870 -covoverwrite' seed=85392115477441747003880510830952927476248039713396324794877460034605293782678 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85392115477441747003880510830952927476248039713396324794877460034605293782678 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/16.i2c_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_intg_err 317641589943918923479215639808197380509533019649544227143591695471413638280 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/16.i2c_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1703752840 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/16.i2c_tl_intg_err.1703752840 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 16.i2c_tl_intg_err.1703752840 -covoverwrite' seed=317641589943918923479215639808197380509533019649544227143591695471413638280 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=317641589943918923479215639808197380509533019649544227143591695471413638280 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/16.i2c_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 75669660560324634607632230855775430148819151728833785200400436558539567604507 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/17.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3570869019 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/17.i2c_host_override.3570869019 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 17.i2c_host_override.3570869019 -covoverwrite' seed=75669660560324634607632230855775430148819151728833785200400436558539567604507 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75669660560324634607632230855775430148819151728833785200400436558539567604507 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/17.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_reset_fmt 8663113358569450526489439905828626764842592361215009015020101963595375012461 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/17.i2c_host_fifo_reset_fmt/latest run_opts='+test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1787390573 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/17.i2c_host_fifo_reset_fmt.1787390573 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 17.i2c_host_fifo_reset_fmt.1787390573 -covoverwrite' seed=8663113358569450526489439905828626764842592361215009015020101963595375012461 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8663113358569450526489439905828626764842592361215009015020101963595375012461 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/17.i2c_host_fifo_reset_fmt/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_reset_fmt_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 95946508063964581259239313244549642818764969704831391454924808195481370844852 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/17.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=467623604 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/17.i2c_host_error_intr.467623604 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 17.i2c_host_error_intr.467623604 -covoverwrite' seed=95946508063964581259239313244549642818764969704831391454924808195481370844852 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95946508063964581259239313244549642818764969704831391454924808195481370844852 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/17.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all 29474208042065985453622471169993654140917109378872975581757896312157362145205 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/17.i2c_host_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2923644853 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/17.i2c_host_stress_all.2923644853 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 17.i2c_host_stress_all.2923644853 -covoverwrite' seed=29474208042065985453622471169993654140917109378872975581757896312157362145205 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29474208042065985453622471169993654140917109378872975581757896312157362145205 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/17.i2c_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 67145402877907467161318392948545287051340690600373058175529543200538369401179 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/17.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2454921563 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/17.i2c_target_fifo_reset_tx.2454921563 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 17.i2c_target_fifo_reset_tx.2454921563 -covoverwrite' seed=67145402877907467161318392948545287051340690600373058175529543200538369401179 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67145402877907467161318392948545287051340690600373058175529543200538369401179 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/17.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all 17450078828804487704083473150322924633988580920408801525038833958394721082418 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/17.i2c_target_stress_all/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3133545522 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/17.i2c_target_stress_all.3133545522 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 17.i2c_target_stress_all.3133545522 -covoverwrite' seed=17450078828804487704083473150322924633988580920408801525038833958394721082418 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17450078828804487704083473150322924633988580920408801525038833958394721082418 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/17.i2c_target_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 111439727418834970630517824440698359494956948407479839895559384356425745346173 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/17.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1399631485 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/17.i2c_target_hrst.1399631485 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 17.i2c_target_hrst.1399631485 -covoverwrite' seed=111439727418834970630517824440698359494956948407479839895559384356425745346173 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111439727418834970630517824440698359494956948407479839895559384356425745346173 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/17.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 64423311987845616238699413342193532865122069635336435489643457065029116599132 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/17.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1854643036 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/17.i2c_host_mode_toggle.1854643036 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 17.i2c_host_mode_toggle.1854643036 -covoverwrite' seed=64423311987845616238699413342193532865122069635336435489643457065029116599132 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64423311987845616238699413342193532865122069635336435489643457065029116599132 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/17.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 33325265360443754241066635431375896505532199055691576842269284380365045082291 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/17.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3320817843 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/17.i2c_host_may_nack.3320817843 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 17.i2c_host_may_nack.3320817843 -covoverwrite' seed=33325265360443754241066635431375896505532199055691576842269284380365045082291 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33325265360443754241066635431375896505532199055691576842269284380365045082291 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/17.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 32617986460874801821743451994058843010712835289319105964303217203817231971309 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/17.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1691644909 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/17.i2c_target_nack_acqfull.1691644909 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 17.i2c_target_nack_acqfull.1691644909 -covoverwrite' seed=32617986460874801821743451994058843010712835289319105964303217203817231971309 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32617986460874801821743451994058843010712835289319105964303217203817231971309 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/17.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 60715428703513288020329704649200037678604296769625802717199720023018047206892 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/17.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1806366188 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/17.i2c_target_nack_acqfull_addr.1806366188 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 17.i2c_target_nack_acqfull_addr.1806366188 -covoverwrite' seed=60715428703513288020329704649200037678604296769625802717199720023018047206892 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60715428703513288020329704649200037678604296769625802717199720023018047206892 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/17.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_txstretch 8432280379810844660950625060835126631324713268808917109467699849911221237329 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/17.i2c_target_nack_txstretch/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1694119505 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/17.i2c_target_nack_txstretch.1694119505 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 17.i2c_target_nack_txstretch.1694119505 -covoverwrite' seed=8432280379810844660950625060835126631324713268808917109467699849911221237329 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8432280379810844660950625060835126631324713268808917109467699849911221237329 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/17.i2c_target_nack_txstretch/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_txstretch_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_errors 85350147661243563841628280200376313250525897937004902712185307110383171403165 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/17.i2c_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2047344029 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/17.i2c_tl_errors.2047344029 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 17.i2c_tl_errors.2047344029 -covoverwrite' seed=85350147661243563841628280200376313250525897937004902712185307110383171403165 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85350147661243563841628280200376313250525897937004902712185307110383171403165 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/17.i2c_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_intg_err 96932610473129422425020427144772461407404274630834338979116832538401178654796 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/17.i2c_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3914340428 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/17.i2c_tl_intg_err.3914340428 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 17.i2c_tl_intg_err.3914340428 -covoverwrite' seed=96932610473129422425020427144772461407404274630834338979116832538401178654796 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96932610473129422425020427144772461407404274630834338979116832538401178654796 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/17.i2c_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 86531785992793284176006144763046621450575783792432324239120466671289605946995 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/18.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1310064243 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/18.i2c_host_override.1310064243 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 18.i2c_host_override.1310064243 -covoverwrite' seed=86531785992793284176006144763046621450575783792432324239120466671289605946995 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86531785992793284176006144763046621450575783792432324239120466671289605946995 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/18.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_reset_fmt 58157926293833055924006168888887420183251605633551597596039854671419212151658 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/18.i2c_host_fifo_reset_fmt/latest run_opts='+test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2139994986 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/18.i2c_host_fifo_reset_fmt.2139994986 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 18.i2c_host_fifo_reset_fmt.2139994986 -covoverwrite' seed=58157926293833055924006168888887420183251605633551597596039854671419212151658 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58157926293833055924006168888887420183251605633551597596039854671419212151658 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/18.i2c_host_fifo_reset_fmt/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_reset_fmt_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 104987010991196216187356670011669241082987476527201968165107384748403433183702 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/18.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2390006230 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/18.i2c_host_error_intr.2390006230 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 18.i2c_host_error_intr.2390006230 -covoverwrite' seed=104987010991196216187356670011669241082987476527201968165107384748403433183702 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104987010991196216187356670011669241082987476527201968165107384748403433183702 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/18.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all 63211049027047984708902369584235782628144073033887168736149204357918277426592 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/18.i2c_host_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3744128416 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/18.i2c_host_stress_all.3744128416 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 18.i2c_host_stress_all.3744128416 -covoverwrite' seed=63211049027047984708902369584235782628144073033887168736149204357918277426592 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63211049027047984708902369584235782628144073033887168736149204357918277426592 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/18.i2c_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 62754280919867436758672294501848286718575346173910466673834797067765101626656 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/18.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1630799136 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/18.i2c_target_fifo_reset_tx.1630799136 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 18.i2c_target_fifo_reset_tx.1630799136 -covoverwrite' seed=62754280919867436758672294501848286718575346173910466673834797067765101626656 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62754280919867436758672294501848286718575346173910466673834797067765101626656 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/18.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all 11352255460861977276238515487968942756942457639895296830920950977947256607602 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/18.i2c_target_stress_all/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3918910322 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/18.i2c_target_stress_all.3918910322 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 18.i2c_target_stress_all.3918910322 -covoverwrite' seed=11352255460861977276238515487968942756942457639895296830920950977947256607602 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11352255460861977276238515487968942756942457639895296830920950977947256607602 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/18.i2c_target_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 83707381418299192835092238344962468574906812824324411412646367441144444621933 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/18.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4115928173 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/18.i2c_target_hrst.4115928173 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 18.i2c_target_hrst.4115928173 -covoverwrite' seed=83707381418299192835092238344962468574906812824324411412646367441144444621933 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83707381418299192835092238344962468574906812824324411412646367441144444621933 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/18.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 18776398195164593177538136555335056418792264726520709505942460699136387566907 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/18.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=894291259 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/18.i2c_host_mode_toggle.894291259 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 18.i2c_host_mode_toggle.894291259 -covoverwrite' seed=18776398195164593177538136555335056418792264726520709505942460699136387566907 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18776398195164593177538136555335056418792264726520709505942460699136387566907 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/18.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 85297210356916389431505295304881802532460857890283463014759824060749140858715 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/18.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1058936667 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/18.i2c_host_may_nack.1058936667 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 18.i2c_host_may_nack.1058936667 -covoverwrite' seed=85297210356916389431505295304881802532460857890283463014759824060749140858715 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85297210356916389431505295304881802532460857890283463014759824060749140858715 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/18.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 6457030534313087044973189094233301247133587721371510802925641714545597767386 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/18.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=757227226 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/18.i2c_target_nack_acqfull.757227226 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 18.i2c_target_nack_acqfull.757227226 -covoverwrite' seed=6457030534313087044973189094233301247133587721371510802925641714545597767386 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6457030534313087044973189094233301247133587721371510802925641714545597767386 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/18.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 56727604240723928587238218102157867655163350582783500848835125855137680537607 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/18.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2949068807 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/18.i2c_target_nack_acqfull_addr.2949068807 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 18.i2c_target_nack_acqfull_addr.2949068807 -covoverwrite' seed=56727604240723928587238218102157867655163350582783500848835125855137680537607 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56727604240723928587238218102157867655163350582783500848835125855137680537607 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/18.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_txstretch 82506629898233413419882207003395201017327836074690186579161222753679318538408 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/18.i2c_target_nack_txstretch/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=469063848 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/18.i2c_target_nack_txstretch.469063848 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 18.i2c_target_nack_txstretch.469063848 -covoverwrite' seed=82506629898233413419882207003395201017327836074690186579161222753679318538408 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82506629898233413419882207003395201017327836074690186579161222753679318538408 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/18.i2c_target_nack_txstretch/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_txstretch_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_errors 82602438526946528490691200630295161948491782200546357951006814572421528087305 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/18.i2c_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2059070217 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/18.i2c_tl_errors.2059070217 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 18.i2c_tl_errors.2059070217 -covoverwrite' seed=82602438526946528490691200630295161948491782200546357951006814572421528087305 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82602438526946528490691200630295161948491782200546357951006814572421528087305 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/18.i2c_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_intg_err 68200979422674516048514033864943857828781867255263298908923403429492667849861 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/18.i2c_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=426646661 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/18.i2c_tl_intg_err.426646661 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 18.i2c_tl_intg_err.426646661 -covoverwrite' seed=68200979422674516048514033864943857828781867255263298908923403429492667849861 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68200979422674516048514033864943857828781867255263298908923403429492667849861 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/18.i2c_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 95547141575563978776185208340622536162021487621998075761897281276278753310034 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/19.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=819574098 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/19.i2c_host_override.819574098 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 19.i2c_host_override.819574098 -covoverwrite' seed=95547141575563978776185208340622536162021487621998075761897281276278753310034 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95547141575563978776185208340622536162021487621998075761897281276278753310034 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/19.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_reset_fmt 54461238122983381818875113763195018421091352237350276968619819919971937868070 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/19.i2c_host_fifo_reset_fmt/latest run_opts='+test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1600575782 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/19.i2c_host_fifo_reset_fmt.1600575782 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 19.i2c_host_fifo_reset_fmt.1600575782 -covoverwrite' seed=54461238122983381818875113763195018421091352237350276968619819919971937868070 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54461238122983381818875113763195018421091352237350276968619819919971937868070 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/19.i2c_host_fifo_reset_fmt/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_reset_fmt_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 60333938632217024017741910799675286830153395519355980619442046515169418045616 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/19.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4049365168 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/19.i2c_host_error_intr.4049365168 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 19.i2c_host_error_intr.4049365168 -covoverwrite' seed=60333938632217024017741910799675286830153395519355980619442046515169418045616 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60333938632217024017741910799675286830153395519355980619442046515169418045616 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/19.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all 70666349950991966852384071190290599285631437145672279865906263613027420701540 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/19.i2c_host_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=857441124 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/19.i2c_host_stress_all.857441124 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 19.i2c_host_stress_all.857441124 -covoverwrite' seed=70666349950991966852384071190290599285631437145672279865906263613027420701540 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70666349950991966852384071190290599285631437145672279865906263613027420701540 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/19.i2c_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 107154703336554537402245719478855316199339980300656972368687557495002254371997 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/19.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1019833501 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/19.i2c_target_fifo_reset_tx.1019833501 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 19.i2c_target_fifo_reset_tx.1019833501 -covoverwrite' seed=107154703336554537402245719478855316199339980300656972368687557495002254371997 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107154703336554537402245719478855316199339980300656972368687557495002254371997 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/19.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all 98025880255050540984873097165138203231733076198967181964174067853510836012020 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/19.i2c_target_stress_all/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1604109300 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/19.i2c_target_stress_all.1604109300 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 19.i2c_target_stress_all.1604109300 -covoverwrite' seed=98025880255050540984873097165138203231733076198967181964174067853510836012020 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98025880255050540984873097165138203231733076198967181964174067853510836012020 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/19.i2c_target_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 41427838098912316855306675990217580882214847853965111696159370848802605281915 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/19.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=969323131 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/19.i2c_target_hrst.969323131 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 19.i2c_target_hrst.969323131 -covoverwrite' seed=41427838098912316855306675990217580882214847853965111696159370848802605281915 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41427838098912316855306675990217580882214847853965111696159370848802605281915 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/19.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 38945580207608158737191720495706252691768846862207904008392106478221883845979 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/19.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3587419483 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/19.i2c_host_mode_toggle.3587419483 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 19.i2c_host_mode_toggle.3587419483 -covoverwrite' seed=38945580207608158737191720495706252691768846862207904008392106478221883845979 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38945580207608158737191720495706252691768846862207904008392106478221883845979 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/19.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 69241172085193772628930831537754203560237553832722244489640217740729793191989 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/19.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3256164405 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/19.i2c_host_may_nack.3256164405 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 19.i2c_host_may_nack.3256164405 -covoverwrite' seed=69241172085193772628930831537754203560237553832722244489640217740729793191989 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69241172085193772628930831537754203560237553832722244489640217740729793191989 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/19.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 66664668178874168714208683288278944089549347995823994365538619316654448813138 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/19.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=875537490 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/19.i2c_target_nack_acqfull.875537490 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 19.i2c_target_nack_acqfull.875537490 -covoverwrite' seed=66664668178874168714208683288278944089549347995823994365538619316654448813138 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66664668178874168714208683288278944089549347995823994365538619316654448813138 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/19.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 92728377982845983033951370520025859082904679908225557471803965820052728150776 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/19.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1675328248 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/19.i2c_target_nack_acqfull_addr.1675328248 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 19.i2c_target_nack_acqfull_addr.1675328248 -covoverwrite' seed=92728377982845983033951370520025859082904679908225557471803965820052728150776 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92728377982845983033951370520025859082904679908225557471803965820052728150776 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/19.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_txstretch 71839794141417215925846630013079750505187868564048357470018709931517480174278 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/19.i2c_target_nack_txstretch/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2919924422 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/19.i2c_target_nack_txstretch.2919924422 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 19.i2c_target_nack_txstretch.2919924422 -covoverwrite' seed=71839794141417215925846630013079750505187868564048357470018709931517480174278 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71839794141417215925846630013079750505187868564048357470018709931517480174278 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/19.i2c_target_nack_txstretch/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_txstretch_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_errors 69199407946776892725016146180805958432559992081405879540317260010818965053498 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/19.i2c_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1300209722 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/19.i2c_tl_errors.1300209722 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 19.i2c_tl_errors.1300209722 -covoverwrite' seed=69199407946776892725016146180805958432559992081405879540317260010818965053498 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69199407946776892725016146180805958432559992081405879540317260010818965053498 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/19.i2c_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_intg_err 20619963264555916283391559367798502304066080357884435513810341328236891111437 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/19.i2c_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3418128397 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/19.i2c_tl_intg_err.3418128397 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 19.i2c_tl_intg_err.3418128397 -covoverwrite' seed=20619963264555916283391559367798502304066080357884435513810341328236891111437 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20619963264555916283391559367798502304066080357884435513810341328236891111437 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/19.i2c_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 89601051468325884332123575314058873812730294074683729712204423260981706200273 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/20.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1334940881 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/20.i2c_host_override.1334940881 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 20.i2c_host_override.1334940881 -covoverwrite' seed=89601051468325884332123575314058873812730294074683729712204423260981706200273 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89601051468325884332123575314058873812730294074683729712204423260981706200273 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/20.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_reset_fmt 57047985482333278684011802810321579814546831726604394479017780719695966663592 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/20.i2c_host_fifo_reset_fmt/latest run_opts='+test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2822927272 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/20.i2c_host_fifo_reset_fmt.2822927272 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 20.i2c_host_fifo_reset_fmt.2822927272 -covoverwrite' seed=57047985482333278684011802810321579814546831726604394479017780719695966663592 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57047985482333278684011802810321579814546831726604394479017780719695966663592 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/20.i2c_host_fifo_reset_fmt/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_reset_fmt_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 80172934522827909998452880697338926085858833644873458045728203600439633244710 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/20.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3237212710 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/20.i2c_host_error_intr.3237212710 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 20.i2c_host_error_intr.3237212710 -covoverwrite' seed=80172934522827909998452880697338926085858833644873458045728203600439633244710 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80172934522827909998452880697338926085858833644873458045728203600439633244710 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/20.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all 78465672657783215916587906477793228572928545227553867469468351719606358020758 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/20.i2c_host_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1584566934 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/20.i2c_host_stress_all.1584566934 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 20.i2c_host_stress_all.1584566934 -covoverwrite' seed=78465672657783215916587906477793228572928545227553867469468351719606358020758 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78465672657783215916587906477793228572928545227553867469468351719606358020758 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/20.i2c_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 55629096834662861342095298762920596555386528135130653626133670774051694924098 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/20.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3406254402 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/20.i2c_target_fifo_reset_tx.3406254402 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 20.i2c_target_fifo_reset_tx.3406254402 -covoverwrite' seed=55629096834662861342095298762920596555386528135130653626133670774051694924098 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55629096834662861342095298762920596555386528135130653626133670774051694924098 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/20.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all 107763094132794063681338445062556754524256087368103272313302549839018801601857 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/20.i2c_target_stress_all/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3102317889 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/20.i2c_target_stress_all.3102317889 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 20.i2c_target_stress_all.3102317889 -covoverwrite' seed=107763094132794063681338445062556754524256087368103272313302549839018801601857 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107763094132794063681338445062556754524256087368103272313302549839018801601857 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/20.i2c_target_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 2232164938088733021261556031160217380726150843248485593509812582475927089566 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/20.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3955978654 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/20.i2c_target_hrst.3955978654 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 20.i2c_target_hrst.3955978654 -covoverwrite' seed=2232164938088733021261556031160217380726150843248485593509812582475927089566 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2232164938088733021261556031160217380726150843248485593509812582475927089566 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/20.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 5403937469370596571794662070570123775374251024296048287740606033687984203797 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/20.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2292705301 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/20.i2c_host_mode_toggle.2292705301 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 20.i2c_host_mode_toggle.2292705301 -covoverwrite' seed=5403937469370596571794662070570123775374251024296048287740606033687984203797 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5403937469370596571794662070570123775374251024296048287740606033687984203797 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/20.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 26258936196546784657147205734527696153708351189684796138752990146108186764064 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/20.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=573907744 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/20.i2c_host_may_nack.573907744 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 20.i2c_host_may_nack.573907744 -covoverwrite' seed=26258936196546784657147205734527696153708351189684796138752990146108186764064 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26258936196546784657147205734527696153708351189684796138752990146108186764064 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/20.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 92371789017333123616901865114034334139326477038220360361868970256104241081794 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/20.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=153202114 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/20.i2c_target_nack_acqfull.153202114 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 20.i2c_target_nack_acqfull.153202114 -covoverwrite' seed=92371789017333123616901865114034334139326477038220360361868970256104241081794 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92371789017333123616901865114034334139326477038220360361868970256104241081794 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/20.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 63850807881691619654370862683042410418884388947563889693997797395481694504227 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/20.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3766158627 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/20.i2c_target_nack_acqfull_addr.3766158627 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 20.i2c_target_nack_acqfull_addr.3766158627 -covoverwrite' seed=63850807881691619654370862683042410418884388947563889693997797395481694504227 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63850807881691619654370862683042410418884388947563889693997797395481694504227 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/20.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_txstretch 80854568580087440253754391597092728543814700198593889774046113534993517708508 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/20.i2c_target_nack_txstretch/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3404399836 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/20.i2c_target_nack_txstretch.3404399836 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 20.i2c_target_nack_txstretch.3404399836 -covoverwrite' seed=80854568580087440253754391597092728543814700198593889774046113534993517708508 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80854568580087440253754391597092728543814700198593889774046113534993517708508 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/20.i2c_target_nack_txstretch/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_txstretch_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_errors 35107026362076435289276928618657341918101779386521559184631489549613293079433 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/20.i2c_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1639943049 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/20.i2c_tl_errors.1639943049 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 20.i2c_tl_errors.1639943049 -covoverwrite' seed=35107026362076435289276928618657341918101779386521559184631489549613293079433 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35107026362076435289276928618657341918101779386521559184631489549613293079433 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/20.i2c_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_intg_err 86048038953091027498931513016811714101708059123982405363030484802918113808104 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/20.i2c_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=668405480 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/20.i2c_tl_intg_err.668405480 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 20.i2c_tl_intg_err.668405480 -covoverwrite' seed=86048038953091027498931513016811714101708059123982405363030484802918113808104 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86048038953091027498931513016811714101708059123982405363030484802918113808104 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/20.i2c_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 6798181342298542776621444287798980087483611104577096547333337330295070552211 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/21.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1855746195 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/21.i2c_host_override.1855746195 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 21.i2c_host_override.1855746195 -covoverwrite' seed=6798181342298542776621444287798980087483611104577096547333337330295070552211 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6798181342298542776621444287798980087483611104577096547333337330295070552211 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/21.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_reset_fmt 32979118375812432359823164152469254388113420960937105319879151011531695840943 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/21.i2c_host_fifo_reset_fmt/latest run_opts='+test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2054413999 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/21.i2c_host_fifo_reset_fmt.2054413999 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 21.i2c_host_fifo_reset_fmt.2054413999 -covoverwrite' seed=32979118375812432359823164152469254388113420960937105319879151011531695840943 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32979118375812432359823164152469254388113420960937105319879151011531695840943 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/21.i2c_host_fifo_reset_fmt/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_reset_fmt_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 64716529114919673159809219636086366195295693533368508691059018175014111148580 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/21.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4123916836 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/21.i2c_host_error_intr.4123916836 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 21.i2c_host_error_intr.4123916836 -covoverwrite' seed=64716529114919673159809219636086366195295693533368508691059018175014111148580 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64716529114919673159809219636086366195295693533368508691059018175014111148580 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/21.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all 95221266812589661296736438356323594520292954395422704768322809439013371735852 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/21.i2c_host_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3609554732 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/21.i2c_host_stress_all.3609554732 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 21.i2c_host_stress_all.3609554732 -covoverwrite' seed=95221266812589661296736438356323594520292954395422704768322809439013371735852 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95221266812589661296736438356323594520292954395422704768322809439013371735852 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/21.i2c_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 26252507672372339128613767411565416149162815381671857419021082288358962433457 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/21.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=19860913 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/21.i2c_target_fifo_reset_tx.19860913 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 21.i2c_target_fifo_reset_tx.19860913 -covoverwrite' seed=26252507672372339128613767411565416149162815381671857419021082288358962433457 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26252507672372339128613767411565416149162815381671857419021082288358962433457 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/21.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all 80255816741583569919585688592394304493310771624115133339509754177421868032880 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/21.i2c_target_stress_all/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=214197104 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/21.i2c_target_stress_all.214197104 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 21.i2c_target_stress_all.214197104 -covoverwrite' seed=80255816741583569919585688592394304493310771624115133339509754177421868032880 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80255816741583569919585688592394304493310771624115133339509754177421868032880 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/21.i2c_target_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 57449589530869870327275287494183287640399502470260296236633171407626276080285 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/21.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1572768413 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/21.i2c_target_hrst.1572768413 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 21.i2c_target_hrst.1572768413 -covoverwrite' seed=57449589530869870327275287494183287640399502470260296236633171407626276080285 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57449589530869870327275287494183287640399502470260296236633171407626276080285 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/21.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 2424005721169475902121321981338971377251267542595259854407107772302068208659 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/21.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3659715603 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/21.i2c_host_mode_toggle.3659715603 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 21.i2c_host_mode_toggle.3659715603 -covoverwrite' seed=2424005721169475902121321981338971377251267542595259854407107772302068208659 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2424005721169475902121321981338971377251267542595259854407107772302068208659 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/21.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 36395880654752455562864402653649257472772680425193317341669588768769469628903 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/21.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=260620775 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/21.i2c_host_may_nack.260620775 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 21.i2c_host_may_nack.260620775 -covoverwrite' seed=36395880654752455562864402653649257472772680425193317341669588768769469628903 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36395880654752455562864402653649257472772680425193317341669588768769469628903 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/21.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 63968103321564930324561655599816601029303410966886842862779838026024001642129 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/21.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2268241553 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/21.i2c_target_nack_acqfull.2268241553 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 21.i2c_target_nack_acqfull.2268241553 -covoverwrite' seed=63968103321564930324561655599816601029303410966886842862779838026024001642129 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63968103321564930324561655599816601029303410966886842862779838026024001642129 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/21.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 53231296127529864784308855315337893349720707876518739189094778315212157457644 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/21.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3586495724 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/21.i2c_target_nack_acqfull_addr.3586495724 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 21.i2c_target_nack_acqfull_addr.3586495724 -covoverwrite' seed=53231296127529864784308855315337893349720707876518739189094778315212157457644 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53231296127529864784308855315337893349720707876518739189094778315212157457644 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/21.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_txstretch 46577905884791525372732856457420695496765027818970926849166527355524711119905 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/21.i2c_target_nack_txstretch/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=171375649 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/21.i2c_target_nack_txstretch.171375649 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 21.i2c_target_nack_txstretch.171375649 -covoverwrite' seed=46577905884791525372732856457420695496765027818970926849166527355524711119905 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46577905884791525372732856457420695496765027818970926849166527355524711119905 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/21.i2c_target_nack_txstretch/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_txstretch_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_errors 43036966022012026944721427782886803248453218024958159642091554168670063488769 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/21.i2c_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=563408641 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/21.i2c_tl_errors.563408641 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 21.i2c_tl_errors.563408641 -covoverwrite' seed=43036966022012026944721427782886803248453218024958159642091554168670063488769 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43036966022012026944721427782886803248453218024958159642091554168670063488769 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/21.i2c_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_intg_err 97995841518805556468785248361654608700765241221974442153880974452162835818252 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/21.i2c_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2815469324 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/21.i2c_tl_intg_err.2815469324 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 21.i2c_tl_intg_err.2815469324 -covoverwrite' seed=97995841518805556468785248361654608700765241221974442153880974452162835818252 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97995841518805556468785248361654608700765241221974442153880974452162835818252 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/21.i2c_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 83826032342691080823510564199846525444566762761461309059678336025026732298773 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/22.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1086132757 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/22.i2c_host_override.1086132757 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 22.i2c_host_override.1086132757 -covoverwrite' seed=83826032342691080823510564199846525444566762761461309059678336025026732298773 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83826032342691080823510564199846525444566762761461309059678336025026732298773 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/22.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_reset_fmt 110529519036492925358237098398900812834801943092344578891245655915933977428141 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/22.i2c_host_fifo_reset_fmt/latest run_opts='+test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1657946285 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/22.i2c_host_fifo_reset_fmt.1657946285 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 22.i2c_host_fifo_reset_fmt.1657946285 -covoverwrite' seed=110529519036492925358237098398900812834801943092344578891245655915933977428141 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110529519036492925358237098398900812834801943092344578891245655915933977428141 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/22.i2c_host_fifo_reset_fmt/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_reset_fmt_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 31348868927237704372280843535439463266612799556885520241933299621743875964418 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/22.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=784973314 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/22.i2c_host_error_intr.784973314 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 22.i2c_host_error_intr.784973314 -covoverwrite' seed=31348868927237704372280843535439463266612799556885520241933299621743875964418 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31348868927237704372280843535439463266612799556885520241933299621743875964418 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/22.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all 48763674100189056531863928587219685584466494417040394808879053975285942772799 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/22.i2c_host_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1151394879 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/22.i2c_host_stress_all.1151394879 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 22.i2c_host_stress_all.1151394879 -covoverwrite' seed=48763674100189056531863928587219685584466494417040394808879053975285942772799 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48763674100189056531863928587219685584466494417040394808879053975285942772799 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/22.i2c_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 11891509920477698984829459760539616207642236842879047983887306563272675213676 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/22.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2480456044 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/22.i2c_target_fifo_reset_tx.2480456044 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 22.i2c_target_fifo_reset_tx.2480456044 -covoverwrite' seed=11891509920477698984829459760539616207642236842879047983887306563272675213676 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11891509920477698984829459760539616207642236842879047983887306563272675213676 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/22.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all 81136116589112469621337461537679549906166379245883119739629750301525040926645 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/22.i2c_target_stress_all/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1108578229 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/22.i2c_target_stress_all.1108578229 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 22.i2c_target_stress_all.1108578229 -covoverwrite' seed=81136116589112469621337461537679549906166379245883119739629750301525040926645 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81136116589112469621337461537679549906166379245883119739629750301525040926645 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/22.i2c_target_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 70838762351405036446332144912966605670835866638865672979835603574069314541462 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/22.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1848465302 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/22.i2c_target_hrst.1848465302 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 22.i2c_target_hrst.1848465302 -covoverwrite' seed=70838762351405036446332144912966605670835866638865672979835603574069314541462 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70838762351405036446332144912966605670835866638865672979835603574069314541462 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/22.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 87461175704669822896233430140832533946278733417440070877727453651552622151232 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/22.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=183830080 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/22.i2c_host_mode_toggle.183830080 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 22.i2c_host_mode_toggle.183830080 -covoverwrite' seed=87461175704669822896233430140832533946278733417440070877727453651552622151232 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87461175704669822896233430140832533946278733417440070877727453651552622151232 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/22.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 110401772996905350118895282837985016044865687630630185174040846768394583025521 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/22.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2542151537 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/22.i2c_host_may_nack.2542151537 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 22.i2c_host_may_nack.2542151537 -covoverwrite' seed=110401772996905350118895282837985016044865687630630185174040846768394583025521 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110401772996905350118895282837985016044865687630630185174040846768394583025521 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/22.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 44949159146296240079097395735314126623528501445595324141913691575451765025926 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/22.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1738124422 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/22.i2c_target_nack_acqfull.1738124422 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 22.i2c_target_nack_acqfull.1738124422 -covoverwrite' seed=44949159146296240079097395735314126623528501445595324141913691575451765025926 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44949159146296240079097395735314126623528501445595324141913691575451765025926 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/22.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 104411306379481977428789742681557777641355560224552980598291339948163281604150 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/22.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2396933686 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/22.i2c_target_nack_acqfull_addr.2396933686 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 22.i2c_target_nack_acqfull_addr.2396933686 -covoverwrite' seed=104411306379481977428789742681557777641355560224552980598291339948163281604150 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104411306379481977428789742681557777641355560224552980598291339948163281604150 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/22.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_txstretch 58267147606594322946193471066641886555674006541137009595392459613112062586877 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/22.i2c_target_nack_txstretch/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2258251773 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/22.i2c_target_nack_txstretch.2258251773 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 22.i2c_target_nack_txstretch.2258251773 -covoverwrite' seed=58267147606594322946193471066641886555674006541137009595392459613112062586877 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58267147606594322946193471066641886555674006541137009595392459613112062586877 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/22.i2c_target_nack_txstretch/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_txstretch_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_errors 61940794617265897610511716823759018034073516200197633634709165279513766320258 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/22.i2c_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=602200194 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/22.i2c_tl_errors.602200194 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 22.i2c_tl_errors.602200194 -covoverwrite' seed=61940794617265897610511716823759018034073516200197633634709165279513766320258 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61940794617265897610511716823759018034073516200197633634709165279513766320258 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/22.i2c_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_intg_err 33168170847546696413779898071505089431325776117006684387933353547900101583576 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/22.i2c_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2616713944 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/22.i2c_tl_intg_err.2616713944 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 22.i2c_tl_intg_err.2616713944 -covoverwrite' seed=33168170847546696413779898071505089431325776117006684387933353547900101583576 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33168170847546696413779898071505089431325776117006684387933353547900101583576 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/22.i2c_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 93031665522827414790580574760163226651396513857519618173950547971998138729729 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/23.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3911419137 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/23.i2c_host_override.3911419137 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 23.i2c_host_override.3911419137 -covoverwrite' seed=93031665522827414790580574760163226651396513857519618173950547971998138729729 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93031665522827414790580574760163226651396513857519618173950547971998138729729 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/23.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_reset_fmt 36132729746135182982788175998322340777738897815817665169148068924159844839943 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/23.i2c_host_fifo_reset_fmt/latest run_opts='+test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2658038279 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/23.i2c_host_fifo_reset_fmt.2658038279 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 23.i2c_host_fifo_reset_fmt.2658038279 -covoverwrite' seed=36132729746135182982788175998322340777738897815817665169148068924159844839943 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36132729746135182982788175998322340777738897815817665169148068924159844839943 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/23.i2c_host_fifo_reset_fmt/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_reset_fmt_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 113978471406521889060836153017047244332359496522755043462995060401863513633282 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/23.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3823923714 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/23.i2c_host_error_intr.3823923714 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 23.i2c_host_error_intr.3823923714 -covoverwrite' seed=113978471406521889060836153017047244332359496522755043462995060401863513633282 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113978471406521889060836153017047244332359496522755043462995060401863513633282 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/23.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all 79243616505375230206001889059310259669870172438307309274073235722775557354081 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/23.i2c_host_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2656350817 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/23.i2c_host_stress_all.2656350817 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 23.i2c_host_stress_all.2656350817 -covoverwrite' seed=79243616505375230206001889059310259669870172438307309274073235722775557354081 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79243616505375230206001889059310259669870172438307309274073235722775557354081 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/23.i2c_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 6517146158792834545309921878838871476316373977488980615300691232591980735923 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/23.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=499068339 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/23.i2c_target_fifo_reset_tx.499068339 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 23.i2c_target_fifo_reset_tx.499068339 -covoverwrite' seed=6517146158792834545309921878838871476316373977488980615300691232591980735923 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6517146158792834545309921878838871476316373977488980615300691232591980735923 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/23.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all 85550388400477373905471250214742445180570300672270249155516160526677852172802 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/23.i2c_target_stress_all/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=868889090 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/23.i2c_target_stress_all.868889090 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 23.i2c_target_stress_all.868889090 -covoverwrite' seed=85550388400477373905471250214742445180570300672270249155516160526677852172802 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85550388400477373905471250214742445180570300672270249155516160526677852172802 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/23.i2c_target_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 85245873242759839113930930578153605168809245090926058551137476609174140645944 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/23.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2990305848 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/23.i2c_target_hrst.2990305848 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 23.i2c_target_hrst.2990305848 -covoverwrite' seed=85245873242759839113930930578153605168809245090926058551137476609174140645944 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85245873242759839113930930578153605168809245090926058551137476609174140645944 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/23.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 61882691393150030143102809895949974674677694919220030219849904943858563889028 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/23.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2732799876 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/23.i2c_host_mode_toggle.2732799876 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 23.i2c_host_mode_toggle.2732799876 -covoverwrite' seed=61882691393150030143102809895949974674677694919220030219849904943858563889028 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61882691393150030143102809895949974674677694919220030219849904943858563889028 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/23.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 20148224956452579827257037692110655004794144035901816219419920772682996168185 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/23.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1416279545 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/23.i2c_host_may_nack.1416279545 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 23.i2c_host_may_nack.1416279545 -covoverwrite' seed=20148224956452579827257037692110655004794144035901816219419920772682996168185 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20148224956452579827257037692110655004794144035901816219419920772682996168185 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/23.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 54972640743197921330227173842796602523034958179520910681400540869563479675575 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/23.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2867253943 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/23.i2c_target_nack_acqfull.2867253943 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 23.i2c_target_nack_acqfull.2867253943 -covoverwrite' seed=54972640743197921330227173842796602523034958179520910681400540869563479675575 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54972640743197921330227173842796602523034958179520910681400540869563479675575 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/23.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 41893447644542300704504335937581211684022182901998157642560988408131435387920 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/23.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1414552592 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/23.i2c_target_nack_acqfull_addr.1414552592 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 23.i2c_target_nack_acqfull_addr.1414552592 -covoverwrite' seed=41893447644542300704504335937581211684022182901998157642560988408131435387920 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41893447644542300704504335937581211684022182901998157642560988408131435387920 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/23.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_txstretch 43503850148874436167557470930356666449098866987704005421018811694438376108401 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/23.i2c_target_nack_txstretch/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1354330481 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/23.i2c_target_nack_txstretch.1354330481 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 23.i2c_target_nack_txstretch.1354330481 -covoverwrite' seed=43503850148874436167557470930356666449098866987704005421018811694438376108401 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43503850148874436167557470930356666449098866987704005421018811694438376108401 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/23.i2c_target_nack_txstretch/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_txstretch_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_errors 16323395317440051316778786914488188271101731282820221194198600518939679153903 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/23.i2c_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=168845039 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/23.i2c_tl_errors.168845039 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 23.i2c_tl_errors.168845039 -covoverwrite' seed=16323395317440051316778786914488188271101731282820221194198600518939679153903 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16323395317440051316778786914488188271101731282820221194198600518939679153903 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/23.i2c_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_intg_err 653010691329918055581022374579914140557744298376789782341144453663225730405 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/23.i2c_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3708212581 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/23.i2c_tl_intg_err.3708212581 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 23.i2c_tl_intg_err.3708212581 -covoverwrite' seed=653010691329918055581022374579914140557744298376789782341144453663225730405 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=653010691329918055581022374579914140557744298376789782341144453663225730405 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/23.i2c_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 25570520695059732718296512971958018572165247846330774009847724638098442808422 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/24.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3722570854 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/24.i2c_host_override.3722570854 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 24.i2c_host_override.3722570854 -covoverwrite' seed=25570520695059732718296512971958018572165247846330774009847724638098442808422 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25570520695059732718296512971958018572165247846330774009847724638098442808422 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/24.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_fifo_reset_fmt 64301625895001851318563703085219376225723914225083828521055760446022250680766 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/24.i2c_host_fifo_reset_fmt/latest run_opts='+test_timeout_ns=10_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=288903614 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_fifo_reset_fmt_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/24.i2c_host_fifo_reset_fmt.288903614 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 24.i2c_host_fifo_reset_fmt.288903614 -covoverwrite' seed=64301625895001851318563703085219376225723914225083828521055760446022250680766 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64301625895001851318563703085219376225723914225083828521055760446022250680766 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/24.i2c_host_fifo_reset_fmt/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_fifo_reset_fmt_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 46110705027228100636923921260732783064302879984959397921130966136871944697252 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/24.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1947448740 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/24.i2c_host_error_intr.1947448740 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 24.i2c_host_error_intr.1947448740 -covoverwrite' seed=46110705027228100636923921260732783064302879984959397921130966136871944697252 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46110705027228100636923921260732783064302879984959397921130966136871944697252 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/24.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all 96459095127462496089404421422593251601374216531104428887398613258817847334441 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/24.i2c_host_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=251827753 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/24.i2c_host_stress_all.251827753 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 24.i2c_host_stress_all.251827753 -covoverwrite' seed=96459095127462496089404421422593251601374216531104428887398613258817847334441 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96459095127462496089404421422593251601374216531104428887398613258817847334441 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/24.i2c_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 77358492866639556834158179152613377104846884208995952582841305189050599129087 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/24.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2375073791 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/24.i2c_target_fifo_reset_tx.2375073791 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 24.i2c_target_fifo_reset_tx.2375073791 -covoverwrite' seed=77358492866639556834158179152613377104846884208995952582841305189050599129087 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77358492866639556834158179152613377104846884208995952582841305189050599129087 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/24.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all 100571271342767049600352190800636631897177390330667936601635981405433966335481 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/24.i2c_target_stress_all/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1524602361 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/24.i2c_target_stress_all.1524602361 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 24.i2c_target_stress_all.1524602361 -covoverwrite' seed=100571271342767049600352190800636631897177390330667936601635981405433966335481 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100571271342767049600352190800636631897177390330667936601635981405433966335481 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/24.i2c_target_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 99513300802062153041037003216304916443625879779397390056481686068026388126039 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/24.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=813832535 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/24.i2c_target_hrst.813832535 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 24.i2c_target_hrst.813832535 -covoverwrite' seed=99513300802062153041037003216304916443625879779397390056481686068026388126039 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99513300802062153041037003216304916443625879779397390056481686068026388126039 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/24.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 53012945092839319566083809666781323335431672123241630568792855784984311344929 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/24.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3898453793 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/24.i2c_host_mode_toggle.3898453793 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 24.i2c_host_mode_toggle.3898453793 -covoverwrite' seed=53012945092839319566083809666781323335431672123241630568792855784984311344929 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53012945092839319566083809666781323335431672123241630568792855784984311344929 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/24.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 48639583156552702632184881947678386570213074524646300120462305034753584589828 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/24.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2433149956 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/24.i2c_host_may_nack.2433149956 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 24.i2c_host_may_nack.2433149956 -covoverwrite' seed=48639583156552702632184881947678386570213074524646300120462305034753584589828 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48639583156552702632184881947678386570213074524646300120462305034753584589828 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/24.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 105070259457385725971597345098562852843687024504103062322132935716626079654852 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/24.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4273447876 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/24.i2c_target_nack_acqfull.4273447876 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 24.i2c_target_nack_acqfull.4273447876 -covoverwrite' seed=105070259457385725971597345098562852843687024504103062322132935716626079654852 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105070259457385725971597345098562852843687024504103062322132935716626079654852 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/24.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 35359087623763971010593450970742415109322789357995755765187289978049775292427 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/24.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1320177675 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/24.i2c_target_nack_acqfull_addr.1320177675 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 24.i2c_target_nack_acqfull_addr.1320177675 -covoverwrite' seed=35359087623763971010593450970742415109322789357995755765187289978049775292427 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35359087623763971010593450970742415109322789357995755765187289978049775292427 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/24.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_txstretch 82721745537732932715643945447576814275509913148324806031481422775177352987717 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/24.i2c_target_nack_txstretch/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2822652997 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/24.i2c_target_nack_txstretch.2822652997 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 24.i2c_target_nack_txstretch.2822652997 -covoverwrite' seed=82721745537732932715643945447576814275509913148324806031481422775177352987717 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82721745537732932715643945447576814275509913148324806031481422775177352987717 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/24.i2c_target_nack_txstretch/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_txstretch_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_errors 8317711660445778605137468208002579489857890950035965484923246515155573207157 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/24.i2c_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3770478709 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/24.i2c_tl_errors.3770478709 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 24.i2c_tl_errors.3770478709 -covoverwrite' seed=8317711660445778605137468208002579489857890950035965484923246515155573207157 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8317711660445778605137468208002579489857890950035965484923246515155573207157 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/24.i2c_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_tl_intg_err 60664706457459119428181744201857553204309395436705657469594307595482549079220 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/24.i2c_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2315406516 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/cover_reg_top/24.i2c_tl_intg_err.2315406516 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope cover_reg_top -covtest 24.i2c_tl_intg_err.2315406516 -covoverwrite' seed=60664706457459119428181744201857553204309395436705657469594307595482549079220 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60664706457459119428181744201857553204309395436705657469594307595482549079220 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/24.i2c_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 55802958281670179782684355881014991326360967148731047758037650130447466040007 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/25.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4044688071 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/25.i2c_host_override.4044688071 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 25.i2c_host_override.4044688071 -covoverwrite' seed=55802958281670179782684355881014991326360967148731047758037650130447466040007 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55802958281670179782684355881014991326360967148731047758037650130447466040007 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/25.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 97202279801715435051277742772565607848031616162517948166043623478261727991097 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/25.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2969933113 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/25.i2c_host_error_intr.2969933113 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 25.i2c_host_error_intr.2969933113 -covoverwrite' seed=97202279801715435051277742772565607848031616162517948166043623478261727991097 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97202279801715435051277742772565607848031616162517948166043623478261727991097 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/25.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all 74259213843301652806296680835850324625728827246219335112999142571083746949255 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/25.i2c_host_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1983297671 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/25.i2c_host_stress_all.1983297671 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 25.i2c_host_stress_all.1983297671 -covoverwrite' seed=74259213843301652806296680835850324625728827246219335112999142571083746949255 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74259213843301652806296680835850324625728827246219335112999142571083746949255 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/25.i2c_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 109509516356464546024839904075909586753327892732327909259366228987764911873728 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/25.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1129553600 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/25.i2c_target_fifo_reset_tx.1129553600 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 25.i2c_target_fifo_reset_tx.1129553600 -covoverwrite' seed=109509516356464546024839904075909586753327892732327909259366228987764911873728 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109509516356464546024839904075909586753327892732327909259366228987764911873728 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/25.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all 69480839664778984267008486201212746960460481389594168114544761695192221779067 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/25.i2c_target_stress_all/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4013982843 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/25.i2c_target_stress_all.4013982843 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 25.i2c_target_stress_all.4013982843 -covoverwrite' seed=69480839664778984267008486201212746960460481389594168114544761695192221779067 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69480839664778984267008486201212746960460481389594168114544761695192221779067 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/25.i2c_target_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 95644672040861219419357111251043302636572592441379582309561738388739594430795 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/25.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3371215179 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/25.i2c_target_hrst.3371215179 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 25.i2c_target_hrst.3371215179 -covoverwrite' seed=95644672040861219419357111251043302636572592441379582309561738388739594430795 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95644672040861219419357111251043302636572592441379582309561738388739594430795 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/25.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 113455147630865438603330272311270664343712298480350922150395474199150702653536 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/25.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1031303264 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/25.i2c_host_mode_toggle.1031303264 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 25.i2c_host_mode_toggle.1031303264 -covoverwrite' seed=113455147630865438603330272311270664343712298480350922150395474199150702653536 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113455147630865438603330272311270664343712298480350922150395474199150702653536 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/25.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 61475836312306801090127185675677341781456540991722139738041403552246915373093 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/25.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2029492261 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/25.i2c_host_may_nack.2029492261 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 25.i2c_host_may_nack.2029492261 -covoverwrite' seed=61475836312306801090127185675677341781456540991722139738041403552246915373093 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61475836312306801090127185675677341781456540991722139738041403552246915373093 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/25.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 4370224876222287013537494130527277382039855892520538463971706573382279847511 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/25.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2285198935 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/25.i2c_target_nack_acqfull.2285198935 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 25.i2c_target_nack_acqfull.2285198935 -covoverwrite' seed=4370224876222287013537494130527277382039855892520538463971706573382279847511 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4370224876222287013537494130527277382039855892520538463971706573382279847511 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/25.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 109349565661169984969563934503814164670124946389130563355499355381291778312746 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/25.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=185600554 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/25.i2c_target_nack_acqfull_addr.185600554 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 25.i2c_target_nack_acqfull_addr.185600554 -covoverwrite' seed=109349565661169984969563934503814164670124946389130563355499355381291778312746 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109349565661169984969563934503814164670124946389130563355499355381291778312746 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/25.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_txstretch 60303411136994742187390576180223624107396428138109479519739065379749765640273 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/25.i2c_target_nack_txstretch/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1263857745 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/25.i2c_target_nack_txstretch.1263857745 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 25.i2c_target_nack_txstretch.1263857745 -covoverwrite' seed=60303411136994742187390576180223624107396428138109479519739065379749765640273 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60303411136994742187390576180223624107396428138109479519739065379749765640273 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/25.i2c_target_nack_txstretch/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_txstretch_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 30630853426953798485625528756635906531968270555613720077664705569431351754834 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/26.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=295206994 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/26.i2c_host_override.295206994 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 26.i2c_host_override.295206994 -covoverwrite' seed=30630853426953798485625528756635906531968270555613720077664705569431351754834 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30630853426953798485625528756635906531968270555613720077664705569431351754834 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/26.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 87390446361497160049250479975931463583178149349993737233130493066673813999922 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/26.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1353470258 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/26.i2c_host_error_intr.1353470258 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 26.i2c_host_error_intr.1353470258 -covoverwrite' seed=87390446361497160049250479975931463583178149349993737233130493066673813999922 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87390446361497160049250479975931463583178149349993737233130493066673813999922 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/26.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all 220218752247921961686220087410441598858619809082493362418748328151446883620 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/26.i2c_host_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3874655524 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/26.i2c_host_stress_all.3874655524 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 26.i2c_host_stress_all.3874655524 -covoverwrite' seed=220218752247921961686220087410441598858619809082493362418748328151446883620 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=220218752247921961686220087410441598858619809082493362418748328151446883620 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/26.i2c_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 36786026382213650413976579749281830723146992327967451917127142311764308907034 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/26.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3887715354 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/26.i2c_target_fifo_reset_tx.3887715354 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 26.i2c_target_fifo_reset_tx.3887715354 -covoverwrite' seed=36786026382213650413976579749281830723146992327967451917127142311764308907034 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36786026382213650413976579749281830723146992327967451917127142311764308907034 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/26.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all 86746088482333639683503764027591123294463694302390895843357627431090513444927 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/26.i2c_target_stress_all/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4251648063 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/26.i2c_target_stress_all.4251648063 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 26.i2c_target_stress_all.4251648063 -covoverwrite' seed=86746088482333639683503764027591123294463694302390895843357627431090513444927 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86746088482333639683503764027591123294463694302390895843357627431090513444927 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/26.i2c_target_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 3658451819323655407892084571191734772016982505900444736569295642486996714153 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/26.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3208102569 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/26.i2c_target_hrst.3208102569 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 26.i2c_target_hrst.3208102569 -covoverwrite' seed=3658451819323655407892084571191734772016982505900444736569295642486996714153 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3658451819323655407892084571191734772016982505900444736569295642486996714153 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/26.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 9085818025245109088936782359700386386300859393701898686466577696264082932473 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/26.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2407777017 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/26.i2c_host_mode_toggle.2407777017 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 26.i2c_host_mode_toggle.2407777017 -covoverwrite' seed=9085818025245109088936782359700386386300859393701898686466577696264082932473 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9085818025245109088936782359700386386300859393701898686466577696264082932473 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/26.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 53305020642302267009036636678830267334523986879674108483665753773584691881326 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/26.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=994436462 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/26.i2c_host_may_nack.994436462 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 26.i2c_host_may_nack.994436462 -covoverwrite' seed=53305020642302267009036636678830267334523986879674108483665753773584691881326 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53305020642302267009036636678830267334523986879674108483665753773584691881326 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/26.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 102163314955685038374048357266315483111714817968480377503043486557314179548351 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/26.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1169573055 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/26.i2c_target_nack_acqfull.1169573055 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 26.i2c_target_nack_acqfull.1169573055 -covoverwrite' seed=102163314955685038374048357266315483111714817968480377503043486557314179548351 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102163314955685038374048357266315483111714817968480377503043486557314179548351 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/26.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 36046787833614724915828783134187082399284839178518937166644713293802656443680 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/26.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3693292832 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/26.i2c_target_nack_acqfull_addr.3693292832 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 26.i2c_target_nack_acqfull_addr.3693292832 -covoverwrite' seed=36046787833614724915828783134187082399284839178518937166644713293802656443680 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36046787833614724915828783134187082399284839178518937166644713293802656443680 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/26.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_txstretch 45209177411996207100469375517769433950708359374715139713096358782818363564307 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/26.i2c_target_nack_txstretch/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1009967379 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/26.i2c_target_nack_txstretch.1009967379 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 26.i2c_target_nack_txstretch.1009967379 -covoverwrite' seed=45209177411996207100469375517769433950708359374715139713096358782818363564307 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45209177411996207100469375517769433950708359374715139713096358782818363564307 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/26.i2c_target_nack_txstretch/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_txstretch_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 56793604887989525354803323587555735615545471797441208140312510450902714248849 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/27.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3035590289 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/27.i2c_host_override.3035590289 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 27.i2c_host_override.3035590289 -covoverwrite' seed=56793604887989525354803323587555735615545471797441208140312510450902714248849 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56793604887989525354803323587555735615545471797441208140312510450902714248849 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/27.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 17911223955205461420059622629059264753672661888314569912389611800233561253075 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/27.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=148858067 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/27.i2c_host_error_intr.148858067 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 27.i2c_host_error_intr.148858067 -covoverwrite' seed=17911223955205461420059622629059264753672661888314569912389611800233561253075 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17911223955205461420059622629059264753672661888314569912389611800233561253075 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/27.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all 70746731760353942832426708189690194680714009067397980541512732212541190712380 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/27.i2c_host_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1575103548 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/27.i2c_host_stress_all.1575103548 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 27.i2c_host_stress_all.1575103548 -covoverwrite' seed=70746731760353942832426708189690194680714009067397980541512732212541190712380 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70746731760353942832426708189690194680714009067397980541512732212541190712380 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/27.i2c_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 15254614090626034738101966967916617603318035341214265609118694963534521789896 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/27.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2864541128 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/27.i2c_target_fifo_reset_tx.2864541128 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 27.i2c_target_fifo_reset_tx.2864541128 -covoverwrite' seed=15254614090626034738101966967916617603318035341214265609118694963534521789896 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15254614090626034738101966967916617603318035341214265609118694963534521789896 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/27.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all 86592526296610175389818173767277471642679642681653893440107444692190567333909 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/27.i2c_target_stress_all/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=871628821 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/27.i2c_target_stress_all.871628821 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 27.i2c_target_stress_all.871628821 -covoverwrite' seed=86592526296610175389818173767277471642679642681653893440107444692190567333909 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86592526296610175389818173767277471642679642681653893440107444692190567333909 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/27.i2c_target_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 59684988204536411504543481033364411925718910610152148397136461914753479168399 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/27.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3705885071 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/27.i2c_target_hrst.3705885071 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 27.i2c_target_hrst.3705885071 -covoverwrite' seed=59684988204536411504543481033364411925718910610152148397136461914753479168399 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=59684988204536411504543481033364411925718910610152148397136461914753479168399 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/27.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 11737693840509329186465478146428029675657242621172708147766516367146012412392 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/27.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=249072104 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/27.i2c_host_mode_toggle.249072104 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 27.i2c_host_mode_toggle.249072104 -covoverwrite' seed=11737693840509329186465478146428029675657242621172708147766516367146012412392 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11737693840509329186465478146428029675657242621172708147766516367146012412392 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/27.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 2925437305802995462527790088745995713717332934587879179264238542907378483992 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/27.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=972800792 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/27.i2c_host_may_nack.972800792 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 27.i2c_host_may_nack.972800792 -covoverwrite' seed=2925437305802995462527790088745995713717332934587879179264238542907378483992 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2925437305802995462527790088745995713717332934587879179264238542907378483992 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/27.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 49201473710057144119980283275673780069309381152825623433731595832392874511014 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/27.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2300627622 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/27.i2c_target_nack_acqfull.2300627622 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 27.i2c_target_nack_acqfull.2300627622 -covoverwrite' seed=49201473710057144119980283275673780069309381152825623433731595832392874511014 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49201473710057144119980283275673780069309381152825623433731595832392874511014 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/27.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 36285491242424073797268282643787713710379848011573299714833541277786519671588 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/27.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=401904420 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/27.i2c_target_nack_acqfull_addr.401904420 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 27.i2c_target_nack_acqfull_addr.401904420 -covoverwrite' seed=36285491242424073797268282643787713710379848011573299714833541277786519671588 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36285491242424073797268282643787713710379848011573299714833541277786519671588 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/27.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_txstretch 95320344580826617011080851562854038538063225606316426542154965148958938228512 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/27.i2c_target_nack_txstretch/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=667019040 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/27.i2c_target_nack_txstretch.667019040 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 27.i2c_target_nack_txstretch.667019040 -covoverwrite' seed=95320344580826617011080851562854038538063225606316426542154965148958938228512 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95320344580826617011080851562854038538063225606316426542154965148958938228512 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/27.i2c_target_nack_txstretch/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_txstretch_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 77718061901621676035557503501934421106962820386361567209743685606766827441835 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/28.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2738261675 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/28.i2c_host_override.2738261675 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 28.i2c_host_override.2738261675 -covoverwrite' seed=77718061901621676035557503501934421106962820386361567209743685606766827441835 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77718061901621676035557503501934421106962820386361567209743685606766827441835 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/28.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 102809297962389863117562132173637635747647821181231507510754778822512314228783 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/28.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3487113263 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/28.i2c_host_error_intr.3487113263 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 28.i2c_host_error_intr.3487113263 -covoverwrite' seed=102809297962389863117562132173637635747647821181231507510754778822512314228783 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102809297962389863117562132173637635747647821181231507510754778822512314228783 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/28.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all 26603388421570649688359378399155505030529824394615066453816193358730478632498 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/28.i2c_host_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2252750386 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/28.i2c_host_stress_all.2252750386 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 28.i2c_host_stress_all.2252750386 -covoverwrite' seed=26603388421570649688359378399155505030529824394615066453816193358730478632498 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26603388421570649688359378399155505030529824394615066453816193358730478632498 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/28.i2c_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 26696277256847445305506117708080525089516432896890723420895295310107301827948 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/28.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=342545772 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/28.i2c_target_fifo_reset_tx.342545772 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 28.i2c_target_fifo_reset_tx.342545772 -covoverwrite' seed=26696277256847445305506117708080525089516432896890723420895295310107301827948 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26696277256847445305506117708080525089516432896890723420895295310107301827948 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/28.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all 101809702635628368847485641977897547864817258327403609928687416216256660824905 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/28.i2c_target_stress_all/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=576643913 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/28.i2c_target_stress_all.576643913 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 28.i2c_target_stress_all.576643913 -covoverwrite' seed=101809702635628368847485641977897547864817258327403609928687416216256660824905 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101809702635628368847485641977897547864817258327403609928687416216256660824905 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/28.i2c_target_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 54833093581745478756823944484115549596338763353753880991001925445636110926392 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/28.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2887238200 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/28.i2c_target_hrst.2887238200 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 28.i2c_target_hrst.2887238200 -covoverwrite' seed=54833093581745478756823944484115549596338763353753880991001925445636110926392 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54833093581745478756823944484115549596338763353753880991001925445636110926392 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/28.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 72250569603720007419114872820652979982400886483468899968217459430932836873619 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/28.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3260380563 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/28.i2c_host_mode_toggle.3260380563 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 28.i2c_host_mode_toggle.3260380563 -covoverwrite' seed=72250569603720007419114872820652979982400886483468899968217459430932836873619 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72250569603720007419114872820652979982400886483468899968217459430932836873619 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/28.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 72312160193817204337988418475159310580151347800650868579653297663221532516680 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/28.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3893944648 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/28.i2c_host_may_nack.3893944648 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 28.i2c_host_may_nack.3893944648 -covoverwrite' seed=72312160193817204337988418475159310580151347800650868579653297663221532516680 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72312160193817204337988418475159310580151347800650868579653297663221532516680 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/28.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 110661674027905256444631291750132610149823679823411462708104397577627024362964 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/28.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1183714772 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/28.i2c_target_nack_acqfull.1183714772 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 28.i2c_target_nack_acqfull.1183714772 -covoverwrite' seed=110661674027905256444631291750132610149823679823411462708104397577627024362964 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110661674027905256444631291750132610149823679823411462708104397577627024362964 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/28.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 6264802538989034003798996893628791490164885471898861144122753562329642460814 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/28.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1260152462 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/28.i2c_target_nack_acqfull_addr.1260152462 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 28.i2c_target_nack_acqfull_addr.1260152462 -covoverwrite' seed=6264802538989034003798996893628791490164885471898861144122753562329642460814 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6264802538989034003798996893628791490164885471898861144122753562329642460814 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/28.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_txstretch 83969253174448662183448009275184112294635397720827445229549854799501089410316 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/28.i2c_target_nack_txstretch/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2083622156 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/28.i2c_target_nack_txstretch.2083622156 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 28.i2c_target_nack_txstretch.2083622156 -covoverwrite' seed=83969253174448662183448009275184112294635397720827445229549854799501089410316 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83969253174448662183448009275184112294635397720827445229549854799501089410316 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/28.i2c_target_nack_txstretch/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_txstretch_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 58284606401398665354629862147742343284668251277988035256089816416920086166842 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/29.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1931394362 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/29.i2c_host_override.1931394362 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 29.i2c_host_override.1931394362 -covoverwrite' seed=58284606401398665354629862147742343284668251277988035256089816416920086166842 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58284606401398665354629862147742343284668251277988035256089816416920086166842 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/29.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 15836039369752483424138569237692408785021502705007046629493363880071751408341 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/29.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=843717333 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/29.i2c_host_error_intr.843717333 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 29.i2c_host_error_intr.843717333 -covoverwrite' seed=15836039369752483424138569237692408785021502705007046629493363880071751408341 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15836039369752483424138569237692408785021502705007046629493363880071751408341 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/29.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_stress_all 32310049682295599560318693816057860204780953559905401542779212300984953244250 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/29.i2c_host_stress_all/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3332803162 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/29.i2c_host_stress_all.3332803162 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 29.i2c_host_stress_all.3332803162 -covoverwrite' seed=32310049682295599560318693816057860204780953559905401542779212300984953244250 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32310049682295599560318693816057860204780953559905401542779212300984953244250 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/29.i2c_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 62382583161611432426061950849806453582406058110417457401749065345083684465406 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/29.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=772319998 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/29.i2c_target_fifo_reset_tx.772319998 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 29.i2c_target_fifo_reset_tx.772319998 -covoverwrite' seed=62382583161611432426061950849806453582406058110417457401749065345083684465406 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62382583161611432426061950849806453582406058110417457401749065345083684465406 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/29.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_stress_all 10200066970900892587993876818871173680875474842474172652020978838997842080374 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/29.i2c_target_stress_all/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=300_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=905785974 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/29.i2c_target_stress_all.905785974 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 29.i2c_target_stress_all.905785974 -covoverwrite' seed=10200066970900892587993876818871173680875474842474172652020978838997842080374 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10200066970900892587993876818871173680875474842474172652020978838997842080374 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/29.i2c_target_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 2444709654244932866720241357331335190844753206693640887709362068472136470861 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/29.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1717834061 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/29.i2c_target_hrst.1717834061 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 29.i2c_target_hrst.1717834061 -covoverwrite' seed=2444709654244932866720241357331335190844753206693640887709362068472136470861 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2444709654244932866720241357331335190844753206693640887709362068472136470861 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/29.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 96523452327629825169453819758584076619475977819409498442774359315658721442048 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/29.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=720091392 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/29.i2c_host_mode_toggle.720091392 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 29.i2c_host_mode_toggle.720091392 -covoverwrite' seed=96523452327629825169453819758584076619475977819409498442774359315658721442048 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96523452327629825169453819758584076619475977819409498442774359315658721442048 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/29.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 39027837249906557118524380794160065566854237128098944299251340203554545976188 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/29.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=938853244 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/29.i2c_host_may_nack.938853244 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 29.i2c_host_may_nack.938853244 -covoverwrite' seed=39027837249906557118524380794160065566854237128098944299251340203554545976188 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39027837249906557118524380794160065566854237128098944299251340203554545976188 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/29.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 64165735886888780248117548831001523346609221152547942573143707157730104231846 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/29.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1778698150 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/29.i2c_target_nack_acqfull.1778698150 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 29.i2c_target_nack_acqfull.1778698150 -covoverwrite' seed=64165735886888780248117548831001523346609221152547942573143707157730104231846 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64165735886888780248117548831001523346609221152547942573143707157730104231846 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/29.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 24286950369363689933531729005016650259053612482402517412484340906517307129788 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/29.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2437218236 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/29.i2c_target_nack_acqfull_addr.2437218236 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 29.i2c_target_nack_acqfull_addr.2437218236 -covoverwrite' seed=24286950369363689933531729005016650259053612482402517412484340906517307129788 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24286950369363689933531729005016650259053612482402517412484340906517307129788 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/29.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_txstretch 65907305428169351552203000190139423259778828115812050403136517729611858048978 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/29.i2c_target_nack_txstretch/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=964687826 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_txstretch_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/29.i2c_target_nack_txstretch.964687826 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 29.i2c_target_nack_txstretch.964687826 -covoverwrite' seed=65907305428169351552203000190139423259778828115812050403136517729611858048978 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65907305428169351552203000190139423259778828115812050403136517729611858048978 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/29.i2c_target_nack_txstretch/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_txstretch_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 42758736425367379413409756309125439834311597260352424914319149419839150396046 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/30.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1741722254 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/30.i2c_host_override.1741722254 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 30.i2c_host_override.1741722254 -covoverwrite' seed=42758736425367379413409756309125439834311597260352424914319149419839150396046 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42758736425367379413409756309125439834311597260352424914319149419839150396046 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/30.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 88766122337815786493509014669239999104416200098406687238500249468027468005082 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/30.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3474734810 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/30.i2c_host_error_intr.3474734810 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 30.i2c_host_error_intr.3474734810 -covoverwrite' seed=88766122337815786493509014669239999104416200098406687238500249468027468005082 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88766122337815786493509014669239999104416200098406687238500249468027468005082 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/30.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 53297868057736931101560154608690794496872010119465015173851793526521728330507 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/30.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1241770763 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/30.i2c_target_fifo_reset_tx.1241770763 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 30.i2c_target_fifo_reset_tx.1241770763 -covoverwrite' seed=53297868057736931101560154608690794496872010119465015173851793526521728330507 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53297868057736931101560154608690794496872010119465015173851793526521728330507 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/30.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 88116261601154763561852040190802810059851568095512829645096985524093832243627 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/30.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3860179371 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/30.i2c_target_hrst.3860179371 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 30.i2c_target_hrst.3860179371 -covoverwrite' seed=88116261601154763561852040190802810059851568095512829645096985524093832243627 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88116261601154763561852040190802810059851568095512829645096985524093832243627 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/30.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 52979816179672647803231456777147902766351593029368006444906668660567796684066 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/30.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1849496866 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/30.i2c_host_mode_toggle.1849496866 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 30.i2c_host_mode_toggle.1849496866 -covoverwrite' seed=52979816179672647803231456777147902766351593029368006444906668660567796684066 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=52979816179672647803231456777147902766351593029368006444906668660567796684066 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/30.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 10923033119751561517393230271230383113350332435269989962680097671617390851883 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/30.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1192769323 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/30.i2c_host_may_nack.1192769323 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 30.i2c_host_may_nack.1192769323 -covoverwrite' seed=10923033119751561517393230271230383113350332435269989962680097671617390851883 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10923033119751561517393230271230383113350332435269989962680097671617390851883 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/30.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 84006575756515138116911384029914228520193803094854193883178734566139019035780 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/30.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=178947204 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/30.i2c_target_nack_acqfull.178947204 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 30.i2c_target_nack_acqfull.178947204 -covoverwrite' seed=84006575756515138116911384029914228520193803094854193883178734566139019035780 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84006575756515138116911384029914228520193803094854193883178734566139019035780 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/30.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 23914434870463395666448703567424055101546322528889047660711396940426850365240 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/30.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=631533368 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/30.i2c_target_nack_acqfull_addr.631533368 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 30.i2c_target_nack_acqfull_addr.631533368 -covoverwrite' seed=23914434870463395666448703567424055101546322528889047660711396940426850365240 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23914434870463395666448703567424055101546322528889047660711396940426850365240 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/30.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 98897703146416848583733059117946067268330299674997370998503706168634837195168 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/31.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1245338016 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/31.i2c_host_override.1245338016 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 31.i2c_host_override.1245338016 -covoverwrite' seed=98897703146416848583733059117946067268330299674997370998503706168634837195168 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98897703146416848583733059117946067268330299674997370998503706168634837195168 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/31.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 65557735098046540712064247316288308909436235387906982264862656110337211767133 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/31.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3165657437 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/31.i2c_host_error_intr.3165657437 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 31.i2c_host_error_intr.3165657437 -covoverwrite' seed=65557735098046540712064247316288308909436235387906982264862656110337211767133 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65557735098046540712064247316288308909436235387906982264862656110337211767133 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/31.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 56475542644383983816258640061394892563972926456703917737775993240463220879868 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/31.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3526308348 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/31.i2c_target_fifo_reset_tx.3526308348 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 31.i2c_target_fifo_reset_tx.3526308348 -covoverwrite' seed=56475542644383983816258640061394892563972926456703917737775993240463220879868 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56475542644383983816258640061394892563972926456703917737775993240463220879868 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/31.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 7782042910884397357619976999656063174930820717120266709011418851758026026684 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/31.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1998352060 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/31.i2c_target_hrst.1998352060 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 31.i2c_target_hrst.1998352060 -covoverwrite' seed=7782042910884397357619976999656063174930820717120266709011418851758026026684 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7782042910884397357619976999656063174930820717120266709011418851758026026684 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/31.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 74921036733668032462809191155437264370384952177185061219159523724577858353438 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/31.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1046444318 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/31.i2c_host_mode_toggle.1046444318 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 31.i2c_host_mode_toggle.1046444318 -covoverwrite' seed=74921036733668032462809191155437264370384952177185061219159523724577858353438 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74921036733668032462809191155437264370384952177185061219159523724577858353438 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/31.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 104396313256778525543186601651330628346073512772653680123642785691364980753465 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/31.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1751974969 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/31.i2c_host_may_nack.1751974969 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 31.i2c_host_may_nack.1751974969 -covoverwrite' seed=104396313256778525543186601651330628346073512772653680123642785691364980753465 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104396313256778525543186601651330628346073512772653680123642785691364980753465 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/31.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 32009877739678882467348999357673297889034583097236503373907962467037045051288 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/31.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2692992920 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/31.i2c_target_nack_acqfull.2692992920 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 31.i2c_target_nack_acqfull.2692992920 -covoverwrite' seed=32009877739678882467348999357673297889034583097236503373907962467037045051288 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32009877739678882467348999357673297889034583097236503373907962467037045051288 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/31.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 100089297895469948506451938349239231892609432356040339892407088703860103283438 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/31.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=539329262 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/31.i2c_target_nack_acqfull_addr.539329262 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 31.i2c_target_nack_acqfull_addr.539329262 -covoverwrite' seed=100089297895469948506451938349239231892609432356040339892407088703860103283438 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100089297895469948506451938349239231892609432356040339892407088703860103283438 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/31.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 631915102494726698364768128500769117888733121912608471230217354725276759290 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/32.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2996286714 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/32.i2c_host_override.2996286714 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 32.i2c_host_override.2996286714 -covoverwrite' seed=631915102494726698364768128500769117888733121912608471230217354725276759290 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=631915102494726698364768128500769117888733121912608471230217354725276759290 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/32.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 91698726583939559403797350590788671325473861614418325106901988337508891549304 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/32.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1575018104 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/32.i2c_host_error_intr.1575018104 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 32.i2c_host_error_intr.1575018104 -covoverwrite' seed=91698726583939559403797350590788671325473861614418325106901988337508891549304 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91698726583939559403797350590788671325473861614418325106901988337508891549304 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/32.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 101504424895888687137632907401339713299572013246004385799560504250154587342094 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/32.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1329415438 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/32.i2c_target_fifo_reset_tx.1329415438 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 32.i2c_target_fifo_reset_tx.1329415438 -covoverwrite' seed=101504424895888687137632907401339713299572013246004385799560504250154587342094 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101504424895888687137632907401339713299572013246004385799560504250154587342094 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/32.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 1568308414281741153304786978353492237993257660002166884217080092457852634721 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/32.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1573029473 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/32.i2c_target_hrst.1573029473 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 32.i2c_target_hrst.1573029473 -covoverwrite' seed=1568308414281741153304786978353492237993257660002166884217080092457852634721 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1568308414281741153304786978353492237993257660002166884217080092457852634721 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/32.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 42058836403955507528347498261064267466226689630687280360321461322701626715953 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/32.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2997661489 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/32.i2c_host_mode_toggle.2997661489 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 32.i2c_host_mode_toggle.2997661489 -covoverwrite' seed=42058836403955507528347498261064267466226689630687280360321461322701626715953 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42058836403955507528347498261064267466226689630687280360321461322701626715953 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/32.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 87160078201929928341925415841524458380171536470570514767726628598598488235737 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/32.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1378557657 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/32.i2c_host_may_nack.1378557657 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 32.i2c_host_may_nack.1378557657 -covoverwrite' seed=87160078201929928341925415841524458380171536470570514767726628598598488235737 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87160078201929928341925415841524458380171536470570514767726628598598488235737 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/32.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 108797175464188999251171003159283266905174043168843914237607768717306927119376 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/32.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=642907152 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/32.i2c_target_nack_acqfull.642907152 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 32.i2c_target_nack_acqfull.642907152 -covoverwrite' seed=108797175464188999251171003159283266905174043168843914237607768717306927119376 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108797175464188999251171003159283266905174043168843914237607768717306927119376 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/32.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 78162632725776556594698620151704816992548394445925728564178463040021002557791 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/32.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1554880863 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/32.i2c_target_nack_acqfull_addr.1554880863 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 32.i2c_target_nack_acqfull_addr.1554880863 -covoverwrite' seed=78162632725776556594698620151704816992548394445925728564178463040021002557791 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78162632725776556594698620151704816992548394445925728564178463040021002557791 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/32.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 33428388628511082923491491018946832033441675290498807065696264903324955661659 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/33.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2639091035 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/33.i2c_host_override.2639091035 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 33.i2c_host_override.2639091035 -covoverwrite' seed=33428388628511082923491491018946832033441675290498807065696264903324955661659 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33428388628511082923491491018946832033441675290498807065696264903324955661659 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/33.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 92785173693741408475716154498999744749257014646241630241676961947086850985636 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/33.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=455708324 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/33.i2c_host_error_intr.455708324 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 33.i2c_host_error_intr.455708324 -covoverwrite' seed=92785173693741408475716154498999744749257014646241630241676961947086850985636 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92785173693741408475716154498999744749257014646241630241676961947086850985636 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/33.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 95711800656289450496639555695227293121665917250420834019034905685410437113287 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/33.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1921230279 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/33.i2c_target_fifo_reset_tx.1921230279 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 33.i2c_target_fifo_reset_tx.1921230279 -covoverwrite' seed=95711800656289450496639555695227293121665917250420834019034905685410437113287 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95711800656289450496639555695227293121665917250420834019034905685410437113287 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/33.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 53026184944126981198747594415483367606318927807478853624858219904371674340117 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/33.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1985764117 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/33.i2c_target_hrst.1985764117 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 33.i2c_target_hrst.1985764117 -covoverwrite' seed=53026184944126981198747594415483367606318927807478853624858219904371674340117 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53026184944126981198747594415483367606318927807478853624858219904371674340117 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/33.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 65505308647603782212915650876071091027910662065937263404563665024462633532931 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/33.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4070800899 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/33.i2c_host_mode_toggle.4070800899 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 33.i2c_host_mode_toggle.4070800899 -covoverwrite' seed=65505308647603782212915650876071091027910662065937263404563665024462633532931 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65505308647603782212915650876071091027910662065937263404563665024462633532931 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/33.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 78942497227684463436084211143031333721247460520891651039911003948759450841440 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/33.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2929389920 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/33.i2c_host_may_nack.2929389920 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 33.i2c_host_may_nack.2929389920 -covoverwrite' seed=78942497227684463436084211143031333721247460520891651039911003948759450841440 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78942497227684463436084211143031333721247460520891651039911003948759450841440 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/33.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 98797889672638538894077769089297222918042064496629684136922732990523146757444 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/33.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2735465796 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/33.i2c_target_nack_acqfull.2735465796 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 33.i2c_target_nack_acqfull.2735465796 -covoverwrite' seed=98797889672638538894077769089297222918042064496629684136922732990523146757444 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98797889672638538894077769089297222918042064496629684136922732990523146757444 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/33.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 6344095120198803709070456567690951863990933393163334815811718422200182962480 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/33.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1473575216 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/33.i2c_target_nack_acqfull_addr.1473575216 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 33.i2c_target_nack_acqfull_addr.1473575216 -covoverwrite' seed=6344095120198803709070456567690951863990933393163334815811718422200182962480 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6344095120198803709070456567690951863990933393163334815811718422200182962480 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/33.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 53265205539147269981063771626457339006652563951409944630944090690976556955527 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/34.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2827138951 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/34.i2c_host_override.2827138951 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 34.i2c_host_override.2827138951 -covoverwrite' seed=53265205539147269981063771626457339006652563951409944630944090690976556955527 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53265205539147269981063771626457339006652563951409944630944090690976556955527 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/34.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 97138760602468534993548620443595559291803413786444003618582174610075582362460 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/34.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=132281180 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/34.i2c_host_error_intr.132281180 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 34.i2c_host_error_intr.132281180 -covoverwrite' seed=97138760602468534993548620443595559291803413786444003618582174610075582362460 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97138760602468534993548620443595559291803413786444003618582174610075582362460 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/34.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 84349868396711755907053948359488089090264352850894007708654851690281241164216 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/34.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3405789624 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/34.i2c_target_fifo_reset_tx.3405789624 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 34.i2c_target_fifo_reset_tx.3405789624 -covoverwrite' seed=84349868396711755907053948359488089090264352850894007708654851690281241164216 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84349868396711755907053948359488089090264352850894007708654851690281241164216 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/34.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 38051151597031932537314740408473497291513759295998039761464899163734534356660 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/34.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4122312372 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/34.i2c_target_hrst.4122312372 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 34.i2c_target_hrst.4122312372 -covoverwrite' seed=38051151597031932537314740408473497291513759295998039761464899163734534356660 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38051151597031932537314740408473497291513759295998039761464899163734534356660 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/34.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 5533120862833168164378157071267082236461591957085945735622442654224514327987 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/34.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2111350195 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/34.i2c_host_mode_toggle.2111350195 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 34.i2c_host_mode_toggle.2111350195 -covoverwrite' seed=5533120862833168164378157071267082236461591957085945735622442654224514327987 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5533120862833168164378157071267082236461591957085945735622442654224514327987 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/34.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 4991325485118563652108812059716917810590282433414961180123240558955133002560 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/34.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=583656256 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/34.i2c_host_may_nack.583656256 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 34.i2c_host_may_nack.583656256 -covoverwrite' seed=4991325485118563652108812059716917810590282433414961180123240558955133002560 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4991325485118563652108812059716917810590282433414961180123240558955133002560 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/34.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 23013704344792101003817475711491855236509296229049689900634961188405981069939 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/34.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1843511923 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/34.i2c_target_nack_acqfull.1843511923 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 34.i2c_target_nack_acqfull.1843511923 -covoverwrite' seed=23013704344792101003817475711491855236509296229049689900634961188405981069939 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23013704344792101003817475711491855236509296229049689900634961188405981069939 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/34.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 1009356203531526651847241793985885238412655881178385064519352807288912351294 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/34.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3733327934 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/34.i2c_target_nack_acqfull_addr.3733327934 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 34.i2c_target_nack_acqfull_addr.3733327934 -covoverwrite' seed=1009356203531526651847241793985885238412655881178385064519352807288912351294 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1009356203531526651847241793985885238412655881178385064519352807288912351294 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/34.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 80280507468633698251272016660268363659361111744040606139111747158637065086765 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/35.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=878520109 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/35.i2c_host_override.878520109 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 35.i2c_host_override.878520109 -covoverwrite' seed=80280507468633698251272016660268363659361111744040606139111747158637065086765 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80280507468633698251272016660268363659361111744040606139111747158637065086765 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/35.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 107867471596578561090381187607346656278377976980844474497476749969129680041142 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/35.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2611377334 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/35.i2c_host_error_intr.2611377334 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 35.i2c_host_error_intr.2611377334 -covoverwrite' seed=107867471596578561090381187607346656278377976980844474497476749969129680041142 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107867471596578561090381187607346656278377976980844474497476749969129680041142 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/35.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 66126682007871889753596392315855556145849825397216833310914721600844605332930 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/35.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=907713986 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/35.i2c_target_fifo_reset_tx.907713986 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 35.i2c_target_fifo_reset_tx.907713986 -covoverwrite' seed=66126682007871889753596392315855556145849825397216833310914721600844605332930 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66126682007871889753596392315855556145849825397216833310914721600844605332930 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/35.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 88246101354640399207779988223851319675839818954661552776057981588969375478892 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/35.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1431647340 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/35.i2c_target_hrst.1431647340 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 35.i2c_target_hrst.1431647340 -covoverwrite' seed=88246101354640399207779988223851319675839818954661552776057981588969375478892 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88246101354640399207779988223851319675839818954661552776057981588969375478892 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/35.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 10248699062647884592254237765288083559241222513755292265631421456818309323897 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/35.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1855609977 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/35.i2c_host_mode_toggle.1855609977 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 35.i2c_host_mode_toggle.1855609977 -covoverwrite' seed=10248699062647884592254237765288083559241222513755292265631421456818309323897 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10248699062647884592254237765288083559241222513755292265631421456818309323897 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/35.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 83929673653189322347960331201069087557813314783747312058061627795564933909868 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/35.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3129445740 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/35.i2c_host_may_nack.3129445740 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 35.i2c_host_may_nack.3129445740 -covoverwrite' seed=83929673653189322347960331201069087557813314783747312058061627795564933909868 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83929673653189322347960331201069087557813314783747312058061627795564933909868 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/35.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 73276126399879939709374552290013675811530601204193379987558988731582342319708 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/35.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=697388636 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/35.i2c_target_nack_acqfull.697388636 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 35.i2c_target_nack_acqfull.697388636 -covoverwrite' seed=73276126399879939709374552290013675811530601204193379987558988731582342319708 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73276126399879939709374552290013675811530601204193379987558988731582342319708 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/35.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 86028008187988243774932931539620805896579929536327366214287702831980488487319 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/35.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2930307479 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/35.i2c_target_nack_acqfull_addr.2930307479 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 35.i2c_target_nack_acqfull_addr.2930307479 -covoverwrite' seed=86028008187988243774932931539620805896579929536327366214287702831980488487319 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86028008187988243774932931539620805896579929536327366214287702831980488487319 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/35.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 76526886360959345196411694705272419243106616020208475023498633537361692042778 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/36.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2407507482 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/36.i2c_host_override.2407507482 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 36.i2c_host_override.2407507482 -covoverwrite' seed=76526886360959345196411694705272419243106616020208475023498633537361692042778 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76526886360959345196411694705272419243106616020208475023498633537361692042778 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/36.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 104104191037660868371900565299323060848565221014552922971213303831717167765055 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/36.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2388399679 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/36.i2c_host_error_intr.2388399679 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 36.i2c_host_error_intr.2388399679 -covoverwrite' seed=104104191037660868371900565299323060848565221014552922971213303831717167765055 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104104191037660868371900565299323060848565221014552922971213303831717167765055 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/36.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 50554565969174039799047961709485356275687706047527798477891583558290820361755 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/36.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=356576795 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/36.i2c_target_fifo_reset_tx.356576795 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 36.i2c_target_fifo_reset_tx.356576795 -covoverwrite' seed=50554565969174039799047961709485356275687706047527798477891583558290820361755 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50554565969174039799047961709485356275687706047527798477891583558290820361755 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/36.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 75642934661918633190761141393738034626862139093454944479992229714339136797661 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/36.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=15727581 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/36.i2c_target_hrst.15727581 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 36.i2c_target_hrst.15727581 -covoverwrite' seed=75642934661918633190761141393738034626862139093454944479992229714339136797661 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75642934661918633190761141393738034626862139093454944479992229714339136797661 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/36.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 62748852588581558195250654432670319685888779430452497098429608000810916077868 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/36.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2460049708 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/36.i2c_host_mode_toggle.2460049708 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 36.i2c_host_mode_toggle.2460049708 -covoverwrite' seed=62748852588581558195250654432670319685888779430452497098429608000810916077868 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62748852588581558195250654432670319685888779430452497098429608000810916077868 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/36.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 93085367637558716930035283372229129321131697641206756549436784129416060181733 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/36.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2376309989 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/36.i2c_host_may_nack.2376309989 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 36.i2c_host_may_nack.2376309989 -covoverwrite' seed=93085367637558716930035283372229129321131697641206756549436784129416060181733 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93085367637558716930035283372229129321131697641206756549436784129416060181733 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/36.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 78692968853506882638274423986827092593006433037503392536898093655257618659491 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/36.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3581753507 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/36.i2c_target_nack_acqfull.3581753507 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 36.i2c_target_nack_acqfull.3581753507 -covoverwrite' seed=78692968853506882638274423986827092593006433037503392536898093655257618659491 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78692968853506882638274423986827092593006433037503392536898093655257618659491 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/36.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 85048769627150505468350334109477387667422937676178391276724744498439520370976 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/36.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2176958752 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/36.i2c_target_nack_acqfull_addr.2176958752 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 36.i2c_target_nack_acqfull_addr.2176958752 -covoverwrite' seed=85048769627150505468350334109477387667422937676178391276724744498439520370976 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85048769627150505468350334109477387667422937676178391276724744498439520370976 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/36.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 19034494705201804660225484414512635252262625634831446312440873053101323366176 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/37.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2739842848 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/37.i2c_host_override.2739842848 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 37.i2c_host_override.2739842848 -covoverwrite' seed=19034494705201804660225484414512635252262625634831446312440873053101323366176 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19034494705201804660225484414512635252262625634831446312440873053101323366176 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/37.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 56184129935704153705091592402279915364187305811410054881152758180618500763248 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/37.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=928181872 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/37.i2c_host_error_intr.928181872 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 37.i2c_host_error_intr.928181872 -covoverwrite' seed=56184129935704153705091592402279915364187305811410054881152758180618500763248 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56184129935704153705091592402279915364187305811410054881152758180618500763248 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/37.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 72756915392751030615681329280038513944778142999725379869837810576267576702525 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/37.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1046050365 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/37.i2c_target_fifo_reset_tx.1046050365 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 37.i2c_target_fifo_reset_tx.1046050365 -covoverwrite' seed=72756915392751030615681329280038513944778142999725379869837810576267576702525 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72756915392751030615681329280038513944778142999725379869837810576267576702525 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/37.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 20637794040828335746586922421890888879197496364496183509456154271235702882878 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/37.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2153873982 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/37.i2c_target_hrst.2153873982 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 37.i2c_target_hrst.2153873982 -covoverwrite' seed=20637794040828335746586922421890888879197496364496183509456154271235702882878 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20637794040828335746586922421890888879197496364496183509456154271235702882878 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/37.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 91096098426139704578327753964044475869858162099183992733788779465798161450497 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/37.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2783626753 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/37.i2c_host_mode_toggle.2783626753 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 37.i2c_host_mode_toggle.2783626753 -covoverwrite' seed=91096098426139704578327753964044475869858162099183992733788779465798161450497 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91096098426139704578327753964044475869858162099183992733788779465798161450497 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/37.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 112264920221496205833416288997165225731374302670371329973627124516463678262218 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/37.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=591858634 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/37.i2c_host_may_nack.591858634 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 37.i2c_host_may_nack.591858634 -covoverwrite' seed=112264920221496205833416288997165225731374302670371329973627124516463678262218 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112264920221496205833416288997165225731374302670371329973627124516463678262218 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/37.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 99771132641764191753806783973637912216095251512006113207365098474871941186828 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/37.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4283385100 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/37.i2c_target_nack_acqfull.4283385100 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 37.i2c_target_nack_acqfull.4283385100 -covoverwrite' seed=99771132641764191753806783973637912216095251512006113207365098474871941186828 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99771132641764191753806783973637912216095251512006113207365098474871941186828 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/37.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 67995736114349589115312207094670888758133587071072012075237500944309673006633 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/37.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3401848361 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/37.i2c_target_nack_acqfull_addr.3401848361 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 37.i2c_target_nack_acqfull_addr.3401848361 -covoverwrite' seed=67995736114349589115312207094670888758133587071072012075237500944309673006633 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67995736114349589115312207094670888758133587071072012075237500944309673006633 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/37.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 93063678817973294633725034146691506151841270808383819499632937468337623717708 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/38.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3489453900 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/38.i2c_host_override.3489453900 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 38.i2c_host_override.3489453900 -covoverwrite' seed=93063678817973294633725034146691506151841270808383819499632937468337623717708 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93063678817973294633725034146691506151841270808383819499632937468337623717708 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/38.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 71511031478515120196500850338694867311945463576571646995805041714707003030559 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/38.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2015837215 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/38.i2c_host_error_intr.2015837215 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 38.i2c_host_error_intr.2015837215 -covoverwrite' seed=71511031478515120196500850338694867311945463576571646995805041714707003030559 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71511031478515120196500850338694867311945463576571646995805041714707003030559 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/38.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 58205962864561241172259317279950098880515988525004515025710971029108689397531 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/38.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=569829147 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/38.i2c_target_fifo_reset_tx.569829147 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 38.i2c_target_fifo_reset_tx.569829147 -covoverwrite' seed=58205962864561241172259317279950098880515988525004515025710971029108689397531 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58205962864561241172259317279950098880515988525004515025710971029108689397531 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/38.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 85076761273461571048832018193178955655344454218265913013926066365617196709238 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/38.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=19346806 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/38.i2c_target_hrst.19346806 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 38.i2c_target_hrst.19346806 -covoverwrite' seed=85076761273461571048832018193178955655344454218265913013926066365617196709238 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85076761273461571048832018193178955655344454218265913013926066365617196709238 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/38.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 85130775742504237992374355210895065423678074790672659751359648127657124312711 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/38.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1536964231 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/38.i2c_host_mode_toggle.1536964231 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 38.i2c_host_mode_toggle.1536964231 -covoverwrite' seed=85130775742504237992374355210895065423678074790672659751359648127657124312711 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85130775742504237992374355210895065423678074790672659751359648127657124312711 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/38.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 31949114917444424149375024593718984847748404097850065678545638706496926280015 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/38.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=833251663 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/38.i2c_host_may_nack.833251663 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 38.i2c_host_may_nack.833251663 -covoverwrite' seed=31949114917444424149375024593718984847748404097850065678545638706496926280015 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31949114917444424149375024593718984847748404097850065678545638706496926280015 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/38.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 35145450128900858334858791310260407308054154700294069012178083437421526877206 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/38.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=924681238 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/38.i2c_target_nack_acqfull.924681238 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 38.i2c_target_nack_acqfull.924681238 -covoverwrite' seed=35145450128900858334858791310260407308054154700294069012178083437421526877206 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35145450128900858334858791310260407308054154700294069012178083437421526877206 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/38.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 21904700807966299821965727418870077643160067498734080392352371840705756232760 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/38.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3928063032 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/38.i2c_target_nack_acqfull_addr.3928063032 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 38.i2c_target_nack_acqfull_addr.3928063032 -covoverwrite' seed=21904700807966299821965727418870077643160067498734080392352371840705756232760 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21904700807966299821965727418870077643160067498734080392352371840705756232760 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/38.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 6962343724605176574167773247178356046891335536699940974333006654191197969869 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/39.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=74669517 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/39.i2c_host_override.74669517 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 39.i2c_host_override.74669517 -covoverwrite' seed=6962343724605176574167773247178356046891335536699940974333006654191197969869 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6962343724605176574167773247178356046891335536699940974333006654191197969869 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/39.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 111099747452142613610062250618411170510104757547406342163861198367467667748510 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/39.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2928178846 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/39.i2c_host_error_intr.2928178846 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 39.i2c_host_error_intr.2928178846 -covoverwrite' seed=111099747452142613610062250618411170510104757547406342163861198367467667748510 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111099747452142613610062250618411170510104757547406342163861198367467667748510 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/39.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 35458939212086379359527274030887905102181903982655150883157885309771587684381 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/39.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3957229597 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/39.i2c_target_fifo_reset_tx.3957229597 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 39.i2c_target_fifo_reset_tx.3957229597 -covoverwrite' seed=35458939212086379359527274030887905102181903982655150883157885309771587684381 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35458939212086379359527274030887905102181903982655150883157885309771587684381 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/39.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 34050716195987519852250492118336519312729388089695136414571293666772998339928 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/39.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3383934296 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/39.i2c_target_hrst.3383934296 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 39.i2c_target_hrst.3383934296 -covoverwrite' seed=34050716195987519852250492118336519312729388089695136414571293666772998339928 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34050716195987519852250492118336519312729388089695136414571293666772998339928 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/39.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 48423051389616270326196880032645413462977958656672272421451157687964290860001 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/39.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1261781985 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/39.i2c_host_mode_toggle.1261781985 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 39.i2c_host_mode_toggle.1261781985 -covoverwrite' seed=48423051389616270326196880032645413462977958656672272421451157687964290860001 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48423051389616270326196880032645413462977958656672272421451157687964290860001 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/39.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 24782395233622490324111116896846791174198827149672627075118486491060700957313 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/39.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3212036737 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/39.i2c_host_may_nack.3212036737 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 39.i2c_host_may_nack.3212036737 -covoverwrite' seed=24782395233622490324111116896846791174198827149672627075118486491060700957313 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24782395233622490324111116896846791174198827149672627075118486491060700957313 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/39.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 7468932006986605129133415983812282148745537825749649545349329348283053250486 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/39.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=297408438 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/39.i2c_target_nack_acqfull.297408438 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 39.i2c_target_nack_acqfull.297408438 -covoverwrite' seed=7468932006986605129133415983812282148745537825749649545349329348283053250486 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7468932006986605129133415983812282148745537825749649545349329348283053250486 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/39.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 65733270016865428691799690608566604630639703882604576431994222844786027215551 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/39.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3638246079 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/39.i2c_target_nack_acqfull_addr.3638246079 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 39.i2c_target_nack_acqfull_addr.3638246079 -covoverwrite' seed=65733270016865428691799690608566604630639703882604576431994222844786027215551 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65733270016865428691799690608566604630639703882604576431994222844786027215551 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/39.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 17122675198677693295112435090680870044941524831311037760304231302017200418825 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/40.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=433057801 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/40.i2c_host_override.433057801 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 40.i2c_host_override.433057801 -covoverwrite' seed=17122675198677693295112435090680870044941524831311037760304231302017200418825 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17122675198677693295112435090680870044941524831311037760304231302017200418825 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/40.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 87080677375464045175095410924631102025933718342349539868693561090316571006255 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/40.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1230263599 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/40.i2c_host_error_intr.1230263599 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 40.i2c_host_error_intr.1230263599 -covoverwrite' seed=87080677375464045175095410924631102025933718342349539868693561090316571006255 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87080677375464045175095410924631102025933718342349539868693561090316571006255 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/40.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 46048418332352136296578100748151120738138175126724615477598365104404286899356 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/40.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2922087580 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/40.i2c_target_fifo_reset_tx.2922087580 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 40.i2c_target_fifo_reset_tx.2922087580 -covoverwrite' seed=46048418332352136296578100748151120738138175126724615477598365104404286899356 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46048418332352136296578100748151120738138175126724615477598365104404286899356 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/40.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 73945635516039750629651208087715315831139992288813302696875017162341094055868 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/40.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=137945020 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/40.i2c_target_hrst.137945020 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 40.i2c_target_hrst.137945020 -covoverwrite' seed=73945635516039750629651208087715315831139992288813302696875017162341094055868 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73945635516039750629651208087715315831139992288813302696875017162341094055868 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/40.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 41380006347519060019682531421577877991127379153071282241324891914984396219044 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/40.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1207493284 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/40.i2c_host_mode_toggle.1207493284 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 40.i2c_host_mode_toggle.1207493284 -covoverwrite' seed=41380006347519060019682531421577877991127379153071282241324891914984396219044 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41380006347519060019682531421577877991127379153071282241324891914984396219044 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/40.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 82212720296502198796828834097102011139115968174160884644926688825076242340233 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/40.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3624294793 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/40.i2c_host_may_nack.3624294793 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 40.i2c_host_may_nack.3624294793 -covoverwrite' seed=82212720296502198796828834097102011139115968174160884644926688825076242340233 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82212720296502198796828834097102011139115968174160884644926688825076242340233 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/40.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 105170865601936279045861728524865115940757724171646087122760569636981230486893 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/40.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3981133165 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/40.i2c_target_nack_acqfull.3981133165 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 40.i2c_target_nack_acqfull.3981133165 -covoverwrite' seed=105170865601936279045861728524865115940757724171646087122760569636981230486893 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105170865601936279045861728524865115940757724171646087122760569636981230486893 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/40.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 21725537518058164218697567457531426302434050020867384781444955643508953358437 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/40.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=44212325 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/40.i2c_target_nack_acqfull_addr.44212325 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 40.i2c_target_nack_acqfull_addr.44212325 -covoverwrite' seed=21725537518058164218697567457531426302434050020867384781444955643508953358437 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21725537518058164218697567457531426302434050020867384781444955643508953358437 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/40.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 41399783858238808810714293979444904200174893334832163791139268889342679678751 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/41.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2163965727 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/41.i2c_host_override.2163965727 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 41.i2c_host_override.2163965727 -covoverwrite' seed=41399783858238808810714293979444904200174893334832163791139268889342679678751 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41399783858238808810714293979444904200174893334832163791139268889342679678751 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/41.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 21227773833124705438738835215163969504135884146640864472371086918588113954862 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/41.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3184863278 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/41.i2c_host_error_intr.3184863278 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 41.i2c_host_error_intr.3184863278 -covoverwrite' seed=21227773833124705438738835215163969504135884146640864472371086918588113954862 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21227773833124705438738835215163969504135884146640864472371086918588113954862 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/41.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 88287328904770535830239599881288596143234499718535629947215299664465613035563 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/41.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1955076139 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/41.i2c_target_fifo_reset_tx.1955076139 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 41.i2c_target_fifo_reset_tx.1955076139 -covoverwrite' seed=88287328904770535830239599881288596143234499718535629947215299664465613035563 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88287328904770535830239599881288596143234499718535629947215299664465613035563 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/41.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 21392077449058015301454942403243624552440555317197423246749771489000426946682 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/41.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=115720314 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/41.i2c_target_hrst.115720314 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 41.i2c_target_hrst.115720314 -covoverwrite' seed=21392077449058015301454942403243624552440555317197423246749771489000426946682 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21392077449058015301454942403243624552440555317197423246749771489000426946682 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/41.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 34811118419626363506406417684250271468033519290066094258697776946001351612636 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/41.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=515709148 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/41.i2c_host_mode_toggle.515709148 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 41.i2c_host_mode_toggle.515709148 -covoverwrite' seed=34811118419626363506406417684250271468033519290066094258697776946001351612636 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34811118419626363506406417684250271468033519290066094258697776946001351612636 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/41.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 1768518800528590706416870211704416450890573783259681490778866146255859258553 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/41.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3576599737 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/41.i2c_host_may_nack.3576599737 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 41.i2c_host_may_nack.3576599737 -covoverwrite' seed=1768518800528590706416870211704416450890573783259681490778866146255859258553 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1768518800528590706416870211704416450890573783259681490778866146255859258553 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/41.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 23741445616378456940311113216422983306183829022847941199918898582248125413260 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/41.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1760868236 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/41.i2c_target_nack_acqfull.1760868236 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 41.i2c_target_nack_acqfull.1760868236 -covoverwrite' seed=23741445616378456940311113216422983306183829022847941199918898582248125413260 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23741445616378456940311113216422983306183829022847941199918898582248125413260 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/41.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 108103267770484183064938180907384331362062795618810621801333879187039870665250 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/41.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3478274594 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/41.i2c_target_nack_acqfull_addr.3478274594 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 41.i2c_target_nack_acqfull_addr.3478274594 -covoverwrite' seed=108103267770484183064938180907384331362062795618810621801333879187039870665250 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108103267770484183064938180907384331362062795618810621801333879187039870665250 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/41.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 45734466250334253344785191888256854663806408885610519984331689962211889607400 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/42.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2154525416 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/42.i2c_host_override.2154525416 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 42.i2c_host_override.2154525416 -covoverwrite' seed=45734466250334253344785191888256854663806408885610519984331689962211889607400 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45734466250334253344785191888256854663806408885610519984331689962211889607400 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/42.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 61585412813479989886901344894931164778975903950258501370165186654782917303880 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/42.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1260248648 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/42.i2c_host_error_intr.1260248648 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 42.i2c_host_error_intr.1260248648 -covoverwrite' seed=61585412813479989886901344894931164778975903950258501370165186654782917303880 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61585412813479989886901344894931164778975903950258501370165186654782917303880 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/42.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 46312814723171988679960423244825383071126670551622634109070681047573083196558 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/42.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2252082318 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/42.i2c_target_fifo_reset_tx.2252082318 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 42.i2c_target_fifo_reset_tx.2252082318 -covoverwrite' seed=46312814723171988679960423244825383071126670551622634109070681047573083196558 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46312814723171988679960423244825383071126670551622634109070681047573083196558 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/42.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 11509934319734574135984082079421246300984856788895382274445285393519614994599 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/42.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1944955047 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/42.i2c_target_hrst.1944955047 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 42.i2c_target_hrst.1944955047 -covoverwrite' seed=11509934319734574135984082079421246300984856788895382274445285393519614994599 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11509934319734574135984082079421246300984856788895382274445285393519614994599 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/42.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 11249398839575301761342732123218162491608894909429382493870174902459886493709 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/42.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=769155085 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/42.i2c_host_mode_toggle.769155085 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 42.i2c_host_mode_toggle.769155085 -covoverwrite' seed=11249398839575301761342732123218162491608894909429382493870174902459886493709 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11249398839575301761342732123218162491608894909429382493870174902459886493709 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/42.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 33982175250553396921168448932398986320540998005295989371613357482200543485295 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/42.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3795803503 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/42.i2c_host_may_nack.3795803503 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 42.i2c_host_may_nack.3795803503 -covoverwrite' seed=33982175250553396921168448932398986320540998005295989371613357482200543485295 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33982175250553396921168448932398986320540998005295989371613357482200543485295 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/42.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 8593222574081937662105486978103227823358602412487848895355280895153839510901 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/42.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2428999029 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/42.i2c_target_nack_acqfull.2428999029 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 42.i2c_target_nack_acqfull.2428999029 -covoverwrite' seed=8593222574081937662105486978103227823358602412487848895355280895153839510901 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8593222574081937662105486978103227823358602412487848895355280895153839510901 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/42.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 8594210636187091644651715253232968076484042506638005952999974159852599606448 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/42.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1877048496 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/42.i2c_target_nack_acqfull_addr.1877048496 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 42.i2c_target_nack_acqfull_addr.1877048496 -covoverwrite' seed=8594210636187091644651715253232968076484042506638005952999974159852599606448 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8594210636187091644651715253232968076484042506638005952999974159852599606448 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/42.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 63637498445788950852330031837855778884849530338946558051162039740223491892148 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/43.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3585041332 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/43.i2c_host_override.3585041332 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 43.i2c_host_override.3585041332 -covoverwrite' seed=63637498445788950852330031837855778884849530338946558051162039740223491892148 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63637498445788950852330031837855778884849530338946558051162039740223491892148 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/43.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 13374281225076863502900186096669334989232045581044490074049638440631852857583 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/43.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3995597039 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/43.i2c_host_error_intr.3995597039 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 43.i2c_host_error_intr.3995597039 -covoverwrite' seed=13374281225076863502900186096669334989232045581044490074049638440631852857583 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13374281225076863502900186096669334989232045581044490074049638440631852857583 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/43.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 90312383773046466278480188322725278220465200583048439653409037666888879528493 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/43.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2673433133 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/43.i2c_target_fifo_reset_tx.2673433133 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 43.i2c_target_fifo_reset_tx.2673433133 -covoverwrite' seed=90312383773046466278480188322725278220465200583048439653409037666888879528493 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90312383773046466278480188322725278220465200583048439653409037666888879528493 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/43.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 77614975013023450664240282297572343499297683070302513280872170914354568370011 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/43.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2880444251 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/43.i2c_target_hrst.2880444251 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 43.i2c_target_hrst.2880444251 -covoverwrite' seed=77614975013023450664240282297572343499297683070302513280872170914354568370011 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77614975013023450664240282297572343499297683070302513280872170914354568370011 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/43.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 109730094447131053854780837095389028426053470917324460707819873284792145973762 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/43.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3295187458 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/43.i2c_host_mode_toggle.3295187458 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 43.i2c_host_mode_toggle.3295187458 -covoverwrite' seed=109730094447131053854780837095389028426053470917324460707819873284792145973762 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109730094447131053854780837095389028426053470917324460707819873284792145973762 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/43.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 3562789326449402162674659912415355959422733822389844701836870659829613560344 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/43.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2600567320 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/43.i2c_host_may_nack.2600567320 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 43.i2c_host_may_nack.2600567320 -covoverwrite' seed=3562789326449402162674659912415355959422733822389844701836870659829613560344 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3562789326449402162674659912415355959422733822389844701836870659829613560344 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/43.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 113094220611373001336906920316889009156497836613714361055394772746236661928104 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/43.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1997082792 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/43.i2c_target_nack_acqfull.1997082792 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 43.i2c_target_nack_acqfull.1997082792 -covoverwrite' seed=113094220611373001336906920316889009156497836613714361055394772746236661928104 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113094220611373001336906920316889009156497836613714361055394772746236661928104 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/43.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 51777636998601837995867410044630271207351130370055518471730852393665437573358 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/43.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3468370158 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/43.i2c_target_nack_acqfull_addr.3468370158 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 43.i2c_target_nack_acqfull_addr.3468370158 -covoverwrite' seed=51777636998601837995867410044630271207351130370055518471730852393665437573358 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51777636998601837995867410044630271207351130370055518471730852393665437573358 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/43.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 43706354868692932776305226383038252049085330499338793721689164406136574108647 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/44.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3878216679 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/44.i2c_host_override.3878216679 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 44.i2c_host_override.3878216679 -covoverwrite' seed=43706354868692932776305226383038252049085330499338793721689164406136574108647 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43706354868692932776305226383038252049085330499338793721689164406136574108647 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/44.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 44639258238085442380102644145520763416789517254492506008292651136204296681280 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/44.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=177207104 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/44.i2c_host_error_intr.177207104 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 44.i2c_host_error_intr.177207104 -covoverwrite' seed=44639258238085442380102644145520763416789517254492506008292651136204296681280 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44639258238085442380102644145520763416789517254492506008292651136204296681280 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/44.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 1127404588824615560968303913878470549630895820793982448291712764564573593280 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/44.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1955667648 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/44.i2c_target_fifo_reset_tx.1955667648 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 44.i2c_target_fifo_reset_tx.1955667648 -covoverwrite' seed=1127404588824615560968303913878470549630895820793982448291712764564573593280 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1127404588824615560968303913878470549630895820793982448291712764564573593280 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/44.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 80266927706351584101666238978024363252886425642110606879849538378137942637124 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/44.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=988559940 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/44.i2c_target_hrst.988559940 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 44.i2c_target_hrst.988559940 -covoverwrite' seed=80266927706351584101666238978024363252886425642110606879849538378137942637124 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80266927706351584101666238978024363252886425642110606879849538378137942637124 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/44.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 11919993989246666402098559574597194563340309211853681031025730501734879323204 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/44.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2121131076 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/44.i2c_host_mode_toggle.2121131076 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 44.i2c_host_mode_toggle.2121131076 -covoverwrite' seed=11919993989246666402098559574597194563340309211853681031025730501734879323204 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11919993989246666402098559574597194563340309211853681031025730501734879323204 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/44.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 69372350181351859705523650670143238196716449747068404356573145138006267866044 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/44.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=542452668 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/44.i2c_host_may_nack.542452668 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 44.i2c_host_may_nack.542452668 -covoverwrite' seed=69372350181351859705523650670143238196716449747068404356573145138006267866044 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69372350181351859705523650670143238196716449747068404356573145138006267866044 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/44.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 94459518209444235520637406231426886911588862975829702039907387876923030562100 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/44.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=628811060 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/44.i2c_target_nack_acqfull.628811060 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 44.i2c_target_nack_acqfull.628811060 -covoverwrite' seed=94459518209444235520637406231426886911588862975829702039907387876923030562100 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94459518209444235520637406231426886911588862975829702039907387876923030562100 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/44.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 36272594561561635561374299465066489839123476911504286160821272938609541359317 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/44.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2028447445 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/44.i2c_target_nack_acqfull_addr.2028447445 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 44.i2c_target_nack_acqfull_addr.2028447445 -covoverwrite' seed=36272594561561635561374299465066489839123476911504286160821272938609541359317 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36272594561561635561374299465066489839123476911504286160821272938609541359317 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/44.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 9200734204583781572875255767649008217863519042893924525054876173808900614291 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/45.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2721949843 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/45.i2c_host_override.2721949843 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 45.i2c_host_override.2721949843 -covoverwrite' seed=9200734204583781572875255767649008217863519042893924525054876173808900614291 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9200734204583781572875255767649008217863519042893924525054876173808900614291 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/45.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 115407378771253626431728563138003676762690115973916775429037532102906693963598 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/45.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1275481934 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/45.i2c_host_error_intr.1275481934 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 45.i2c_host_error_intr.1275481934 -covoverwrite' seed=115407378771253626431728563138003676762690115973916775429037532102906693963598 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115407378771253626431728563138003676762690115973916775429037532102906693963598 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/45.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 11961575986919554728693191770426579354913399141237496605315302511670301050484 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/45.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4175447668 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/45.i2c_target_fifo_reset_tx.4175447668 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 45.i2c_target_fifo_reset_tx.4175447668 -covoverwrite' seed=11961575986919554728693191770426579354913399141237496605315302511670301050484 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11961575986919554728693191770426579354913399141237496605315302511670301050484 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/45.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 112162121356619723488130602952516971647900957059043112378074032925578900950383 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/45.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4254223727 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/45.i2c_target_hrst.4254223727 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 45.i2c_target_hrst.4254223727 -covoverwrite' seed=112162121356619723488130602952516971647900957059043112378074032925578900950383 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112162121356619723488130602952516971647900957059043112378074032925578900950383 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/45.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 51240232096716790067133990030878576294122116776359131683073477908265284051676 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/45.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1860084444 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/45.i2c_host_mode_toggle.1860084444 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 45.i2c_host_mode_toggle.1860084444 -covoverwrite' seed=51240232096716790067133990030878576294122116776359131683073477908265284051676 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51240232096716790067133990030878576294122116776359131683073477908265284051676 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/45.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 25257358756212531908916717315181285990862717915173554438165240995864732609913 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/45.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=149794169 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/45.i2c_host_may_nack.149794169 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 45.i2c_host_may_nack.149794169 -covoverwrite' seed=25257358756212531908916717315181285990862717915173554438165240995864732609913 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25257358756212531908916717315181285990862717915173554438165240995864732609913 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/45.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 44318186776205345688989770045577570945017678468136361986388452830693575474822 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/45.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1254473350 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/45.i2c_target_nack_acqfull.1254473350 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 45.i2c_target_nack_acqfull.1254473350 -covoverwrite' seed=44318186776205345688989770045577570945017678468136361986388452830693575474822 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44318186776205345688989770045577570945017678468136361986388452830693575474822 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/45.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 27781964005531645010661940990461675895440013648752131574729004850884162356381 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/45.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=886834333 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/45.i2c_target_nack_acqfull_addr.886834333 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 45.i2c_target_nack_acqfull_addr.886834333 -covoverwrite' seed=27781964005531645010661940990461675895440013648752131574729004850884162356381 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27781964005531645010661940990461675895440013648752131574729004850884162356381 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/45.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 105719633803548726204507752391075701456033517217878628733373076633883670837494 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/46.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2932439286 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/46.i2c_host_override.2932439286 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 46.i2c_host_override.2932439286 -covoverwrite' seed=105719633803548726204507752391075701456033517217878628733373076633883670837494 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105719633803548726204507752391075701456033517217878628733373076633883670837494 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/46.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 43619669645375591471474541438898637508704035207246220214015294552087468688729 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/46.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=302499161 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/46.i2c_host_error_intr.302499161 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 46.i2c_host_error_intr.302499161 -covoverwrite' seed=43619669645375591471474541438898637508704035207246220214015294552087468688729 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43619669645375591471474541438898637508704035207246220214015294552087468688729 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/46.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 20716556243367692262373598353001022016478283317667059988712271942660566803285 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/46.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1157358421 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/46.i2c_target_fifo_reset_tx.1157358421 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 46.i2c_target_fifo_reset_tx.1157358421 -covoverwrite' seed=20716556243367692262373598353001022016478283317667059988712271942660566803285 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20716556243367692262373598353001022016478283317667059988712271942660566803285 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/46.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 51371365323149875598149545799962692895678054214935081776705936915950738929011 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/46.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1955919219 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/46.i2c_target_hrst.1955919219 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 46.i2c_target_hrst.1955919219 -covoverwrite' seed=51371365323149875598149545799962692895678054214935081776705936915950738929011 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51371365323149875598149545799962692895678054214935081776705936915950738929011 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/46.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 53546869773885251131237096991277986597600474202267434009255427372705074306101 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/46.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4209171509 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/46.i2c_host_mode_toggle.4209171509 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 46.i2c_host_mode_toggle.4209171509 -covoverwrite' seed=53546869773885251131237096991277986597600474202267434009255427372705074306101 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53546869773885251131237096991277986597600474202267434009255427372705074306101 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/46.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 86170455522378384276810825783733535701538694724262868573063018337252780207718 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/46.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=802877030 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/46.i2c_host_may_nack.802877030 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 46.i2c_host_may_nack.802877030 -covoverwrite' seed=86170455522378384276810825783733535701538694724262868573063018337252780207718 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86170455522378384276810825783733535701538694724262868573063018337252780207718 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/46.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 36056494900105929939409150969115325518559961255055520329736598737364989266724 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/46.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=219171620 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/46.i2c_target_nack_acqfull.219171620 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 46.i2c_target_nack_acqfull.219171620 -covoverwrite' seed=36056494900105929939409150969115325518559961255055520329736598737364989266724 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36056494900105929939409150969115325518559961255055520329736598737364989266724 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/46.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 27194245575571957793398763634993569039047299272325659425475495248953232571337 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/46.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3053173705 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/46.i2c_target_nack_acqfull_addr.3053173705 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 46.i2c_target_nack_acqfull_addr.3053173705 -covoverwrite' seed=27194245575571957793398763634993569039047299272325659425475495248953232571337 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27194245575571957793398763634993569039047299272325659425475495248953232571337 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/46.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 38949572417130468175248919895401288518258193368460722969346765016123706658992 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/47.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1472417968 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/47.i2c_host_override.1472417968 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 47.i2c_host_override.1472417968 -covoverwrite' seed=38949572417130468175248919895401288518258193368460722969346765016123706658992 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38949572417130468175248919895401288518258193368460722969346765016123706658992 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/47.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 25571970986844415550948448224242749053399501087014185243954168852485836860179 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/47.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3678890771 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/47.i2c_host_error_intr.3678890771 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 47.i2c_host_error_intr.3678890771 -covoverwrite' seed=25571970986844415550948448224242749053399501087014185243954168852485836860179 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25571970986844415550948448224242749053399501087014185243954168852485836860179 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/47.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 31693880896094054121058352097604067800238800341375792857177639642170942977059 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/47.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2418963491 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/47.i2c_target_fifo_reset_tx.2418963491 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 47.i2c_target_fifo_reset_tx.2418963491 -covoverwrite' seed=31693880896094054121058352097604067800238800341375792857177639642170942977059 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31693880896094054121058352097604067800238800341375792857177639642170942977059 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/47.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 7744578401823360846559900746887802203761060327527767220686223456839917644732 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/47.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1952721852 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/47.i2c_target_hrst.1952721852 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 47.i2c_target_hrst.1952721852 -covoverwrite' seed=7744578401823360846559900746887802203761060327527767220686223456839917644732 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7744578401823360846559900746887802203761060327527767220686223456839917644732 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/47.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 11036679116949576550065715348098698479513748834726556098809465176908488113139 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/47.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1416231923 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/47.i2c_host_mode_toggle.1416231923 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 47.i2c_host_mode_toggle.1416231923 -covoverwrite' seed=11036679116949576550065715348098698479513748834726556098809465176908488113139 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11036679116949576550065715348098698479513748834726556098809465176908488113139 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/47.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 43944639420672103762092063966936367471668850558155872840702319171516496700719 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/47.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2154652975 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/47.i2c_host_may_nack.2154652975 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 47.i2c_host_may_nack.2154652975 -covoverwrite' seed=43944639420672103762092063966936367471668850558155872840702319171516496700719 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43944639420672103762092063966936367471668850558155872840702319171516496700719 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/47.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 46570106715058846931026693045178304345244261761854864778950752125173648382057 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/47.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2571688041 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/47.i2c_target_nack_acqfull.2571688041 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 47.i2c_target_nack_acqfull.2571688041 -covoverwrite' seed=46570106715058846931026693045178304345244261761854864778950752125173648382057 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46570106715058846931026693045178304345244261761854864778950752125173648382057 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/47.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 8086122805358840149479467432379606480350541820003647703566541341255199663040 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/47.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4058555328 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/47.i2c_target_nack_acqfull_addr.4058555328 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 47.i2c_target_nack_acqfull_addr.4058555328 -covoverwrite' seed=8086122805358840149479467432379606480350541820003647703566541341255199663040 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8086122805358840149479467432379606480350541820003647703566541341255199663040 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/47.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 40950485845285455573339114598471458465883086718218818004356695484217821046543 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/48.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3652003599 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/48.i2c_host_override.3652003599 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 48.i2c_host_override.3652003599 -covoverwrite' seed=40950485845285455573339114598471458465883086718218818004356695484217821046543 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40950485845285455573339114598471458465883086718218818004356695484217821046543 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/48.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 90088551340709290862457398518625014774491498217211510248054244443985983103347 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/48.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3357073779 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/48.i2c_host_error_intr.3357073779 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 48.i2c_host_error_intr.3357073779 -covoverwrite' seed=90088551340709290862457398518625014774491498217211510248054244443985983103347 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90088551340709290862457398518625014774491498217211510248054244443985983103347 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/48.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 112226991423359384271631138713634646336200260138522091953100385945615286796542 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/48.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4118413566 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/48.i2c_target_fifo_reset_tx.4118413566 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 48.i2c_target_fifo_reset_tx.4118413566 -covoverwrite' seed=112226991423359384271631138713634646336200260138522091953100385945615286796542 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112226991423359384271631138713634646336200260138522091953100385945615286796542 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/48.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 74584325266985867718369186771089778129678374109604437767513310038680819237986 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/48.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2191557730 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/48.i2c_target_hrst.2191557730 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 48.i2c_target_hrst.2191557730 -covoverwrite' seed=74584325266985867718369186771089778129678374109604437767513310038680819237986 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74584325266985867718369186771089778129678374109604437767513310038680819237986 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/48.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 48876467242865111096740605195423408206975972838934420864463898907620129016738 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/48.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4119497634 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/48.i2c_host_mode_toggle.4119497634 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 48.i2c_host_mode_toggle.4119497634 -covoverwrite' seed=48876467242865111096740605195423408206975972838934420864463898907620129016738 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48876467242865111096740605195423408206975972838934420864463898907620129016738 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/48.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 82984117109703029278909594304655538295629214258949720842397544621938225984399 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/48.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2502701967 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/48.i2c_host_may_nack.2502701967 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 48.i2c_host_may_nack.2502701967 -covoverwrite' seed=82984117109703029278909594304655538295629214258949720842397544621938225984399 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82984117109703029278909594304655538295629214258949720842397544621938225984399 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/48.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 39587439589983634316453190653007122702594179395458516037064980772385143490861 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/48.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=270371117 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/48.i2c_target_nack_acqfull.270371117 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 48.i2c_target_nack_acqfull.270371117 -covoverwrite' seed=39587439589983634316453190653007122702594179395458516037064980772385143490861 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39587439589983634316453190653007122702594179395458516037064980772385143490861 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/48.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 57306946147425929780552091230899541842894837009087406347583476598510621522144 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/48.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1672444128 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/48.i2c_target_nack_acqfull_addr.1672444128 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 48.i2c_target_nack_acqfull_addr.1672444128 -covoverwrite' seed=57306946147425929780552091230899541842894837009087406347583476598510621522144 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57306946147425929780552091230899541842894837009087406347583476598510621522144 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/48.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_override 32853366084327689499463337142658548969525670624863128758588895414846813118836 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/49.i2c_host_override/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1582834036 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_override_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/49.i2c_host_override.1582834036 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 49.i2c_host_override.1582834036 -covoverwrite' seed=32853366084327689499463337142658548969525670624863128758588895414846813118836 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32853366084327689499463337142658548969525670624863128758588895414846813118836 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/49.i2c_host_override/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_override_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_error_intr 45819333001533604443441079342769667151168019260435374174350692957537466227776 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/49.i2c_host_error_intr/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=311598144 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_error_intr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/49.i2c_host_error_intr.311598144 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 49.i2c_host_error_intr.311598144 -covoverwrite' seed=45819333001533604443441079342769667151168019260435374174350692957537466227776 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45819333001533604443441079342769667151168019260435374174350692957537466227776 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/49.i2c_host_error_intr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_error_intr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_fifo_reset_tx 8639195156666821057249787278641192357869085877247848461540847923989964580889 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/49.i2c_target_fifo_reset_tx/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3211716633 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_fifo_reset_tx_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/49.i2c_target_fifo_reset_tx.3211716633 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 49.i2c_target_fifo_reset_tx.3211716633 -covoverwrite' seed=8639195156666821057249787278641192357869085877247848461540847923989964580889 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8639195156666821057249787278641192357869085877247848461540847923989964580889 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/49.i2c_target_fifo_reset_tx/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_fifo_reset_tx_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_hrst 47244483088442879718384958434244029312625885495622119570568200332584391673048 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/49.i2c_target_hrst/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=4005168344 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_hrst_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/49.i2c_target_hrst.4005168344 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 49.i2c_target_hrst.4005168344 -covoverwrite' seed=47244483088442879718384958434244029312625885495622119570568200332584391673048 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47244483088442879718384958434244029312625885495622119570568200332584391673048 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/49.i2c_target_hrst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_hrst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_mode_toggle 62010261254688107571570407857178313712000005962219594558959877992680028920912 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/49.i2c_host_mode_toggle/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=2866830416 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_mode_toggle_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/49.i2c_host_mode_toggle.2866830416 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 49.i2c_host_mode_toggle.2866830416 -covoverwrite' seed=62010261254688107571570407857178313712000005962219594558959877992680028920912 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62010261254688107571570407857178313712000005962219594558959877992680028920912 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/49.i2c_host_mode_toggle/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_mode_toggle_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_host_may_nack 45983719778542763430937186014272332198320275790765293500992560936981109910662 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/49.i2c_host_may_nack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=3715083398 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_host_may_nack_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/49.i2c_host_may_nack.3715083398 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 49.i2c_host_may_nack.3715083398 -covoverwrite' seed=45983719778542763430937186014272332198320275790765293500992560936981109910662 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45983719778542763430937186014272332198320275790765293500992560936981109910662 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/49.i2c_host_may_nack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_host_may_nack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull 282032995126508467761392626414435322677960365968633384393929635946644805447 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/49.i2c_target_nack_acqfull/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=1404475207 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/49.i2c_target_nack_acqfull.1404475207 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 49.i2c_target_nack_acqfull.1404475207 -covoverwrite' seed=282032995126508467761392626414435322677960365968633384393929635946644805447 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=282032995126508467761392626414435322677960365968633384393929635946644805447 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/49.i2c_target_nack_acqfull/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
i2c_target_nack_acqfull_addr 99664598222330629003952495409404564794984563287443096378813224560940327533315 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/49.i2c_target_nack_acqfull_addr/latest run_opts='+i2c_agent_mode=Host +test_timeout_ns=20_000_000 +use_intr_handler=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/i2c-sim-xcelium/default/xcelium.d -r tb +SVSEED=796556035 +UVM_TESTNAME=i2c_base_test +UVM_TEST_SEQ=i2c_target_nack_acqfull_addr_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage/default/49.i2c_target_nack_acqfull_addr.796556035 -covworkdir /nightly/current_run/scratch/master/i2c-sim-xcelium/coverage -covscope default -covtest 49.i2c_target_nack_acqfull_addr.796556035 -covoverwrite' seed=99664598222330629003952495409404564794984563287443096378813224560940327533315 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99664598222330629003952495409404564794984563287443096378813224560940327533315 --run-dir=/nightly/current_run/scratch/master/i2c-sim-xcelium/49.i2c_target_nack_acqfull_addr/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=i2c_base_test uvm_test_seq=i2c_target_nack_acqfull_addr_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
Job cancelled because all of its dependencies failed or were killed. 1 test run
i2c None None
Job cancelled because one of its dependencies failed or was killed. 1 test run
i2c None None