Simulation Results: kmac/masked

 
28/08/2026 21:54:34 DVSim: v1.49.0 sha: a099412 json Branch: master Tool: vcs [unknown]
Validation stages
V1
0.00%
V2
0.71%
V2S
0.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 0 20 0.00
kmac_smoke 1.486s 0.000us 0 20 0.00
csr_hw_reset 0 1 0.00
kmac_csr_hw_reset 0.801s 0.000us 0 1 0.00
csr_rw 0 5 0.00
kmac_csr_rw 1.478s 0.000us 0 5 0.00
csr_bit_bash 0 1 0.00
kmac_csr_bit_bash 0.818s 0.000us 0 1 0.00
csr_aliasing 0 1 0.00
kmac_csr_aliasing 0.805s 0.000us 0 1 0.00
csr_mem_rw_with_rand_reset 0 5 0.00
kmac_csr_mem_rw_with_rand_reset 0.822s 0.000us 0 5 0.00
regwen_csr_and_corresponding_lockable_csr 0 6 0.00
kmac_csr_rw 1.478s 0.000us 0 5 0.00
kmac_csr_aliasing 0.805s 0.000us 0 1 0.00
mem_walk 0 1 0.00
kmac_mem_walk 0.701s 0.000us 0 1 0.00
mem_partial_access 0 1 0.00
kmac_mem_partial_access 0.848s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 0 20 0.00
kmac_long_msg_and_output 1.859s 0.000us 0 20 0.00
burst_write 0 20 0.00
kmac_burst_write 1.507s 0.000us 0 20 0.00
test_vectors 0 40 0.00
kmac_test_vectors_sha3_224 1.460s 0.000us 0 5 0.00
kmac_test_vectors_sha3_256 1.357s 0.000us 0 5 0.00
kmac_test_vectors_sha3_384 1.490s 0.000us 0 5 0.00
kmac_test_vectors_sha3_512 0.827s 0.000us 0 5 0.00
kmac_test_vectors_shake_128 0.907s 0.000us 0 5 0.00
kmac_test_vectors_shake_256 0.918s 0.000us 0 5 0.00
kmac_test_vectors_kmac 0.846s 0.000us 0 5 0.00
kmac_test_vectors_kmac_xof 0.840s 0.000us 0 5 0.00
sideload 0 20 0.00
kmac_sideload 1.478s 0.000us 0 20 0.00
app 0 25 0.00
kmac_app 1.547s 0.000us 0 25 0.00
app_with_partial_data 0 10 0.00
kmac_app_with_partial_data 0.848s 0.000us 0 10 0.00
entropy_refresh 0 20 0.00
kmac_entropy_refresh 1.552s 0.000us 0 20 0.00
error 0 20 0.00
kmac_error 1.499s 0.000us 0 20 0.00
key_error 0 20 0.00
kmac_key_error 1.952s 0.000us 0 20 0.00
sideload_invalid 0 50 0.00
kmac_sideload_invalid 1.548s 0.000us 0 50 0.00
edn_timeout_error 0 20 0.00
kmac_edn_timeout_error 0.836s 0.000us 0 20 0.00
entropy_mode_error 0 20 0.00
kmac_entropy_mode_error 0.855s 0.000us 0 20 0.00
entropy_ready_error 0 10 0.00
kmac_entropy_ready_error 0.829s 0.000us 0 10 0.00
lc_escalation 0 50 0.00
kmac_lc_escalation 2.035s 0.000us 0 50 0.00
stress_all 3 20 15.00
kmac_stress_all 3423.880s 248563.171us 3 20 15.00
intr_test 0 10 0.00
kmac_intr_test 0.876s 0.000us 0 10 0.00
alert_test 0 10 0.00
kmac_alert_test 1.493s 0.000us 0 10 0.00
tl_d_oob_addr_access 0 25 0.00
kmac_tl_errors 1.498s 0.000us 0 25 0.00
tl_d_illegal_access 0 25 0.00
kmac_tl_errors 1.498s 0.000us 0 25 0.00
tl_d_outstanding_access 0 12 0.00
kmac_csr_hw_reset 0.801s 0.000us 0 1 0.00
kmac_csr_rw 1.478s 0.000us 0 5 0.00
kmac_csr_aliasing 0.805s 0.000us 0 1 0.00
kmac_same_csr_outstanding 0.843s 0.000us 0 5 0.00
tl_d_partial_access 0 12 0.00
kmac_csr_hw_reset 0.801s 0.000us 0 1 0.00
kmac_csr_rw 1.478s 0.000us 0 5 0.00
kmac_csr_aliasing 0.805s 0.000us 0 1 0.00
kmac_same_csr_outstanding 0.843s 0.000us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 0 20 0.00
kmac_shadow_reg_errors 1.500s 0.000us 0 20 0.00
shadow_reg_read_clear_staged_value 0 20 0.00
kmac_shadow_reg_errors 1.500s 0.000us 0 20 0.00
shadow_reg_storage_error 0 20 0.00
kmac_shadow_reg_errors 1.500s 0.000us 0 20 0.00
shadowed_reset_glitch 0 20 0.00
kmac_shadow_reg_errors 1.500s 0.000us 0 20 0.00
shadow_reg_update_error_with_csr_rw 0 20 0.00
kmac_shadow_reg_errors_with_csr_rw 0.851s 0.000us 0 20 0.00
tl_intg_err 0 30 0.00
kmac_sec_cm 0.844s 0.000us 0 5 0.00
kmac_tl_intg_err 1.530s 0.000us 0 25 0.00
sec_cm_bus_integrity 0 25 0.00
kmac_tl_intg_err 1.530s 0.000us 0 25 0.00
sec_cm_lc_escalate_en_intersig_mubi 0 50 0.00
kmac_lc_escalation 2.035s 0.000us 0 50 0.00
sec_cm_sw_key_key_masking 0 20 0.00
kmac_smoke 1.486s 0.000us 0 20 0.00
sec_cm_key_sideload 0 20 0.00
kmac_sideload 1.478s 0.000us 0 20 0.00
sec_cm_cfg_shadowed_config_shadow 0 20 0.00
kmac_shadow_reg_errors 1.500s 0.000us 0 20 0.00
sec_cm_fsm_sparse 0 5 0.00
kmac_sec_cm 0.844s 0.000us 0 5 0.00
sec_cm_ctr_redun 0 5 0.00
kmac_sec_cm 0.844s 0.000us 0 5 0.00
sec_cm_packer_ctr_redun 0 5 0.00
kmac_sec_cm 0.844s 0.000us 0 5 0.00
sec_cm_cfg_shadowed_config_regwen 0 20 0.00
kmac_smoke 1.486s 0.000us 0 20 0.00
sec_cm_fsm_global_esc 0 50 0.00
kmac_lc_escalation 2.035s 0.000us 0 50 0.00
sec_cm_fsm_local_esc 0 5 0.00
kmac_sec_cm 0.844s 0.000us 0 5 0.00
sec_cm_absorbed_ctrl_mubi 0 10 0.00
kmac_mubi 0.843s 0.000us 0 10 0.00
sec_cm_sw_cmd_ctrl_sparse 0 20 0.00
kmac_smoke 1.486s 0.000us 0 20 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
kmac_stress_all_with_rand_reset 1.540s 0.000us 0 10 0.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 520 test runs
kmac_smoke 71550725331629087030612663126059284550607238255620465413345182199564616545227 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3054973899 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.3054973899 +enable_masking=1 +sw_key_masked=0' seed=71550725331629087030612663126059284550607238255620465413345182199564616545227 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71550725331629087030612663126059284550607238255620465413345182199564616545227 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_long_msg_and_output 77130009153297628127518229947736168192591489558970399007699997789475204536344 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_long_msg_and_output/latest run_opts='+test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1637652504 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_and_output.1637652504 +enable_masking=1 +sw_key_masked=0' seed=77130009153297628127518229947736168192591489558970399007699997789475204536344 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77130009153297628127518229947736168192591489558970399007699997789475204536344 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_long_msg_and_output/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_long_msg_and_output_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload 115151074150943089542496988823674920976908603980596645442013475143949106623642 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_sideload/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=620835994 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.620835994 +enable_masking=1 +sw_key_masked=0' seed=115151074150943089542496988823674920976908603980596645442013475143949106623642 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115151074150943089542496988823674920976908603980596645442013475143949106623642 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_sideload/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 78046417291568069350370030310221547091163834604352419737714975667041191297723 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2076934843 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload_invalid.2076934843 +enable_masking=1 +sw_key_masked=0' seed=78046417291568069350370030310221547091163834604352419737714975667041191297723 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78046417291568069350370030310221547091163834604352419737714975667041191297723 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_burst_write 16578657597150061200637725043220955155339196022879066003187793209077745021143 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_burst_write/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2609344727 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.2609344727 +enable_masking=1 +sw_key_masked=0' seed=16578657597150061200637725043220955155339196022879066003187793209077745021143 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16578657597150061200637725043220955155339196022879066003187793209077745021143 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_burst_write/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_burst_write_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_sha3_224 99621805068092851885501259643719310059942087826152012505248158592892760216459 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_224/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1801442187 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.1801442187 +enable_masking=1 +sw_key_masked=0' seed=99621805068092851885501259643719310059942087826152012505248158592892760216459 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99621805068092851885501259643719310059942087826152012505248158592892760216459 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_224/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_sha3_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_sha3_256 46315033256777363476694844402352163607593361909607350624087641427382830518112 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_256/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1708019552 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.1708019552 +enable_masking=1 +sw_key_masked=0' seed=46315033256777363476694844402352163607593361909607350624087641427382830518112 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46315033256777363476694844402352163607593361909607350624087641427382830518112 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_256/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_sha3_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_sha3_384 10125358018436466992082621911041112573593579324464060854633546507837888978590 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_384/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1952112286 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.1952112286 +enable_masking=1 +sw_key_masked=0' seed=10125358018436466992082621911041112573593579324464060854633546507837888978590 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10125358018436466992082621911041112573593579324464060854633546507837888978590 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_384/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_sha3_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_sha3_512 36525595598156661534118043071675176823196619504874926066733881841534918768987 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_512/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1234745691 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.1234745691 +enable_masking=1 +sw_key_masked=0' seed=36525595598156661534118043071675176823196619504874926066733881841534918768987 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36525595598156661534118043071675176823196619504874926066733881841534918768987 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_test_vectors_sha3_512/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_sha3_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_shake_128 28709068992163821943569494155903718787166724330692690373974263461720229498843 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_128/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3049869275 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.3049869275 +enable_masking=1 +sw_key_masked=0' seed=28709068992163821943569494155903718787166724330692690373974263461720229498843 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28709068992163821943569494155903718787166724330692690373974263461720229498843 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_128/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_shake_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_shake_256 51335805316664885198277695014884142505968265405235040287565597441304899932389 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_256/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4123578597 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.4123578597 +enable_masking=1 +sw_key_masked=0' seed=51335805316664885198277695014884142505968265405235040287565597441304899932389 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51335805316664885198277695014884142505968265405235040287565597441304899932389 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_test_vectors_shake_256/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_shake_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_kmac 81939215993666921267356219053603899412775959765861168950154316261191208434764 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_test_vectors_kmac/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3189800012 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac.3189800012 +enable_masking=1 +sw_key_masked=0' seed=81939215993666921267356219053603899412775959765861168950154316261191208434764 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81939215993666921267356219053603899412775959765861168950154316261191208434764 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_test_vectors_kmac/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_kmac_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_kmac_xof 104727079220330285487294999980600399049458152007225128293620568536458180094513 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_test_vectors_kmac_xof/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3674139185 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac_xof.3674139185 +enable_masking=1 +sw_key_masked=0' seed=104727079220330285487294999980600399049458152007225128293620568536458180094513 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104727079220330285487294999980600399049458152007225128293620568536458180094513 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_test_vectors_kmac_xof/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_kmac_xof_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_app 7785189397061960224516768806278799022612716407379518171166987825975794278741 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_app/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=14098773 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.14098773 +enable_masking=1 +sw_key_masked=0' seed=7785189397061960224516768806278799022612716407379518171166987825975794278741 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7785189397061960224516768806278799022612716407379518171166987825975794278741 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_app/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_app_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_app_with_partial_data 41465659532556685535508074519627861574632535666770478391084195303383022531545 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_app_with_partial_data/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1101886425 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.1101886425 +enable_masking=1 +sw_key_masked=0' seed=41465659532556685535508074519627861574632535666770478391084195303383022531545 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41465659532556685535508074519627861574632535666770478391084195303383022531545 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_app_with_partial_data/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_app_with_partial_data_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_refresh 77594982420596060900136482760463127584840500534310562958486154215754290101289 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_entropy_refresh/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=433257513 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.433257513 +enable_masking=1 +sw_key_masked=0' seed=77594982420596060900136482760463127584840500534310562958486154215754290101289 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77594982420596060900136482760463127584840500534310562958486154215754290101289 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_entropy_refresh/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_refresh_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_mubi 99104116021901014380023499587834955838076013211346111444017922815935740960174 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_mubi/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2769083822 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.2769083822 +enable_masking=1 +sw_key_masked=0' seed=99104116021901014380023499587834955838076013211346111444017922815935740960174 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99104116021901014380023499587834955838076013211346111444017922815935740960174 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_mubi_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_error 94622326830450872870613945745094870840022103297028008527436763762684744186935 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2257599543 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.2257599543 +enable_masking=1 +sw_key_masked=0' seed=94622326830450872870613945745094870840022103297028008527436763762684744186935 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94622326830450872870613945745094870840022103297028008527436763762684744186935 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_key_error 4110250948987858479530393262730062457124607757208715168622178472533215389928 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_key_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=24094952 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.24094952 +enable_masking=1 +sw_key_masked=0' seed=4110250948987858479530393262730062457124607757208715168622178472533215389928 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4110250948987858479530393262730062457124607757208715168622178472533215389928 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_key_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_key_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_edn_timeout_error 7672405194420578757476026423562568813576498925738538456414257376088129599340 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_edn_timeout_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3982292844 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.3982292844 +enable_masking=1 +sw_key_masked=0' seed=7672405194420578757476026423562568813576498925738538456414257376088129599340 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7672405194420578757476026423562568813576498925738538456414257376088129599340 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_edn_timeout_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_edn_timeout_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_mode_error 74410037002987024914079526479279049016441878642408053806747567518196354213642 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_entropy_mode_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3805243146 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.3805243146 +enable_masking=1 +sw_key_masked=0' seed=74410037002987024914079526479279049016441878642408053806747567518196354213642 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74410037002987024914079526479279049016441878642408053806747567518196354213642 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_entropy_mode_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_mode_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_ready_error 104837495030239361386506147918708767747324553733140888226580267480478348222938 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_entropy_ready_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1344020954 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.1344020954 +enable_masking=1 +sw_key_masked=0' seed=104837495030239361386506147918708767747324553733140888226580267480478348222938 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104837495030239361386506147918708767747324553733140888226580267480478348222938 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_entropy_ready_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_ready_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 89280055427865550146269939661132214468407096779302392156007677196954602861221 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=122712741 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.122712741 +enable_masking=1 +sw_key_masked=0' seed=89280055427865550146269939661132214468407096779302392156007677196954602861221 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89280055427865550146269939661132214468407096779302392156007677196954602861221 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_stress_all_with_rand_reset 68628812709113419299121657618946169158110883248916762630903114995639856320902 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2178339206 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all_with_rand_reset.2178339206 +enable_masking=1 +sw_key_masked=0' seed=68628812709113419299121657618946169158110883248916762630903114995639856320902 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68628812709113419299121657618946169158110883248916762630903114995639856320902 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sec_cm 49851918432725697312401529851466760346033929627839515339066874016297358461070 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=77334670 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.77334670 +enable_masking=1 +sw_key_masked=0' seed=49851918432725697312401529851466760346033929627839515339066874016297358461070 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49851918432725697312401529851466760346033929627839515339066874016297358461070 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors 63742353232031266563918419530498735166293227052237423044364443146971286648683 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2743383915 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors.2743383915 +enable_masking=1 +sw_key_masked=0' seed=63742353232031266563918419530498735166293227052237423044364443146971286648683 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63742353232031266563918419530498735166293227052237423044364443146971286648683 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors_with_csr_rw 24568205768739235101618644749505170963984123484626900681876258402438734117267 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2007464339 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors_with_csr_rw.2007464339 +enable_masking=1 +sw_key_masked=0' seed=24568205768739235101618644749505170963984123484626900681876258402438734117267 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24568205768739235101618644749505170963984123484626900681876258402438734117267 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_alert_test 12370430859548289868520778136339696656900410345481221310795396614772322779088 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1195687888 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.1195687888 +enable_masking=1 +sw_key_masked=0' seed=12370430859548289868520778136339696656900410345481221310795396614772322779088 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12370430859548289868520778136339696656900410345481221310795396614772322779088 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_mem_walk 58313946743546186060119601758675944055104331293211753757727443449338589919750 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_mem_walk/latest run_opts='+csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2745481734 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.2745481734 +enable_masking=1 +sw_key_masked=0' seed=58313946743546186060119601758675944055104331293211753757727443449338589919750 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58313946743546186060119601758675944055104331293211753757727443449338589919750 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_mem_walk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_mem_partial_access 111264364856516882551592092402239271220871417154895442022403121439688448527962 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_mem_partial_access/latest run_opts='+run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=164089434 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partial_access.164089434 +enable_masking=1 +sw_key_masked=0' seed=111264364856516882551592092402239271220871417154895442022403121439688448527962 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111264364856516882551592092402239271220871417154895442022403121439688448527962 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_mem_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_errors 5737398850334879162886951685878037173592378100743633897353544014755960803644 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=438391100 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.438391100 +enable_masking=1 +sw_key_masked=0' seed=5737398850334879162886951685878037173592378100743633897353544014755960803644 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5737398850334879162886951685878037173592378100743633897353544014755960803644 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_intg_err 107383581766127556822337404254972832405285961245955999703565031434252625631657 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=228317609 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.228317609 +enable_masking=1 +sw_key_masked=0' seed=107383581766127556822337404254972832405285961245955999703565031434252625631657 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107383581766127556822337404254972832405285961245955999703565031434252625631657 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_intr_test 104276680235484786447675960508590084486232273060942859943823699240219438448056 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2032631224 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.2032631224 +enable_masking=1 +sw_key_masked=0' seed=104276680235484786447675960508590084486232273060942859943823699240219438448056 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104276680235484786447675960508590084486232273060942859943823699240219438448056 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_csr_hw_reset 6453236152255642263825455567076291058493836651670525720934577980521423223625 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_csr_hw_reset/latest run_opts='+csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3361651529 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.3361651529 +enable_masking=1 +sw_key_masked=0' seed=6453236152255642263825455567076291058493836651670525720934577980521423223625 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6453236152255642263825455567076291058493836651670525720934577980521423223625 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_csr_rw 95635868203132073245501363848218620294053722816727195188886339025596746680492 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=879872172 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.879872172 +enable_masking=1 +sw_key_masked=0' seed=95635868203132073245501363848218620294053722816727195188886339025596746680492 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95635868203132073245501363848218620294053722816727195188886339025596746680492 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_csr_bit_bash 61738597992284279421318443057656345329348011240928048512862577603882398072157 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_csr_bit_bash/latest run_opts='+csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3388030301 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.3388030301 +enable_masking=1 +sw_key_masked=0' seed=61738597992284279421318443057656345329348011240928048512862577603882398072157 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61738597992284279421318443057656345329348011240928048512862577603882398072157 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_csr_aliasing 46921115687444061363550472993377199750739851724973492353127363373207760456351 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_csr_aliasing/latest run_opts='+csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=313576095 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.313576095 +enable_masking=1 +sw_key_masked=0' seed=46921115687444061363550472993377199750739851724973492353127363373207760456351 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46921115687444061363550472993377199750739851724973492353127363373207760456351 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_same_csr_outstanding 114699431441594851986755731547727469919248219566913463322965292546153120822450 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=962622642 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr_outstanding.962622642 +enable_masking=1 +sw_key_masked=0' seed=114699431441594851986755731547727469919248219566913463322965292546153120822450 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114699431441594851986755731547727469919248219566913463322965292546153120822450 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_csr_mem_rw_with_rand_reset 50047131561964965237689428062720009705698243300277053132916151609501502259007 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3941449535 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.3941449535 +enable_masking=1 +sw_key_masked=0' seed=50047131561964965237689428062720009705698243300277053132916151609501502259007 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50047131561964965237689428062720009705698243300277053132916151609501502259007 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/0.kmac_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_smoke 32174608270077985396104647544288810431204060902533129659228384703146380917829 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=66223173 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_smoke.66223173 +enable_masking=1 +sw_key_masked=0' seed=32174608270077985396104647544288810431204060902533129659228384703146380917829 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32174608270077985396104647544288810431204060902533129659228384703146380917829 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_long_msg_and_output 106306810270295960176786953885308933950615779818595839634049127214712861604122 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_long_msg_and_output/latest run_opts='+test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1001765146 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_long_msg_and_output.1001765146 +enable_masking=1 +sw_key_masked=0' seed=106306810270295960176786953885308933950615779818595839634049127214712861604122 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106306810270295960176786953885308933950615779818595839634049127214712861604122 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_long_msg_and_output/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_long_msg_and_output_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload 72520531703712596712289816324503658821246380225431033287510418353281292545723 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_sideload/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1772596923 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload.1772596923 +enable_masking=1 +sw_key_masked=0' seed=72520531703712596712289816324503658821246380225431033287510418353281292545723 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72520531703712596712289816324503658821246380225431033287510418353281292545723 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_sideload/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 17781156089729343579611829929504196101026019894644601204080924967053295895712 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=811877536 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sideload_invalid.811877536 +enable_masking=1 +sw_key_masked=0' seed=17781156089729343579611829929504196101026019894644601204080924967053295895712 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17781156089729343579611829929504196101026019894644601204080924967053295895712 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_burst_write 14160574995404107914266603114062818605979875739827761129783695368161476993090 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_burst_write/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2540691522 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_burst_write.2540691522 +enable_masking=1 +sw_key_masked=0' seed=14160574995404107914266603114062818605979875739827761129783695368161476993090 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=14160574995404107914266603114062818605979875739827761129783695368161476993090 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_burst_write/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_burst_write_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_sha3_224 56694432482428995582762825841067277425396973858649740647193091461858336130795 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_224/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1029916395 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_224.1029916395 +enable_masking=1 +sw_key_masked=0' seed=56694432482428995582762825841067277425396973858649740647193091461858336130795 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56694432482428995582762825841067277425396973858649740647193091461858336130795 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_224/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_sha3_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_sha3_256 110292702798579003881577973708106437521283753131831178750883746115618633686222 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_256/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=448011470 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_256.448011470 +enable_masking=1 +sw_key_masked=0' seed=110292702798579003881577973708106437521283753131831178750883746115618633686222 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110292702798579003881577973708106437521283753131831178750883746115618633686222 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_256/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_sha3_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_sha3_384 45708960654810386241313915636342725334890253558060931641200381695908701807242 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_384/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2988712586 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_384.2988712586 +enable_masking=1 +sw_key_masked=0' seed=45708960654810386241313915636342725334890253558060931641200381695908701807242 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45708960654810386241313915636342725334890253558060931641200381695908701807242 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_384/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_sha3_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_sha3_512 22592358730081509151062135249339960453769991224563944964263465577693638756017 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_512/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1189807793 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_sha3_512.1189807793 +enable_masking=1 +sw_key_masked=0' seed=22592358730081509151062135249339960453769991224563944964263465577693638756017 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22592358730081509151062135249339960453769991224563944964263465577693638756017 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_test_vectors_sha3_512/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_sha3_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_shake_128 678858348709525083105857488045677453751001646780071671934946211832779514725 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_128/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1380983653 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_128.1380983653 +enable_masking=1 +sw_key_masked=0' seed=678858348709525083105857488045677453751001646780071671934946211832779514725 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=678858348709525083105857488045677453751001646780071671934946211832779514725 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_128/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_shake_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_shake_256 80764998909083275192921375793182874801013188375978847944756857016078180564858 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_256/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=454049658 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_shake_256.454049658 +enable_masking=1 +sw_key_masked=0' seed=80764998909083275192921375793182874801013188375978847944756857016078180564858 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80764998909083275192921375793182874801013188375978847944756857016078180564858 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_test_vectors_shake_256/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_shake_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_kmac 86545882489754828280650139125084122571235820472472659592450336529525109644506 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_test_vectors_kmac/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=861887706 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac.861887706 +enable_masking=1 +sw_key_masked=0' seed=86545882489754828280650139125084122571235820472472659592450336529525109644506 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86545882489754828280650139125084122571235820472472659592450336529525109644506 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_test_vectors_kmac/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_kmac_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_kmac_xof 34360873530547346786525913511918965237091301875376924264694448801026205645749 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_test_vectors_kmac_xof/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3353967541 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_test_vectors_kmac_xof.3353967541 +enable_masking=1 +sw_key_masked=0' seed=34360873530547346786525913511918965237091301875376924264694448801026205645749 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34360873530547346786525913511918965237091301875376924264694448801026205645749 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_test_vectors_kmac_xof/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_kmac_xof_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_app 34475143511465657188775918363258880708132082950677959300599165740738428548438 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_app/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2220111190 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app.2220111190 +enable_masking=1 +sw_key_masked=0' seed=34475143511465657188775918363258880708132082950677959300599165740738428548438 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34475143511465657188775918363258880708132082950677959300599165740738428548438 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_app/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_app_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_app_with_partial_data 2445371626040573175513372303258190309877348937838263724920334993554962067533 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_app_with_partial_data/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1215246413 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_app_with_partial_data.1215246413 +enable_masking=1 +sw_key_masked=0' seed=2445371626040573175513372303258190309877348937838263724920334993554962067533 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2445371626040573175513372303258190309877348937838263724920334993554962067533 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_app_with_partial_data/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_app_with_partial_data_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_refresh 4819396730474076200199926826670454837768437141064354097709373096195698280229 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_entropy_refresh/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=943277861 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_refresh.943277861 +enable_masking=1 +sw_key_masked=0' seed=4819396730474076200199926826670454837768437141064354097709373096195698280229 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4819396730474076200199926826670454837768437141064354097709373096195698280229 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_entropy_refresh/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_refresh_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_mubi 31190504758862549194847540478617388699565711783962366963985536047950975724526 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_mubi/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3055545326 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_mubi.3055545326 +enable_masking=1 +sw_key_masked=0' seed=31190504758862549194847540478617388699565711783962366963985536047950975724526 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31190504758862549194847540478617388699565711783962366963985536047950975724526 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_mubi_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_error 59369947910792209968091107053984658549597155171075901698101949011998743733360 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3899139184 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_error.3899139184 +enable_masking=1 +sw_key_masked=0' seed=59369947910792209968091107053984658549597155171075901698101949011998743733360 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=59369947910792209968091107053984658549597155171075901698101949011998743733360 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_key_error 32853870031863858316735055241348313488252060620704117819273600119801952827882 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_key_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=311917034 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_key_error.311917034 +enable_masking=1 +sw_key_masked=0' seed=32853870031863858316735055241348313488252060620704117819273600119801952827882 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32853870031863858316735055241348313488252060620704117819273600119801952827882 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_key_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_key_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_edn_timeout_error 77149096995915568016946224729488637391706751833755704318581518765361063597522 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_edn_timeout_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2494371282 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_edn_timeout_error.2494371282 +enable_masking=1 +sw_key_masked=0' seed=77149096995915568016946224729488637391706751833755704318581518765361063597522 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77149096995915568016946224729488637391706751833755704318581518765361063597522 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_edn_timeout_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_edn_timeout_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_mode_error 47819507191851624710053946733523493214086423174243527367343324639351262818982 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_entropy_mode_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2977837734 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_mode_error.2977837734 +enable_masking=1 +sw_key_masked=0' seed=47819507191851624710053946733523493214086423174243527367343324639351262818982 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47819507191851624710053946733523493214086423174243527367343324639351262818982 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_entropy_mode_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_mode_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_ready_error 17097737773956708198763544954155141330594715085620525618243828022771701650212 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_entropy_ready_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2221019940 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_entropy_ready_error.2221019940 +enable_masking=1 +sw_key_masked=0' seed=17097737773956708198763544954155141330594715085620525618243828022771701650212 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17097737773956708198763544954155141330594715085620525618243828022771701650212 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_entropy_ready_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_ready_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 88178741612066657525295013949424038456670624104381731560971257344298519726578 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2475264498 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_lc_escalation.2475264498 +enable_masking=1 +sw_key_masked=0' seed=88178741612066657525295013949424038456670624104381731560971257344298519726578 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88178741612066657525295013949424038456670624104381731560971257344298519726578 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_stress_all_with_rand_reset 61659347999231341673565066415488129303406455631185670952778692422530306421720 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3360437208 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_stress_all_with_rand_reset.3360437208 +enable_masking=1 +sw_key_masked=0' seed=61659347999231341673565066415488129303406455631185670952778692422530306421720 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61659347999231341673565066415488129303406455631185670952778692422530306421720 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sec_cm 44867719489865719262831958078715105072082837428426262228398282527104005451555 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3550621475 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_sec_cm.3550621475 +enable_masking=1 +sw_key_masked=0' seed=44867719489865719262831958078715105072082837428426262228398282527104005451555 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44867719489865719262831958078715105072082837428426262228398282527104005451555 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors 108978992736899475847993990476793418844617229150206112288235086926824672017358 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1188248526 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors.1188248526 +enable_masking=1 +sw_key_masked=0' seed=108978992736899475847993990476793418844617229150206112288235086926824672017358 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108978992736899475847993990476793418844617229150206112288235086926824672017358 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors_with_csr_rw 49608444024808176923586600239971684601314549884765181917345766826436286257875 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3776748243 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_shadow_reg_errors_with_csr_rw.3776748243 +enable_masking=1 +sw_key_masked=0' seed=49608444024808176923586600239971684601314549884765181917345766826436286257875 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49608444024808176923586600239971684601314549884765181917345766826436286257875 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_alert_test 84129504438222438038024780042649974366543160187986897134284541671091924714521 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2801091609 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.kmac_alert_test.2801091609 +enable_masking=1 +sw_key_masked=0' seed=84129504438222438038024780042649974366543160187986897134284541671091924714521 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84129504438222438038024780042649974366543160187986897134284541671091924714521 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_errors 41810919347619266843588224855955899325503889111556538340114642964286457241134 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3667123758 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_errors.3667123758 +enable_masking=1 +sw_key_masked=0' seed=41810919347619266843588224855955899325503889111556538340114642964286457241134 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41810919347619266843588224855955899325503889111556538340114642964286457241134 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_intg_err 64243608799949701074978954301303519695159009658593191020083730958216397263502 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3002012302 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_tl_intg_err.3002012302 +enable_masking=1 +sw_key_masked=0' seed=64243608799949701074978954301303519695159009658593191020083730958216397263502 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64243608799949701074978954301303519695159009658593191020083730958216397263502 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_intr_test 96227404721027715113708421321738881640889166416833470857630765867838402770961 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2023536657 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_intr_test.2023536657 +enable_masking=1 +sw_key_masked=0' seed=96227404721027715113708421321738881640889166416833470857630765867838402770961 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96227404721027715113708421321738881640889166416833470857630765867838402770961 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_csr_rw 38144490774994156713043407582473901386110059577487207237814959459465817000943 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=494963695 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_rw.494963695 +enable_masking=1 +sw_key_masked=0' seed=38144490774994156713043407582473901386110059577487207237814959459465817000943 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38144490774994156713043407582473901386110059577487207237814959459465817000943 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_same_csr_outstanding 35494222343682669156600682695257025173541388206541765930827382991251147815354 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3943397818 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_same_csr_outstanding.3943397818 +enable_masking=1 +sw_key_masked=0' seed=35494222343682669156600682695257025173541388206541765930827382991251147815354 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35494222343682669156600682695257025173541388206541765930827382991251147815354 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_csr_mem_rw_with_rand_reset 65862297295554840292017124390613790856987506192642349251430083095589606300135 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1522178535 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.kmac_csr_mem_rw_with_rand_reset.1522178535 +enable_masking=1 +sw_key_masked=0' seed=65862297295554840292017124390613790856987506192642349251430083095589606300135 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65862297295554840292017124390613790856987506192642349251430083095589606300135 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/1.kmac_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_smoke 71241930078874094857252164901210333223643810218576626175342770135781519186066 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3074218130 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_smoke.3074218130 +enable_masking=1 +sw_key_masked=0' seed=71241930078874094857252164901210333223643810218576626175342770135781519186066 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71241930078874094857252164901210333223643810218576626175342770135781519186066 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_long_msg_and_output 61691136025312721313410367696542270663883000092620964395552546613834722255964 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_long_msg_and_output/latest run_opts='+test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2356094044 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_long_msg_and_output.2356094044 +enable_masking=1 +sw_key_masked=0' seed=61691136025312721313410367696542270663883000092620964395552546613834722255964 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61691136025312721313410367696542270663883000092620964395552546613834722255964 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_long_msg_and_output/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_long_msg_and_output_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload 68308996449792129248140041942956932598932211827244205634014293459389172227826 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_sideload/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3293912818 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload.3293912818 +enable_masking=1 +sw_key_masked=0' seed=68308996449792129248140041942956932598932211827244205634014293459389172227826 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68308996449792129248140041942956932598932211827244205634014293459389172227826 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_sideload/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 95222743763180501157313618954461027309263435534110239839377211279451924394245 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1743712517 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sideload_invalid.1743712517 +enable_masking=1 +sw_key_masked=0' seed=95222743763180501157313618954461027309263435534110239839377211279451924394245 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95222743763180501157313618954461027309263435534110239839377211279451924394245 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_burst_write 33986538021327103010753160647130012756870464140538034172164104264049062737911 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_burst_write/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1758099447 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_burst_write.1758099447 +enable_masking=1 +sw_key_masked=0' seed=33986538021327103010753160647130012756870464140538034172164104264049062737911 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33986538021327103010753160647130012756870464140538034172164104264049062737911 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_burst_write/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_burst_write_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_sha3_224 88653413064322219877144191943611589647498996894104032533166743808325967273359 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_224/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=943316367 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_224.943316367 +enable_masking=1 +sw_key_masked=0' seed=88653413064322219877144191943611589647498996894104032533166743808325967273359 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88653413064322219877144191943611589647498996894104032533166743808325967273359 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_224/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_sha3_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_sha3_256 70939676639676185659817279651266567013167950223802686601063483594405815230197 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_256/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2604113653 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_256.2604113653 +enable_masking=1 +sw_key_masked=0' seed=70939676639676185659817279651266567013167950223802686601063483594405815230197 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70939676639676185659817279651266567013167950223802686601063483594405815230197 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_256/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_sha3_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_sha3_384 115374266050903690933477453307150001591246243529501543360835058266565207402761 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_384/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3030657289 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_384.3030657289 +enable_masking=1 +sw_key_masked=0' seed=115374266050903690933477453307150001591246243529501543360835058266565207402761 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115374266050903690933477453307150001591246243529501543360835058266565207402761 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_384/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_sha3_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_sha3_512 59625052337409961709021454153489469222800838070452008835191722252500330650162 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_512/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3084163634 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_sha3_512.3084163634 +enable_masking=1 +sw_key_masked=0' seed=59625052337409961709021454153489469222800838070452008835191722252500330650162 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=59625052337409961709021454153489469222800838070452008835191722252500330650162 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_test_vectors_sha3_512/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_sha3_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_shake_128 46451970773692008419215212205275912925004829823254499619113761851691825203586 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_128/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3116992898 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_128.3116992898 +enable_masking=1 +sw_key_masked=0' seed=46451970773692008419215212205275912925004829823254499619113761851691825203586 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46451970773692008419215212205275912925004829823254499619113761851691825203586 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_128/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_shake_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_shake_256 18087721375964023658605617576800898645952973021323499417497876041554330872317 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_256/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1562601981 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_shake_256.1562601981 +enable_masking=1 +sw_key_masked=0' seed=18087721375964023658605617576800898645952973021323499417497876041554330872317 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18087721375964023658605617576800898645952973021323499417497876041554330872317 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_test_vectors_shake_256/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_shake_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_kmac 66871373940525594488046687552635544075134079423879721269180859589581660782160 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_test_vectors_kmac/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4243881552 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac.4243881552 +enable_masking=1 +sw_key_masked=0' seed=66871373940525594488046687552635544075134079423879721269180859589581660782160 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66871373940525594488046687552635544075134079423879721269180859589581660782160 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_test_vectors_kmac/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_kmac_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_kmac_xof 3192741185442746426682134101522233437419929224979342281198756891431254199594 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_test_vectors_kmac_xof/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1080659242 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_test_vectors_kmac_xof.1080659242 +enable_masking=1 +sw_key_masked=0' seed=3192741185442746426682134101522233437419929224979342281198756891431254199594 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3192741185442746426682134101522233437419929224979342281198756891431254199594 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_test_vectors_kmac_xof/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_kmac_xof_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_app 88054357842274251896760316857229264361679355608259874773278769470721920088419 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_app/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3604232547 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app.3604232547 +enable_masking=1 +sw_key_masked=0' seed=88054357842274251896760316857229264361679355608259874773278769470721920088419 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88054357842274251896760316857229264361679355608259874773278769470721920088419 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_app/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_app_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_app_with_partial_data 15119405016312217551599149280488577402801546969552519329697192073153352641827 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_app_with_partial_data/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2925341987 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_app_with_partial_data.2925341987 +enable_masking=1 +sw_key_masked=0' seed=15119405016312217551599149280488577402801546969552519329697192073153352641827 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15119405016312217551599149280488577402801546969552519329697192073153352641827 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_app_with_partial_data/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_app_with_partial_data_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_refresh 54197000112227398070076487923740251622479075468814761892311719247833639105580 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_entropy_refresh/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1719874604 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_refresh.1719874604 +enable_masking=1 +sw_key_masked=0' seed=54197000112227398070076487923740251622479075468814761892311719247833639105580 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54197000112227398070076487923740251622479075468814761892311719247833639105580 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_entropy_refresh/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_refresh_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_mubi 105095917464739165170296336631930236617706764639987651172978482019726169440646 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_mubi/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3415703942 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_mubi.3415703942 +enable_masking=1 +sw_key_masked=0' seed=105095917464739165170296336631930236617706764639987651172978482019726169440646 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105095917464739165170296336631930236617706764639987651172978482019726169440646 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_mubi_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_error 68136029972103133432552176673636512975872069242235221128333419342882361534103 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3092473495 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_error.3092473495 +enable_masking=1 +sw_key_masked=0' seed=68136029972103133432552176673636512975872069242235221128333419342882361534103 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68136029972103133432552176673636512975872069242235221128333419342882361534103 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_key_error 37566232576163117485210971613245353093486325268575340409541508235445217630553 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_key_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=778672473 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_key_error.778672473 +enable_masking=1 +sw_key_masked=0' seed=37566232576163117485210971613245353093486325268575340409541508235445217630553 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37566232576163117485210971613245353093486325268575340409541508235445217630553 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_key_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_key_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_edn_timeout_error 15110454850652201550236872989332040427957249569670974482597971476637728931229 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_edn_timeout_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1591770525 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_edn_timeout_error.1591770525 +enable_masking=1 +sw_key_masked=0' seed=15110454850652201550236872989332040427957249569670974482597971476637728931229 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15110454850652201550236872989332040427957249569670974482597971476637728931229 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_edn_timeout_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_edn_timeout_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_mode_error 65295494128310509229304357164185821845792491249349911803557766759075601147182 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_entropy_mode_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=351757614 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_mode_error.351757614 +enable_masking=1 +sw_key_masked=0' seed=65295494128310509229304357164185821845792491249349911803557766759075601147182 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65295494128310509229304357164185821845792491249349911803557766759075601147182 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_entropy_mode_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_mode_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_ready_error 48122016344029077233436693422338825693506117118502028819298249960086926362112 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_entropy_ready_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=227378688 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_entropy_ready_error.227378688 +enable_masking=1 +sw_key_masked=0' seed=48122016344029077233436693422338825693506117118502028819298249960086926362112 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48122016344029077233436693422338825693506117118502028819298249960086926362112 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_entropy_ready_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_ready_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 34553112587592143762703366453340134901283028862525435454700311154686220309581 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1049367629 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_lc_escalation.1049367629 +enable_masking=1 +sw_key_masked=0' seed=34553112587592143762703366453340134901283028862525435454700311154686220309581 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34553112587592143762703366453340134901283028862525435454700311154686220309581 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_stress_all_with_rand_reset 80732407472716042553230652969601332811038481216647901648145342512906918230851 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3850173251 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_stress_all_with_rand_reset.3850173251 +enable_masking=1 +sw_key_masked=0' seed=80732407472716042553230652969601332811038481216647901648145342512906918230851 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80732407472716042553230652969601332811038481216647901648145342512906918230851 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sec_cm 57893965815895388666382720672153059426888433500833866842394124053331156106967 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1424719575 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_sec_cm.1424719575 +enable_masking=1 +sw_key_masked=0' seed=57893965815895388666382720672153059426888433500833866842394124053331156106967 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57893965815895388666382720672153059426888433500833866842394124053331156106967 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors 37890554025740266344135987546050704046640345321745315186369958876426309812600 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=269828472 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors.269828472 +enable_masking=1 +sw_key_masked=0' seed=37890554025740266344135987546050704046640345321745315186369958876426309812600 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37890554025740266344135987546050704046640345321745315186369958876426309812600 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors_with_csr_rw 110993672839532152429525816003489592661177426582496631119468822052356292761041 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2445956561 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_shadow_reg_errors_with_csr_rw.2445956561 +enable_masking=1 +sw_key_masked=0' seed=110993672839532152429525816003489592661177426582496631119468822052356292761041 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110993672839532152429525816003489592661177426582496631119468822052356292761041 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_alert_test 20259064674045121830965812780976984426876945521749525063205535692754628698789 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3856196261 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.kmac_alert_test.3856196261 +enable_masking=1 +sw_key_masked=0' seed=20259064674045121830965812780976984426876945521749525063205535692754628698789 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20259064674045121830965812780976984426876945521749525063205535692754628698789 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_errors 48219990338309392973495242750130673269552563712250544018121772827025269159787 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=797013867 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_errors.797013867 +enable_masking=1 +sw_key_masked=0' seed=48219990338309392973495242750130673269552563712250544018121772827025269159787 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48219990338309392973495242750130673269552563712250544018121772827025269159787 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_intg_err 52298803004435658784712152414546438282328607608221168476008054384834125195306 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=198404138 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_tl_intg_err.198404138 +enable_masking=1 +sw_key_masked=0' seed=52298803004435658784712152414546438282328607608221168476008054384834125195306 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=52298803004435658784712152414546438282328607608221168476008054384834125195306 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_intr_test 464273942269801970527454853151285179796256105597274562526355370863642982850 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=799979970 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_intr_test.799979970 +enable_masking=1 +sw_key_masked=0' seed=464273942269801970527454853151285179796256105597274562526355370863642982850 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=464273942269801970527454853151285179796256105597274562526355370863642982850 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_csr_rw 54767583044596244696875538184734335274574994041803946616222830693162853886176 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2365090016 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_rw.2365090016 +enable_masking=1 +sw_key_masked=0' seed=54767583044596244696875538184734335274574994041803946616222830693162853886176 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54767583044596244696875538184734335274574994041803946616222830693162853886176 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_same_csr_outstanding 6778474508001578696904071798424134060209490896808207633058228404256821379942 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4132340582 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_same_csr_outstanding.4132340582 +enable_masking=1 +sw_key_masked=0' seed=6778474508001578696904071798424134060209490896808207633058228404256821379942 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6778474508001578696904071798424134060209490896808207633058228404256821379942 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_csr_mem_rw_with_rand_reset 62637503389748798781864892366452171258168700978345096869586747329112886652477 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3354570301 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.kmac_csr_mem_rw_with_rand_reset.3354570301 +enable_masking=1 +sw_key_masked=0' seed=62637503389748798781864892366452171258168700978345096869586747329112886652477 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62637503389748798781864892366452171258168700978345096869586747329112886652477 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/2.kmac_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_smoke 106670853471560715273476401011326433396006316603542822077809700770918787053951 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3932027263 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_smoke.3932027263 +enable_masking=1 +sw_key_masked=0' seed=106670853471560715273476401011326433396006316603542822077809700770918787053951 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106670853471560715273476401011326433396006316603542822077809700770918787053951 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_long_msg_and_output 76972024730731048348046487383727368152894315243796460629106129280546690573982 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_long_msg_and_output/latest run_opts='+test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2690918046 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_long_msg_and_output.2690918046 +enable_masking=1 +sw_key_masked=0' seed=76972024730731048348046487383727368152894315243796460629106129280546690573982 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76972024730731048348046487383727368152894315243796460629106129280546690573982 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_long_msg_and_output/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_long_msg_and_output_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload 62481760407785452900864329788662596703215287293280140868462537799894485613292 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_sideload/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2416360172 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload.2416360172 +enable_masking=1 +sw_key_masked=0' seed=62481760407785452900864329788662596703215287293280140868462537799894485613292 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62481760407785452900864329788662596703215287293280140868462537799894485613292 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_sideload/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 86344070882320219448051619155553660579308721887127214893125453514234686696952 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3909709304 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sideload_invalid.3909709304 +enable_masking=1 +sw_key_masked=0' seed=86344070882320219448051619155553660579308721887127214893125453514234686696952 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86344070882320219448051619155553660579308721887127214893125453514234686696952 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_burst_write 76767410333640030132935107056470673334483806023450239133742612795890104896915 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_burst_write/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=964529555 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_burst_write.964529555 +enable_masking=1 +sw_key_masked=0' seed=76767410333640030132935107056470673334483806023450239133742612795890104896915 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76767410333640030132935107056470673334483806023450239133742612795890104896915 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_burst_write/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_burst_write_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_sha3_224 12505119299618652801081982594052886972397066131489136298006044980261479297785 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_224/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3187192569 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_224.3187192569 +enable_masking=1 +sw_key_masked=0' seed=12505119299618652801081982594052886972397066131489136298006044980261479297785 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12505119299618652801081982594052886972397066131489136298006044980261479297785 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_224/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_sha3_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_sha3_256 4138323395814227501939578582239569645031369108657470784711506182327548752725 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_256/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3487282005 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_256.3487282005 +enable_masking=1 +sw_key_masked=0' seed=4138323395814227501939578582239569645031369108657470784711506182327548752725 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4138323395814227501939578582239569645031369108657470784711506182327548752725 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_256/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_sha3_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_sha3_384 88091764018712295909498342664450200850647120985323100717361602410342391050834 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_384/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=828469842 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_384.828469842 +enable_masking=1 +sw_key_masked=0' seed=88091764018712295909498342664450200850647120985323100717361602410342391050834 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88091764018712295909498342664450200850647120985323100717361602410342391050834 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_384/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_sha3_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_sha3_512 21023901340124531725724350107853972489503856046731228964403941191969146787891 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_512/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=727570483 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_sha3_512.727570483 +enable_masking=1 +sw_key_masked=0' seed=21023901340124531725724350107853972489503856046731228964403941191969146787891 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21023901340124531725724350107853972489503856046731228964403941191969146787891 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_test_vectors_sha3_512/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_sha3_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_shake_128 32156493930171508040382450033448258951338291505635350849832271050086577010459 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_test_vectors_shake_128/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1247999771 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_128.1247999771 +enable_masking=1 +sw_key_masked=0' seed=32156493930171508040382450033448258951338291505635350849832271050086577010459 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32156493930171508040382450033448258951338291505635350849832271050086577010459 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_test_vectors_shake_128/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_shake_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_shake_256 37290004818864926197572535970770931461596707923178724185235642712923625421844 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_test_vectors_shake_256/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2678782996 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_shake_256.2678782996 +enable_masking=1 +sw_key_masked=0' seed=37290004818864926197572535970770931461596707923178724185235642712923625421844 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37290004818864926197572535970770931461596707923178724185235642712923625421844 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_test_vectors_shake_256/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_shake_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_kmac 12557119407919047476923254027505991449583237765178963072608593067516639359235 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_test_vectors_kmac/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4271681795 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac.4271681795 +enable_masking=1 +sw_key_masked=0' seed=12557119407919047476923254027505991449583237765178963072608593067516639359235 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12557119407919047476923254027505991449583237765178963072608593067516639359235 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_test_vectors_kmac/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_kmac_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_kmac_xof 32136138139101165834930176145539164296486273327835771109121922459773791440391 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_test_vectors_kmac_xof/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=600903175 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_test_vectors_kmac_xof.600903175 +enable_masking=1 +sw_key_masked=0' seed=32136138139101165834930176145539164296486273327835771109121922459773791440391 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32136138139101165834930176145539164296486273327835771109121922459773791440391 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_test_vectors_kmac_xof/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_kmac_xof_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_app 54239740903724926827825460007314308373951194485389068952987620779532696908967 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_app/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4157043879 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app.4157043879 +enable_masking=1 +sw_key_masked=0' seed=54239740903724926827825460007314308373951194485389068952987620779532696908967 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54239740903724926827825460007314308373951194485389068952987620779532696908967 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_app/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_app_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_app_with_partial_data 59117586476272085878635919450644121076076400933647232260312428479741072708538 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_app_with_partial_data/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2222396346 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_app_with_partial_data.2222396346 +enable_masking=1 +sw_key_masked=0' seed=59117586476272085878635919450644121076076400933647232260312428479741072708538 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=59117586476272085878635919450644121076076400933647232260312428479741072708538 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_app_with_partial_data/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_app_with_partial_data_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_refresh 60160503897289377116309542224308707321018341702561923828229038142219982506983 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_entropy_refresh/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3455355879 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_refresh.3455355879 +enable_masking=1 +sw_key_masked=0' seed=60160503897289377116309542224308707321018341702561923828229038142219982506983 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60160503897289377116309542224308707321018341702561923828229038142219982506983 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_entropy_refresh/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_refresh_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_mubi 108217112596378161695698889595404721366553892006614978613888362861853878954416 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_mubi/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3103697328 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_mubi.3103697328 +enable_masking=1 +sw_key_masked=0' seed=108217112596378161695698889595404721366553892006614978613888362861853878954416 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108217112596378161695698889595404721366553892006614978613888362861853878954416 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_mubi_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_error 87423991141928353840411151698409997134033751450069722947946704216257684921347 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3217382403 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_error.3217382403 +enable_masking=1 +sw_key_masked=0' seed=87423991141928353840411151698409997134033751450069722947946704216257684921347 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87423991141928353840411151698409997134033751450069722947946704216257684921347 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_key_error 105617829835722950410677666599661459123260209452468374699565583799182340751344 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_key_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=136937456 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_key_error.136937456 +enable_masking=1 +sw_key_masked=0' seed=105617829835722950410677666599661459123260209452468374699565583799182340751344 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105617829835722950410677666599661459123260209452468374699565583799182340751344 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_key_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_key_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_edn_timeout_error 1613197880417233893425331844547671099779207119141147075042699285246309461402 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_edn_timeout_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2839178650 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_edn_timeout_error.2839178650 +enable_masking=1 +sw_key_masked=0' seed=1613197880417233893425331844547671099779207119141147075042699285246309461402 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1613197880417233893425331844547671099779207119141147075042699285246309461402 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_edn_timeout_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_edn_timeout_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_mode_error 59288285008788024447891169819558415957258613855595751614139567441762668899411 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_entropy_mode_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4104514643 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_mode_error.4104514643 +enable_masking=1 +sw_key_masked=0' seed=59288285008788024447891169819558415957258613855595751614139567441762668899411 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=59288285008788024447891169819558415957258613855595751614139567441762668899411 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_entropy_mode_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_mode_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_ready_error 58110723183636973395675156510593201440357234691935190015193355165545797049433 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_entropy_ready_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1970592857 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_entropy_ready_error.1970592857 +enable_masking=1 +sw_key_masked=0' seed=58110723183636973395675156510593201440357234691935190015193355165545797049433 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58110723183636973395675156510593201440357234691935190015193355165545797049433 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_entropy_ready_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_ready_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 50923923700007847495925146638509425349608683841025002253321980465803137326939 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=418324315 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_lc_escalation.418324315 +enable_masking=1 +sw_key_masked=0' seed=50923923700007847495925146638509425349608683841025002253321980465803137326939 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50923923700007847495925146638509425349608683841025002253321980465803137326939 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_stress_all_with_rand_reset 23155518618855427345552835104753112618774546218075073808032912564315768547778 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4204063170 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_stress_all_with_rand_reset.4204063170 +enable_masking=1 +sw_key_masked=0' seed=23155518618855427345552835104753112618774546218075073808032912564315768547778 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23155518618855427345552835104753112618774546218075073808032912564315768547778 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sec_cm 14848256730845063718431232362296847049361585158794665679568026907304070262952 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=372813992 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_sec_cm.372813992 +enable_masking=1 +sw_key_masked=0' seed=14848256730845063718431232362296847049361585158794665679568026907304070262952 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=14848256730845063718431232362296847049361585158794665679568026907304070262952 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors 68706070598125210231781183491491098976752559417791545360201330227719724899730 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3769933202 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors.3769933202 +enable_masking=1 +sw_key_masked=0' seed=68706070598125210231781183491491098976752559417791545360201330227719724899730 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68706070598125210231781183491491098976752559417791545360201330227719724899730 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors_with_csr_rw 51057627068763882200512674365977564055461504116605025316960350054489893116765 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3080461149 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_shadow_reg_errors_with_csr_rw.3080461149 +enable_masking=1 +sw_key_masked=0' seed=51057627068763882200512674365977564055461504116605025316960350054489893116765 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51057627068763882200512674365977564055461504116605025316960350054489893116765 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_alert_test 98117721413687334013990709413301179581224031353252334529299837827747632532214 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4177939190 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.kmac_alert_test.4177939190 +enable_masking=1 +sw_key_masked=0' seed=98117721413687334013990709413301179581224031353252334529299837827747632532214 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98117721413687334013990709413301179581224031353252334529299837827747632532214 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_errors 112203258270001655205017440895731047537324786095575913832908698206972753785372 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=643871260 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_errors.643871260 +enable_masking=1 +sw_key_masked=0' seed=112203258270001655205017440895731047537324786095575913832908698206972753785372 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112203258270001655205017440895731047537324786095575913832908698206972753785372 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_intg_err 87240284364487476414665703889132660200118852257464344231870323708766060683179 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=871505835 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_tl_intg_err.871505835 +enable_masking=1 +sw_key_masked=0' seed=87240284364487476414665703889132660200118852257464344231870323708766060683179 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87240284364487476414665703889132660200118852257464344231870323708766060683179 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_intr_test 92115308685422473750668789799628672881756663256309068451539365928639729956971 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=665516139 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_intr_test.665516139 +enable_masking=1 +sw_key_masked=0' seed=92115308685422473750668789799628672881756663256309068451539365928639729956971 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92115308685422473750668789799628672881756663256309068451539365928639729956971 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_csr_rw 81603245050134152252725419593632456487999296065118139779956827384596629178408 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1409697832 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_rw.1409697832 +enable_masking=1 +sw_key_masked=0' seed=81603245050134152252725419593632456487999296065118139779956827384596629178408 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81603245050134152252725419593632456487999296065118139779956827384596629178408 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_same_csr_outstanding 54657618780505264754636103461603044120275117774155285698724417062679809619976 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3408918536 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_same_csr_outstanding.3408918536 +enable_masking=1 +sw_key_masked=0' seed=54657618780505264754636103461603044120275117774155285698724417062679809619976 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54657618780505264754636103461603044120275117774155285698724417062679809619976 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_csr_mem_rw_with_rand_reset 83077566629402179728968522752008528428245546169107538341740441925031419946603 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2102634091 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.kmac_csr_mem_rw_with_rand_reset.2102634091 +enable_masking=1 +sw_key_masked=0' seed=83077566629402179728968522752008528428245546169107538341740441925031419946603 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83077566629402179728968522752008528428245546169107538341740441925031419946603 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/3.kmac_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_smoke 106876041085775832510209909198337303779482173912712465295545889913155290770958 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1431416334 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_smoke.1431416334 +enable_masking=1 +sw_key_masked=0' seed=106876041085775832510209909198337303779482173912712465295545889913155290770958 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106876041085775832510209909198337303779482173912712465295545889913155290770958 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_long_msg_and_output 46169233384074933694264860191999986738803423907265526984500108894181895443316 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_long_msg_and_output/latest run_opts='+test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3528201076 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_long_msg_and_output.3528201076 +enable_masking=1 +sw_key_masked=0' seed=46169233384074933694264860191999986738803423907265526984500108894181895443316 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46169233384074933694264860191999986738803423907265526984500108894181895443316 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_long_msg_and_output/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_long_msg_and_output_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload 72424677917619263120699006229888783793642817741069130578844951146654242168700 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_sideload/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3294093180 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload.3294093180 +enable_masking=1 +sw_key_masked=0' seed=72424677917619263120699006229888783793642817741069130578844951146654242168700 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72424677917619263120699006229888783793642817741069130578844951146654242168700 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_sideload/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 78143822916552887689915973802625074753520796625350094919362420146568584065581 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1876259373 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sideload_invalid.1876259373 +enable_masking=1 +sw_key_masked=0' seed=78143822916552887689915973802625074753520796625350094919362420146568584065581 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78143822916552887689915973802625074753520796625350094919362420146568584065581 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_burst_write 92607423435458348053511775648747038322326559026700044285677520985051141055160 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_burst_write/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3659604664 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_burst_write.3659604664 +enable_masking=1 +sw_key_masked=0' seed=92607423435458348053511775648747038322326559026700044285677520985051141055160 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92607423435458348053511775648747038322326559026700044285677520985051141055160 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_burst_write/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_burst_write_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_sha3_224 68946660882371917996239007193400613291739039843391134741408374089159138473455 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_224/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1061549551 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_224.1061549551 +enable_masking=1 +sw_key_masked=0' seed=68946660882371917996239007193400613291739039843391134741408374089159138473455 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68946660882371917996239007193400613291739039843391134741408374089159138473455 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_224/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_sha3_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_sha3_256 1499421034625166595160749066642557606064467916715385961227463245056338507905 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_256/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3763288193 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_256.3763288193 +enable_masking=1 +sw_key_masked=0' seed=1499421034625166595160749066642557606064467916715385961227463245056338507905 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1499421034625166595160749066642557606064467916715385961227463245056338507905 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_256/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_sha3_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_sha3_384 28920781340956897695256048730289720573423071045197443696633644687203646388377 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_384/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=551106713 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_384.551106713 +enable_masking=1 +sw_key_masked=0' seed=28920781340956897695256048730289720573423071045197443696633644687203646388377 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28920781340956897695256048730289720573423071045197443696633644687203646388377 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_384/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_sha3_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_sha3_512 108796556469158868331396486703060504112907188097218193668707802241897423997899 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_512/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3146812363 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_sha3_512.3146812363 +enable_masking=1 +sw_key_masked=0' seed=108796556469158868331396486703060504112907188097218193668707802241897423997899 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108796556469158868331396486703060504112907188097218193668707802241897423997899 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_test_vectors_sha3_512/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_sha3_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_shake_128 21562284291622547704145647309543433388883668340876418034294367880814577544900 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_test_vectors_shake_128/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1756065476 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_128.1756065476 +enable_masking=1 +sw_key_masked=0' seed=21562284291622547704145647309543433388883668340876418034294367880814577544900 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21562284291622547704145647309543433388883668340876418034294367880814577544900 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_test_vectors_shake_128/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_shake_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_shake_256 41488450572021603408999073021523680443093902928883227595540382792667294718176 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_test_vectors_shake_256/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2626279648 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_shake_256.2626279648 +enable_masking=1 +sw_key_masked=0' seed=41488450572021603408999073021523680443093902928883227595540382792667294718176 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41488450572021603408999073021523680443093902928883227595540382792667294718176 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_test_vectors_shake_256/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_shake_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_kmac 88037122989767839469413841651933133858511641808869725075387927070654581874862 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_test_vectors_kmac/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4195786926 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac.4195786926 +enable_masking=1 +sw_key_masked=0' seed=88037122989767839469413841651933133858511641808869725075387927070654581874862 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88037122989767839469413841651933133858511641808869725075387927070654581874862 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_test_vectors_kmac/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_kmac_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_test_vectors_kmac_xof 69772869261055322035082445640900823108435437366554182092405214968438365724076 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_test_vectors_kmac_xof/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3077152172 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_test_vectors_kmac_xof.3077152172 +enable_masking=1 +sw_key_masked=0' seed=69772869261055322035082445640900823108435437366554182092405214968438365724076 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69772869261055322035082445640900823108435437366554182092405214968438365724076 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_test_vectors_kmac_xof/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_kmac_xof_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_app 70259113660031654231331932547840457995378325543388213364672291680533674354136 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_app/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2895013336 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app.2895013336 +enable_masking=1 +sw_key_masked=0' seed=70259113660031654231331932547840457995378325543388213364672291680533674354136 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70259113660031654231331932547840457995378325543388213364672291680533674354136 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_app/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_app_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_app_with_partial_data 4058907202958332226036914878413631721957518916688917229081956587932214066399 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_app_with_partial_data/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1221557471 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_app_with_partial_data.1221557471 +enable_masking=1 +sw_key_masked=0' seed=4058907202958332226036914878413631721957518916688917229081956587932214066399 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4058907202958332226036914878413631721957518916688917229081956587932214066399 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_app_with_partial_data/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_app_with_partial_data_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_refresh 65330767640860595343984536259907879141949858081982154915696256441854277774027 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_entropy_refresh/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3582257867 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_refresh.3582257867 +enable_masking=1 +sw_key_masked=0' seed=65330767640860595343984536259907879141949858081982154915696256441854277774027 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65330767640860595343984536259907879141949858081982154915696256441854277774027 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_entropy_refresh/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_refresh_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_mubi 78685164813562864971564864366911855555675467786779599225673866361675343579659 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_mubi/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1768016395 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_mubi.1768016395 +enable_masking=1 +sw_key_masked=0' seed=78685164813562864971564864366911855555675467786779599225673866361675343579659 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78685164813562864971564864366911855555675467786779599225673866361675343579659 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_mubi_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_error 107728602890702647262291396652478023087605286581148841275934771570320446022727 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2065916999 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_error.2065916999 +enable_masking=1 +sw_key_masked=0' seed=107728602890702647262291396652478023087605286581148841275934771570320446022727 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107728602890702647262291396652478023087605286581148841275934771570320446022727 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_key_error 115297605237019207374174131549506108103139974634223818890498588802117106803525 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_key_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2347639621 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_key_error.2347639621 +enable_masking=1 +sw_key_masked=0' seed=115297605237019207374174131549506108103139974634223818890498588802117106803525 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115297605237019207374174131549506108103139974634223818890498588802117106803525 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_key_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_key_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_edn_timeout_error 24580652640271957388377410122365166796863379492221498529362384630339716800939 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_edn_timeout_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3333448107 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_edn_timeout_error.3333448107 +enable_masking=1 +sw_key_masked=0' seed=24580652640271957388377410122365166796863379492221498529362384630339716800939 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24580652640271957388377410122365166796863379492221498529362384630339716800939 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_edn_timeout_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_edn_timeout_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_mode_error 63832127853630129365417463072388973667768396788699874254529960523375363173927 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_entropy_mode_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2774478375 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_mode_error.2774478375 +enable_masking=1 +sw_key_masked=0' seed=63832127853630129365417463072388973667768396788699874254529960523375363173927 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63832127853630129365417463072388973667768396788699874254529960523375363173927 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_entropy_mode_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_mode_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_ready_error 88248218043482194107403602430143614016621807405683258716622164166812597363979 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_entropy_ready_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2067670283 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_entropy_ready_error.2067670283 +enable_masking=1 +sw_key_masked=0' seed=88248218043482194107403602430143614016621807405683258716622164166812597363979 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88248218043482194107403602430143614016621807405683258716622164166812597363979 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_entropy_ready_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_ready_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 15792270494243063563361811945369394978980711205697919565455334590454130127983 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2223354991 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_lc_escalation.2223354991 +enable_masking=1 +sw_key_masked=0' seed=15792270494243063563361811945369394978980711205697919565455334590454130127983 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15792270494243063563361811945369394978980711205697919565455334590454130127983 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_stress_all_with_rand_reset 74693146402731208101590089003012008680343831411508615266926253406548790411761 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2439053809 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_stress_all_with_rand_reset.2439053809 +enable_masking=1 +sw_key_masked=0' seed=74693146402731208101590089003012008680343831411508615266926253406548790411761 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74693146402731208101590089003012008680343831411508615266926253406548790411761 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sec_cm 41822771835193731450648789145060404915716687695818977247366197066522717002592 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4060289888 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_sec_cm.4060289888 +enable_masking=1 +sw_key_masked=0' seed=41822771835193731450648789145060404915716687695818977247366197066522717002592 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41822771835193731450648789145060404915716687695818977247366197066522717002592 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors 19192696858447596658736980364957508136135968889768834349759740464896679125029 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=181444645 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors.181444645 +enable_masking=1 +sw_key_masked=0' seed=19192696858447596658736980364957508136135968889768834349759740464896679125029 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19192696858447596658736980364957508136135968889768834349759740464896679125029 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors_with_csr_rw 6755709431112961606806814879308769033572536697904896801520923198428330410166 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3751100598 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_shadow_reg_errors_with_csr_rw.3751100598 +enable_masking=1 +sw_key_masked=0' seed=6755709431112961606806814879308769033572536697904896801520923198428330410166 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6755709431112961606806814879308769033572536697904896801520923198428330410166 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_alert_test 47539563324117627489692250347588860319736737587565432663349611572909763759100 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1953270780 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.kmac_alert_test.1953270780 +enable_masking=1 +sw_key_masked=0' seed=47539563324117627489692250347588860319736737587565432663349611572909763759100 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47539563324117627489692250347588860319736737587565432663349611572909763759100 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_errors 104193155357877198288205276052918918367631699976944804840674636576767899023732 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4046141812 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_errors.4046141812 +enable_masking=1 +sw_key_masked=0' seed=104193155357877198288205276052918918367631699976944804840674636576767899023732 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104193155357877198288205276052918918367631699976944804840674636576767899023732 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_intg_err 64405110433674071651927724769603014335797603007559121558735091869939918236894 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2285432030 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_tl_intg_err.2285432030 +enable_masking=1 +sw_key_masked=0' seed=64405110433674071651927724769603014335797603007559121558735091869939918236894 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64405110433674071651927724769603014335797603007559121558735091869939918236894 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_intr_test 90736428239857855222813651351675792598200151113932005337098242646409198183723 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3425707307 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_intr_test.3425707307 +enable_masking=1 +sw_key_masked=0' seed=90736428239857855222813651351675792598200151113932005337098242646409198183723 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90736428239857855222813651351675792598200151113932005337098242646409198183723 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_csr_rw 37105632688395989543168032331498800549359605781816007255742471420418116018848 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1977868960 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_rw.1977868960 +enable_masking=1 +sw_key_masked=0' seed=37105632688395989543168032331498800549359605781816007255742471420418116018848 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37105632688395989543168032331498800549359605781816007255742471420418116018848 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_same_csr_outstanding 60611799729452389945844169349896479781341777698077920898869153135258402171820 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3411684268 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_same_csr_outstanding.3411684268 +enable_masking=1 +sw_key_masked=0' seed=60611799729452389945844169349896479781341777698077920898869153135258402171820 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60611799729452389945844169349896479781341777698077920898869153135258402171820 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_csr_mem_rw_with_rand_reset 32509045669612121406360697950470777341841900416984952087401934070529765333972 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4258716628 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.kmac_csr_mem_rw_with_rand_reset.4258716628 +enable_masking=1 +sw_key_masked=0' seed=32509045669612121406360697950470777341841900416984952087401934070529765333972 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32509045669612121406360697950470777341841900416984952087401934070529765333972 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/4.kmac_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_smoke 74643303808771203341337222209494524195363066936704330591466205489742710854143 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1085035007 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_smoke.1085035007 +enable_masking=1 +sw_key_masked=0' seed=74643303808771203341337222209494524195363066936704330591466205489742710854143 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74643303808771203341337222209494524195363066936704330591466205489742710854143 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_long_msg_and_output 65943048046295171039935192543119769085205508888856048943741192918948140933162 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_long_msg_and_output/latest run_opts='+test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1647697962 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_long_msg_and_output.1647697962 +enable_masking=1 +sw_key_masked=0' seed=65943048046295171039935192543119769085205508888856048943741192918948140933162 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65943048046295171039935192543119769085205508888856048943741192918948140933162 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_long_msg_and_output/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_long_msg_and_output_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload 56655089480757211884218603564792252656146784207166716289953616088433907195196 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_sideload/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2401754428 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload.2401754428 +enable_masking=1 +sw_key_masked=0' seed=56655089480757211884218603564792252656146784207166716289953616088433907195196 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56655089480757211884218603564792252656146784207166716289953616088433907195196 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_sideload/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 30708721682264720335409887455211993103560419792579882955962722739278431298459 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1388749723 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_sideload_invalid.1388749723 +enable_masking=1 +sw_key_masked=0' seed=30708721682264720335409887455211993103560419792579882955962722739278431298459 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30708721682264720335409887455211993103560419792579882955962722739278431298459 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_burst_write 47079771221453744383719445035107568044904347662656079463809232220955175537811 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_burst_write/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3288845459 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_burst_write.3288845459 +enable_masking=1 +sw_key_masked=0' seed=47079771221453744383719445035107568044904347662656079463809232220955175537811 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47079771221453744383719445035107568044904347662656079463809232220955175537811 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_burst_write/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_burst_write_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_app 60726139508511482718115609562624412888262850811211279221139302175288671601600 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_app/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2006451136 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app.2006451136 +enable_masking=1 +sw_key_masked=0' seed=60726139508511482718115609562624412888262850811211279221139302175288671601600 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60726139508511482718115609562624412888262850811211279221139302175288671601600 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_app/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_app_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_app_with_partial_data 34851262035290162226014934152521479054436465973393392003629173638278346980127 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_app_with_partial_data/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4040964895 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_app_with_partial_data.4040964895 +enable_masking=1 +sw_key_masked=0' seed=34851262035290162226014934152521479054436465973393392003629173638278346980127 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34851262035290162226014934152521479054436465973393392003629173638278346980127 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_app_with_partial_data/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_app_with_partial_data_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_refresh 29758455784721895344513147173291451185732842176366588599244162015085347527824 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_entropy_refresh/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2316622992 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_refresh.2316622992 +enable_masking=1 +sw_key_masked=0' seed=29758455784721895344513147173291451185732842176366588599244162015085347527824 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29758455784721895344513147173291451185732842176366588599244162015085347527824 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_entropy_refresh/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_refresh_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_mubi 38462192828331710253315381744318818419138588704359738323551632306479035687336 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_mubi/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=641049000 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_mubi.641049000 +enable_masking=1 +sw_key_masked=0' seed=38462192828331710253315381744318818419138588704359738323551632306479035687336 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38462192828331710253315381744318818419138588704359738323551632306479035687336 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_mubi_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_error 87827779728198635678609485618906981324374494246280799594143032604401876121135 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2936845871 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_error.2936845871 +enable_masking=1 +sw_key_masked=0' seed=87827779728198635678609485618906981324374494246280799594143032604401876121135 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87827779728198635678609485618906981324374494246280799594143032604401876121135 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_key_error 7890239651809921913383455198032191010291018168381164826252410628119414988825 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_key_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3677642777 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_key_error.3677642777 +enable_masking=1 +sw_key_masked=0' seed=7890239651809921913383455198032191010291018168381164826252410628119414988825 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7890239651809921913383455198032191010291018168381164826252410628119414988825 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_key_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_key_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_edn_timeout_error 60749207007014887802652688203429156727530115768907421089341703457168208601920 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_edn_timeout_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1553638208 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_edn_timeout_error.1553638208 +enable_masking=1 +sw_key_masked=0' seed=60749207007014887802652688203429156727530115768907421089341703457168208601920 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60749207007014887802652688203429156727530115768907421089341703457168208601920 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_edn_timeout_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_edn_timeout_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_mode_error 39760131026711847745598163647533766380013133648137045666535845371256515761411 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_entropy_mode_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=992908547 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_mode_error.992908547 +enable_masking=1 +sw_key_masked=0' seed=39760131026711847745598163647533766380013133648137045666535845371256515761411 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39760131026711847745598163647533766380013133648137045666535845371256515761411 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_entropy_mode_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_mode_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_ready_error 86346883428094736257638401901342046679103049186875440658357307508823011909260 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_entropy_ready_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=111173260 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_entropy_ready_error.111173260 +enable_masking=1 +sw_key_masked=0' seed=86346883428094736257638401901342046679103049186875440658357307508823011909260 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86346883428094736257638401901342046679103049186875440658357307508823011909260 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_entropy_ready_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_ready_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 103003302472239003265137318445763490170247776097267595045543899802455660507981 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2212967245 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_lc_escalation.2212967245 +enable_masking=1 +sw_key_masked=0' seed=103003302472239003265137318445763490170247776097267595045543899802455660507981 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103003302472239003265137318445763490170247776097267595045543899802455660507981 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_stress_all_with_rand_reset 104312220485308361032608436065527633615572339244931821262664572882295266783182 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2610737102 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_stress_all_with_rand_reset.2610737102 +enable_masking=1 +sw_key_masked=0' seed=104312220485308361032608436065527633615572339244931821262664572882295266783182 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104312220485308361032608436065527633615572339244931821262664572882295266783182 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors 78752955049334283209420044552503933401886457498885956260457725516904072835403 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1909551435 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors.1909551435 +enable_masking=1 +sw_key_masked=0' seed=78752955049334283209420044552503933401886457498885956260457725516904072835403 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78752955049334283209420044552503933401886457498885956260457725516904072835403 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors_with_csr_rw 89148022516001360894598227870807027308964893500668154093814636737769587763544 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=359819608 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_shadow_reg_errors_with_csr_rw.359819608 +enable_masking=1 +sw_key_masked=0' seed=89148022516001360894598227870807027308964893500668154093814636737769587763544 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89148022516001360894598227870807027308964893500668154093814636737769587763544 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_alert_test 51056314333580008003322855223146145905534913539042966813238975698512051676867 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2312087235 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.kmac_alert_test.2312087235 +enable_masking=1 +sw_key_masked=0' seed=51056314333580008003322855223146145905534913539042966813238975698512051676867 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51056314333580008003322855223146145905534913539042966813238975698512051676867 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_errors 58163552580627529907517263976831552836124317068755246236453955929107320599841 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3049321761 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_errors.3049321761 +enable_masking=1 +sw_key_masked=0' seed=58163552580627529907517263976831552836124317068755246236453955929107320599841 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58163552580627529907517263976831552836124317068755246236453955929107320599841 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_intg_err 41450672884109218566495733210951878909994818815900486387845899931577052887331 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1800993059 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_tl_intg_err.1800993059 +enable_masking=1 +sw_key_masked=0' seed=41450672884109218566495733210951878909994818815900486387845899931577052887331 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41450672884109218566495733210951878909994818815900486387845899931577052887331 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_intr_test 62592293814889957556671198164257321615133604704446285679716440120887057487902 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2119866398 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.kmac_intr_test.2119866398 +enable_masking=1 +sw_key_masked=0' seed=62592293814889957556671198164257321615133604704446285679716440120887057487902 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62592293814889957556671198164257321615133604704446285679716440120887057487902 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/5.kmac_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_smoke 36346171343061836928428713287026698738716629255499936581483292767427531848577 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1252211585 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_smoke.1252211585 +enable_masking=1 +sw_key_masked=0' seed=36346171343061836928428713287026698738716629255499936581483292767427531848577 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36346171343061836928428713287026698738716629255499936581483292767427531848577 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_long_msg_and_output 12150200636966615840962836038350722154814436476473780313553446531987092313922 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_long_msg_and_output/latest run_opts='+test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4095776578 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_long_msg_and_output.4095776578 +enable_masking=1 +sw_key_masked=0' seed=12150200636966615840962836038350722154814436476473780313553446531987092313922 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12150200636966615840962836038350722154814436476473780313553446531987092313922 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_long_msg_and_output/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_long_msg_and_output_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload 71218181381732193758378382451078768016164444757636939446560938078357872884865 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_sideload/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=218020993 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload.218020993 +enable_masking=1 +sw_key_masked=0' seed=71218181381732193758378382451078768016164444757636939446560938078357872884865 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71218181381732193758378382451078768016164444757636939446560938078357872884865 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_sideload/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 41749755883877267595814799369052747191781946558337514790815689994871508299561 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=540274473 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_sideload_invalid.540274473 +enable_masking=1 +sw_key_masked=0' seed=41749755883877267595814799369052747191781946558337514790815689994871508299561 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41749755883877267595814799369052747191781946558337514790815689994871508299561 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_burst_write 45494083917956347856258009008667988889056916833471321489583440025393983840735 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_burst_write/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=569041375 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_burst_write.569041375 +enable_masking=1 +sw_key_masked=0' seed=45494083917956347856258009008667988889056916833471321489583440025393983840735 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45494083917956347856258009008667988889056916833471321489583440025393983840735 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_burst_write/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_burst_write_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_app 86767971117298769365559084866692801703751110458836605148551646847320884279963 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_app/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2868148891 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app.2868148891 +enable_masking=1 +sw_key_masked=0' seed=86767971117298769365559084866692801703751110458836605148551646847320884279963 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86767971117298769365559084866692801703751110458836605148551646847320884279963 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_app/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_app_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_app_with_partial_data 2478413543987948517925999026766092796703929199145799786045100869053107311853 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_app_with_partial_data/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=706647277 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_app_with_partial_data.706647277 +enable_masking=1 +sw_key_masked=0' seed=2478413543987948517925999026766092796703929199145799786045100869053107311853 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2478413543987948517925999026766092796703929199145799786045100869053107311853 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_app_with_partial_data/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_app_with_partial_data_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_refresh 89525309181943029484720903015872382314458700123610703520483272265213625120828 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_entropy_refresh/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2759735356 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_refresh.2759735356 +enable_masking=1 +sw_key_masked=0' seed=89525309181943029484720903015872382314458700123610703520483272265213625120828 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89525309181943029484720903015872382314458700123610703520483272265213625120828 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_entropy_refresh/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_refresh_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_mubi 57796191534563900213258349690845566417188597322485161559561424897353548870511 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_mubi/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2328671087 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_mubi.2328671087 +enable_masking=1 +sw_key_masked=0' seed=57796191534563900213258349690845566417188597322485161559561424897353548870511 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57796191534563900213258349690845566417188597322485161559561424897353548870511 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_mubi_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_error 39354667865166023460021460884082539696853563820319954325938010759836921293640 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3373329224 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_error.3373329224 +enable_masking=1 +sw_key_masked=0' seed=39354667865166023460021460884082539696853563820319954325938010759836921293640 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39354667865166023460021460884082539696853563820319954325938010759836921293640 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_key_error 62663460692221109970199880596917614904734193782099381710436288730801027479025 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_key_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2584016369 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_key_error.2584016369 +enable_masking=1 +sw_key_masked=0' seed=62663460692221109970199880596917614904734193782099381710436288730801027479025 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62663460692221109970199880596917614904734193782099381710436288730801027479025 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_key_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_key_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_edn_timeout_error 72464935211239716620956329949977818057972325583622651504546607495034526442432 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_edn_timeout_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=285942720 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_edn_timeout_error.285942720 +enable_masking=1 +sw_key_masked=0' seed=72464935211239716620956329949977818057972325583622651504546607495034526442432 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72464935211239716620956329949977818057972325583622651504546607495034526442432 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_edn_timeout_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_edn_timeout_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_mode_error 65502616248293143148955141478080868939824491412504019477331576817236111069474 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_entropy_mode_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1277497634 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_mode_error.1277497634 +enable_masking=1 +sw_key_masked=0' seed=65502616248293143148955141478080868939824491412504019477331576817236111069474 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65502616248293143148955141478080868939824491412504019477331576817236111069474 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_entropy_mode_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_mode_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_ready_error 36305360210181602103998764434589891321577146673506710442201284411730862826622 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_entropy_ready_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2144101502 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_entropy_ready_error.2144101502 +enable_masking=1 +sw_key_masked=0' seed=36305360210181602103998764434589891321577146673506710442201284411730862826622 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36305360210181602103998764434589891321577146673506710442201284411730862826622 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_entropy_ready_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_ready_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 93721306174685032209418844289822006314866864147913061635195449286169441006973 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1091761533 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_lc_escalation.1091761533 +enable_masking=1 +sw_key_masked=0' seed=93721306174685032209418844289822006314866864147913061635195449286169441006973 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93721306174685032209418844289822006314866864147913061635195449286169441006973 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_stress_all_with_rand_reset 18125172772916424732662402411879780540662686566206852572480705457902367116820 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3348467220 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_stress_all_with_rand_reset.3348467220 +enable_masking=1 +sw_key_masked=0' seed=18125172772916424732662402411879780540662686566206852572480705457902367116820 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18125172772916424732662402411879780540662686566206852572480705457902367116820 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors 19986967196937713253869939231201489870957517489331943547731807572077034792634 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1872422586 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors.1872422586 +enable_masking=1 +sw_key_masked=0' seed=19986967196937713253869939231201489870957517489331943547731807572077034792634 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19986967196937713253869939231201489870957517489331943547731807572077034792634 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors_with_csr_rw 11885889866451545581695916327262712003834309436541958631382161351926090199046 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=403075078 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_shadow_reg_errors_with_csr_rw.403075078 +enable_masking=1 +sw_key_masked=0' seed=11885889866451545581695916327262712003834309436541958631382161351926090199046 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11885889866451545581695916327262712003834309436541958631382161351926090199046 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_alert_test 10340024930802142920449332187016975141894538500523519032646688557661294827420 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=305272732 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.kmac_alert_test.305272732 +enable_masking=1 +sw_key_masked=0' seed=10340024930802142920449332187016975141894538500523519032646688557661294827420 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10340024930802142920449332187016975141894538500523519032646688557661294827420 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_errors 114280491278923968918925387847606800113138979737203907564307039597146843076045 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=136271309 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_errors.136271309 +enable_masking=1 +sw_key_masked=0' seed=114280491278923968918925387847606800113138979737203907564307039597146843076045 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114280491278923968918925387847606800113138979737203907564307039597146843076045 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_intg_err 40086379055875352443672960143760684930686434567154554874381941127994559693377 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2751201857 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_tl_intg_err.2751201857 +enable_masking=1 +sw_key_masked=0' seed=40086379055875352443672960143760684930686434567154554874381941127994559693377 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40086379055875352443672960143760684930686434567154554874381941127994559693377 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_intr_test 8327554638607664462316471672767823343639848986707055070569560323786826013684 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2902154228 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.kmac_intr_test.2902154228 +enable_masking=1 +sw_key_masked=0' seed=8327554638607664462316471672767823343639848986707055070569560323786826013684 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8327554638607664462316471672767823343639848986707055070569560323786826013684 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/6.kmac_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_smoke 94074706962798440368952816815802778002832300250557552716626361009908458540140 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3289992300 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_smoke.3289992300 +enable_masking=1 +sw_key_masked=0' seed=94074706962798440368952816815802778002832300250557552716626361009908458540140 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94074706962798440368952816815802778002832300250557552716626361009908458540140 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_long_msg_and_output 114268690485559939229354519353889391201170507318828229761890456614751525602447 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_long_msg_and_output/latest run_opts='+test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=539690127 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_long_msg_and_output.539690127 +enable_masking=1 +sw_key_masked=0' seed=114268690485559939229354519353889391201170507318828229761890456614751525602447 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114268690485559939229354519353889391201170507318828229761890456614751525602447 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_long_msg_and_output/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_long_msg_and_output_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload 23448997108648715072584354474841159522182327057151246495877240059869118916219 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_sideload/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2392647291 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload.2392647291 +enable_masking=1 +sw_key_masked=0' seed=23448997108648715072584354474841159522182327057151246495877240059869118916219 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23448997108648715072584354474841159522182327057151246495877240059869118916219 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_sideload/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 25539216998837011613970676719530232538538141454710698656520437597692606759132 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3581624540 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_sideload_invalid.3581624540 +enable_masking=1 +sw_key_masked=0' seed=25539216998837011613970676719530232538538141454710698656520437597692606759132 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25539216998837011613970676719530232538538141454710698656520437597692606759132 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_burst_write 79545910859082673567159611331713488553025575672548882377848457392496623492587 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_burst_write/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=185343467 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_burst_write.185343467 +enable_masking=1 +sw_key_masked=0' seed=79545910859082673567159611331713488553025575672548882377848457392496623492587 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79545910859082673567159611331713488553025575672548882377848457392496623492587 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_burst_write/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_burst_write_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_app 86438304829274888142814095286683193731919869043726281239049414734051125262060 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_app/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1545107180 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app.1545107180 +enable_masking=1 +sw_key_masked=0' seed=86438304829274888142814095286683193731919869043726281239049414734051125262060 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86438304829274888142814095286683193731919869043726281239049414734051125262060 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_app/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_app_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_app_with_partial_data 1124595433965924094499117524547040974908797977768786107148387773887554558234 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_app_with_partial_data/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=965515546 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_app_with_partial_data.965515546 +enable_masking=1 +sw_key_masked=0' seed=1124595433965924094499117524547040974908797977768786107148387773887554558234 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1124595433965924094499117524547040974908797977768786107148387773887554558234 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_app_with_partial_data/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_app_with_partial_data_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_refresh 56311967868053648089122130579984497306623956921873328841575213803615701379457 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_entropy_refresh/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2060396929 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_refresh.2060396929 +enable_masking=1 +sw_key_masked=0' seed=56311967868053648089122130579984497306623956921873328841575213803615701379457 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56311967868053648089122130579984497306623956921873328841575213803615701379457 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_entropy_refresh/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_refresh_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_mubi 66024240420519377385909943363596773730953928341195819807524190692715036816464 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_mubi/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=186004560 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_mubi.186004560 +enable_masking=1 +sw_key_masked=0' seed=66024240420519377385909943363596773730953928341195819807524190692715036816464 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66024240420519377385909943363596773730953928341195819807524190692715036816464 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_mubi_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_error 29773081722997951236747943958757824452190708841089199659066005519963934329780 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=237145012 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_error.237145012 +enable_masking=1 +sw_key_masked=0' seed=29773081722997951236747943958757824452190708841089199659066005519963934329780 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29773081722997951236747943958757824452190708841089199659066005519963934329780 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_key_error 90662992245524286376769381516080833382921935321894593876156186627789783130938 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_key_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2561499962 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_key_error.2561499962 +enable_masking=1 +sw_key_masked=0' seed=90662992245524286376769381516080833382921935321894593876156186627789783130938 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90662992245524286376769381516080833382921935321894593876156186627789783130938 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_key_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_key_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_edn_timeout_error 54207129273636098904515426592182491277684961209035999765450838609475634692719 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_edn_timeout_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3177415279 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_edn_timeout_error.3177415279 +enable_masking=1 +sw_key_masked=0' seed=54207129273636098904515426592182491277684961209035999765450838609475634692719 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54207129273636098904515426592182491277684961209035999765450838609475634692719 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_edn_timeout_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_edn_timeout_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_mode_error 1034589137414036136469717129041358279470639856503571537170166677003867321167 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_entropy_mode_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=818213711 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_mode_error.818213711 +enable_masking=1 +sw_key_masked=0' seed=1034589137414036136469717129041358279470639856503571537170166677003867321167 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1034589137414036136469717129041358279470639856503571537170166677003867321167 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_entropy_mode_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_mode_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_ready_error 89401959313687952694635576388910070989776511990981275697710290792381604575338 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_entropy_ready_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1021720682 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_entropy_ready_error.1021720682 +enable_masking=1 +sw_key_masked=0' seed=89401959313687952694635576388910070989776511990981275697710290792381604575338 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89401959313687952694635576388910070989776511990981275697710290792381604575338 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_entropy_ready_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_ready_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 45052742166368242416915356624340036579997396895466682481541054306594522596098 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1584333570 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_lc_escalation.1584333570 +enable_masking=1 +sw_key_masked=0' seed=45052742166368242416915356624340036579997396895466682481541054306594522596098 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45052742166368242416915356624340036579997396895466682481541054306594522596098 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_stress_all_with_rand_reset 114214293755011120185853588192757845084486523490300927687886908157033141486243 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3005465251 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_stress_all_with_rand_reset.3005465251 +enable_masking=1 +sw_key_masked=0' seed=114214293755011120185853588192757845084486523490300927687886908157033141486243 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114214293755011120185853588192757845084486523490300927687886908157033141486243 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors 66857751572182339246857802911058617905778348465938180540763787642481320069293 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3919775917 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors.3919775917 +enable_masking=1 +sw_key_masked=0' seed=66857751572182339246857802911058617905778348465938180540763787642481320069293 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66857751572182339246857802911058617905778348465938180540763787642481320069293 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors_with_csr_rw 73919964805091025356281814578379777704217025202921173784517039885206757738938 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=680167866 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_shadow_reg_errors_with_csr_rw.680167866 +enable_masking=1 +sw_key_masked=0' seed=73919964805091025356281814578379777704217025202921173784517039885206757738938 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73919964805091025356281814578379777704217025202921173784517039885206757738938 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_alert_test 40643983100558174018567341437914177129808701543260787741404791727984537307487 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=520423775 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.kmac_alert_test.520423775 +enable_masking=1 +sw_key_masked=0' seed=40643983100558174018567341437914177129808701543260787741404791727984537307487 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40643983100558174018567341437914177129808701543260787741404791727984537307487 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_errors 53261028349315515030582388905342944247524704299360014012279884445483662513698 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3898807842 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_errors.3898807842 +enable_masking=1 +sw_key_masked=0' seed=53261028349315515030582388905342944247524704299360014012279884445483662513698 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53261028349315515030582388905342944247524704299360014012279884445483662513698 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_intg_err 89969590264057858605693286564188426099000114714152322549448359755564749148475 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3505901883 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_tl_intg_err.3505901883 +enable_masking=1 +sw_key_masked=0' seed=89969590264057858605693286564188426099000114714152322549448359755564749148475 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89969590264057858605693286564188426099000114714152322549448359755564749148475 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_intr_test 7477688227297046242395223502907950741295557854335188778109858970721350238149 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=442417093 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.kmac_intr_test.442417093 +enable_masking=1 +sw_key_masked=0' seed=7477688227297046242395223502907950741295557854335188778109858970721350238149 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7477688227297046242395223502907950741295557854335188778109858970721350238149 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/7.kmac_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_smoke 7464554039455030137591744425626385115492276888205154729100828541383576739752 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2625462184 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_smoke.2625462184 +enable_masking=1 +sw_key_masked=0' seed=7464554039455030137591744425626385115492276888205154729100828541383576739752 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7464554039455030137591744425626385115492276888205154729100828541383576739752 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_long_msg_and_output 22333157867837165741259150878859308239965680014208101877246840855899107486914 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_long_msg_and_output/latest run_opts='+test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1053813954 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_long_msg_and_output.1053813954 +enable_masking=1 +sw_key_masked=0' seed=22333157867837165741259150878859308239965680014208101877246840855899107486914 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22333157867837165741259150878859308239965680014208101877246840855899107486914 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_long_msg_and_output/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_long_msg_and_output_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload 20292725608975440422958310740455870010823018331083344754419648642489524653209 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_sideload/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1380158617 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload.1380158617 +enable_masking=1 +sw_key_masked=0' seed=20292725608975440422958310740455870010823018331083344754419648642489524653209 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20292725608975440422958310740455870010823018331083344754419648642489524653209 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_sideload/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 74284386965169690710012108251122807385388808179170402875520134427445267980501 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=759357653 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_sideload_invalid.759357653 +enable_masking=1 +sw_key_masked=0' seed=74284386965169690710012108251122807385388808179170402875520134427445267980501 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74284386965169690710012108251122807385388808179170402875520134427445267980501 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_burst_write 95783847253386938303952438810103358082238174313572965958380440648668312651692 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_burst_write/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=699811756 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_burst_write.699811756 +enable_masking=1 +sw_key_masked=0' seed=95783847253386938303952438810103358082238174313572965958380440648668312651692 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95783847253386938303952438810103358082238174313572965958380440648668312651692 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_burst_write/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_burst_write_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_app 92108840913624205833312509842420872933931720466809335016340446317834535638600 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_app/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1111168584 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app.1111168584 +enable_masking=1 +sw_key_masked=0' seed=92108840913624205833312509842420872933931720466809335016340446317834535638600 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92108840913624205833312509842420872933931720466809335016340446317834535638600 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_app/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_app_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_app_with_partial_data 97181471631998165713896080505988999313994634799597783111992399083886104968987 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_app_with_partial_data/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1958641435 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_app_with_partial_data.1958641435 +enable_masking=1 +sw_key_masked=0' seed=97181471631998165713896080505988999313994634799597783111992399083886104968987 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97181471631998165713896080505988999313994634799597783111992399083886104968987 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_app_with_partial_data/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_app_with_partial_data_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_refresh 93292498507234213039797934079720779706751751701235020658672194268668437096765 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_entropy_refresh/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2263771453 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_refresh.2263771453 +enable_masking=1 +sw_key_masked=0' seed=93292498507234213039797934079720779706751751701235020658672194268668437096765 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93292498507234213039797934079720779706751751701235020658672194268668437096765 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_entropy_refresh/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_refresh_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_mubi 7652161679828646019088972837578166016653346088202338675194334193183282430622 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_mubi/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1938817694 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_mubi.1938817694 +enable_masking=1 +sw_key_masked=0' seed=7652161679828646019088972837578166016653346088202338675194334193183282430622 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7652161679828646019088972837578166016653346088202338675194334193183282430622 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_mubi_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_error 56093115287248989424636734779679390192825424205320137640224709349497215031798 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1939511798 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_error.1939511798 +enable_masking=1 +sw_key_masked=0' seed=56093115287248989424636734779679390192825424205320137640224709349497215031798 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56093115287248989424636734779679390192825424205320137640224709349497215031798 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_key_error 6575832523047925560170113110124131945537794727072677854089802186492886761439 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_key_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=413515743 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_key_error.413515743 +enable_masking=1 +sw_key_masked=0' seed=6575832523047925560170113110124131945537794727072677854089802186492886761439 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6575832523047925560170113110124131945537794727072677854089802186492886761439 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_key_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_key_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_edn_timeout_error 74299648313700937858190086764264194085285233061852115551655228913970234431208 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_edn_timeout_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=774805224 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_edn_timeout_error.774805224 +enable_masking=1 +sw_key_masked=0' seed=74299648313700937858190086764264194085285233061852115551655228913970234431208 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74299648313700937858190086764264194085285233061852115551655228913970234431208 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_edn_timeout_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_edn_timeout_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_mode_error 63719784620255112081093970135975199980753261396498893097745904505235702632464 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_entropy_mode_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2704101392 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_mode_error.2704101392 +enable_masking=1 +sw_key_masked=0' seed=63719784620255112081093970135975199980753261396498893097745904505235702632464 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63719784620255112081093970135975199980753261396498893097745904505235702632464 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_entropy_mode_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_mode_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_ready_error 100724703806780551228813846406071474679055131202937238071803576516586621548082 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_entropy_ready_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=331265586 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_entropy_ready_error.331265586 +enable_masking=1 +sw_key_masked=0' seed=100724703806780551228813846406071474679055131202937238071803576516586621548082 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100724703806780551228813846406071474679055131202937238071803576516586621548082 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_entropy_ready_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_ready_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 86479539207795159187047521930766320345152537897756157386347283365940477865908 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4268535732 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_lc_escalation.4268535732 +enable_masking=1 +sw_key_masked=0' seed=86479539207795159187047521930766320345152537897756157386347283365940477865908 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86479539207795159187047521930766320345152537897756157386347283365940477865908 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_stress_all_with_rand_reset 112595383170645815716126019980703571445695952455774676412204382656881027056055 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3920232887 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_stress_all_with_rand_reset.3920232887 +enable_masking=1 +sw_key_masked=0' seed=112595383170645815716126019980703571445695952455774676412204382656881027056055 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112595383170645815716126019980703571445695952455774676412204382656881027056055 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors 94292046656033980223918455623983852620916754677302642749570396204858409023608 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4102617208 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors.4102617208 +enable_masking=1 +sw_key_masked=0' seed=94292046656033980223918455623983852620916754677302642749570396204858409023608 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94292046656033980223918455623983852620916754677302642749570396204858409023608 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors_with_csr_rw 77755695180851163919035304054750565037249129747556524423895855079690654638849 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4246397697 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_shadow_reg_errors_with_csr_rw.4246397697 +enable_masking=1 +sw_key_masked=0' seed=77755695180851163919035304054750565037249129747556524423895855079690654638849 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77755695180851163919035304054750565037249129747556524423895855079690654638849 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_alert_test 10502137412403088778210296270050202153990764738144673240537036552057240170380 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=459288460 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.kmac_alert_test.459288460 +enable_masking=1 +sw_key_masked=0' seed=10502137412403088778210296270050202153990764738144673240537036552057240170380 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10502137412403088778210296270050202153990764738144673240537036552057240170380 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_errors 111471945267290070046822688470797640443961863530869007461148469707919021326357 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=946094101 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_errors.946094101 +enable_masking=1 +sw_key_masked=0' seed=111471945267290070046822688470797640443961863530869007461148469707919021326357 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111471945267290070046822688470797640443961863530869007461148469707919021326357 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_intg_err 70810127706816711308220011292474982734626023888554576071650032440360231449367 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=105067287 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_tl_intg_err.105067287 +enable_masking=1 +sw_key_masked=0' seed=70810127706816711308220011292474982734626023888554576071650032440360231449367 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70810127706816711308220011292474982734626023888554576071650032440360231449367 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_intr_test 99440086662708673433357820897908498955814105926138712686515654847278287709665 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4083443169 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.kmac_intr_test.4083443169 +enable_masking=1 +sw_key_masked=0' seed=99440086662708673433357820897908498955814105926138712686515654847278287709665 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99440086662708673433357820897908498955814105926138712686515654847278287709665 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/8.kmac_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_smoke 21558847386028736107002660960567842555612186142208152186719687284631083185512 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2171106664 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_smoke.2171106664 +enable_masking=1 +sw_key_masked=0' seed=21558847386028736107002660960567842555612186142208152186719687284631083185512 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21558847386028736107002660960567842555612186142208152186719687284631083185512 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_long_msg_and_output 57326750314667073698309928630097371857453401463668804481602210274630835280950 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_long_msg_and_output/latest run_opts='+test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1409195062 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_long_msg_and_output.1409195062 +enable_masking=1 +sw_key_masked=0' seed=57326750314667073698309928630097371857453401463668804481602210274630835280950 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57326750314667073698309928630097371857453401463668804481602210274630835280950 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_long_msg_and_output/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_long_msg_and_output_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload 75266507630632015943975592830238004745243450961979156094499522004722469532687 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_sideload/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=546010127 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload.546010127 +enable_masking=1 +sw_key_masked=0' seed=75266507630632015943975592830238004745243450961979156094499522004722469532687 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75266507630632015943975592830238004745243450961979156094499522004722469532687 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_sideload/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 11689775823224128083932996978538771213227689016261247245440438243719794343682 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4251139842 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_sideload_invalid.4251139842 +enable_masking=1 +sw_key_masked=0' seed=11689775823224128083932996978538771213227689016261247245440438243719794343682 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11689775823224128083932996978538771213227689016261247245440438243719794343682 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_burst_write 2703621456942503210543879837878928826973525346264393017535639945986288469430 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_burst_write/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1740981686 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_burst_write.1740981686 +enable_masking=1 +sw_key_masked=0' seed=2703621456942503210543879837878928826973525346264393017535639945986288469430 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2703621456942503210543879837878928826973525346264393017535639945986288469430 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_burst_write/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_burst_write_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_app 20450674317065179650781184403179054143356083871079337636975361483226431919353 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_app/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=739808505 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app.739808505 +enable_masking=1 +sw_key_masked=0' seed=20450674317065179650781184403179054143356083871079337636975361483226431919353 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20450674317065179650781184403179054143356083871079337636975361483226431919353 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_app/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_app_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_app_with_partial_data 69529320426376385488808003687335454432769130690062069670750795251372026878248 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_app_with_partial_data/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4085635368 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_app_with_partial_data.4085635368 +enable_masking=1 +sw_key_masked=0' seed=69529320426376385488808003687335454432769130690062069670750795251372026878248 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69529320426376385488808003687335454432769130690062069670750795251372026878248 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_app_with_partial_data/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_app_with_partial_data_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_refresh 21963152163748208024748704883326181175964406220090569349378374806708205176087 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_entropy_refresh/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=818464023 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_refresh.818464023 +enable_masking=1 +sw_key_masked=0' seed=21963152163748208024748704883326181175964406220090569349378374806708205176087 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21963152163748208024748704883326181175964406220090569349378374806708205176087 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_entropy_refresh/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_refresh_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_mubi 113612149185170727122593747812105622082451701762725671484222786833790178397599 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_mubi/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1729334687 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_mubi.1729334687 +enable_masking=1 +sw_key_masked=0' seed=113612149185170727122593747812105622082451701762725671484222786833790178397599 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113612149185170727122593747812105622082451701762725671484222786833790178397599 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_mubi_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_error 73578592289632604369269703885812855175482371068636936654783448180189790782578 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3480536178 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_error.3480536178 +enable_masking=1 +sw_key_masked=0' seed=73578592289632604369269703885812855175482371068636936654783448180189790782578 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73578592289632604369269703885812855175482371068636936654783448180189790782578 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_key_error 29602990541719264140987708414997196001058903459740016835965644650500853092621 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_key_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2608091405 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_key_error.2608091405 +enable_masking=1 +sw_key_masked=0' seed=29602990541719264140987708414997196001058903459740016835965644650500853092621 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29602990541719264140987708414997196001058903459740016835965644650500853092621 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_key_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_key_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_edn_timeout_error 78472685927655028638968877911685849666111364323732987694181710371715213201978 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_edn_timeout_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1782092346 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_edn_timeout_error.1782092346 +enable_masking=1 +sw_key_masked=0' seed=78472685927655028638968877911685849666111364323732987694181710371715213201978 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78472685927655028638968877911685849666111364323732987694181710371715213201978 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_edn_timeout_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_edn_timeout_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_mode_error 58063856624586773480635012948880640324749647138345920885224626886246617158378 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_entropy_mode_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=584159978 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_mode_error.584159978 +enable_masking=1 +sw_key_masked=0' seed=58063856624586773480635012948880640324749647138345920885224626886246617158378 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58063856624586773480635012948880640324749647138345920885224626886246617158378 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_entropy_mode_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_mode_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_ready_error 81589699801235298467889421069768436219841870268899104837447981291017142382915 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_entropy_ready_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1791603011 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_entropy_ready_error.1791603011 +enable_masking=1 +sw_key_masked=0' seed=81589699801235298467889421069768436219841870268899104837447981291017142382915 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81589699801235298467889421069768436219841870268899104837447981291017142382915 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_entropy_ready_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_ready_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 58524512261511163877818344353661325821023245823899978243635957805698849982090 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1824016010 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_lc_escalation.1824016010 +enable_masking=1 +sw_key_masked=0' seed=58524512261511163877818344353661325821023245823899978243635957805698849982090 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58524512261511163877818344353661325821023245823899978243635957805698849982090 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_stress_all_with_rand_reset 74337827235481338705696524705257432103985832003616920692349966806943480949921 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2221157537 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_stress_all_with_rand_reset.2221157537 +enable_masking=1 +sw_key_masked=0' seed=74337827235481338705696524705257432103985832003616920692349966806943480949921 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74337827235481338705696524705257432103985832003616920692349966806943480949921 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors 112626260179460518529342906683860599222680484647849577389319940965908115125182 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4071650238 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors.4071650238 +enable_masking=1 +sw_key_masked=0' seed=112626260179460518529342906683860599222680484647849577389319940965908115125182 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112626260179460518529342906683860599222680484647849577389319940965908115125182 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors_with_csr_rw 33266842969482501444785811698219759699839504787125859765886279892311837823791 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4188853039 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_shadow_reg_errors_with_csr_rw.4188853039 +enable_masking=1 +sw_key_masked=0' seed=33266842969482501444785811698219759699839504787125859765886279892311837823791 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33266842969482501444785811698219759699839504787125859765886279892311837823791 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_alert_test 37804057879180099614483880274225496018756094554613031930880517468766108651045 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2453933605 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.kmac_alert_test.2453933605 +enable_masking=1 +sw_key_masked=0' seed=37804057879180099614483880274225496018756094554613031930880517468766108651045 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37804057879180099614483880274225496018756094554613031930880517468766108651045 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_errors 101121940352752525527748961921092312097313828528437962989155225730863554331720 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3031139400 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_errors.3031139400 +enable_masking=1 +sw_key_masked=0' seed=101121940352752525527748961921092312097313828528437962989155225730863554331720 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101121940352752525527748961921092312097313828528437962989155225730863554331720 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_intg_err 100620006536725207057280504432800136018609752995904920521715242468850044719286 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2616152246 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_tl_intg_err.2616152246 +enable_masking=1 +sw_key_masked=0' seed=100620006536725207057280504432800136018609752995904920521715242468850044719286 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100620006536725207057280504432800136018609752995904920521715242468850044719286 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_intr_test 43830960728315167024213352782292867839678287565008308067370927728845970830607 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3194057999 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.kmac_intr_test.3194057999 +enable_masking=1 +sw_key_masked=0' seed=43830960728315167024213352782292867839678287565008308067370927728845970830607 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43830960728315167024213352782292867839678287565008308067370927728845970830607 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/9.kmac_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_smoke 28106328909683199743609349196336775050066910821575616765979623471298397364855 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/10.kmac_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3693896311 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_smoke.3693896311 +enable_masking=1 +sw_key_masked=0' seed=28106328909683199743609349196336775050066910821575616765979623471298397364855 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28106328909683199743609349196336775050066910821575616765979623471298397364855 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/10.kmac_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_long_msg_and_output 29421704450930662859156236381945090644318088556258917707430454696534976443379 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/10.kmac_long_msg_and_output/latest run_opts='+test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1790391283 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_long_msg_and_output.1790391283 +enable_masking=1 +sw_key_masked=0' seed=29421704450930662859156236381945090644318088556258917707430454696534976443379 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29421704450930662859156236381945090644318088556258917707430454696534976443379 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/10.kmac_long_msg_and_output/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_long_msg_and_output_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload 50769723664026585944175767325450334075811163059672125158965249197691148387052 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/10.kmac_sideload/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2473804524 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload.2473804524 +enable_masking=1 +sw_key_masked=0' seed=50769723664026585944175767325450334075811163059672125158965249197691148387052 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50769723664026585944175767325450334075811163059672125158965249197691148387052 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/10.kmac_sideload/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 51620856955658829147202595679760079925460564674243798119710327594092555756851 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/10.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3204801843 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_sideload_invalid.3204801843 +enable_masking=1 +sw_key_masked=0' seed=51620856955658829147202595679760079925460564674243798119710327594092555756851 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51620856955658829147202595679760079925460564674243798119710327594092555756851 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/10.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_burst_write 79909450889674954016642707097210625249809438467251919676176270046629415654060 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/10.kmac_burst_write/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2908525228 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_burst_write.2908525228 +enable_masking=1 +sw_key_masked=0' seed=79909450889674954016642707097210625249809438467251919676176270046629415654060 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79909450889674954016642707097210625249809438467251919676176270046629415654060 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/10.kmac_burst_write/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_burst_write_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_app 7321569134855978209130766589499146176581667419525298690889712206092828410020 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/10.kmac_app/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1231814820 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_app.1231814820 +enable_masking=1 +sw_key_masked=0' seed=7321569134855978209130766589499146176581667419525298690889712206092828410020 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7321569134855978209130766589499146176581667419525298690889712206092828410020 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/10.kmac_app/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_app_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_refresh 74358416626659823580435020283008824170773217204182953175767526671531374829824 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/10.kmac_entropy_refresh/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2716098816 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_refresh.2716098816 +enable_masking=1 +sw_key_masked=0' seed=74358416626659823580435020283008824170773217204182953175767526671531374829824 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74358416626659823580435020283008824170773217204182953175767526671531374829824 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/10.kmac_entropy_refresh/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_refresh_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_error 87965466742590287606536855000507345789054360842215672775372139230647795129156 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/10.kmac_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2203917124 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_error.2203917124 +enable_masking=1 +sw_key_masked=0' seed=87965466742590287606536855000507345789054360842215672775372139230647795129156 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87965466742590287606536855000507345789054360842215672775372139230647795129156 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/10.kmac_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_key_error 82755565135029545327714877784486308490919557649630752297748436831668973040534 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/10.kmac_key_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=664236950 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_key_error.664236950 +enable_masking=1 +sw_key_masked=0' seed=82755565135029545327714877784486308490919557649630752297748436831668973040534 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82755565135029545327714877784486308490919557649630752297748436831668973040534 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/10.kmac_key_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_key_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_edn_timeout_error 29758597397487894614756851248372669028591709541942576353807849199352558057273 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/10.kmac_edn_timeout_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2945644345 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_edn_timeout_error.2945644345 +enable_masking=1 +sw_key_masked=0' seed=29758597397487894614756851248372669028591709541942576353807849199352558057273 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29758597397487894614756851248372669028591709541942576353807849199352558057273 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/10.kmac_edn_timeout_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_edn_timeout_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_mode_error 70138577025450506339932814179801537701046928330796534062942015359906496667552 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/10.kmac_entropy_mode_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2101108640 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_entropy_mode_error.2101108640 +enable_masking=1 +sw_key_masked=0' seed=70138577025450506339932814179801537701046928330796534062942015359906496667552 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70138577025450506339932814179801537701046928330796534062942015359906496667552 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/10.kmac_entropy_mode_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_mode_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 62160636775025846683311065399550817312935706903046400043846523806519436398353 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/10.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2741128977 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.kmac_lc_escalation.2741128977 +enable_masking=1 +sw_key_masked=0' seed=62160636775025846683311065399550817312935706903046400043846523806519436398353 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62160636775025846683311065399550817312935706903046400043846523806519436398353 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/10.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors 38558907722465616493247185940735065938072685284119807102323868572721242561079 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=86891063 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors.86891063 +enable_masking=1 +sw_key_masked=0' seed=38558907722465616493247185940735065938072685284119807102323868572721242561079 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38558907722465616493247185940735065938072685284119807102323868572721242561079 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors_with_csr_rw 99312951648667035532369520743749706509204509759695501601816462491928230889051 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=923797083 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_shadow_reg_errors_with_csr_rw.923797083 +enable_masking=1 +sw_key_masked=0' seed=99312951648667035532369520743749706509204509759695501601816462491928230889051 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99312951648667035532369520743749706509204509759695501601816462491928230889051 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/10.kmac_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_errors 26267231139171104403695633498920737661777872094445143746020140523676661918613 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/10.kmac_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2668047253 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_errors.2668047253 +enable_masking=1 +sw_key_masked=0' seed=26267231139171104403695633498920737661777872094445143746020140523676661918613 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26267231139171104403695633498920737661777872094445143746020140523676661918613 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/10.kmac_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_intg_err 32899119895567926813326995397003604798830719359066168501377388661202636480312 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/10.kmac_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1652793144 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.kmac_tl_intg_err.1652793144 +enable_masking=1 +sw_key_masked=0' seed=32899119895567926813326995397003604798830719359066168501377388661202636480312 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32899119895567926813326995397003604798830719359066168501377388661202636480312 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/10.kmac_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_smoke 60402192282945656330317462045121193160455248747300408433288356828850777519306 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/11.kmac_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=357856458 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_smoke.357856458 +enable_masking=1 +sw_key_masked=0' seed=60402192282945656330317462045121193160455248747300408433288356828850777519306 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60402192282945656330317462045121193160455248747300408433288356828850777519306 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/11.kmac_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_long_msg_and_output 83820666676357162063346421955351311747976493201640903712392360162957471699882 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/11.kmac_long_msg_and_output/latest run_opts='+test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3665482666 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_long_msg_and_output.3665482666 +enable_masking=1 +sw_key_masked=0' seed=83820666676357162063346421955351311747976493201640903712392360162957471699882 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83820666676357162063346421955351311747976493201640903712392360162957471699882 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/11.kmac_long_msg_and_output/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_long_msg_and_output_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload 40440299035110912483235063582324864904058605910623727807767979190176245011621 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/11.kmac_sideload/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2627654821 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload.2627654821 +enable_masking=1 +sw_key_masked=0' seed=40440299035110912483235063582324864904058605910623727807767979190176245011621 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40440299035110912483235063582324864904058605910623727807767979190176245011621 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/11.kmac_sideload/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 94376888541355977228861834328912624473065614709424392293847953515804023613152 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/11.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=193488608 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_sideload_invalid.193488608 +enable_masking=1 +sw_key_masked=0' seed=94376888541355977228861834328912624473065614709424392293847953515804023613152 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94376888541355977228861834328912624473065614709424392293847953515804023613152 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/11.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_burst_write 37105114927249378053882015877353990797781687427013046957241651117679084792758 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/11.kmac_burst_write/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2551671734 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_burst_write.2551671734 +enable_masking=1 +sw_key_masked=0' seed=37105114927249378053882015877353990797781687427013046957241651117679084792758 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37105114927249378053882015877353990797781687427013046957241651117679084792758 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/11.kmac_burst_write/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_burst_write_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_app 71727831388981951051954081342550123126755593343318822654340149022805956216613 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/11.kmac_app/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3355690789 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_app.3355690789 +enable_masking=1 +sw_key_masked=0' seed=71727831388981951051954081342550123126755593343318822654340149022805956216613 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71727831388981951051954081342550123126755593343318822654340149022805956216613 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/11.kmac_app/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_app_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_refresh 40303284231962630141220315089130934040146632634095582596724863119690938194327 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/11.kmac_entropy_refresh/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2186549655 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_refresh.2186549655 +enable_masking=1 +sw_key_masked=0' seed=40303284231962630141220315089130934040146632634095582596724863119690938194327 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40303284231962630141220315089130934040146632634095582596724863119690938194327 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/11.kmac_entropy_refresh/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_refresh_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_error 20485128270835982092703647551905712964881236846806163656814034340308987960049 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/11.kmac_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1806457585 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_error.1806457585 +enable_masking=1 +sw_key_masked=0' seed=20485128270835982092703647551905712964881236846806163656814034340308987960049 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20485128270835982092703647551905712964881236846806163656814034340308987960049 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/11.kmac_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_key_error 29031317933681808026996183542592863709717796289845991650460123973747887811062 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/11.kmac_key_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3577981430 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_key_error.3577981430 +enable_masking=1 +sw_key_masked=0' seed=29031317933681808026996183542592863709717796289845991650460123973747887811062 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29031317933681808026996183542592863709717796289845991650460123973747887811062 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/11.kmac_key_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_key_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_edn_timeout_error 46529389380002972726569062031989577916562085964338128276363740636785032316232 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/11.kmac_edn_timeout_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2394703176 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_edn_timeout_error.2394703176 +enable_masking=1 +sw_key_masked=0' seed=46529389380002972726569062031989577916562085964338128276363740636785032316232 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46529389380002972726569062031989577916562085964338128276363740636785032316232 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/11.kmac_edn_timeout_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_edn_timeout_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_mode_error 113017769911751184090283413058914374109618520599382253285440334734244897427219 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/11.kmac_entropy_mode_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1246039827 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_entropy_mode_error.1246039827 +enable_masking=1 +sw_key_masked=0' seed=113017769911751184090283413058914374109618520599382253285440334734244897427219 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113017769911751184090283413058914374109618520599382253285440334734244897427219 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/11.kmac_entropy_mode_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_mode_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 70098291603123996244649155036811905079718504450889557107868654243629941959033 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/11.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2284890489 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.kmac_lc_escalation.2284890489 +enable_masking=1 +sw_key_masked=0' seed=70098291603123996244649155036811905079718504450889557107868654243629941959033 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70098291603123996244649155036811905079718504450889557107868654243629941959033 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/11.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors 3404348036719570396474848248555430503154253214899842442232146309936285415285 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2017916789 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors.2017916789 +enable_masking=1 +sw_key_masked=0' seed=3404348036719570396474848248555430503154253214899842442232146309936285415285 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3404348036719570396474848248555430503154253214899842442232146309936285415285 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors_with_csr_rw 107629955681804262062464284276184278432967579551759848442671646875166721511721 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1976635689 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_shadow_reg_errors_with_csr_rw.1976635689 +enable_masking=1 +sw_key_masked=0' seed=107629955681804262062464284276184278432967579551759848442671646875166721511721 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107629955681804262062464284276184278432967579551759848442671646875166721511721 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/11.kmac_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_errors 103481381903285496887918128190361960221787797753107838545714494896740179270593 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/11.kmac_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2624216001 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_errors.2624216001 +enable_masking=1 +sw_key_masked=0' seed=103481381903285496887918128190361960221787797753107838545714494896740179270593 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103481381903285496887918128190361960221787797753107838545714494896740179270593 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/11.kmac_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_intg_err 46695121403627846615347130265813170495651928071543453061854449562788466816947 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/11.kmac_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2542041011 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.kmac_tl_intg_err.2542041011 +enable_masking=1 +sw_key_masked=0' seed=46695121403627846615347130265813170495651928071543453061854449562788466816947 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46695121403627846615347130265813170495651928071543453061854449562788466816947 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/11.kmac_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_smoke 39093141160674323157335993077679858130158751661269442638847338834211341805264 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/12.kmac_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=761472720 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_smoke.761472720 +enable_masking=1 +sw_key_masked=0' seed=39093141160674323157335993077679858130158751661269442638847338834211341805264 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39093141160674323157335993077679858130158751661269442638847338834211341805264 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/12.kmac_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_long_msg_and_output 83581788449205960514430342910767508636999710192924174219708301719222759703657 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/12.kmac_long_msg_and_output/latest run_opts='+test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=133153897 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_long_msg_and_output.133153897 +enable_masking=1 +sw_key_masked=0' seed=83581788449205960514430342910767508636999710192924174219708301719222759703657 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83581788449205960514430342910767508636999710192924174219708301719222759703657 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/12.kmac_long_msg_and_output/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_long_msg_and_output_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload 71023637669951350373905154470509726316908049481146897293232260581399128184762 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/12.kmac_sideload/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=316413882 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload.316413882 +enable_masking=1 +sw_key_masked=0' seed=71023637669951350373905154470509726316908049481146897293232260581399128184762 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71023637669951350373905154470509726316908049481146897293232260581399128184762 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/12.kmac_sideload/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 30871308706015657450425221145786219783180890402940472364912969937548838679727 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/12.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3835147439 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_sideload_invalid.3835147439 +enable_masking=1 +sw_key_masked=0' seed=30871308706015657450425221145786219783180890402940472364912969937548838679727 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30871308706015657450425221145786219783180890402940472364912969937548838679727 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/12.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_burst_write 41362501492210634450839669585769153729206305435952873909731828605016820961283 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/12.kmac_burst_write/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1751404547 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_burst_write.1751404547 +enable_masking=1 +sw_key_masked=0' seed=41362501492210634450839669585769153729206305435952873909731828605016820961283 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41362501492210634450839669585769153729206305435952873909731828605016820961283 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/12.kmac_burst_write/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_burst_write_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_app 37909688305703562114025406273166927091181386245880539919762155938966142735384 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/12.kmac_app/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=110908440 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_app.110908440 +enable_masking=1 +sw_key_masked=0' seed=37909688305703562114025406273166927091181386245880539919762155938966142735384 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37909688305703562114025406273166927091181386245880539919762155938966142735384 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/12.kmac_app/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_app_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_refresh 79648751785336970453176473531513604476951136445263853939997509060529611447709 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/12.kmac_entropy_refresh/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1325243805 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_refresh.1325243805 +enable_masking=1 +sw_key_masked=0' seed=79648751785336970453176473531513604476951136445263853939997509060529611447709 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79648751785336970453176473531513604476951136445263853939997509060529611447709 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/12.kmac_entropy_refresh/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_refresh_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_error 7781451387388449266189594896282865124770559165152651163467194169383473443733 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/12.kmac_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=243069845 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_error.243069845 +enable_masking=1 +sw_key_masked=0' seed=7781451387388449266189594896282865124770559165152651163467194169383473443733 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7781451387388449266189594896282865124770559165152651163467194169383473443733 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/12.kmac_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_key_error 112662826642688732140245572831184319995944718875463979648301784068683078330637 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/12.kmac_key_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2264426765 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_key_error.2264426765 +enable_masking=1 +sw_key_masked=0' seed=112662826642688732140245572831184319995944718875463979648301784068683078330637 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112662826642688732140245572831184319995944718875463979648301784068683078330637 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/12.kmac_key_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_key_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_edn_timeout_error 52812593452641768234260308795490296761372016942014465967963944414194506509167 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/12.kmac_edn_timeout_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=82946927 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_edn_timeout_error.82946927 +enable_masking=1 +sw_key_masked=0' seed=52812593452641768234260308795490296761372016942014465967963944414194506509167 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=52812593452641768234260308795490296761372016942014465967963944414194506509167 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/12.kmac_edn_timeout_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_edn_timeout_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_mode_error 84780979460138974285127523412921650902550404878485281782481337392674547776748 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/12.kmac_entropy_mode_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3839966444 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_entropy_mode_error.3839966444 +enable_masking=1 +sw_key_masked=0' seed=84780979460138974285127523412921650902550404878485281782481337392674547776748 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84780979460138974285127523412921650902550404878485281782481337392674547776748 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/12.kmac_entropy_mode_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_mode_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 54358467411523437314146894469143619352839990088062374333245867870694405241555 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/12.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2446523091 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.kmac_lc_escalation.2446523091 +enable_masking=1 +sw_key_masked=0' seed=54358467411523437314146894469143619352839990088062374333245867870694405241555 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54358467411523437314146894469143619352839990088062374333245867870694405241555 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/12.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors 90208447686765097626030995821150863451281331215176865068539833582483685389739 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/12.kmac_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=169489835 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors.169489835 +enable_masking=1 +sw_key_masked=0' seed=90208447686765097626030995821150863451281331215176865068539833582483685389739 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90208447686765097626030995821150863451281331215176865068539833582483685389739 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/12.kmac_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors_with_csr_rw 43325676746198065871252172955920346548642940579809655391218384080708945732510 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/12.kmac_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=374498206 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_shadow_reg_errors_with_csr_rw.374498206 +enable_masking=1 +sw_key_masked=0' seed=43325676746198065871252172955920346548642940579809655391218384080708945732510 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43325676746198065871252172955920346548642940579809655391218384080708945732510 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/12.kmac_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_errors 79608034158673120150241808723653349930483256907254860392837336772464749226120 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/12.kmac_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3061229704 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_errors.3061229704 +enable_masking=1 +sw_key_masked=0' seed=79608034158673120150241808723653349930483256907254860392837336772464749226120 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79608034158673120150241808723653349930483256907254860392837336772464749226120 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/12.kmac_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_intg_err 102265168144148955383632619297272176673002175771052259078875918648915235240063 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/12.kmac_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4101044351 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.kmac_tl_intg_err.4101044351 +enable_masking=1 +sw_key_masked=0' seed=102265168144148955383632619297272176673002175771052259078875918648915235240063 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102265168144148955383632619297272176673002175771052259078875918648915235240063 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/12.kmac_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_smoke 6273762273837852842823401874111850235600883738426688147434504552627487768955 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/13.kmac_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3779985787 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_smoke.3779985787 +enable_masking=1 +sw_key_masked=0' seed=6273762273837852842823401874111850235600883738426688147434504552627487768955 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6273762273837852842823401874111850235600883738426688147434504552627487768955 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/13.kmac_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_long_msg_and_output 54234981445802287198192278685852316318187705887437141692878590792429679257657 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/13.kmac_long_msg_and_output/latest run_opts='+test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=25012281 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_long_msg_and_output.25012281 +enable_masking=1 +sw_key_masked=0' seed=54234981445802287198192278685852316318187705887437141692878590792429679257657 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54234981445802287198192278685852316318187705887437141692878590792429679257657 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/13.kmac_long_msg_and_output/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_long_msg_and_output_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload 70207898416042125798920518449732198773612584495962188387746728124658254728591 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/13.kmac_sideload/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4173450639 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload.4173450639 +enable_masking=1 +sw_key_masked=0' seed=70207898416042125798920518449732198773612584495962188387746728124658254728591 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70207898416042125798920518449732198773612584495962188387746728124658254728591 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/13.kmac_sideload/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 31854265673397638177101524398322496511400409769053441104287468594293457140150 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/13.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2959456694 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_sideload_invalid.2959456694 +enable_masking=1 +sw_key_masked=0' seed=31854265673397638177101524398322496511400409769053441104287468594293457140150 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31854265673397638177101524398322496511400409769053441104287468594293457140150 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/13.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_burst_write 56250709301046812172102713249707777971188464280759347148013530544891136024105 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/13.kmac_burst_write/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3307445801 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_burst_write.3307445801 +enable_masking=1 +sw_key_masked=0' seed=56250709301046812172102713249707777971188464280759347148013530544891136024105 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56250709301046812172102713249707777971188464280759347148013530544891136024105 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/13.kmac_burst_write/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_burst_write_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_app 9074415610238504548611021971404147328092293714102163548668561069358013939468 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/13.kmac_app/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2369191692 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_app.2369191692 +enable_masking=1 +sw_key_masked=0' seed=9074415610238504548611021971404147328092293714102163548668561069358013939468 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9074415610238504548611021971404147328092293714102163548668561069358013939468 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/13.kmac_app/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_app_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_refresh 23895607520007330047822314684112696267694582688397716678390795798101674465191 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/13.kmac_entropy_refresh/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3981744039 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_refresh.3981744039 +enable_masking=1 +sw_key_masked=0' seed=23895607520007330047822314684112696267694582688397716678390795798101674465191 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23895607520007330047822314684112696267694582688397716678390795798101674465191 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/13.kmac_entropy_refresh/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_refresh_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_error 75199941789504109683324435292301484287523825533701416427560054926964338939001 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/13.kmac_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=497243257 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_error.497243257 +enable_masking=1 +sw_key_masked=0' seed=75199941789504109683324435292301484287523825533701416427560054926964338939001 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75199941789504109683324435292301484287523825533701416427560054926964338939001 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/13.kmac_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_key_error 103818616624903567091761015287181713227651445727538039728893228497980871324996 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/13.kmac_key_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3415127364 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_key_error.3415127364 +enable_masking=1 +sw_key_masked=0' seed=103818616624903567091761015287181713227651445727538039728893228497980871324996 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103818616624903567091761015287181713227651445727538039728893228497980871324996 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/13.kmac_key_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_key_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_edn_timeout_error 81766734191203718327659830018442155895280884386333884086501174035670179594254 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/13.kmac_edn_timeout_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3082895374 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_edn_timeout_error.3082895374 +enable_masking=1 +sw_key_masked=0' seed=81766734191203718327659830018442155895280884386333884086501174035670179594254 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81766734191203718327659830018442155895280884386333884086501174035670179594254 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/13.kmac_edn_timeout_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_edn_timeout_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_mode_error 93675201091219530751470522030667583985029238006211314839984028438486457562108 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/13.kmac_entropy_mode_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1409332220 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_entropy_mode_error.1409332220 +enable_masking=1 +sw_key_masked=0' seed=93675201091219530751470522030667583985029238006211314839984028438486457562108 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93675201091219530751470522030667583985029238006211314839984028438486457562108 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/13.kmac_entropy_mode_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_mode_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 71562725145573354199771279229192831821045231059330740659865334155671405926938 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/13.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4036565530 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.kmac_lc_escalation.4036565530 +enable_masking=1 +sw_key_masked=0' seed=71562725145573354199771279229192831821045231059330740659865334155671405926938 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71562725145573354199771279229192831821045231059330740659865334155671405926938 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/13.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors 35368732263098285487614968120904467100383920954796724601578398850919993545997 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/13.kmac_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=905286925 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors.905286925 +enable_masking=1 +sw_key_masked=0' seed=35368732263098285487614968120904467100383920954796724601578398850919993545997 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35368732263098285487614968120904467100383920954796724601578398850919993545997 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/13.kmac_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors_with_csr_rw 103784030253313080143283999036618524359392375224413440685022113547711617391979 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/13.kmac_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3703266667 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_shadow_reg_errors_with_csr_rw.3703266667 +enable_masking=1 +sw_key_masked=0' seed=103784030253313080143283999036618524359392375224413440685022113547711617391979 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103784030253313080143283999036618524359392375224413440685022113547711617391979 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/13.kmac_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_errors 112984085672087662488793314709268943343695574629544068619604911929453068921219 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/13.kmac_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3342051715 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_errors.3342051715 +enable_masking=1 +sw_key_masked=0' seed=112984085672087662488793314709268943343695574629544068619604911929453068921219 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112984085672087662488793314709268943343695574629544068619604911929453068921219 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/13.kmac_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_intg_err 89622432460352826787283373933654904248204818338641085440214822874074694359182 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/13.kmac_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3802208398 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.kmac_tl_intg_err.3802208398 +enable_masking=1 +sw_key_masked=0' seed=89622432460352826787283373933654904248204818338641085440214822874074694359182 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89622432460352826787283373933654904248204818338641085440214822874074694359182 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/13.kmac_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_smoke 77412096232843512361866479575304616561088842304916252522688336081024189973897 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/14.kmac_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2576860553 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_smoke.2576860553 +enable_masking=1 +sw_key_masked=0' seed=77412096232843512361866479575304616561088842304916252522688336081024189973897 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77412096232843512361866479575304616561088842304916252522688336081024189973897 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/14.kmac_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_long_msg_and_output 51010532169769113440539160697913538223032125721558801490451641590986435878644 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/14.kmac_long_msg_and_output/latest run_opts='+test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=168189684 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_long_msg_and_output.168189684 +enable_masking=1 +sw_key_masked=0' seed=51010532169769113440539160697913538223032125721558801490451641590986435878644 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51010532169769113440539160697913538223032125721558801490451641590986435878644 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/14.kmac_long_msg_and_output/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_long_msg_and_output_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload 58240718677915079425626788465950557530025399441827212067309606745259455798724 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/14.kmac_sideload/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2794970564 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload.2794970564 +enable_masking=1 +sw_key_masked=0' seed=58240718677915079425626788465950557530025399441827212067309606745259455798724 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58240718677915079425626788465950557530025399441827212067309606745259455798724 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/14.kmac_sideload/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 76010314046671963376916913640392321778928897825797035057641675768795007935903 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/14.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3200378271 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_sideload_invalid.3200378271 +enable_masking=1 +sw_key_masked=0' seed=76010314046671963376916913640392321778928897825797035057641675768795007935903 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76010314046671963376916913640392321778928897825797035057641675768795007935903 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/14.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_burst_write 74719439271370529883836650369600969856910568884531839082688838821143549495616 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/14.kmac_burst_write/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3462056256 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_burst_write.3462056256 +enable_masking=1 +sw_key_masked=0' seed=74719439271370529883836650369600969856910568884531839082688838821143549495616 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74719439271370529883836650369600969856910568884531839082688838821143549495616 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/14.kmac_burst_write/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_burst_write_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_app 12241400752066389072321699255838321556510035648825137121420485633034880341311 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/14.kmac_app/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3253523775 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_app.3253523775 +enable_masking=1 +sw_key_masked=0' seed=12241400752066389072321699255838321556510035648825137121420485633034880341311 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12241400752066389072321699255838321556510035648825137121420485633034880341311 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/14.kmac_app/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_app_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_refresh 69137603520618486713194929410384335397990084749932037210944530666781399521818 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/14.kmac_entropy_refresh/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1282087450 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_refresh.1282087450 +enable_masking=1 +sw_key_masked=0' seed=69137603520618486713194929410384335397990084749932037210944530666781399521818 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69137603520618486713194929410384335397990084749932037210944530666781399521818 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/14.kmac_entropy_refresh/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_refresh_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_error 24897862722860276088476760121319316499015500930282093445063115840517835472590 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/14.kmac_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=250232526 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_error.250232526 +enable_masking=1 +sw_key_masked=0' seed=24897862722860276088476760121319316499015500930282093445063115840517835472590 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24897862722860276088476760121319316499015500930282093445063115840517835472590 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/14.kmac_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_key_error 56691880405957506661072432491616300239470406791837498935894743053490331113130 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/14.kmac_key_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2414139050 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_key_error.2414139050 +enable_masking=1 +sw_key_masked=0' seed=56691880405957506661072432491616300239470406791837498935894743053490331113130 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56691880405957506661072432491616300239470406791837498935894743053490331113130 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/14.kmac_key_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_key_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_edn_timeout_error 69217342011459051164493449598032426639654090636449249691512229386418375539326 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/14.kmac_edn_timeout_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2725427838 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_edn_timeout_error.2725427838 +enable_masking=1 +sw_key_masked=0' seed=69217342011459051164493449598032426639654090636449249691512229386418375539326 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69217342011459051164493449598032426639654090636449249691512229386418375539326 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/14.kmac_edn_timeout_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_edn_timeout_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_mode_error 31583730468118434807195030720516784905445311563278399884905125096189084453341 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/14.kmac_entropy_mode_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1495681501 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_entropy_mode_error.1495681501 +enable_masking=1 +sw_key_masked=0' seed=31583730468118434807195030720516784905445311563278399884905125096189084453341 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31583730468118434807195030720516784905445311563278399884905125096189084453341 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/14.kmac_entropy_mode_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_mode_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 4858771180886669966647154704137990059502764194346998323381983200189699491213 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/14.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3151398285 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.kmac_lc_escalation.3151398285 +enable_masking=1 +sw_key_masked=0' seed=4858771180886669966647154704137990059502764194346998323381983200189699491213 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4858771180886669966647154704137990059502764194346998323381983200189699491213 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/14.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors 5300294444948835200996271354204043669822923912075516035130027163168940715886 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/14.kmac_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=139947886 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors.139947886 +enable_masking=1 +sw_key_masked=0' seed=5300294444948835200996271354204043669822923912075516035130027163168940715886 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5300294444948835200996271354204043669822923912075516035130027163168940715886 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/14.kmac_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors_with_csr_rw 43780100715432322488692206300676143964671214238778270479691971785362852738489 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/14.kmac_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1158608313 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_shadow_reg_errors_with_csr_rw.1158608313 +enable_masking=1 +sw_key_masked=0' seed=43780100715432322488692206300676143964671214238778270479691971785362852738489 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43780100715432322488692206300676143964671214238778270479691971785362852738489 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/14.kmac_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_errors 69646746131639472548617517893153106402376205692320489014288335985939352018980 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/14.kmac_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2329567268 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_errors.2329567268 +enable_masking=1 +sw_key_masked=0' seed=69646746131639472548617517893153106402376205692320489014288335985939352018980 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69646746131639472548617517893153106402376205692320489014288335985939352018980 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/14.kmac_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_intg_err 63325036818920542723371728522594707674600796154355515553024024429971428709184 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/14.kmac_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2900464448 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.kmac_tl_intg_err.2900464448 +enable_masking=1 +sw_key_masked=0' seed=63325036818920542723371728522594707674600796154355515553024024429971428709184 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63325036818920542723371728522594707674600796154355515553024024429971428709184 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/14.kmac_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_smoke 32260825720229880061597973595335981236052576713206679794562605772902731836139 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/15.kmac_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3333122795 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_smoke.3333122795 +enable_masking=1 +sw_key_masked=0' seed=32260825720229880061597973595335981236052576713206679794562605772902731836139 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32260825720229880061597973595335981236052576713206679794562605772902731836139 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/15.kmac_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_long_msg_and_output 103386049587410235565240137884065891541641560304353886300545648030876466290809 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/15.kmac_long_msg_and_output/latest run_opts='+test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1889935481 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_long_msg_and_output.1889935481 +enable_masking=1 +sw_key_masked=0' seed=103386049587410235565240137884065891541641560304353886300545648030876466290809 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103386049587410235565240137884065891541641560304353886300545648030876466290809 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/15.kmac_long_msg_and_output/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_long_msg_and_output_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload 39086077931597752674180556299532611147613310076236084621409487202372658292900 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/15.kmac_sideload/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=820668580 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload.820668580 +enable_masking=1 +sw_key_masked=0' seed=39086077931597752674180556299532611147613310076236084621409487202372658292900 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39086077931597752674180556299532611147613310076236084621409487202372658292900 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/15.kmac_sideload/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 107322487457038053100473631482941498056030878359494794663213815132259387058299 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/15.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1045309563 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_sideload_invalid.1045309563 +enable_masking=1 +sw_key_masked=0' seed=107322487457038053100473631482941498056030878359494794663213815132259387058299 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107322487457038053100473631482941498056030878359494794663213815132259387058299 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/15.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_burst_write 8960849298181958562933919018719267085359341575254810342351789302198483056035 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/15.kmac_burst_write/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=786462115 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_burst_write.786462115 +enable_masking=1 +sw_key_masked=0' seed=8960849298181958562933919018719267085359341575254810342351789302198483056035 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8960849298181958562933919018719267085359341575254810342351789302198483056035 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/15.kmac_burst_write/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_burst_write_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_app 94248823711737282215341517948767170588756410256367312721546570259380994061414 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/15.kmac_app/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2380543078 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_app.2380543078 +enable_masking=1 +sw_key_masked=0' seed=94248823711737282215341517948767170588756410256367312721546570259380994061414 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94248823711737282215341517948767170588756410256367312721546570259380994061414 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/15.kmac_app/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_app_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_refresh 101608992873805883741724701557141787336032680878345948632140877525748668929441 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/15.kmac_entropy_refresh/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1683723681 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_refresh.1683723681 +enable_masking=1 +sw_key_masked=0' seed=101608992873805883741724701557141787336032680878345948632140877525748668929441 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101608992873805883741724701557141787336032680878345948632140877525748668929441 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/15.kmac_entropy_refresh/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_refresh_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_error 7673540846401512250746080960124454403668476713642974847853037146997063150139 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/15.kmac_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=771746363 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_error.771746363 +enable_masking=1 +sw_key_masked=0' seed=7673540846401512250746080960124454403668476713642974847853037146997063150139 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7673540846401512250746080960124454403668476713642974847853037146997063150139 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/15.kmac_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_key_error 62423707607661011574717071059240899370070630139455501009099403233953669281286 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/15.kmac_key_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3055646214 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_key_error.3055646214 +enable_masking=1 +sw_key_masked=0' seed=62423707607661011574717071059240899370070630139455501009099403233953669281286 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62423707607661011574717071059240899370070630139455501009099403233953669281286 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/15.kmac_key_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_key_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_edn_timeout_error 3639542805977157237573081200449953901665055463013206828213956980429916493584 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/15.kmac_edn_timeout_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3756021520 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_edn_timeout_error.3756021520 +enable_masking=1 +sw_key_masked=0' seed=3639542805977157237573081200449953901665055463013206828213956980429916493584 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3639542805977157237573081200449953901665055463013206828213956980429916493584 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/15.kmac_edn_timeout_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_edn_timeout_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_mode_error 84806337016386045335631861558959580423053138816457133038145729519950384749065 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/15.kmac_entropy_mode_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1134713353 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_entropy_mode_error.1134713353 +enable_masking=1 +sw_key_masked=0' seed=84806337016386045335631861558959580423053138816457133038145729519950384749065 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84806337016386045335631861558959580423053138816457133038145729519950384749065 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/15.kmac_entropy_mode_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_mode_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 74395978462698532899145187032775841744143509685337470997602784925370393436898 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/15.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=432415458 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.kmac_lc_escalation.432415458 +enable_masking=1 +sw_key_masked=0' seed=74395978462698532899145187032775841744143509685337470997602784925370393436898 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74395978462698532899145187032775841744143509685337470997602784925370393436898 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/15.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors 10077021510483373962472116707680288056798604673797236006220524986496225421338 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/15.kmac_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3642009626 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors.3642009626 +enable_masking=1 +sw_key_masked=0' seed=10077021510483373962472116707680288056798604673797236006220524986496225421338 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10077021510483373962472116707680288056798604673797236006220524986496225421338 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/15.kmac_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors_with_csr_rw 45645334165902120692300425186781388626664071044612733627495734233262963869471 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/15.kmac_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3195586335 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_shadow_reg_errors_with_csr_rw.3195586335 +enable_masking=1 +sw_key_masked=0' seed=45645334165902120692300425186781388626664071044612733627495734233262963869471 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45645334165902120692300425186781388626664071044612733627495734233262963869471 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/15.kmac_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_errors 41212822002860874704851940462261498536336592409558434952093007822275074682638 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/15.kmac_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3950866190 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_errors.3950866190 +enable_masking=1 +sw_key_masked=0' seed=41212822002860874704851940462261498536336592409558434952093007822275074682638 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41212822002860874704851940462261498536336592409558434952093007822275074682638 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/15.kmac_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_intg_err 20053203196490599967600143731152416894842083494118856304000392655217015704565 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/15.kmac_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=258788341 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.kmac_tl_intg_err.258788341 +enable_masking=1 +sw_key_masked=0' seed=20053203196490599967600143731152416894842083494118856304000392655217015704565 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20053203196490599967600143731152416894842083494118856304000392655217015704565 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/15.kmac_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_smoke 63900446704530692552680984384180193665453908918796903786128300658928126940562 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/16.kmac_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3251525010 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_smoke.3251525010 +enable_masking=1 +sw_key_masked=0' seed=63900446704530692552680984384180193665453908918796903786128300658928126940562 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63900446704530692552680984384180193665453908918796903786128300658928126940562 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/16.kmac_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_long_msg_and_output 19299756447426647940362896720205060799602458650276972908786714012762148921178 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/16.kmac_long_msg_and_output/latest run_opts='+test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2038652762 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_long_msg_and_output.2038652762 +enable_masking=1 +sw_key_masked=0' seed=19299756447426647940362896720205060799602458650276972908786714012762148921178 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19299756447426647940362896720205060799602458650276972908786714012762148921178 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/16.kmac_long_msg_and_output/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_long_msg_and_output_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload 35397903266807375068053181041746577997635936947646188043958770093915969095547 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/16.kmac_sideload/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1511982971 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload.1511982971 +enable_masking=1 +sw_key_masked=0' seed=35397903266807375068053181041746577997635936947646188043958770093915969095547 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35397903266807375068053181041746577997635936947646188043958770093915969095547 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/16.kmac_sideload/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 4475575037972409071609262605995125098306767987627731240645432576201419542815 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/16.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2413449503 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_sideload_invalid.2413449503 +enable_masking=1 +sw_key_masked=0' seed=4475575037972409071609262605995125098306767987627731240645432576201419542815 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4475575037972409071609262605995125098306767987627731240645432576201419542815 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/16.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_burst_write 3206561723281305840949460164514906222342235517371178191347755401241933206477 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/16.kmac_burst_write/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3359462349 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_burst_write.3359462349 +enable_masking=1 +sw_key_masked=0' seed=3206561723281305840949460164514906222342235517371178191347755401241933206477 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3206561723281305840949460164514906222342235517371178191347755401241933206477 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/16.kmac_burst_write/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_burst_write_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_app 104579240478278770080005753010483304555391286449377179256175854907286045097443 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/16.kmac_app/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=888700387 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_app.888700387 +enable_masking=1 +sw_key_masked=0' seed=104579240478278770080005753010483304555391286449377179256175854907286045097443 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104579240478278770080005753010483304555391286449377179256175854907286045097443 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/16.kmac_app/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_app_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_refresh 91188625139993528791433434397884025254279658479961270979382587172189203620651 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/16.kmac_entropy_refresh/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1519412011 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_refresh.1519412011 +enable_masking=1 +sw_key_masked=0' seed=91188625139993528791433434397884025254279658479961270979382587172189203620651 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91188625139993528791433434397884025254279658479961270979382587172189203620651 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/16.kmac_entropy_refresh/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_refresh_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_error 85833379742173337065628366493580359405595708818113725441013599414915034736504 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/16.kmac_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1516988280 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_error.1516988280 +enable_masking=1 +sw_key_masked=0' seed=85833379742173337065628366493580359405595708818113725441013599414915034736504 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85833379742173337065628366493580359405595708818113725441013599414915034736504 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/16.kmac_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_key_error 11907720960204981993664021361334198467353957500361014623837754700933492529982 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/16.kmac_key_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=600726334 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_key_error.600726334 +enable_masking=1 +sw_key_masked=0' seed=11907720960204981993664021361334198467353957500361014623837754700933492529982 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11907720960204981993664021361334198467353957500361014623837754700933492529982 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/16.kmac_key_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_key_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_edn_timeout_error 17278528400947921210017525289754579776812622565907676749368874404535206500918 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/16.kmac_edn_timeout_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=349788726 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_edn_timeout_error.349788726 +enable_masking=1 +sw_key_masked=0' seed=17278528400947921210017525289754579776812622565907676749368874404535206500918 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17278528400947921210017525289754579776812622565907676749368874404535206500918 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/16.kmac_edn_timeout_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_edn_timeout_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_mode_error 97847549759332964571818623956881661967914378390516245713787774028323818915870 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/16.kmac_entropy_mode_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2958903326 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_entropy_mode_error.2958903326 +enable_masking=1 +sw_key_masked=0' seed=97847549759332964571818623956881661967914378390516245713787774028323818915870 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97847549759332964571818623956881661967914378390516245713787774028323818915870 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/16.kmac_entropy_mode_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_mode_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 7908784488167158788647092336034484302190168321437195088463645079573607369656 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/16.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2224442296 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.kmac_lc_escalation.2224442296 +enable_masking=1 +sw_key_masked=0' seed=7908784488167158788647092336034484302190168321437195088463645079573607369656 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7908784488167158788647092336034484302190168321437195088463645079573607369656 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/16.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors 109759215378091567117132391428270476476260875165952367949449667806885029550375 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/16.kmac_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2369984807 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors.2369984807 +enable_masking=1 +sw_key_masked=0' seed=109759215378091567117132391428270476476260875165952367949449667806885029550375 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109759215378091567117132391428270476476260875165952367949449667806885029550375 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/16.kmac_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors_with_csr_rw 11257138159090598970896185863390480205032868568421960796252560455798273557985 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/16.kmac_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2287420897 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_shadow_reg_errors_with_csr_rw.2287420897 +enable_masking=1 +sw_key_masked=0' seed=11257138159090598970896185863390480205032868568421960796252560455798273557985 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11257138159090598970896185863390480205032868568421960796252560455798273557985 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/16.kmac_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_errors 84069474149541702687195394294403219145959966871385026124301534710367996471736 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/16.kmac_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3459901880 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_errors.3459901880 +enable_masking=1 +sw_key_masked=0' seed=84069474149541702687195394294403219145959966871385026124301534710367996471736 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84069474149541702687195394294403219145959966871385026124301534710367996471736 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/16.kmac_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_intg_err 16999769349848014945555712937050032571552503335050572525164164550993484826641 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/16.kmac_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1347012625 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.kmac_tl_intg_err.1347012625 +enable_masking=1 +sw_key_masked=0' seed=16999769349848014945555712937050032571552503335050572525164164550993484826641 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16999769349848014945555712937050032571552503335050572525164164550993484826641 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/16.kmac_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_smoke 52711604637230175653432241156569852909802305716100781662283943409775416944185 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/17.kmac_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3349653049 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_smoke.3349653049 +enable_masking=1 +sw_key_masked=0' seed=52711604637230175653432241156569852909802305716100781662283943409775416944185 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=52711604637230175653432241156569852909802305716100781662283943409775416944185 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/17.kmac_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_long_msg_and_output 96694720126925521584359723035171930067387202338653811208262718838255348024295 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/17.kmac_long_msg_and_output/latest run_opts='+test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=844301287 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_long_msg_and_output.844301287 +enable_masking=1 +sw_key_masked=0' seed=96694720126925521584359723035171930067387202338653811208262718838255348024295 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96694720126925521584359723035171930067387202338653811208262718838255348024295 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/17.kmac_long_msg_and_output/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_long_msg_and_output_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload 79838808588120864093615656220782535895014358692620439009577129657634176126825 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/17.kmac_sideload/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2122338153 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload.2122338153 +enable_masking=1 +sw_key_masked=0' seed=79838808588120864093615656220782535895014358692620439009577129657634176126825 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79838808588120864093615656220782535895014358692620439009577129657634176126825 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/17.kmac_sideload/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 93552162420541947356719321999544797854086553855478422572373481032569968296574 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/17.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2324595326 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_sideload_invalid.2324595326 +enable_masking=1 +sw_key_masked=0' seed=93552162420541947356719321999544797854086553855478422572373481032569968296574 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93552162420541947356719321999544797854086553855478422572373481032569968296574 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/17.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_burst_write 50734574662976434803766274834044657163602477426672474366672657856738361042245 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/17.kmac_burst_write/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=475751749 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_burst_write.475751749 +enable_masking=1 +sw_key_masked=0' seed=50734574662976434803766274834044657163602477426672474366672657856738361042245 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50734574662976434803766274834044657163602477426672474366672657856738361042245 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/17.kmac_burst_write/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_burst_write_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_app 29805270300107070025228036239775767641296255944968329778055391405660969587840 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/17.kmac_app/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2867287168 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_app.2867287168 +enable_masking=1 +sw_key_masked=0' seed=29805270300107070025228036239775767641296255944968329778055391405660969587840 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29805270300107070025228036239775767641296255944968329778055391405660969587840 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/17.kmac_app/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_app_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_refresh 66987361629484254398194276774644265937529596243538372483358962952926511155834 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/17.kmac_entropy_refresh/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=299289210 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_refresh.299289210 +enable_masking=1 +sw_key_masked=0' seed=66987361629484254398194276774644265937529596243538372483358962952926511155834 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66987361629484254398194276774644265937529596243538372483358962952926511155834 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/17.kmac_entropy_refresh/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_refresh_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_error 17437632263116143334966351716881123575131881669200601766738542672963938556613 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/17.kmac_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2798394053 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_error.2798394053 +enable_masking=1 +sw_key_masked=0' seed=17437632263116143334966351716881123575131881669200601766738542672963938556613 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17437632263116143334966351716881123575131881669200601766738542672963938556613 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/17.kmac_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_key_error 5290789962536028598264223576166482341662031531642485639390210271782035405299 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/17.kmac_key_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2738502131 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_key_error.2738502131 +enable_masking=1 +sw_key_masked=0' seed=5290789962536028598264223576166482341662031531642485639390210271782035405299 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5290789962536028598264223576166482341662031531642485639390210271782035405299 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/17.kmac_key_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_key_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_edn_timeout_error 54266982879496717083618308408649002930343741331553383941433174412491062549877 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/17.kmac_edn_timeout_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3346046325 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_edn_timeout_error.3346046325 +enable_masking=1 +sw_key_masked=0' seed=54266982879496717083618308408649002930343741331553383941433174412491062549877 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54266982879496717083618308408649002930343741331553383941433174412491062549877 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/17.kmac_edn_timeout_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_edn_timeout_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_mode_error 101986169463542861436264708928240868365676579925262970946387659359251647298815 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/17.kmac_entropy_mode_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1731853567 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_entropy_mode_error.1731853567 +enable_masking=1 +sw_key_masked=0' seed=101986169463542861436264708928240868365676579925262970946387659359251647298815 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101986169463542861436264708928240868365676579925262970946387659359251647298815 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/17.kmac_entropy_mode_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_mode_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 82692769708966130485534252864111764665118742582532428324265992886334212003867 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/17.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=437245979 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.kmac_lc_escalation.437245979 +enable_masking=1 +sw_key_masked=0' seed=82692769708966130485534252864111764665118742582532428324265992886334212003867 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82692769708966130485534252864111764665118742582532428324265992886334212003867 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/17.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors 83198665626849213439656996996119475542160203957899480341491019889147860182669 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/17.kmac_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2298701453 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors.2298701453 +enable_masking=1 +sw_key_masked=0' seed=83198665626849213439656996996119475542160203957899480341491019889147860182669 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83198665626849213439656996996119475542160203957899480341491019889147860182669 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/17.kmac_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors_with_csr_rw 76289478435029573842871155029159256328474685097791553963714992348251092840947 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/17.kmac_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=967209459 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_shadow_reg_errors_with_csr_rw.967209459 +enable_masking=1 +sw_key_masked=0' seed=76289478435029573842871155029159256328474685097791553963714992348251092840947 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76289478435029573842871155029159256328474685097791553963714992348251092840947 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/17.kmac_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_errors 8748838176827503054051637373589370274128430916453744536790690999774632459627 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/17.kmac_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1752153451 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_errors.1752153451 +enable_masking=1 +sw_key_masked=0' seed=8748838176827503054051637373589370274128430916453744536790690999774632459627 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8748838176827503054051637373589370274128430916453744536790690999774632459627 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/17.kmac_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_intg_err 101825889461394735703473415949884600277634878525421970724237529875985930302078 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/17.kmac_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1115075198 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.kmac_tl_intg_err.1115075198 +enable_masking=1 +sw_key_masked=0' seed=101825889461394735703473415949884600277634878525421970724237529875985930302078 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101825889461394735703473415949884600277634878525421970724237529875985930302078 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/17.kmac_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_smoke 97032726636573246165034376265833981587858796824386077923309650621484647479225 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/18.kmac_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4282021817 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_smoke.4282021817 +enable_masking=1 +sw_key_masked=0' seed=97032726636573246165034376265833981587858796824386077923309650621484647479225 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97032726636573246165034376265833981587858796824386077923309650621484647479225 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/18.kmac_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_long_msg_and_output 34740524964703946673728261609636964326018537005612653582851370998189768392731 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/18.kmac_long_msg_and_output/latest run_opts='+test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1872838683 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_long_msg_and_output.1872838683 +enable_masking=1 +sw_key_masked=0' seed=34740524964703946673728261609636964326018537005612653582851370998189768392731 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34740524964703946673728261609636964326018537005612653582851370998189768392731 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/18.kmac_long_msg_and_output/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_long_msg_and_output_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload 74447436968422726756115344514917981838443949955373344925194791762894469629355 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/18.kmac_sideload/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3105523115 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload.3105523115 +enable_masking=1 +sw_key_masked=0' seed=74447436968422726756115344514917981838443949955373344925194791762894469629355 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74447436968422726756115344514917981838443949955373344925194791762894469629355 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/18.kmac_sideload/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 92667071441541035202651872210499837798141875013920162528525198804078729411373 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/18.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4037327661 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_sideload_invalid.4037327661 +enable_masking=1 +sw_key_masked=0' seed=92667071441541035202651872210499837798141875013920162528525198804078729411373 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92667071441541035202651872210499837798141875013920162528525198804078729411373 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/18.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_burst_write 86358213991053463922982614167716841018805236756138382230667099419002522150299 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/18.kmac_burst_write/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3431835035 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_burst_write.3431835035 +enable_masking=1 +sw_key_masked=0' seed=86358213991053463922982614167716841018805236756138382230667099419002522150299 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86358213991053463922982614167716841018805236756138382230667099419002522150299 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/18.kmac_burst_write/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_burst_write_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_app 113516559550569047572304863097321939870480671674940227292095557513495835513685 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/18.kmac_app/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1147081557 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_app.1147081557 +enable_masking=1 +sw_key_masked=0' seed=113516559550569047572304863097321939870480671674940227292095557513495835513685 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113516559550569047572304863097321939870480671674940227292095557513495835513685 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/18.kmac_app/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_app_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_refresh 59274801885219398051842215463382014909239355291527870745808583631692817649859 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/18.kmac_entropy_refresh/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1666076867 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_refresh.1666076867 +enable_masking=1 +sw_key_masked=0' seed=59274801885219398051842215463382014909239355291527870745808583631692817649859 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=59274801885219398051842215463382014909239355291527870745808583631692817649859 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/18.kmac_entropy_refresh/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_refresh_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_error 103755739507675983310241258884076767916333678797152262325863953801137666221070 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/18.kmac_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2117166094 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_error.2117166094 +enable_masking=1 +sw_key_masked=0' seed=103755739507675983310241258884076767916333678797152262325863953801137666221070 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103755739507675983310241258884076767916333678797152262325863953801137666221070 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/18.kmac_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_key_error 24935267288608997348402041091846974191089672754820624358251854386325889388663 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/18.kmac_key_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2992803959 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_key_error.2992803959 +enable_masking=1 +sw_key_masked=0' seed=24935267288608997348402041091846974191089672754820624358251854386325889388663 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24935267288608997348402041091846974191089672754820624358251854386325889388663 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/18.kmac_key_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_key_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_edn_timeout_error 25570712549402689949478399638111486754631339252519246936447672239307230610224 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/18.kmac_edn_timeout_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3861185328 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_edn_timeout_error.3861185328 +enable_masking=1 +sw_key_masked=0' seed=25570712549402689949478399638111486754631339252519246936447672239307230610224 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25570712549402689949478399638111486754631339252519246936447672239307230610224 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/18.kmac_edn_timeout_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_edn_timeout_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_mode_error 65735081688969665096375705391162660795615995859086684673150383627547233658333 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/18.kmac_entropy_mode_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4062356957 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_entropy_mode_error.4062356957 +enable_masking=1 +sw_key_masked=0' seed=65735081688969665096375705391162660795615995859086684673150383627547233658333 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65735081688969665096375705391162660795615995859086684673150383627547233658333 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/18.kmac_entropy_mode_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_mode_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 11658751429562193630752849981560276187804732589794466536132022109034516715630 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/18.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=222435438 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.kmac_lc_escalation.222435438 +enable_masking=1 +sw_key_masked=0' seed=11658751429562193630752849981560276187804732589794466536132022109034516715630 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11658751429562193630752849981560276187804732589794466536132022109034516715630 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/18.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors 15632533246006769102570632270801516421001466610635725354248253261091499350441 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/18.kmac_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3781106089 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors.3781106089 +enable_masking=1 +sw_key_masked=0' seed=15632533246006769102570632270801516421001466610635725354248253261091499350441 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15632533246006769102570632270801516421001466610635725354248253261091499350441 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/18.kmac_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors_with_csr_rw 57057502171340945978901414654761678099759952135659490160167225112664467220251 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/18.kmac_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=138323739 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_shadow_reg_errors_with_csr_rw.138323739 +enable_masking=1 +sw_key_masked=0' seed=57057502171340945978901414654761678099759952135659490160167225112664467220251 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57057502171340945978901414654761678099759952135659490160167225112664467220251 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/18.kmac_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_errors 76556988687363873487812776876209968057652702469416111590043323275268990561490 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/18.kmac_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=912649426 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_errors.912649426 +enable_masking=1 +sw_key_masked=0' seed=76556988687363873487812776876209968057652702469416111590043323275268990561490 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76556988687363873487812776876209968057652702469416111590043323275268990561490 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/18.kmac_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_intg_err 102184391556754202522127880087875197802076622201454206535667206782578641947086 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/18.kmac_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2174568910 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.kmac_tl_intg_err.2174568910 +enable_masking=1 +sw_key_masked=0' seed=102184391556754202522127880087875197802076622201454206535667206782578641947086 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102184391556754202522127880087875197802076622201454206535667206782578641947086 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/18.kmac_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_smoke 56796730390962682030301538738045455511763023331785019263538037996941812390774 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/19.kmac_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=80698230 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_smoke.80698230 +enable_masking=1 +sw_key_masked=0' seed=56796730390962682030301538738045455511763023331785019263538037996941812390774 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56796730390962682030301538738045455511763023331785019263538037996941812390774 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/19.kmac_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_long_msg_and_output 5195458857915058278683052122868211141482374894688993279600886081987489706759 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/19.kmac_long_msg_and_output/latest run_opts='+test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3992072967 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_long_msg_and_output.3992072967 +enable_masking=1 +sw_key_masked=0' seed=5195458857915058278683052122868211141482374894688993279600886081987489706759 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5195458857915058278683052122868211141482374894688993279600886081987489706759 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/19.kmac_long_msg_and_output/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_long_msg_and_output_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload 112952727171154464855801043315131020582034777149601636831458659861408356486028 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/19.kmac_sideload/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1952172940 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload.1952172940 +enable_masking=1 +sw_key_masked=0' seed=112952727171154464855801043315131020582034777149601636831458659861408356486028 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112952727171154464855801043315131020582034777149601636831458659861408356486028 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/19.kmac_sideload/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 113247313512568545428530274242679940533078348467411507532928659218250922628679 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/19.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=766678599 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_sideload_invalid.766678599 +enable_masking=1 +sw_key_masked=0' seed=113247313512568545428530274242679940533078348467411507532928659218250922628679 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113247313512568545428530274242679940533078348467411507532928659218250922628679 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/19.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_burst_write 81440673615938804399643728396603244406486586425772992094721131378389491507953 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/19.kmac_burst_write/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3962692337 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_burst_write.3962692337 +enable_masking=1 +sw_key_masked=0' seed=81440673615938804399643728396603244406486586425772992094721131378389491507953 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81440673615938804399643728396603244406486586425772992094721131378389491507953 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/19.kmac_burst_write/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_burst_write_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_app 2322205203614730520912388994979152115721564163280630094289607076553702190030 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/19.kmac_app/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=730278862 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_app.730278862 +enable_masking=1 +sw_key_masked=0' seed=2322205203614730520912388994979152115721564163280630094289607076553702190030 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2322205203614730520912388994979152115721564163280630094289607076553702190030 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/19.kmac_app/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_app_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_refresh 71452610691078526535076113283730413247999852802835422712472360678581094082388 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/19.kmac_entropy_refresh/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2610194260 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_refresh.2610194260 +enable_masking=1 +sw_key_masked=0' seed=71452610691078526535076113283730413247999852802835422712472360678581094082388 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71452610691078526535076113283730413247999852802835422712472360678581094082388 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/19.kmac_entropy_refresh/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_refresh_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_error 60837615204755949332235428382350421439778125120465947585043466689657201933311 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/19.kmac_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=441105407 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_error.441105407 +enable_masking=1 +sw_key_masked=0' seed=60837615204755949332235428382350421439778125120465947585043466689657201933311 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60837615204755949332235428382350421439778125120465947585043466689657201933311 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/19.kmac_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_key_error 56286119181428278134381252016136430193864574884001967527332589441343762581146 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/19.kmac_key_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3874866842 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_key_error.3874866842 +enable_masking=1 +sw_key_masked=0' seed=56286119181428278134381252016136430193864574884001967527332589441343762581146 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56286119181428278134381252016136430193864574884001967527332589441343762581146 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/19.kmac_key_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_key_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_edn_timeout_error 12504130836960302255987658235514199325942763200508950350024030752105175022633 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/19.kmac_edn_timeout_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1462598697 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_edn_timeout_error.1462598697 +enable_masking=1 +sw_key_masked=0' seed=12504130836960302255987658235514199325942763200508950350024030752105175022633 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12504130836960302255987658235514199325942763200508950350024030752105175022633 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/19.kmac_edn_timeout_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_edn_timeout_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_entropy_mode_error 110870272789029132892857146012659195932086825931516775581130534268466539813087 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/19.kmac_entropy_mode_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4222900447 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_entropy_mode_error.4222900447 +enable_masking=1 +sw_key_masked=0' seed=110870272789029132892857146012659195932086825931516775581130534268466539813087 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110870272789029132892857146012659195932086825931516775581130534268466539813087 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/19.kmac_entropy_mode_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_mode_error_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 76744801468060681129772435923062761340841365189343548910739356847503603740430 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/19.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1102393102 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.kmac_lc_escalation.1102393102 +enable_masking=1 +sw_key_masked=0' seed=76744801468060681129772435923062761340841365189343548910739356847503603740430 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76744801468060681129772435923062761340841365189343548910739356847503603740430 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/19.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors 70596333585805148009333597057578289777252800094981489330992058582791208830094 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/19.kmac_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2863924366 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors.2863924366 +enable_masking=1 +sw_key_masked=0' seed=70596333585805148009333597057578289777252800094981489330992058582791208830094 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70596333585805148009333597057578289777252800094981489330992058582791208830094 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/19.kmac_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_shadow_reg_errors_with_csr_rw 34574348010908119733276580167674061734438215746094651959057526650254144602073 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/19.kmac_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=13402073 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_shadow_reg_errors_with_csr_rw.13402073 +enable_masking=1 +sw_key_masked=0' seed=34574348010908119733276580167674061734438215746094651959057526650254144602073 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34574348010908119733276580167674061734438215746094651959057526650254144602073 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/19.kmac_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_errors 34944013585256466957554547802105346626334235463895177331505266456037803922441 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/19.kmac_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4289958921 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_errors.4289958921 +enable_masking=1 +sw_key_masked=0' seed=34944013585256466957554547802105346626334235463895177331505266456037803922441 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34944013585256466957554547802105346626334235463895177331505266456037803922441 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/19.kmac_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_intg_err 26124988129510221603240719512905857182148068684203996510876738439718088911450 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/19.kmac_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2242554458 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.kmac_tl_intg_err.2242554458 +enable_masking=1 +sw_key_masked=0' seed=26124988129510221603240719512905857182148068684203996510876738439718088911450 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26124988129510221603240719512905857182148068684203996510876738439718088911450 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/19.kmac_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 76442068038194171693241971387551342662849025748778051234600727644574704413286 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/20.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2711562854 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_sideload_invalid.2711562854 +enable_masking=1 +sw_key_masked=0' seed=76442068038194171693241971387551342662849025748778051234600727644574704413286 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76442068038194171693241971387551342662849025748778051234600727644574704413286 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/20.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_app 26689590301378930537932578642452935676891442891481450023875427008792861671254 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/20.kmac_app/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3819503446 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_app.3819503446 +enable_masking=1 +sw_key_masked=0' seed=26689590301378930537932578642452935676891442891481450023875427008792861671254 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26689590301378930537932578642452935676891442891481450023875427008792861671254 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/20.kmac_app/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_app_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 94935478710379055808721658904801619846265798593410600948784394511087475626587 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/20.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2679116379 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.kmac_lc_escalation.2679116379 +enable_masking=1 +sw_key_masked=0' seed=94935478710379055808721658904801619846265798593410600948784394511087475626587 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94935478710379055808721658904801619846265798593410600948784394511087475626587 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/20.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_errors 53773464059015408450084596215223662383938640631704161246115229777955809148265 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/20.kmac_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2045001065 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_tl_errors.2045001065 +enable_masking=1 +sw_key_masked=0' seed=53773464059015408450084596215223662383938640631704161246115229777955809148265 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53773464059015408450084596215223662383938640631704161246115229777955809148265 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/20.kmac_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_intg_err 25362460543914045513486319535743571257555529269374210584373249660467706548414 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/20.kmac_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1741639870 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.kmac_tl_intg_err.1741639870 +enable_masking=1 +sw_key_masked=0' seed=25362460543914045513486319535743571257555529269374210584373249660467706548414 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25362460543914045513486319535743571257555529269374210584373249660467706548414 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/20.kmac_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 17396514874792181283816468858323452772674286330314826128775807425639700962680 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/21.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4272364920 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_sideload_invalid.4272364920 +enable_masking=1 +sw_key_masked=0' seed=17396514874792181283816468858323452772674286330314826128775807425639700962680 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17396514874792181283816468858323452772674286330314826128775807425639700962680 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/21.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_app 21566822838357166247063588626822906302809341082461150625429594714415605053018 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/21.kmac_app/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3525670490 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_app.3525670490 +enable_masking=1 +sw_key_masked=0' seed=21566822838357166247063588626822906302809341082461150625429594714415605053018 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21566822838357166247063588626822906302809341082461150625429594714415605053018 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/21.kmac_app/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_app_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 64530632337429870234498994685047915097634943004224744411974360665983034704359 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/21.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=716292583 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.kmac_lc_escalation.716292583 +enable_masking=1 +sw_key_masked=0' seed=64530632337429870234498994685047915097634943004224744411974360665983034704359 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64530632337429870234498994685047915097634943004224744411974360665983034704359 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/21.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_errors 13155473842127343649737389748486885934295748286712779312630256959756702930147 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/21.kmac_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2045859043 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_tl_errors.2045859043 +enable_masking=1 +sw_key_masked=0' seed=13155473842127343649737389748486885934295748286712779312630256959756702930147 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13155473842127343649737389748486885934295748286712779312630256959756702930147 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/21.kmac_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_intg_err 43838804325575306759202775654490162294183453797671764287651207276291722314092 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/21.kmac_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2133066092 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.kmac_tl_intg_err.2133066092 +enable_masking=1 +sw_key_masked=0' seed=43838804325575306759202775654490162294183453797671764287651207276291722314092 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43838804325575306759202775654490162294183453797671764287651207276291722314092 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/21.kmac_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 78811694230341435741409463004883701767345913845614108022158992674530522021054 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/22.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4006591678 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_sideload_invalid.4006591678 +enable_masking=1 +sw_key_masked=0' seed=78811694230341435741409463004883701767345913845614108022158992674530522021054 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78811694230341435741409463004883701767345913845614108022158992674530522021054 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/22.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_app 21583382124366101405061336126114397171012433849266923104618704915770829618124 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/22.kmac_app/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4165385164 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_app.4165385164 +enable_masking=1 +sw_key_masked=0' seed=21583382124366101405061336126114397171012433849266923104618704915770829618124 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21583382124366101405061336126114397171012433849266923104618704915770829618124 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/22.kmac_app/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_app_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 103559641079668799725848793769190233018408989318171330067702113380046316848900 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/22.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1936541444 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.kmac_lc_escalation.1936541444 +enable_masking=1 +sw_key_masked=0' seed=103559641079668799725848793769190233018408989318171330067702113380046316848900 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103559641079668799725848793769190233018408989318171330067702113380046316848900 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/22.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_errors 79890762836318779803543422436310187407977983348952346808158329106464521684621 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/22.kmac_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1238468237 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_tl_errors.1238468237 +enable_masking=1 +sw_key_masked=0' seed=79890762836318779803543422436310187407977983348952346808158329106464521684621 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79890762836318779803543422436310187407977983348952346808158329106464521684621 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/22.kmac_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_intg_err 96317762083482146825375391564101893936861301549533512048701115683979290851807 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/22.kmac_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3198794207 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.kmac_tl_intg_err.3198794207 +enable_masking=1 +sw_key_masked=0' seed=96317762083482146825375391564101893936861301549533512048701115683979290851807 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96317762083482146825375391564101893936861301549533512048701115683979290851807 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/22.kmac_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 29560276780536230973197247283940209247415044943900435032537061368174647153774 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/23.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2183107694 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_sideload_invalid.2183107694 +enable_masking=1 +sw_key_masked=0' seed=29560276780536230973197247283940209247415044943900435032537061368174647153774 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29560276780536230973197247283940209247415044943900435032537061368174647153774 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/23.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_app 16324210085633963361414975862825288368802536754891632577881930419865033226148 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/23.kmac_app/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1359591332 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_app.1359591332 +enable_masking=1 +sw_key_masked=0' seed=16324210085633963361414975862825288368802536754891632577881930419865033226148 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16324210085633963361414975862825288368802536754891632577881930419865033226148 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/23.kmac_app/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_app_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 55485675171957629734597999137379468912528899038761360785356847717883467825896 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/23.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1904771816 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.kmac_lc_escalation.1904771816 +enable_masking=1 +sw_key_masked=0' seed=55485675171957629734597999137379468912528899038761360785356847717883467825896 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55485675171957629734597999137379468912528899038761360785356847717883467825896 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/23.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_errors 114729235004807021267070390577949248048076968910998053975562656575251420563236 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/23.kmac_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=119818020 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_tl_errors.119818020 +enable_masking=1 +sw_key_masked=0' seed=114729235004807021267070390577949248048076968910998053975562656575251420563236 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114729235004807021267070390577949248048076968910998053975562656575251420563236 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/23.kmac_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_intg_err 69712975829064302481607006664272403852403051640513996752595223745508528456516 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/23.kmac_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=324633412 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.kmac_tl_intg_err.324633412 +enable_masking=1 +sw_key_masked=0' seed=69712975829064302481607006664272403852403051640513996752595223745508528456516 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69712975829064302481607006664272403852403051640513996752595223745508528456516 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/23.kmac_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 35743562854844286043042707704811827350231282680485677186465395779107094926909 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/24.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1506678333 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_sideload_invalid.1506678333 +enable_masking=1 +sw_key_masked=0' seed=35743562854844286043042707704811827350231282680485677186465395779107094926909 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35743562854844286043042707704811827350231282680485677186465395779107094926909 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/24.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_app 54091855831991727479660206400324491134178945677377997740575566926661503537932 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/24.kmac_app/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3988378380 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_app.3988378380 +enable_masking=1 +sw_key_masked=0' seed=54091855831991727479660206400324491134178945677377997740575566926661503537932 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54091855831991727479660206400324491134178945677377997740575566926661503537932 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/24.kmac_app/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_app_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 50675116001719343534396026183033078779981265144972514738873677685419130914501 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/24.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=335972037 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.kmac_lc_escalation.335972037 +enable_masking=1 +sw_key_masked=0' seed=50675116001719343534396026183033078779981265144972514738873677685419130914501 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50675116001719343534396026183033078779981265144972514738873677685419130914501 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/24.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_errors 55396188153819313839791037539563967509893306630669646451531678608105018051075 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/24.kmac_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1469663747 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_tl_errors.1469663747 +enable_masking=1 +sw_key_masked=0' seed=55396188153819313839791037539563967509893306630669646451531678608105018051075 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55396188153819313839791037539563967509893306630669646451531678608105018051075 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/24.kmac_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_tl_intg_err 31890612860508572468299408690189368779403026029446368107153316394498084879931 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/24.kmac_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2598420027 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.kmac_tl_intg_err.2598420027 +enable_masking=1 +sw_key_masked=0' seed=31890612860508572468299408690189368779403026029446368107153316394498084879931 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31890612860508572468299408690189368779403026029446368107153316394498084879931 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/24.kmac_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 29237276888655668735217342091669994600343813177458814015098769438706126201074 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/25.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2428412146 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_sideload_invalid.2428412146 +enable_masking=1 +sw_key_masked=0' seed=29237276888655668735217342091669994600343813177458814015098769438706126201074 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29237276888655668735217342091669994600343813177458814015098769438706126201074 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/25.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 86882742284217840282574370897586430482833512586080697639775169399653919261939 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/25.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1057654003 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.kmac_lc_escalation.1057654003 +enable_masking=1 +sw_key_masked=0' seed=86882742284217840282574370897586430482833512586080697639775169399653919261939 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86882742284217840282574370897586430482833512586080697639775169399653919261939 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/25.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 77088260987985828281639487254250791802826624300851838063094774013089573755517 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/26.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1436801661 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_sideload_invalid.1436801661 +enable_masking=1 +sw_key_masked=0' seed=77088260987985828281639487254250791802826624300851838063094774013089573755517 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77088260987985828281639487254250791802826624300851838063094774013089573755517 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/26.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 24072658891424045184313866672253421650827507386938386868462055401356793707871 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/26.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3468393823 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.kmac_lc_escalation.3468393823 +enable_masking=1 +sw_key_masked=0' seed=24072658891424045184313866672253421650827507386938386868462055401356793707871 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24072658891424045184313866672253421650827507386938386868462055401356793707871 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/26.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 115789464083227656547680533322659070315964464181453749687142888279226504005768 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/27.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=720980104 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_sideload_invalid.720980104 +enable_masking=1 +sw_key_masked=0' seed=115789464083227656547680533322659070315964464181453749687142888279226504005768 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115789464083227656547680533322659070315964464181453749687142888279226504005768 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/27.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 93034957450073670551746636942064266533956304477469178591021852332031707231556 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/27.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1965864260 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.kmac_lc_escalation.1965864260 +enable_masking=1 +sw_key_masked=0' seed=93034957450073670551746636942064266533956304477469178591021852332031707231556 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93034957450073670551746636942064266533956304477469178591021852332031707231556 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/27.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 112625322939635874359670734658721984359778187912420955664069085731888362332394 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/28.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2276892906 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_sideload_invalid.2276892906 +enable_masking=1 +sw_key_masked=0' seed=112625322939635874359670734658721984359778187912420955664069085731888362332394 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112625322939635874359670734658721984359778187912420955664069085731888362332394 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/28.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 113644000621670445677999486534221502349779393229934669432432169871567118969452 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/28.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3813714540 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.kmac_lc_escalation.3813714540 +enable_masking=1 +sw_key_masked=0' seed=113644000621670445677999486534221502349779393229934669432432169871567118969452 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113644000621670445677999486534221502349779393229934669432432169871567118969452 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/28.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 109137461209465712767623760664107224373495830660487739394651345632643290027586 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/29.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=916510274 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_sideload_invalid.916510274 +enable_masking=1 +sw_key_masked=0' seed=109137461209465712767623760664107224373495830660487739394651345632643290027586 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109137461209465712767623760664107224373495830660487739394651345632643290027586 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/29.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 113679182882707092657984940903820912659234274127039908623470868797844060222691 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/29.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2043524323 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.kmac_lc_escalation.2043524323 +enable_masking=1 +sw_key_masked=0' seed=113679182882707092657984940903820912659234274127039908623470868797844060222691 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113679182882707092657984940903820912659234274127039908623470868797844060222691 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/29.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 43847510528697957005062306363714051626193870800152290792525202491784658434182 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/30.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3079944326 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_sideload_invalid.3079944326 +enable_masking=1 +sw_key_masked=0' seed=43847510528697957005062306363714051626193870800152290792525202491784658434182 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43847510528697957005062306363714051626193870800152290792525202491784658434182 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/30.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 98262608952350128962808776520417035480787590824512004846924878832827533881448 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/30.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1271656552 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.kmac_lc_escalation.1271656552 +enable_masking=1 +sw_key_masked=0' seed=98262608952350128962808776520417035480787590824512004846924878832827533881448 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98262608952350128962808776520417035480787590824512004846924878832827533881448 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/30.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 50599218221940348358831433260186746857514596582659486915546303207951921187408 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/31.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2994604624 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_sideload_invalid.2994604624 +enable_masking=1 +sw_key_masked=0' seed=50599218221940348358831433260186746857514596582659486915546303207951921187408 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50599218221940348358831433260186746857514596582659486915546303207951921187408 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/31.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 26843861912350221235872557886949879025526734072931364422690514223773521123466 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/31.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4145125514 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.kmac_lc_escalation.4145125514 +enable_masking=1 +sw_key_masked=0' seed=26843861912350221235872557886949879025526734072931364422690514223773521123466 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26843861912350221235872557886949879025526734072931364422690514223773521123466 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/31.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 28609881198746774964684507907162814277182645494191796101950393512738738159367 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/32.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1967931143 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_sideload_invalid.1967931143 +enable_masking=1 +sw_key_masked=0' seed=28609881198746774964684507907162814277182645494191796101950393512738738159367 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28609881198746774964684507907162814277182645494191796101950393512738738159367 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/32.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 30281387388659577621951393072646787102682187273104676077679977151111729798138 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/32.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3739507706 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.kmac_lc_escalation.3739507706 +enable_masking=1 +sw_key_masked=0' seed=30281387388659577621951393072646787102682187273104676077679977151111729798138 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30281387388659577621951393072646787102682187273104676077679977151111729798138 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/32.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 98893123609921130269555144975308338025284485545860054787361831665102309289800 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/33.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=455077704 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_sideload_invalid.455077704 +enable_masking=1 +sw_key_masked=0' seed=98893123609921130269555144975308338025284485545860054787361831665102309289800 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98893123609921130269555144975308338025284485545860054787361831665102309289800 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/33.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 16017170658474129781566720255126136889561421042811817934294250731869624741508 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/33.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1483878020 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.kmac_lc_escalation.1483878020 +enable_masking=1 +sw_key_masked=0' seed=16017170658474129781566720255126136889561421042811817934294250731869624741508 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16017170658474129781566720255126136889561421042811817934294250731869624741508 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/33.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 70303983857836396263572195947702379074426681238407020775583838139061744381388 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/34.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1321414092 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_sideload_invalid.1321414092 +enable_masking=1 +sw_key_masked=0' seed=70303983857836396263572195947702379074426681238407020775583838139061744381388 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70303983857836396263572195947702379074426681238407020775583838139061744381388 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/34.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 92316834125564080237373517703886303059727076401684296867700019140918443303413 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/34.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1372381685 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.kmac_lc_escalation.1372381685 +enable_masking=1 +sw_key_masked=0' seed=92316834125564080237373517703886303059727076401684296867700019140918443303413 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92316834125564080237373517703886303059727076401684296867700019140918443303413 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/34.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 98177998162373562763597212695940604633639007971304181210022241792320895948762 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/35.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3410204634 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_sideload_invalid.3410204634 +enable_masking=1 +sw_key_masked=0' seed=98177998162373562763597212695940604633639007971304181210022241792320895948762 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98177998162373562763597212695940604633639007971304181210022241792320895948762 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/35.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 33265237174408916387749454746625554033410772143499370889436096303461981338379 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/35.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3824794379 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.kmac_lc_escalation.3824794379 +enable_masking=1 +sw_key_masked=0' seed=33265237174408916387749454746625554033410772143499370889436096303461981338379 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33265237174408916387749454746625554033410772143499370889436096303461981338379 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/35.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 42308954965836267591694935565836279805559003554946356221063241795173943540883 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/36.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=285932691 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_sideload_invalid.285932691 +enable_masking=1 +sw_key_masked=0' seed=42308954965836267591694935565836279805559003554946356221063241795173943540883 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42308954965836267591694935565836279805559003554946356221063241795173943540883 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/36.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 48284707201410681201587952623875701318644110226645452551148061930437472354690 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/36.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3666018690 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.kmac_lc_escalation.3666018690 +enable_masking=1 +sw_key_masked=0' seed=48284707201410681201587952623875701318644110226645452551148061930437472354690 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48284707201410681201587952623875701318644110226645452551148061930437472354690 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/36.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 63045374393726304911835418636188434385447918081287985016013591848368535594767 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/37.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3532220175 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_sideload_invalid.3532220175 +enable_masking=1 +sw_key_masked=0' seed=63045374393726304911835418636188434385447918081287985016013591848368535594767 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63045374393726304911835418636188434385447918081287985016013591848368535594767 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/37.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 48894541056883695631039972103779884743365715372885591126204631544469626007543 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/37.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=157003767 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.kmac_lc_escalation.157003767 +enable_masking=1 +sw_key_masked=0' seed=48894541056883695631039972103779884743365715372885591126204631544469626007543 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48894541056883695631039972103779884743365715372885591126204631544469626007543 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/37.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 85041001609452903188887717673448711398078995069880756530250188289314364149838 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/38.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3566555214 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_sideload_invalid.3566555214 +enable_masking=1 +sw_key_masked=0' seed=85041001609452903188887717673448711398078995069880756530250188289314364149838 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85041001609452903188887717673448711398078995069880756530250188289314364149838 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/38.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 115331425527339674196109906337721766968108343228083851458864834495047977904728 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/38.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3427510872 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.kmac_lc_escalation.3427510872 +enable_masking=1 +sw_key_masked=0' seed=115331425527339674196109906337721766968108343228083851458864834495047977904728 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115331425527339674196109906337721766968108343228083851458864834495047977904728 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/38.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 81744673694408991454269514424589651695660642038052872997361900551474284596619 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/39.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2144603531 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_sideload_invalid.2144603531 +enable_masking=1 +sw_key_masked=0' seed=81744673694408991454269514424589651695660642038052872997361900551474284596619 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81744673694408991454269514424589651695660642038052872997361900551474284596619 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/39.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 29039359539337785553010599443892387850249635090273243399895376452904487673602 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/39.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4221755138 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.kmac_lc_escalation.4221755138 +enable_masking=1 +sw_key_masked=0' seed=29039359539337785553010599443892387850249635090273243399895376452904487673602 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29039359539337785553010599443892387850249635090273243399895376452904487673602 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/39.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 84187552697781098260320399887855101101739769280794085210776993731080097095007 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/40.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=181656927 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_sideload_invalid.181656927 +enable_masking=1 +sw_key_masked=0' seed=84187552697781098260320399887855101101739769280794085210776993731080097095007 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84187552697781098260320399887855101101739769280794085210776993731080097095007 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/40.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 43390627409980165164468024110002267800395356187658810966048628690453589267224 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/40.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3831370520 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.kmac_lc_escalation.3831370520 +enable_masking=1 +sw_key_masked=0' seed=43390627409980165164468024110002267800395356187658810966048628690453589267224 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43390627409980165164468024110002267800395356187658810966048628690453589267224 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/40.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 7307364907659831591311173895442504544182370699511570029642370605482492971666 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/41.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1521896082 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_sideload_invalid.1521896082 +enable_masking=1 +sw_key_masked=0' seed=7307364907659831591311173895442504544182370699511570029642370605482492971666 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7307364907659831591311173895442504544182370699511570029642370605482492971666 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/41.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 113274686122599432083835227314433007142090941322999976282927422296437018159798 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/41.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1170041526 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.kmac_lc_escalation.1170041526 +enable_masking=1 +sw_key_masked=0' seed=113274686122599432083835227314433007142090941322999976282927422296437018159798 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113274686122599432083835227314433007142090941322999976282927422296437018159798 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/41.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 77409510327231134196379604146411291024617209469909263501647135876555994426825 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/42.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=691400137 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_sideload_invalid.691400137 +enable_masking=1 +sw_key_masked=0' seed=77409510327231134196379604146411291024617209469909263501647135876555994426825 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77409510327231134196379604146411291024617209469909263501647135876555994426825 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/42.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 29697660514105370217735874599816175190076646302347496080588850126625240172558 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/42.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1262143502 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.kmac_lc_escalation.1262143502 +enable_masking=1 +sw_key_masked=0' seed=29697660514105370217735874599816175190076646302347496080588850126625240172558 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29697660514105370217735874599816175190076646302347496080588850126625240172558 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/42.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 104714353075666024951774360783440499955146942231024867116732001670433778898621 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/43.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1903367869 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_sideload_invalid.1903367869 +enable_masking=1 +sw_key_masked=0' seed=104714353075666024951774360783440499955146942231024867116732001670433778898621 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104714353075666024951774360783440499955146942231024867116732001670433778898621 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/43.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 35124117981767891267145412467919906919143960672502561872211819568306384888806 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/43.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1420387302 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.kmac_lc_escalation.1420387302 +enable_masking=1 +sw_key_masked=0' seed=35124117981767891267145412467919906919143960672502561872211819568306384888806 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35124117981767891267145412467919906919143960672502561872211819568306384888806 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/43.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 107490770766557804204748518010524504614051894571145786155395202847731578995475 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/44.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1953399571 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_sideload_invalid.1953399571 +enable_masking=1 +sw_key_masked=0' seed=107490770766557804204748518010524504614051894571145786155395202847731578995475 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107490770766557804204748518010524504614051894571145786155395202847731578995475 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/44.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 55484706263177153333189407711899062516485686907591473608307689276255574623184 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/44.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2274296784 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.kmac_lc_escalation.2274296784 +enable_masking=1 +sw_key_masked=0' seed=55484706263177153333189407711899062516485686907591473608307689276255574623184 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55484706263177153333189407711899062516485686907591473608307689276255574623184 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/44.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 113022009164507004990503200291910477888933722898898537886338623384194205453629 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/45.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3070070077 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_sideload_invalid.3070070077 +enable_masking=1 +sw_key_masked=0' seed=113022009164507004990503200291910477888933722898898537886338623384194205453629 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113022009164507004990503200291910477888933722898898537886338623384194205453629 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/45.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 31522077669258059439751622170653661104321594109908085353665445009567547414399 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/45.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1840535423 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.kmac_lc_escalation.1840535423 +enable_masking=1 +sw_key_masked=0' seed=31522077669258059439751622170653661104321594109908085353665445009567547414399 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31522077669258059439751622170653661104321594109908085353665445009567547414399 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/45.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 100322136042370691660625325557691892857103609512397882592421356648440828147076 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/46.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2629186948 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_sideload_invalid.2629186948 +enable_masking=1 +sw_key_masked=0' seed=100322136042370691660625325557691892857103609512397882592421356648440828147076 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100322136042370691660625325557691892857103609512397882592421356648440828147076 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/46.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 5950667228026126977129872562534694721039451137285677907082374308707756582378 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/46.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=101885418 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.kmac_lc_escalation.101885418 +enable_masking=1 +sw_key_masked=0' seed=5950667228026126977129872562534694721039451137285677907082374308707756582378 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5950667228026126977129872562534694721039451137285677907082374308707756582378 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/46.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 86542188043807527904797981544291505819088133989877213060123950548000302093918 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/47.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1401083486 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_sideload_invalid.1401083486 +enable_masking=1 +sw_key_masked=0' seed=86542188043807527904797981544291505819088133989877213060123950548000302093918 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86542188043807527904797981544291505819088133989877213060123950548000302093918 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/47.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 93206761924331811559848472731498582938812711695718011449892625896786808213516 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/47.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3453161484 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.kmac_lc_escalation.3453161484 +enable_masking=1 +sw_key_masked=0' seed=93206761924331811559848472731498582938812711695718011449892625896786808213516 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93206761924331811559848472731498582938812711695718011449892625896786808213516 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/47.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 22787774126386016982723094752976418531454881592297829182998942388082576499119 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/48.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=824222127 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_sideload_invalid.824222127 +enable_masking=1 +sw_key_masked=0' seed=22787774126386016982723094752976418531454881592297829182998942388082576499119 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22787774126386016982723094752976418531454881592297829182998942388082576499119 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/48.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 72469139986919174767083841566478888929308862562603020576839565336954303023063 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/48.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=6162391 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.kmac_lc_escalation.6162391 +enable_masking=1 +sw_key_masked=0' seed=72469139986919174767083841566478888929308862562603020576839565336954303023063 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72469139986919174767083841566478888929308862562603020576839565336954303023063 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/48.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_sideload_invalid 53538708711752840181869975364545907128954538299730527308922964912827839555368 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/49.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1010837288 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_sideload_invalid.1010837288 +enable_masking=1 +sw_key_masked=0' seed=53538708711752840181869975364545907128954538299730527308922964912827839555368 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53538708711752840181869975364545907128954538299730527308922964912827839555368 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/49.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
kmac_lc_escalation 86695676780391990057399806712916632160760039349056331541899014752830681235706 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/49.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2273034490 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.kmac_lc_escalation.2273034490 +enable_masking=1 +sw_key_masked=0' seed=86695676780391990057399806712916632160760039349056331541899014752830681235706 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86695676780391990057399806712916632160760039349056331541899014752830681235706 --run-dir=/nightly/current_run/scratch/master/kmac_masked-sim-vcs/49.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
UVM_ERROR (kmac_scoreboard.sv:524) scoreboard [scoreboard] Saw request be handled for app * when that app was not selected. 8 test runs
kmac_stress_all 42112321434656327482335423346785074168310224651491382410263056442538271970 112
UVM_INFO @ 2046686155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 20445224518738582717060145480844449484244150543383155652283048701210851139495 163
UVM_INFO @ 16590858146 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 49137145073994361572986386175911980141847409485523904969938775422782789205952 130
UVM_INFO @ 18762851012 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 35058849393271129977840964543203243832402417152377741765015332654241926259466 80
UVM_INFO @ 131408302 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 60462770339517823345609833022469324188884261011452815874980730384514986925550 126
UVM_INFO @ 9221245088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 77130979710175011998442719916146719932145912797108612737062903253336087952545 82
UVM_INFO @ 138398530 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 73835399971608553125930552876082958239649909010768323623982927505577738371737 145
UVM_INFO @ 5696451339 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 36677690682491550535483618488838281793438366079090427833209290083992973195481 168
UVM_INFO @ 12353394221 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:1671) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] 7 test runs
kmac_stress_all 75027410724711998470919063636781945957792635846505718249322404548310206799483 113
UVM_INFO @ 623973245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 71340179818893100044393556308857062356235362002541205531890081394503563577550 79
UVM_INFO @ 46496217 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 67488547398125899001108818816062833731464148839370507187837817923190134762541 115
UVM_INFO @ 90365925681 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 45771416552739381326708552142815642421052484801344667885668143981315689425932 86
UVM_INFO @ 763143439 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 71661664240580906721873536030159351339318084268602503541211071697683000945777 127
UVM_INFO @ 3240747903 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 75640294626004634141389615962272279629904728466961495037125178194953695925685 92
UVM_INFO @ 14662591835 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 9250575306415045582948215788641908504061675311361027000026334166765166855069 81
UVM_INFO @ 595854480 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (kmac_scoreboard.sv:601) scoreboard [scoreboard] Unexpected m_error value in the app response (*) 1 test run
kmac_stress_all 113896090424843521873571819761369741092752716000388265239784845642531669295675 151
UVM_INFO @ 10113861887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Error-[FCULIBNF] Ucapi library not found 1 test run
kmac_stress_all 103442179250630512756629240306222438574442882239052538552704745833738744154911 420
Unable to locate ucapi library at
/nas/lowrisc/tools/synopsys/vcs/U-2023.03-SP2/linux64/lib/libucapi.so.
Job returned a non-zero exit code: * 1 test run
kmac None None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk cov_merge cov_merge_cmd=urg cov_merge_opts='-lca -full64 -noreport +urg+lic+wait -merge_across_libs -show tests -flex_merge union -dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/default.vdb -dir /nightly/current_run/scratch/master/kmac_masked-sim-vcs/coverage/cover_reg_top.vdb -dbname /nightly/current_run/scratch/master/kmac_masked-sim-vcs/cov_merge/merged.vdb'
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:109: cov_merge] Error 126
Job cancelled because one of its dependencies failed or was killed. 1 test run
kmac None None