Simulation Results

Simulation Results: kmac/unmasked

28/08/2026 21:54:34 DVSim: v1.49.0 sha: a099412 json Branch: master Tool: vcs [unknown]

Validation stages

V1		0.00%
V2		0.71%
V2S		0.00%
V3		0.00%

0/35 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
smoke				20
	kmac_smoke	1.544s	0.000us	20
csr_hw_reset				1
	kmac_csr_hw_reset	0.838s	0.000us	1
csr_rw				5
	kmac_csr_rw	0.811s	0.000us	5
csr_bit_bash				1
	kmac_csr_bit_bash	0.805s	0.000us	1
csr_aliasing				1
	kmac_csr_aliasing	0.822s	0.000us	1
csr_mem_rw_with_rand_reset				5
	kmac_csr_mem_rw_with_rand_reset	0.829s	0.000us	5
regwen_csr_and_corresponding_lockable_csr				6
	kmac_csr_rw	0.811s	0.000us	5
	kmac_csr_aliasing	0.822s	0.000us	1
mem_walk				1
	kmac_mem_walk	0.816s	0.000us	1
mem_partial_access				1
	kmac_mem_partial_access	0.808s	0.000us	1

3/422 passed

0.71 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
long_msg_and_output				0	20	0.00
	kmac_long_msg_and_output	1.819s	0.000us	0	20	0.00
burst_write				0	20	0.00
	kmac_burst_write	0.842s	0.000us	0	20	0.00
test_vectors				0	40	0.00
	kmac_test_vectors_sha3_224	0.973s	0.000us	0	5	0.00
	kmac_test_vectors_sha3_256	0.897s	0.000us	0	5	0.00
	kmac_test_vectors_sha3_384	1.522s	0.000us	0	5	0.00
	kmac_test_vectors_sha3_512	0.845s	0.000us	0	5	0.00
	kmac_test_vectors_shake_128	0.909s	0.000us	0	5	0.00
	kmac_test_vectors_shake_256	0.895s	0.000us	0	5	0.00
	kmac_test_vectors_kmac	0.834s	0.000us	0	5	0.00
	kmac_test_vectors_kmac_xof	1.502s	0.000us	0	5	0.00
sideload				0	20	0.00
	kmac_sideload	1.527s	0.000us	0	20	0.00
app				0	25	0.00
	kmac_app	0.858s	0.000us	0	25	0.00
app_with_partial_data				0	10	0.00
	kmac_app_with_partial_data	1.535s	0.000us	0	10	0.00
entropy_refresh				0	20	0.00
	kmac_entropy_refresh	0.879s	0.000us	0	20	0.00
error				0	20	0.00
	kmac_error	1.512s	0.000us	0	20	0.00
key_error				0	20	0.00
	kmac_key_error	1.549s	0.000us	0	20	0.00
sideload_invalid				0	50	0.00
	kmac_sideload_invalid	1.526s	0.000us	0	50	0.00
edn_timeout_error				0	20	0.00
	kmac_edn_timeout_error	1.485s	0.000us	0	20	0.00
entropy_mode_error				0	20	0.00
	kmac_entropy_mode_error	0.877s	0.000us	0	20	0.00
entropy_ready_error				0	10	0.00
	kmac_entropy_ready_error	0.848s	0.000us	0	10	0.00
lc_escalation				0	50	0.00
	kmac_lc_escalation	1.548s	0.000us	0	50	0.00
stress_all				3	20	15.00
	kmac_stress_all	1540.260s	46341.925us	3	20	15.00
intr_test				0	10	0.00
	kmac_intr_test	1.483s	0.000us	0	10	0.00
alert_test				0	10	0.00
	kmac_alert_test	1.525s	0.000us	0	10	0.00
tl_d_oob_addr_access				0	25	0.00
	kmac_tl_errors	1.519s	0.000us	0	25	0.00
tl_d_illegal_access				0	25	0.00
	kmac_tl_errors	1.519s	0.000us	0	25	0.00
tl_d_outstanding_access				0	12	0.00
	kmac_csr_hw_reset	0.838s	0.000us	0	1	0.00
	kmac_csr_rw	0.811s	0.000us	0	5	0.00
	kmac_csr_aliasing	0.822s	0.000us	0	1	0.00
	kmac_same_csr_outstanding	0.852s	0.000us	0	5	0.00
tl_d_partial_access				0	12	0.00
	kmac_csr_hw_reset	0.838s	0.000us	0	1	0.00
	kmac_csr_rw	0.811s	0.000us	0	5	0.00
	kmac_csr_aliasing	0.822s	0.000us	0	1	0.00
	kmac_same_csr_outstanding	0.852s	0.000us	0	5	0.00

V2S

0/170 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
shadow_reg_update_error				20
	kmac_shadow_reg_errors	1.400s	0.000us	20
shadow_reg_read_clear_staged_value				20
	kmac_shadow_reg_errors	1.400s	0.000us	20
shadow_reg_storage_error				20
	kmac_shadow_reg_errors	1.400s	0.000us	20
shadowed_reset_glitch				20
	kmac_shadow_reg_errors	1.400s	0.000us	20
shadow_reg_update_error_with_csr_rw				20
	kmac_shadow_reg_errors_with_csr_rw	1.395s	0.000us	20
tl_intg_err				30
	kmac_sec_cm	0.829s	0.000us	5
	kmac_tl_intg_err	1.534s	0.000us	25
sec_cm_bus_integrity				25
	kmac_tl_intg_err	1.534s	0.000us	25
sec_cm_lc_escalate_en_intersig_mubi				50
	kmac_lc_escalation	1.548s	0.000us	50
sec_cm_sw_key_key_masking				20
	kmac_smoke	1.544s	0.000us	20
sec_cm_key_sideload				20
	kmac_sideload	1.527s	0.000us	20
sec_cm_cfg_shadowed_config_shadow				20
	kmac_shadow_reg_errors	1.400s	0.000us	20
sec_cm_fsm_sparse				5
	kmac_sec_cm	0.829s	0.000us	5
sec_cm_ctr_redun				5
	kmac_sec_cm	0.829s	0.000us	5
sec_cm_packer_ctr_redun				5
	kmac_sec_cm	0.829s	0.000us	5
sec_cm_cfg_shadowed_config_regwen				20
	kmac_smoke	1.544s	0.000us	20
sec_cm_fsm_global_esc				50
	kmac_lc_escalation	1.548s	0.000us	50
sec_cm_fsm_local_esc				5
	kmac_sec_cm	0.829s	0.000us	5
sec_cm_absorbed_ctrl_mubi				10
	kmac_mubi	0.844s	0.000us	10
sec_cm_sw_cmd_ctrl_sparse				20
	kmac_smoke	1.544s	0.000us	20

0/10 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	10	0.00
	kmac_stress_all_with_rand_reset	1.526s	0.000us	0	10	0.00

Error Messages

	Test	seed	line	log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				520 test runs
	kmac_smoke	85128995558368976911942374503582615138076502568153793477994736711677488771670	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=838971990 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_smoke.838971990 +enable_masking=0 +sw_key_masked=0' seed=85128995558368976911942374503582615138076502568153793477994736711677488771670 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85128995558368976911942374503582615138076502568153793477994736711677488771670 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_smoke_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_long_msg_and_output	93735466243975220062133527701948308017234479279881325042994604608472701978518	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_long_msg_and_output/latest run_opts='+test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3776956310 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_long_msg_and_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_long_msg_and_output.3776956310 +enable_masking=0 +sw_key_masked=0' seed=93735466243975220062133527701948308017234479279881325042994604608472701978518 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93735466243975220062133527701948308017234479279881325042994604608472701978518 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_long_msg_and_output/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_long_msg_and_output_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_sideload	105109595650845188434628003495744397582669315734182921663979671680338009180317	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3396520093 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload.3396520093 +enable_masking=0 +sw_key_masked=0' seed=105109595650845188434628003495744397582669315734182921663979671680338009180317 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105109595650845188434628003495744397582669315734182921663979671680338009180317 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_sideload_invalid	8962987949722437504616902021878306741533480963881863177638417278812792918501	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2410254821 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_sideload_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sideload_invalid.2410254821 +enable_masking=0 +sw_key_masked=0' seed=8962987949722437504616902021878306741533480963881863177638417278812792918501 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8962987949722437504616902021878306741533480963881863177638417278812792918501 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sideload_invalid/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_sideload_invalid_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_burst_write	66369088259665934626266433111119775541746640597930152555333834489116548699459	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_burst_write/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=717526339 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_burst_write_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_burst_write.717526339 +enable_masking=0 +sw_key_masked=0' seed=66369088259665934626266433111119775541746640597930152555333834489116548699459 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66369088259665934626266433111119775541746640597930152555333834489116548699459 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_burst_write/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_burst_write_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_test_vectors_sha3_224	7789848221181345860021744443178078236535890714119834395100276728684499879502	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_224/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=224 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2025244238 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_224.2025244238 +enable_masking=0 +sw_key_masked=0' seed=7789848221181345860021744443178078236535890714119834395100276728684499879502 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7789848221181345860021744443178078236535890714119834395100276728684499879502 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_224/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_sha3_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_test_vectors_sha3_256	49302728204118511230839363955508928051317220338757045107430849314002007474946	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_256/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3426992898 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_256.3426992898 +enable_masking=0 +sw_key_masked=0' seed=49302728204118511230839363955508928051317220338757045107430849314002007474946 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49302728204118511230839363955508928051317220338757045107430849314002007474946 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_256/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_sha3_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_test_vectors_sha3_384	55960368290341261881898448774372510501357154424450353387372074593913811824116	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_384/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=384 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2438524404 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_384.2438524404 +enable_masking=0 +sw_key_masked=0' seed=55960368290341261881898448774372510501357154424450353387372074593913811824116 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55960368290341261881898448774372510501357154424450353387372074593913811824116 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_384/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_sha3_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_test_vectors_sha3_512	79209878593041315876872454742121575889672377331307827042229004556764508425613	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_512/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_sha3_variant=512 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3213725069 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_sha3_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_sha3_512.3213725069 +enable_masking=0 +sw_key_masked=0' seed=79209878593041315876872454742121575889672377331307827042229004556764508425613 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79209878593041315876872454742121575889672377331307827042229004556764508425613 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_test_vectors_sha3_512/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_sha3_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_test_vectors_shake_128	74367309131565719980771363632737683272028770609565941396121146453689032492445	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_128/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=128 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1100465565 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_128.1100465565 +enable_masking=0 +sw_key_masked=0' seed=74367309131565719980771363632737683272028770609565941396121146453689032492445 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74367309131565719980771363632737683272028770609565941396121146453689032492445 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_128/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_shake_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_test_vectors_shake_256	37631740627441235821297974955234867334006068566339561098271054966696834755372	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_256/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +test_timeout_ns=5_000_000_000 +test_vectors_shake_variant=256 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1550576428 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_shake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_shake_256.1550576428 +enable_masking=0 +sw_key_masked=0' seed=37631740627441235821297974955234867334006068566339561098271054966696834755372 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37631740627441235821297974955234867334006068566339561098271054966696834755372 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_test_vectors_shake_256/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_shake_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_test_vectors_kmac	16511678899443891826426696149219120558949226945978823215657872226608646261836	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_test_vectors_kmac/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1795492940 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac.1795492940 +enable_masking=0 +sw_key_masked=0' seed=16511678899443891826426696149219120558949226945978823215657872226608646261836 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16511678899443891826426696149219120558949226945978823215657872226608646261836 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_test_vectors_kmac/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_kmac_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_test_vectors_kmac_xof	42204271739741092462478871849752449793134300043697311208789594910803375951119	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_test_vectors_kmac_xof/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=209194255 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_test_vectors_kmac_xof_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_test_vectors_kmac_xof.209194255 +enable_masking=0 +sw_key_masked=0' seed=42204271739741092462478871849752449793134300043697311208789594910803375951119 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42204271739741092462478871849752449793134300043697311208789594910803375951119 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_test_vectors_kmac_xof/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_test_vectors_kmac_xof_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_app	41284092407754951755930750473328047239123874197880523821090290850260338512094	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_app/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3449196766 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app.3449196766 +enable_masking=0 +sw_key_masked=0' seed=41284092407754951755930750473328047239123874197880523821090290850260338512094 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41284092407754951755930750473328047239123874197880523821090290850260338512094 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_app/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_app_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_app_with_partial_data	110038744933286893317105179651991371565027772501290597462052470450109025108310	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_app_with_partial_data/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4211884374 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_app_with_partial_data_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_app_with_partial_data.4211884374 +enable_masking=0 +sw_key_masked=0' seed=110038744933286893317105179651991371565027772501290597462052470450109025108310 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110038744933286893317105179651991371565027772501290597462052470450109025108310 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_app_with_partial_data/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_app_with_partial_data_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_entropy_refresh	15921000710904223736344663540061271349054707701489307852832744481503182073896	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_entropy_refresh/latest run_opts='+test_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4286853160 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_refresh_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_refresh.4286853160 +enable_masking=0 +sw_key_masked=0' seed=15921000710904223736344663540061271349054707701489307852832744481503182073896 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15921000710904223736344663540061271349054707701489307852832744481503182073896 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_entropy_refresh/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_refresh_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_mubi	27173753763866942149019883898382734881849048984943180131992697886102300000305	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_mubi/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3232104497 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_mubi.3232104497 +enable_masking=0 +sw_key_masked=0' seed=27173753763866942149019883898382734881849048984943180131992697886102300000305 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27173753763866942149019883898382734881849048984943180131992697886102300000305 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_mubi_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_error	53302963747842316454406361389175212538088540828072688956063961012419961508378	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3416740378 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_error.3416740378 +enable_masking=0 +sw_key_masked=0' seed=53302963747842316454406361389175212538088540828072688956063961012419961508378 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53302963747842316454406361389175212538088540828072688956063961012419961508378 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_error_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_key_error	77229953646227623660090462646131865364708475113796170236661143787842543810485	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_key_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3901487029 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_key_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_key_error.3901487029 +enable_masking=0 +sw_key_masked=0' seed=77229953646227623660090462646131865364708475113796170236661143787842543810485 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77229953646227623660090462646131865364708475113796170236661143787842543810485 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_key_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_key_error_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_edn_timeout_error	108115913338367773376520804042703629070029885961056611926172330742797868433266	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_edn_timeout_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2212986738 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_edn_timeout_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_edn_timeout_error.2212986738 +enable_masking=0 +sw_key_masked=0' seed=108115913338367773376520804042703629070029885961056611926172330742797868433266 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108115913338367773376520804042703629070029885961056611926172330742797868433266 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_edn_timeout_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_edn_timeout_error_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_entropy_mode_error	9015652206149810812071082129174382663349207594394169742203067467870751022070	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_entropy_mode_error/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2666126326 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_mode_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_mode_error.2666126326 +enable_masking=0 +sw_key_masked=0' seed=9015652206149810812071082129174382663349207594394169742203067467870751022070 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9015652206149810812071082129174382663349207594394169742203067467870751022070 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_entropy_mode_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_mode_error_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_entropy_ready_error	107744751477512684323597641521763384637459666329687398047274644310073733106659	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_entropy_ready_error/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1551453155 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_entropy_ready_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_entropy_ready_error.1551453155 +enable_masking=0 +sw_key_masked=0' seed=107744751477512684323597641521763384637459666329687398047274644310073733106659 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107744751477512684323597641521763384637459666329687398047274644310073733106659 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_entropy_ready_error/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_entropy_ready_error_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_lc_escalation	50039217110864718659877013750150279059239494571578695557159337312636712126759	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_lc_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1370884391 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_lc_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_lc_escalation.1370884391 +enable_masking=0 +sw_key_masked=0' seed=50039217110864718659877013750150279059239494571578695557159337312636712126759 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50039217110864718659877013750150279059239494571578695557159337312636712126759 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_lc_escalation_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_stress_all_with_rand_reset	58363034561211281420778350921337463760591934721966893570503350371217572769122	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest run_opts='+test_vectors_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/default/fusesoc-work/src/lowrisc_dv_test_vectors_0 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=kmac_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4256050530 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_stress_all_with_rand_reset.4256050530 +enable_masking=0 +sw_key_masked=0' seed=58363034561211281420778350921337463760591934721966893570503350371217572769122 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58363034561211281420778350921337463760591934721966893570503350371217572769122 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_sec_cm	42461139676984073962292864313012321928988072205162518763450487678673011507489	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4027220257 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_sec_cm.4027220257 +enable_masking=0 +sw_key_masked=0' seed=42461139676984073962292864313012321928988072205162518763450487678673011507489 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42461139676984073962292864313012321928988072205162518763450487678673011507489 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_shadow_reg_errors	30778260938858533100280288960067512194296743052849055377854879423709414128419	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors/latest run_opts='+run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2397535011 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors.2397535011 +enable_masking=0 +sw_key_masked=0' seed=30778260938858533100280288960067512194296743052849055377854879423709414128419 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30778260938858533100280288960067512194296743052849055377854879423709414128419 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_shadow_reg_errors_with_csr_rw	73699012969305471098529854878322693910364375852630435115639339048899719901284	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest run_opts='+run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3838226532 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_shadow_reg_errors_with_csr_rw.3838226532 +enable_masking=0 +sw_key_masked=0' seed=73699012969305471098529854878322693910364375852630435115639339048899719901284 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73699012969305471098529854878322693910364375852630435115639339048899719901284 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_shadow_reg_errors_with_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_alert_test	43856724209078295815695976113465457755901946267836906109263105073460814673835	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1862924203 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.kmac_alert_test.1862924203 +enable_masking=0 +sw_key_masked=0' seed=43856724209078295815695976113465457755901946267836906109263105073460814673835 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43856724209078295815695976113465457755901946267836906109263105073460814673835 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_mem_walk	50040423409775297941881671574301243655697399315441225974127388610645573234318	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_mem_walk/latest run_opts='+csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3048205966 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_walk.3048205966 +enable_masking=0 +sw_key_masked=0' seed=50040423409775297941881671574301243655697399315441225974127388610645573234318 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50040423409775297941881671574301243655697399315441225974127388610645573234318 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_mem_walk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_mem_partial_access	108978302825374861534000502517453817895395075582102398843550638410297943981139	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_mem_partial_access/latest run_opts='+run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2376006739 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_mem_partial_access.2376006739 +enable_masking=0 +sw_key_masked=0' seed=108978302825374861534000502517453817895395075582102398843550638410297943981139 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108978302825374861534000502517453817895395075582102398843550638410297943981139 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_mem_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_tl_errors	36876449821831895900208247232822280709031496360098189416689688909457134610375	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1208903623 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_errors.1208903623 +enable_masking=0 +sw_key_masked=0' seed=36876449821831895900208247232822280709031496360098189416689688909457134610375 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36876449821831895900208247232822280709031496360098189416689688909457134610375 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_tl_intg_err	112032610793566160020818152003088717081102193285032507666234739128531148928485	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4012176869 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_tl_intg_err.4012176869 +enable_masking=0 +sw_key_masked=0' seed=112032610793566160020818152003088717081102193285032507666234739128531148928485 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112032610793566160020818152003088717081102193285032507666234739128531148928485 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_intr_test	23162728497879440058986132406651740534455226834703100782100899742831909924734	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2567040894 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_intr_test.2567040894 +enable_masking=0 +sw_key_masked=0' seed=23162728497879440058986132406651740534455226834703100782100899742831909924734 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23162728497879440058986132406651740534455226834703100782100899742831909924734 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_csr_hw_reset	41200998911769785536359341553884987946321371831284885880290891726967388375765	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_csr_hw_reset/latest run_opts='+csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1645873877 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_hw_reset.1645873877 +enable_masking=0 +sw_key_masked=0' seed=41200998911769785536359341553884987946321371831284885880290891726967388375765 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41200998911769785536359341553884987946321371831284885880290891726967388375765 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_csr_rw	114860114846247717337228571400625178661277338632226044053695327866418049476031	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=691692991 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_rw.691692991 +enable_masking=0 +sw_key_masked=0' seed=114860114846247717337228571400625178661277338632226044053695327866418049476031 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114860114846247717337228571400625178661277338632226044053695327866418049476031 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_csr_bit_bash	14033088948751916168038418591976720064936310872797882629307427447792327907397	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_csr_bit_bash/latest run_opts='+csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1405540421 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_bit_bash.1405540421 +enable_masking=0 +sw_key_masked=0' seed=14033088948751916168038418591976720064936310872797882629307427447792327907397 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=14033088948751916168038418591976720064936310872797882629307427447792327907397 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_csr_aliasing	65687850786001073483349045768300143725951897747771124693040151254441274788353	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_csr_aliasing/latest run_opts='+csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=765610497 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_aliasing.765610497 +enable_masking=0 +sw_key_masked=0' seed=65687850786001073483349045768300143725951897747771124693040151254441274788353 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65687850786001073483349045768300143725951897747771124693040151254441274788353 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_same_csr_outstanding	107832341913550445857102078419910202136831606859626857190604101034628304587751	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3184249831 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_same_csr_outstanding.3184249831 +enable_masking=0 +sw_key_masked=0' seed=107832341913550445857102078419910202136831606859626857190604101034628304587751 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107832341913550445857102078419910202136831606859626857190604101034628304587751 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
	kmac_csr_mem_rw_with_rand_reset	63094338898940337810498421539338747365177970778555316438608985957932394664441	None	[Executing]: make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2870792697 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=kmac_base_test +UVM_TEST_SEQ=kmac_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.kmac_csr_mem_rw_with_rand_reset.2870792697 +enable_masking=0 +sw_key_masked=0' seed=63094338898940337810498421539338747365177970778555316438608985957932394664441 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63094338898940337810498421539338747365177970778555316438608985957932394664441 --run-dir=/nightly/current_run/scratch/master/kmac_unmasked-sim-vcs/0.kmac_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=kmac_base_test uvm_test_seq=kmac_common_vseq /usr/bin/env: ‘bash’: Input/output error make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126