Simulation Results: lc_ctrl/volatile_unlock_disabled

 
28/08/2026 21:54:34 DVSim: v1.49.0 sha: a099412 json Branch: master Tool: xcelium [unknown]
Validation stages
V1
0.00%
V2
0.00%
V2S
0.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 0 20 0.00
lc_ctrl_smoke 0.911s 0.000us 0 20 0.00
csr_hw_reset 0 1 0.00
lc_ctrl_csr_hw_reset 0.796s 0.000us 0 1 0.00
csr_rw 0 5 0.00
lc_ctrl_csr_rw 0.855s 0.000us 0 5 0.00
csr_bit_bash 0 1 0.00
lc_ctrl_csr_bit_bash 0.822s 0.000us 0 1 0.00
csr_aliasing 0 1 0.00
lc_ctrl_csr_aliasing 0.823s 0.000us 0 1 0.00
csr_mem_rw_with_rand_reset 0 5 0.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.841s 0.000us 0 5 0.00
regwen_csr_and_corresponding_lockable_csr 0 6 0.00
lc_ctrl_csr_rw 0.855s 0.000us 0 5 0.00
lc_ctrl_csr_aliasing 0.823s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 20 0.00
lc_ctrl_state_post_trans 1.390s 0.000us 0 20 0.00
regwen_during_op 0 10 0.00
lc_ctrl_regwen_during_op 1.381s 0.000us 0 10 0.00
rand_wr_claim_transition_if 0 10 0.00
lc_ctrl_claim_transition_if 2.163s 0.000us 0 10 0.00
lc_prog_failure 0 20 0.00
lc_ctrl_prog_failure 0.928s 0.000us 0 20 0.00
lc_state_failure 0 20 0.00
lc_ctrl_state_failure 1.509s 0.000us 0 20 0.00
lc_errors 0 20 0.00
lc_ctrl_errors 1.444s 0.000us 0 20 0.00
security_escalation 0 140 0.00
lc_ctrl_state_failure 1.509s 0.000us 0 20 0.00
lc_ctrl_prog_failure 0.928s 0.000us 0 20 0.00
lc_ctrl_errors 1.444s 0.000us 0 20 0.00
lc_ctrl_security_escalation 1.545s 0.000us 0 20 0.00
lc_ctrl_jtag_state_failure 1.667s 0.000us 0 20 0.00
lc_ctrl_jtag_prog_failure 1.421s 0.000us 0 20 0.00
lc_ctrl_jtag_errors 1.682s 0.000us 0 20 0.00
jtag_access 0 210 0.00
lc_ctrl_jtag_smoke 1.389s 0.000us 0 20 0.00
lc_ctrl_jtag_state_post_trans 1.397s 0.000us 0 20 0.00
lc_ctrl_jtag_prog_failure 1.421s 0.000us 0 20 0.00
lc_ctrl_jtag_errors 1.682s 0.000us 0 20 0.00
lc_ctrl_jtag_access 1.513s 0.000us 0 50 0.00
lc_ctrl_jtag_regwen_during_op 1.508s 0.000us 0 10 0.00
lc_ctrl_jtag_csr_hw_reset 1.473s 0.000us 0 10 0.00
lc_ctrl_jtag_csr_rw 1.546s 0.000us 0 10 0.00
lc_ctrl_jtag_csr_bit_bash 1.495s 0.000us 0 10 0.00
lc_ctrl_jtag_csr_aliasing 0.913s 0.000us 0 10 0.00
lc_ctrl_jtag_same_csr_outstanding 1.390s 0.000us 0 10 0.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.365s 0.000us 0 10 0.00
lc_ctrl_jtag_alert_test 1.001s 0.000us 0 10 0.00
jtag_priority 0 10 0.00
lc_ctrl_jtag_priority 2.382s 0.000us 0 10 0.00
lc_ctrl_volatile_unlock 0 10 0.00
lc_ctrl_volatile_unlock_smoke 1.376s 0.000us 0 10 0.00
stress_all 0 10 0.00
lc_ctrl_stress_all 10802.000s 0.000us 0 10 0.00
alert_test 0 10 0.00
lc_ctrl_alert_test 1.465s 0.000us 0 10 0.00
tl_d_oob_addr_access 0 25 0.00
lc_ctrl_tl_errors 1.447s 0.000us 0 25 0.00
tl_d_illegal_access 0 25 0.00
lc_ctrl_tl_errors 1.447s 0.000us 0 25 0.00
tl_d_outstanding_access 0 12 0.00
lc_ctrl_csr_hw_reset 0.796s 0.000us 0 1 0.00
lc_ctrl_csr_rw 0.855s 0.000us 0 5 0.00
lc_ctrl_csr_aliasing 0.823s 0.000us 0 1 0.00
lc_ctrl_same_csr_outstanding 0.835s 0.000us 0 5 0.00
tl_d_partial_access 0 12 0.00
lc_ctrl_csr_hw_reset 0.796s 0.000us 0 1 0.00
lc_ctrl_csr_rw 0.855s 0.000us 0 5 0.00
lc_ctrl_csr_aliasing 0.823s 0.000us 0 1 0.00
lc_ctrl_same_csr_outstanding 0.835s 0.000us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 30 0.00
lc_ctrl_sec_cm 0.843s 0.000us 0 5 0.00
lc_ctrl_tl_intg_err 1.503s 0.000us 0 25 0.00
sec_cm_bus_integrity 0 25 0.00
lc_ctrl_tl_intg_err 1.503s 0.000us 0 25 0.00
sec_cm_transition_config_regwen 0 10 0.00
lc_ctrl_regwen_during_op 1.381s 0.000us 0 10 0.00
sec_cm_manuf_state_sparse 0 25 0.00
lc_ctrl_state_failure 1.509s 0.000us 0 20 0.00
lc_ctrl_sec_cm 0.843s 0.000us 0 5 0.00
sec_cm_transition_ctr_sparse 0 25 0.00
lc_ctrl_state_failure 1.509s 0.000us 0 20 0.00
lc_ctrl_sec_cm 0.843s 0.000us 0 5 0.00
sec_cm_manuf_state_bkgn_chk 0 25 0.00
lc_ctrl_state_failure 1.509s 0.000us 0 20 0.00
lc_ctrl_sec_cm 0.843s 0.000us 0 5 0.00
sec_cm_transition_ctr_bkgn_chk 0 25 0.00
lc_ctrl_state_failure 1.509s 0.000us 0 20 0.00
lc_ctrl_sec_cm 0.843s 0.000us 0 5 0.00
sec_cm_state_config_sparse 0 25 0.00
lc_ctrl_state_failure 1.509s 0.000us 0 20 0.00
lc_ctrl_sec_cm 0.843s 0.000us 0 5 0.00
sec_cm_main_fsm_sparse 0 25 0.00
lc_ctrl_state_failure 1.509s 0.000us 0 20 0.00
lc_ctrl_sec_cm 0.843s 0.000us 0 5 0.00
sec_cm_kmac_fsm_sparse 0 25 0.00
lc_ctrl_state_failure 1.509s 0.000us 0 20 0.00
lc_ctrl_sec_cm 0.843s 0.000us 0 5 0.00
sec_cm_main_fsm_local_esc 0 25 0.00
lc_ctrl_state_failure 1.509s 0.000us 0 20 0.00
lc_ctrl_sec_cm 0.843s 0.000us 0 5 0.00
sec_cm_main_fsm_global_esc 0 20 0.00
lc_ctrl_security_escalation 1.545s 0.000us 0 20 0.00
sec_cm_main_ctrl_flow_consistency 0 40 0.00
lc_ctrl_state_post_trans 1.390s 0.000us 0 20 0.00
lc_ctrl_jtag_state_post_trans 1.397s 0.000us 0 20 0.00
sec_cm_intersig_mubi 0 10 0.00
lc_ctrl_sec_mubi 1.544s 0.000us 0 10 0.00
sec_cm_token_valid_ctrl_mubi 0 10 0.00
lc_ctrl_sec_mubi 1.544s 0.000us 0 10 0.00
sec_cm_token_digest 0 10 0.00
lc_ctrl_sec_token_digest 1.404s 0.000us 0 10 0.00
sec_cm_token_mux_ctrl_redun 0 10 0.00
lc_ctrl_sec_token_mux 1.367s 0.000us 0 10 0.00
sec_cm_token_valid_mux_redun 0 10 0.00
lc_ctrl_sec_token_mux 1.367s 0.000us 0 10 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
lc_ctrl_stress_all_with_rand_reset 1.520s 0.000us 0 10 0.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 513 test runs
lc_ctrl_smoke 35137400309654842566589413303448553549860575853808327749804171692729826291390 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=50343614 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/0.lc_ctrl_smoke.50343614 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_smoke.50343614 -covoverwrite' seed=35137400309654842566589413303448553549860575853808327749804171692729826291390 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35137400309654842566589413303448553549860575853808327749804171692729826291390 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_volatile_unlock_smoke 77565230822261645268512813554840917244575460800762622899676469521096253329697 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_volatile_unlock_smoke/latest run_opts='+en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2594918689 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/0.lc_ctrl_volatile_unlock_smoke.2594918689 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_volatile_unlock_smoke.2594918689 -covoverwrite' seed=77565230822261645268512813554840917244575460800762622899676469521096253329697 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77565230822261645268512813554840917244575460800762622899676469521096253329697 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_volatile_unlock_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_volatile_unlock_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 46606091118107874716602709976983248957364432152859962271275281194580119799811 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=177883139 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/0.lc_ctrl_state_failure.177883139 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_state_failure.177883139 -covoverwrite' seed=46606091118107874716602709976983248957364432152859962271275281194580119799811 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46606091118107874716602709976983248957364432152859962271275281194580119799811 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 30054809795984309334133718788312673614344124883977765261304970677630131364301 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1816519117 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/0.lc_ctrl_state_post_trans.1816519117 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_state_post_trans.1816519117 -covoverwrite' seed=30054809795984309334133718788312673614344124883977765261304970677630131364301 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30054809795984309334133718788312673614344124883977765261304970677630131364301 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 37982308975823963661295406760248905836402747019680656492484276183376432609497 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=833763545 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/0.lc_ctrl_prog_failure.833763545 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_prog_failure.833763545 -covoverwrite' seed=37982308975823963661295406760248905836402747019680656492484276183376432609497 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37982308975823963661295406760248905836402747019680656492484276183376432609497 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 11038887496599212243448579259737072173857701410547112660652028656998199711313 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1161156177 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/0.lc_ctrl_errors.1161156177 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_errors.1161156177 -covoverwrite' seed=11038887496599212243448579259737072173857701410547112660652028656998199711313 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11038887496599212243448579259737072173857701410547112660652028656998199711313 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 71348753691993183158843417551318593830058907254246213825356598316896208263503 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2873858383 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/0.lc_ctrl_security_escalation.2873858383 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_security_escalation.2873858383 -covoverwrite' seed=71348753691993183158843417551318593830058907254246213825356598316896208263503 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71348753691993183158843417551318593830058907254246213825356598316896208263503 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_regwen_during_op 71972624284483835474109032659617231096602440486718693225500151427400112047286 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_regwen_during_op/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2816509110 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/0.lc_ctrl_regwen_during_op.2816509110 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_regwen_during_op.2816509110 -covoverwrite' seed=71972624284483835474109032659617231096602440486718693225500151427400112047286 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71972624284483835474109032659617231096602440486718693225500151427400112047286 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_claim_transition_if 31290784099205168674961060143157777519191952964548592037550536665900426504529 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_claim_transition_if/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3287591249 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/0.lc_ctrl_claim_transition_if.3287591249 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_claim_transition_if.3287591249 -covoverwrite' seed=31290784099205168674961060143157777519191952964548592037550536665900426504529 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31290784099205168674961060143157777519191952964548592037550536665900426504529 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_claim_transition_if/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_claim_transition_if_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 98856562102654074913653775167743746920875985656411888667068231107148940039189 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2937050133 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/0.lc_ctrl_jtag_smoke.2937050133 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_jtag_smoke.2937050133 -covoverwrite' seed=98856562102654074913653775167743746920875985656411888667068231107148940039189 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98856562102654074913653775167743746920875985656411888667068231107148940039189 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 90721103561449415326547894989219588908095829366428544342216241719663693936471 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=131348311 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/0.lc_ctrl_jtag_state_failure.131348311 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_jtag_state_failure.131348311 -covoverwrite' seed=90721103561449415326547894989219588908095829366428544342216241719663693936471 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90721103561449415326547894989219588908095829366428544342216241719663693936471 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 90940415935394599929020459874515102012590340274606569678230942896384230811897 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2460739833 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/0.lc_ctrl_jtag_state_post_trans.2460739833 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_jtag_state_post_trans.2460739833 -covoverwrite' seed=90940415935394599929020459874515102012590340274606569678230942896384230811897 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90940415935394599929020459874515102012590340274606569678230942896384230811897 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 75819827326706219555903824692203969104734762917761626122094060712879996530114 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=376696258 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/0.lc_ctrl_jtag_prog_failure.376696258 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_jtag_prog_failure.376696258 -covoverwrite' seed=75819827326706219555903824692203969104734762917761626122094060712879996530114 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75819827326706219555903824692203969104734762917761626122094060712879996530114 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 79778151042138775719128571143058916890004859961845340049805586122850022640755 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1147849843 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/0.lc_ctrl_jtag_errors.1147849843 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_jtag_errors.1147849843 -covoverwrite' seed=79778151042138775719128571143058916890004859961845340049805586122850022640755 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79778151042138775719128571143058916890004859961845340049805586122850022640755 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 57186733302686265224774019032914121008946638152076972077478192013147514411670 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1755650710 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/0.lc_ctrl_jtag_access.1755650710 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_jtag_access.1755650710 -covoverwrite' seed=57186733302686265224774019032914121008946638152076972077478192013147514411670 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57186733302686265224774019032914121008946638152076972077478192013147514411670 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_priority 101171337784849613881943770789495223997331295127698669644042869417240607098255 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_jtag_priority/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1239713167 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/0.lc_ctrl_jtag_priority.1239713167 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_jtag_priority.1239713167 -covoverwrite' seed=101171337784849613881943770789495223997331295127698669644042869417240607098255 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101171337784849613881943770789495223997331295127698669644042869417240607098255 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_jtag_priority/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_priority_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_regwen_during_op 21558224961856615762790573143336327734953767791881367353528069672877235927967 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_jtag_regwen_during_op/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=167803807 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/0.lc_ctrl_jtag_regwen_during_op.167803807 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_jtag_regwen_during_op.167803807 -covoverwrite' seed=21558224961856615762790573143336327734953767791881367353528069672877235927967 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21558224961856615762790573143336327734953767791881367353528069672877235927967 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_jtag_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_hw_reset 74863956203281276246406327001871503405352689875432651770032304716916876590438 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_jtag_csr_hw_reset/latest run_opts='+csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=406535526 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.406535526 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.lc_ctrl_jtag_csr_hw_reset.406535526 -covoverwrite' seed=74863956203281276246406327001871503405352689875432651770032304716916876590438 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74863956203281276246406327001871503405352689875432651770032304716916876590438 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_jtag_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_rw 46091837664697400735305067601305178783220916783095188972635242357451165380306 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_jtag_csr_rw/latest run_opts='+csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3924668114 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3924668114 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.lc_ctrl_jtag_csr_rw.3924668114 -covoverwrite' seed=46091837664697400735305067601305178783220916783095188972635242357451165380306 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46091837664697400735305067601305178783220916783095188972635242357451165380306 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_jtag_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_bit_bash 89792965647681710696987073743772473817237364407146901860657031174887719982080 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_jtag_csr_bit_bash/latest run_opts='+csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1520063488 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.1520063488 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.lc_ctrl_jtag_csr_bit_bash.1520063488 -covoverwrite' seed=89792965647681710696987073743772473817237364407146901860657031174887719982080 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89792965647681710696987073743772473817237364407146901860657031174887719982080 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_jtag_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_aliasing 94938582193936938233736953084653643466299738411142478038199396488286979744085 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_jtag_csr_aliasing/latest run_opts='+csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1199825237 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1199825237 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.lc_ctrl_jtag_csr_aliasing.1199825237 -covoverwrite' seed=94938582193936938233736953084653643466299738411142478038199396488286979744085 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94938582193936938233736953084653643466299738411142478038199396488286979744085 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_jtag_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_same_csr_outstanding 49870954412644611416524086430258800709839536153478394483873269520376599987884 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_jtag_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3638347436 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3638347436 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.lc_ctrl_jtag_same_csr_outstanding.3638347436 -covoverwrite' seed=49870954412644611416524086430258800709839536153478394483873269520376599987884 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49870954412644611416524086430258800709839536153478394483873269520376599987884 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_jtag_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 40186610425961765941695049448218364269824118603031605994969380292306659738552 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3775431608 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3775431608 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3775431608 -covoverwrite' seed=40186610425961765941695049448218364269824118603031605994969380292306659738552 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40186610425961765941695049448218364269824118603031605994969380292306659738552 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_alert_test 37278062888528342845183983030411295954551244776969752220099559188467852052593 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_jtag_alert_test/latest run_opts='+run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=167577713 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.167577713 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.lc_ctrl_jtag_alert_test.167577713 -covoverwrite' seed=37278062888528342845183983030411295954551244776969752220099559188467852052593 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37278062888528342845183983030411295954551244776969752220099559188467852052593 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_jtag_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_mubi 94815898879618078828310628138317969700820043887734321705449652590386000169842 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_sec_mubi/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=459541362 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/0.lc_ctrl_sec_mubi.459541362 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_sec_mubi.459541362 -covoverwrite' seed=94815898879618078828310628138317969700820043887734321705449652590386000169842 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94815898879618078828310628138317969700820043887734321705449652590386000169842 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_sec_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_mubi_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_mux 115491395980492601276034165655105963633193939732575873687672263465757059336619 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_sec_token_mux/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3269478827 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/0.lc_ctrl_sec_token_mux.3269478827 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_sec_token_mux.3269478827 -covoverwrite' seed=115491395980492601276034165655105963633193939732575873687672263465757059336619 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115491395980492601276034165655105963633193939732575873687672263465757059336619 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_sec_token_mux/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_mux_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_digest 78503848115766496035393905387209921634631017826196476792958237974752017077323 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_sec_token_digest/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1387615307 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/0.lc_ctrl_sec_token_digest.1387615307 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_sec_token_digest.1387615307 -covoverwrite' seed=78503848115766496035393905387209921634631017826196476792958237974752017077323 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78503848115766496035393905387209921634631017826196476792958237974752017077323 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_sec_token_digest/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_digest_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_stress_all_with_rand_reset 47200060190083839133231060688286128843120732246062259625040657151550926224134 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_stress_all_with_rand_reset/latest run_opts='+create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3553491718 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.3553491718 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_stress_all_with_rand_reset.3553491718 -covoverwrite' seed=47200060190083839133231060688286128843120732246062259625040657151550926224134 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47200060190083839133231060688286128843120732246062259625040657151550926224134 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_cm 89396585868274408664602067648516728838235505611434779428951499724256252978859 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1050076843 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/0.lc_ctrl_sec_cm.1050076843 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_sec_cm.1050076843 -covoverwrite' seed=89396585868274408664602067648516728838235505611434779428951499724256252978859 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89396585868274408664602067648516728838235505611434779428951499724256252978859 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 109157432275358962030387929974367422576542742332647677468401793938775499294170 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1815037402 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/0.lc_ctrl_tl_errors.1815037402 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.lc_ctrl_tl_errors.1815037402 -covoverwrite' seed=109157432275358962030387929974367422576542742332647677468401793938775499294170 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109157432275358962030387929974367422576542742332647677468401793938775499294170 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 104439962142991122510540277159389518680804908296545689674767635143582258701771 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4039255499 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.4039255499 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.lc_ctrl_tl_intg_err.4039255499 -covoverwrite' seed=104439962142991122510540277159389518680804908296545689674767635143582258701771 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104439962142991122510540277159389518680804908296545689674767635143582258701771 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_alert_test 32280095067764506307824947770962654747701932871089370326791319119005584982950 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1219756966 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/0.lc_ctrl_alert_test.1219756966 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_alert_test.1219756966 -covoverwrite' seed=32280095067764506307824947770962654747701932871089370326791319119005584982950 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32280095067764506307824947770962654747701932871089370326791319119005584982950 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_csr_hw_reset 78276373795363553750715848504050537202987101100162040376613735916977247398093 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_csr_hw_reset/latest run_opts='+csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1115072717 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.1115072717 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.lc_ctrl_csr_hw_reset.1115072717 -covoverwrite' seed=78276373795363553750715848504050537202987101100162040376613735916977247398093 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78276373795363553750715848504050537202987101100162040376613735916977247398093 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_csr_rw 80043876865809800849057850363956328880474765607345595412848587642827650347705 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=749187769 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/0.lc_ctrl_csr_rw.749187769 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.lc_ctrl_csr_rw.749187769 -covoverwrite' seed=80043876865809800849057850363956328880474765607345595412848587642827650347705 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80043876865809800849057850363956328880474765607345595412848587642827650347705 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_csr_bit_bash 88022117631488255559538761739324982033422497964581694726434909639840073125494 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_csr_bit_bash/latest run_opts='+csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2489454198 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2489454198 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.lc_ctrl_csr_bit_bash.2489454198 -covoverwrite' seed=88022117631488255559538761739324982033422497964581694726434909639840073125494 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88022117631488255559538761739324982033422497964581694726434909639840073125494 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_csr_aliasing 19408621532868102831247738421597596349493742305582064439270036660174759930121 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_csr_aliasing/latest run_opts='+csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1439705353 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.1439705353 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.lc_ctrl_csr_aliasing.1439705353 -covoverwrite' seed=19408621532868102831247738421597596349493742305582064439270036660174759930121 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19408621532868102831247738421597596349493742305582064439270036660174759930121 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_same_csr_outstanding 95005709542116593100713214480131804544603536826704157565001157632868237635642 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1740566586 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1740566586 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.lc_ctrl_same_csr_outstanding.1740566586 -covoverwrite' seed=95005709542116593100713214480131804544603536826704157565001157632868237635642 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95005709542116593100713214480131804544603536826704157565001157632868237635642 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_csr_mem_rw_with_rand_reset 253160081415883796250283976309817105093936344394848899914936332492671213501 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3225083837 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.3225083837 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.lc_ctrl_csr_mem_rw_with_rand_reset.3225083837 -covoverwrite' seed=253160081415883796250283976309817105093936344394848899914936332492671213501 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=253160081415883796250283976309817105093936344394848899914936332492671213501 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 35414157686995464509042189008666859810172390940185070310331066018504251770015 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2291369119 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/1.lc_ctrl_smoke.2291369119 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_smoke.2291369119 -covoverwrite' seed=35414157686995464509042189008666859810172390940185070310331066018504251770015 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35414157686995464509042189008666859810172390940185070310331066018504251770015 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_volatile_unlock_smoke 112219156822694170092521792608663390135749514480448406769820274087495843259357 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_volatile_unlock_smoke/latest run_opts='+en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1410147293 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/1.lc_ctrl_volatile_unlock_smoke.1410147293 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_volatile_unlock_smoke.1410147293 -covoverwrite' seed=112219156822694170092521792608663390135749514480448406769820274087495843259357 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112219156822694170092521792608663390135749514480448406769820274087495843259357 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_volatile_unlock_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_volatile_unlock_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 61174704956033156750180765819421371335567953859284727765334410635775877859115 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=14436139 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/1.lc_ctrl_state_failure.14436139 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_state_failure.14436139 -covoverwrite' seed=61174704956033156750180765819421371335567953859284727765334410635775877859115 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61174704956033156750180765819421371335567953859284727765334410635775877859115 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 9374215744649792069792362856502644346768860174451056139843763083924785225590 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3855507318 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/1.lc_ctrl_state_post_trans.3855507318 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_state_post_trans.3855507318 -covoverwrite' seed=9374215744649792069792362856502644346768860174451056139843763083924785225590 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9374215744649792069792362856502644346768860174451056139843763083924785225590 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 42688362789584217944307188369880105289186285827967886960080528628772700710289 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3693110673 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/1.lc_ctrl_prog_failure.3693110673 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_prog_failure.3693110673 -covoverwrite' seed=42688362789584217944307188369880105289186285827967886960080528628772700710289 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42688362789584217944307188369880105289186285827967886960080528628772700710289 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 9694075472955138102101340414152455863913882044668319970586914942202294065876 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2447923924 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/1.lc_ctrl_errors.2447923924 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_errors.2447923924 -covoverwrite' seed=9694075472955138102101340414152455863913882044668319970586914942202294065876 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9694075472955138102101340414152455863913882044668319970586914942202294065876 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 27168687409030818075948895085353239289174035227828683695826011875470162154329 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2224444249 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/1.lc_ctrl_security_escalation.2224444249 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_security_escalation.2224444249 -covoverwrite' seed=27168687409030818075948895085353239289174035227828683695826011875470162154329 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27168687409030818075948895085353239289174035227828683695826011875470162154329 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_regwen_during_op 75814693532541894960392711711097674923578918942990588893981353572556351981122 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_regwen_during_op/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1644414530 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/1.lc_ctrl_regwen_during_op.1644414530 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_regwen_during_op.1644414530 -covoverwrite' seed=75814693532541894960392711711097674923578918942990588893981353572556351981122 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75814693532541894960392711711097674923578918942990588893981353572556351981122 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_claim_transition_if 61605461913613441482649608554332464218019890884586803372012637422676195822309 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_claim_transition_if/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1721649893 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/1.lc_ctrl_claim_transition_if.1721649893 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_claim_transition_if.1721649893 -covoverwrite' seed=61605461913613441482649608554332464218019890884586803372012637422676195822309 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61605461913613441482649608554332464218019890884586803372012637422676195822309 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_claim_transition_if/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_claim_transition_if_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 110680944905364936988514244879814092700759221974900755981423283435747111184364 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=328312812 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/1.lc_ctrl_jtag_smoke.328312812 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_jtag_smoke.328312812 -covoverwrite' seed=110680944905364936988514244879814092700759221974900755981423283435747111184364 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110680944905364936988514244879814092700759221974900755981423283435747111184364 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 55365148766530597622724869814214685669647619943641003876188304508460741027176 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=763487592 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/1.lc_ctrl_jtag_state_failure.763487592 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_jtag_state_failure.763487592 -covoverwrite' seed=55365148766530597622724869814214685669647619943641003876188304508460741027176 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55365148766530597622724869814214685669647619943641003876188304508460741027176 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 50714419128192298798408224354269522512578346757200535992982265819182589421979 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=491923867 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/1.lc_ctrl_jtag_state_post_trans.491923867 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_jtag_state_post_trans.491923867 -covoverwrite' seed=50714419128192298798408224354269522512578346757200535992982265819182589421979 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50714419128192298798408224354269522512578346757200535992982265819182589421979 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 108128260686088936439282988151337888739966487269444132953456733844022457048973 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2799214477 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/1.lc_ctrl_jtag_prog_failure.2799214477 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_jtag_prog_failure.2799214477 -covoverwrite' seed=108128260686088936439282988151337888739966487269444132953456733844022457048973 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108128260686088936439282988151337888739966487269444132953456733844022457048973 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 33168738615039955595756761779490560915146225640640984017953406731436374958609 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3825279505 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/1.lc_ctrl_jtag_errors.3825279505 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_jtag_errors.3825279505 -covoverwrite' seed=33168738615039955595756761779490560915146225640640984017953406731436374958609 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33168738615039955595756761779490560915146225640640984017953406731436374958609 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 115177546041228205128140681830733161319824781761398393100474209406759031074304 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2084892160 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/1.lc_ctrl_jtag_access.2084892160 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_jtag_access.2084892160 -covoverwrite' seed=115177546041228205128140681830733161319824781761398393100474209406759031074304 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115177546041228205128140681830733161319824781761398393100474209406759031074304 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_priority 18940574069846509202150289084609039737422048129204718591685149038484380155472 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_jtag_priority/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3343613520 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/1.lc_ctrl_jtag_priority.3343613520 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_jtag_priority.3343613520 -covoverwrite' seed=18940574069846509202150289084609039737422048129204718591685149038484380155472 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18940574069846509202150289084609039737422048129204718591685149038484380155472 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_jtag_priority/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_priority_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_regwen_during_op 44238550445988610573286509027801590678487593789753102429450732960001889024769 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_jtag_regwen_during_op/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=554842881 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/1.lc_ctrl_jtag_regwen_during_op.554842881 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_jtag_regwen_during_op.554842881 -covoverwrite' seed=44238550445988610573286509027801590678487593789753102429450732960001889024769 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44238550445988610573286509027801590678487593789753102429450732960001889024769 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_jtag_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_hw_reset 94372645376146974283915731673629513851157067763717440849087054756212327941282 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_jtag_csr_hw_reset/latest run_opts='+csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2628355234 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2628355234 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.lc_ctrl_jtag_csr_hw_reset.2628355234 -covoverwrite' seed=94372645376146974283915731673629513851157067763717440849087054756212327941282 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94372645376146974283915731673629513851157067763717440849087054756212327941282 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_jtag_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_rw 59870769352615510079145492162969389911016291457195387028000087055756845143647 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_jtag_csr_rw/latest run_opts='+csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2598917727 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.2598917727 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.lc_ctrl_jtag_csr_rw.2598917727 -covoverwrite' seed=59870769352615510079145492162969389911016291457195387028000087055756845143647 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=59870769352615510079145492162969389911016291457195387028000087055756845143647 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_jtag_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_bit_bash 8054290696085323724087888622736995800165717558157157674578075561647920763629 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_jtag_csr_bit_bash/latest run_opts='+csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3036533485 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.3036533485 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.lc_ctrl_jtag_csr_bit_bash.3036533485 -covoverwrite' seed=8054290696085323724087888622736995800165717558157157674578075561647920763629 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8054290696085323724087888622736995800165717558157157674578075561647920763629 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_jtag_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_aliasing 28031123788248719726555628983696660408605008507951169266599085210675671290434 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_jtag_csr_aliasing/latest run_opts='+csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1420907074 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1420907074 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.lc_ctrl_jtag_csr_aliasing.1420907074 -covoverwrite' seed=28031123788248719726555628983696660408605008507951169266599085210675671290434 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28031123788248719726555628983696660408605008507951169266599085210675671290434 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_jtag_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_same_csr_outstanding 55794883229320395623954166212225638080181380308937044474921803150428555301332 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_jtag_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2051133908 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2051133908 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.lc_ctrl_jtag_same_csr_outstanding.2051133908 -covoverwrite' seed=55794883229320395623954166212225638080181380308937044474921803150428555301332 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55794883229320395623954166212225638080181380308937044474921803150428555301332 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_jtag_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 104786537962845386275265682253422423988938139760673614525234275171644430169134 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3020764206 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3020764206 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3020764206 -covoverwrite' seed=104786537962845386275265682253422423988938139760673614525234275171644430169134 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104786537962845386275265682253422423988938139760673614525234275171644430169134 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_alert_test 24438340261981433737329789394871053844252549997635242054731208220625053005663 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_jtag_alert_test/latest run_opts='+run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=25016159 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.25016159 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.lc_ctrl_jtag_alert_test.25016159 -covoverwrite' seed=24438340261981433737329789394871053844252549997635242054731208220625053005663 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24438340261981433737329789394871053844252549997635242054731208220625053005663 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_jtag_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_mubi 72267400942974710547774763813199542089570711585671416486211691643988561558028 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_sec_mubi/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2624256524 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/1.lc_ctrl_sec_mubi.2624256524 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_sec_mubi.2624256524 -covoverwrite' seed=72267400942974710547774763813199542089570711585671416486211691643988561558028 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72267400942974710547774763813199542089570711585671416486211691643988561558028 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_sec_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_mubi_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_mux 23502631416196188305034569771730392723403244337998663885436860129861038319486 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_sec_token_mux/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2287282046 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/1.lc_ctrl_sec_token_mux.2287282046 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_sec_token_mux.2287282046 -covoverwrite' seed=23502631416196188305034569771730392723403244337998663885436860129861038319486 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23502631416196188305034569771730392723403244337998663885436860129861038319486 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_sec_token_mux/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_mux_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_digest 3423674968744812288659031129232898014365825064319949016278140457258429226424 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_sec_token_digest/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2154077624 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/1.lc_ctrl_sec_token_digest.2154077624 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_sec_token_digest.2154077624 -covoverwrite' seed=3423674968744812288659031129232898014365825064319949016278140457258429226424 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3423674968744812288659031129232898014365825064319949016278140457258429226424 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_sec_token_digest/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_digest_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_stress_all_with_rand_reset 19834124959631736363476333828602161914102817985926197228718650804847293966937 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_stress_all_with_rand_reset/latest run_opts='+create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2466720345 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.2466720345 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_stress_all_with_rand_reset.2466720345 -covoverwrite' seed=19834124959631736363476333828602161914102817985926197228718650804847293966937 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19834124959631736363476333828602161914102817985926197228718650804847293966937 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_cm 65326953597504312256788187673158175517112358252412794653039467560369167346581 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3416337301 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/1.lc_ctrl_sec_cm.3416337301 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_sec_cm.3416337301 -covoverwrite' seed=65326953597504312256788187673158175517112358252412794653039467560369167346581 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65326953597504312256788187673158175517112358252412794653039467560369167346581 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 54377097621945674118591266588679713448703158920231895536382257888505709577945 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3820078809 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/1.lc_ctrl_tl_errors.3820078809 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.lc_ctrl_tl_errors.3820078809 -covoverwrite' seed=54377097621945674118591266588679713448703158920231895536382257888505709577945 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54377097621945674118591266588679713448703158920231895536382257888505709577945 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 38442908146456051018719770142941334315020419528335297868969758696196426296890 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2440162874 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2440162874 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.lc_ctrl_tl_intg_err.2440162874 -covoverwrite' seed=38442908146456051018719770142941334315020419528335297868969758696196426296890 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38442908146456051018719770142941334315020419528335297868969758696196426296890 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_alert_test 101514653170077807400688422945731639451727193287648080784679344661978219538579 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1335355539 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/1.lc_ctrl_alert_test.1335355539 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_alert_test.1335355539 -covoverwrite' seed=101514653170077807400688422945731639451727193287648080784679344661978219538579 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101514653170077807400688422945731639451727193287648080784679344661978219538579 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_csr_rw 108878523483861457103624827848117812645878211494319645203177503606244029127207 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1946835495 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/1.lc_ctrl_csr_rw.1946835495 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.lc_ctrl_csr_rw.1946835495 -covoverwrite' seed=108878523483861457103624827848117812645878211494319645203177503606244029127207 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108878523483861457103624827848117812645878211494319645203177503606244029127207 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_same_csr_outstanding 100055901585724455490352806614638238188853517451301438824775755922800845538528 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2529182944 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.2529182944 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.lc_ctrl_same_csr_outstanding.2529182944 -covoverwrite' seed=100055901585724455490352806614638238188853517451301438824775755922800845538528 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100055901585724455490352806614638238188853517451301438824775755922800845538528 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_csr_mem_rw_with_rand_reset 34596064896136729677273852665311773031159662635064671237191440397387202257346 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3706675650 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.3706675650 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.lc_ctrl_csr_mem_rw_with_rand_reset.3706675650 -covoverwrite' seed=34596064896136729677273852665311773031159662635064671237191440397387202257346 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34596064896136729677273852665311773031159662635064671237191440397387202257346 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 21593504836427692656369272104174264790797036399411195054755995854361234661177 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1712742201 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/2.lc_ctrl_smoke.1712742201 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_smoke.1712742201 -covoverwrite' seed=21593504836427692656369272104174264790797036399411195054755995854361234661177 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21593504836427692656369272104174264790797036399411195054755995854361234661177 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_volatile_unlock_smoke 52849560275968128008526095150778236597648276067667888611440849759934213939838 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_volatile_unlock_smoke/latest run_opts='+en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=720265854 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/2.lc_ctrl_volatile_unlock_smoke.720265854 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_volatile_unlock_smoke.720265854 -covoverwrite' seed=52849560275968128008526095150778236597648276067667888611440849759934213939838 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=52849560275968128008526095150778236597648276067667888611440849759934213939838 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_volatile_unlock_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_volatile_unlock_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 12191971053384997379635544601485410947430139315871909004821282935172480328625 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1700488113 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/2.lc_ctrl_state_failure.1700488113 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_state_failure.1700488113 -covoverwrite' seed=12191971053384997379635544601485410947430139315871909004821282935172480328625 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12191971053384997379635544601485410947430139315871909004821282935172480328625 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 21329323207506892755122062659377092559858746447365430516409639394706229171288 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=525472856 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/2.lc_ctrl_state_post_trans.525472856 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_state_post_trans.525472856 -covoverwrite' seed=21329323207506892755122062659377092559858746447365430516409639394706229171288 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21329323207506892755122062659377092559858746447365430516409639394706229171288 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 86712045076450285818680012357516565294533752936196824268412551746775984130303 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1223706879 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/2.lc_ctrl_prog_failure.1223706879 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_prog_failure.1223706879 -covoverwrite' seed=86712045076450285818680012357516565294533752936196824268412551746775984130303 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86712045076450285818680012357516565294533752936196824268412551746775984130303 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 83725455215005407730026059883708831553939487522523612024032191653308074386921 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=994928105 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/2.lc_ctrl_errors.994928105 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_errors.994928105 -covoverwrite' seed=83725455215005407730026059883708831553939487522523612024032191653308074386921 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83725455215005407730026059883708831553939487522523612024032191653308074386921 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 55283212053189877866985289702622816896380707969348814467247656659247693151504 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2056633616 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/2.lc_ctrl_security_escalation.2056633616 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_security_escalation.2056633616 -covoverwrite' seed=55283212053189877866985289702622816896380707969348814467247656659247693151504 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55283212053189877866985289702622816896380707969348814467247656659247693151504 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_regwen_during_op 77068934590363358294925064267704666637972055319144086978826607649536500741925 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_regwen_during_op/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2700523301 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/2.lc_ctrl_regwen_during_op.2700523301 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_regwen_during_op.2700523301 -covoverwrite' seed=77068934590363358294925064267704666637972055319144086978826607649536500741925 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77068934590363358294925064267704666637972055319144086978826607649536500741925 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_claim_transition_if 69261950124186832500700814760532812662260842674829429616374656968767144391860 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_claim_transition_if/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3158504628 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/2.lc_ctrl_claim_transition_if.3158504628 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_claim_transition_if.3158504628 -covoverwrite' seed=69261950124186832500700814760532812662260842674829429616374656968767144391860 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69261950124186832500700814760532812662260842674829429616374656968767144391860 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_claim_transition_if/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_claim_transition_if_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 91680552683827355858503908199667102087711258359876080750417913529535455631214 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2404194158 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/2.lc_ctrl_jtag_smoke.2404194158 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_jtag_smoke.2404194158 -covoverwrite' seed=91680552683827355858503908199667102087711258359876080750417913529535455631214 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91680552683827355858503908199667102087711258359876080750417913529535455631214 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 62137196600573143510136508637265051753240472915355687661932804394908883614416 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=626260688 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/2.lc_ctrl_jtag_state_failure.626260688 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_jtag_state_failure.626260688 -covoverwrite' seed=62137196600573143510136508637265051753240472915355687661932804394908883614416 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62137196600573143510136508637265051753240472915355687661932804394908883614416 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 87072041354572862931057241193441015626647981324584995791928260702920531156209 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2013961457 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/2.lc_ctrl_jtag_state_post_trans.2013961457 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_jtag_state_post_trans.2013961457 -covoverwrite' seed=87072041354572862931057241193441015626647981324584995791928260702920531156209 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87072041354572862931057241193441015626647981324584995791928260702920531156209 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 45021157329130493868782142607457618200491905384339404467449372493060966776233 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=612171177 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/2.lc_ctrl_jtag_prog_failure.612171177 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_jtag_prog_failure.612171177 -covoverwrite' seed=45021157329130493868782142607457618200491905384339404467449372493060966776233 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45021157329130493868782142607457618200491905384339404467449372493060966776233 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 52773988448846167510084969888567849084038703615984963598516733944260022318848 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=165754624 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/2.lc_ctrl_jtag_errors.165754624 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_jtag_errors.165754624 -covoverwrite' seed=52773988448846167510084969888567849084038703615984963598516733944260022318848 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=52773988448846167510084969888567849084038703615984963598516733944260022318848 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 28238760693985041592453186648821976732786223029352046588745931949113974094684 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3064888156 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/2.lc_ctrl_jtag_access.3064888156 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_jtag_access.3064888156 -covoverwrite' seed=28238760693985041592453186648821976732786223029352046588745931949113974094684 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28238760693985041592453186648821976732786223029352046588745931949113974094684 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_priority 69964652377268315991070036344204244705256807080867540811973444383526520340797 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_jtag_priority/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1379647805 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/2.lc_ctrl_jtag_priority.1379647805 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_jtag_priority.1379647805 -covoverwrite' seed=69964652377268315991070036344204244705256807080867540811973444383526520340797 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69964652377268315991070036344204244705256807080867540811973444383526520340797 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_jtag_priority/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_priority_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_regwen_during_op 13057377213621263734122523407012984789068484302296431249975846741511089298142 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_jtag_regwen_during_op/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3884587742 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/2.lc_ctrl_jtag_regwen_during_op.3884587742 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_jtag_regwen_during_op.3884587742 -covoverwrite' seed=13057377213621263734122523407012984789068484302296431249975846741511089298142 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13057377213621263734122523407012984789068484302296431249975846741511089298142 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_jtag_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_hw_reset 97356109969447919867022831329794365765934172958627522361289316639240466932915 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_jtag_csr_hw_reset/latest run_opts='+csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=327099571 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.327099571 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.lc_ctrl_jtag_csr_hw_reset.327099571 -covoverwrite' seed=97356109969447919867022831329794365765934172958627522361289316639240466932915 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97356109969447919867022831329794365765934172958627522361289316639240466932915 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_jtag_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_rw 2871722218962111043814144552800032309437654474226678990485341079810868122424 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_jtag_csr_rw/latest run_opts='+csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2886603576 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.2886603576 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.lc_ctrl_jtag_csr_rw.2886603576 -covoverwrite' seed=2871722218962111043814144552800032309437654474226678990485341079810868122424 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2871722218962111043814144552800032309437654474226678990485341079810868122424 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_jtag_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_bit_bash 51806990965019368603435545318735429008306165302840444165609855792713912392165 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_jtag_csr_bit_bash/latest run_opts='+csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=404855269 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.404855269 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.lc_ctrl_jtag_csr_bit_bash.404855269 -covoverwrite' seed=51806990965019368603435545318735429008306165302840444165609855792713912392165 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51806990965019368603435545318735429008306165302840444165609855792713912392165 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_jtag_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_aliasing 35090465107125650046394012937470859290918474598301012324946451942945587288840 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_jtag_csr_aliasing/latest run_opts='+csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=276912904 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.276912904 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.lc_ctrl_jtag_csr_aliasing.276912904 -covoverwrite' seed=35090465107125650046394012937470859290918474598301012324946451942945587288840 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35090465107125650046394012937470859290918474598301012324946451942945587288840 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_jtag_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_same_csr_outstanding 30027773438804116615630039571102186428985279376465371016824794088796401257183 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_jtag_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=75320031 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.75320031 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.lc_ctrl_jtag_same_csr_outstanding.75320031 -covoverwrite' seed=30027773438804116615630039571102186428985279376465371016824794088796401257183 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30027773438804116615630039571102186428985279376465371016824794088796401257183 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_jtag_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 105306603207127893941432585364143499533009454031918403631377563208248480929898 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1659541610 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1659541610 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1659541610 -covoverwrite' seed=105306603207127893941432585364143499533009454031918403631377563208248480929898 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105306603207127893941432585364143499533009454031918403631377563208248480929898 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_alert_test 19891869935941148942560437839031116133429926295042249358960492751888844244274 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_jtag_alert_test/latest run_opts='+run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3837183282 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3837183282 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.lc_ctrl_jtag_alert_test.3837183282 -covoverwrite' seed=19891869935941148942560437839031116133429926295042249358960492751888844244274 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19891869935941148942560437839031116133429926295042249358960492751888844244274 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_jtag_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_mubi 67211769337116165784566775753442519284015654837266650240875260779087719161513 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_sec_mubi/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3408256681 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/2.lc_ctrl_sec_mubi.3408256681 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_sec_mubi.3408256681 -covoverwrite' seed=67211769337116165784566775753442519284015654837266650240875260779087719161513 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67211769337116165784566775753442519284015654837266650240875260779087719161513 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_sec_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_mubi_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_mux 41899106447653151678583977716748684474497751631205351089172556076955064228813 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_sec_token_mux/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2184338381 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/2.lc_ctrl_sec_token_mux.2184338381 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_sec_token_mux.2184338381 -covoverwrite' seed=41899106447653151678583977716748684474497751631205351089172556076955064228813 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41899106447653151678583977716748684474497751631205351089172556076955064228813 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_sec_token_mux/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_mux_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_digest 31550484886595318600530849967388092697481656693225891588991483704484930260077 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_sec_token_digest/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1730415725 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/2.lc_ctrl_sec_token_digest.1730415725 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_sec_token_digest.1730415725 -covoverwrite' seed=31550484886595318600530849967388092697481656693225891588991483704484930260077 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31550484886595318600530849967388092697481656693225891588991483704484930260077 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_sec_token_digest/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_digest_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_stress_all_with_rand_reset 32345464066940081380955401866458796238016481722646418732318585490724589886619 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_stress_all_with_rand_reset/latest run_opts='+create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2486131867 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.2486131867 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_stress_all_with_rand_reset.2486131867 -covoverwrite' seed=32345464066940081380955401866458796238016481722646418732318585490724589886619 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32345464066940081380955401866458796238016481722646418732318585490724589886619 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_cm 32460528629917806481242599827081531304468798188498104526892638189914871118571 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=206650091 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/2.lc_ctrl_sec_cm.206650091 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_sec_cm.206650091 -covoverwrite' seed=32460528629917806481242599827081531304468798188498104526892638189914871118571 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32460528629917806481242599827081531304468798188498104526892638189914871118571 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 46653486619686024285489969423725855694373648314263386606824171818403011133479 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3220865063 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3220865063 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.lc_ctrl_tl_errors.3220865063 -covoverwrite' seed=46653486619686024285489969423725855694373648314263386606824171818403011133479 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46653486619686024285489969423725855694373648314263386606824171818403011133479 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 49097779793492340452957137513165903934853569162928018970685813850840778132161 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1536150209 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.1536150209 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.lc_ctrl_tl_intg_err.1536150209 -covoverwrite' seed=49097779793492340452957137513165903934853569162928018970685813850840778132161 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49097779793492340452957137513165903934853569162928018970685813850840778132161 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_alert_test 45789221075984899277098588910973815102517300641311585900488711162478748349694 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1837217022 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/2.lc_ctrl_alert_test.1837217022 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_alert_test.1837217022 -covoverwrite' seed=45789221075984899277098588910973815102517300641311585900488711162478748349694 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45789221075984899277098588910973815102517300641311585900488711162478748349694 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_csr_rw 78828940093322164117751778547645270217653676295474597482358240744922776284476 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1470573884 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/2.lc_ctrl_csr_rw.1470573884 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.lc_ctrl_csr_rw.1470573884 -covoverwrite' seed=78828940093322164117751778547645270217653676295474597482358240744922776284476 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78828940093322164117751778547645270217653676295474597482358240744922776284476 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_same_csr_outstanding 1330306964768515947601856498669066828104957628006867853643770575913485917058 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3659062146 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.3659062146 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.lc_ctrl_same_csr_outstanding.3659062146 -covoverwrite' seed=1330306964768515947601856498669066828104957628006867853643770575913485917058 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1330306964768515947601856498669066828104957628006867853643770575913485917058 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_csr_mem_rw_with_rand_reset 78449201866785351015762142558932469437583111240576200337983371266761878159604 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3158589684 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.3158589684 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.lc_ctrl_csr_mem_rw_with_rand_reset.3158589684 -covoverwrite' seed=78449201866785351015762142558932469437583111240576200337983371266761878159604 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78449201866785351015762142558932469437583111240576200337983371266761878159604 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 27913504857793526977290904918823707520678865784649650637821798762007791696399 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=542407183 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/3.lc_ctrl_smoke.542407183 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_smoke.542407183 -covoverwrite' seed=27913504857793526977290904918823707520678865784649650637821798762007791696399 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27913504857793526977290904918823707520678865784649650637821798762007791696399 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_volatile_unlock_smoke 39227532783703567521008744081957702775789031418271127094932310538751091391487 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_volatile_unlock_smoke/latest run_opts='+en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1771813887 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/3.lc_ctrl_volatile_unlock_smoke.1771813887 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_volatile_unlock_smoke.1771813887 -covoverwrite' seed=39227532783703567521008744081957702775789031418271127094932310538751091391487 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39227532783703567521008744081957702775789031418271127094932310538751091391487 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_volatile_unlock_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_volatile_unlock_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 110522852106681502298055287963386555578534392210637402238169695609619772289052 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2493722652 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/3.lc_ctrl_state_failure.2493722652 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_state_failure.2493722652 -covoverwrite' seed=110522852106681502298055287963386555578534392210637402238169695609619772289052 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110522852106681502298055287963386555578534392210637402238169695609619772289052 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 101076723367662033873671434374796663178519257102011715865360905808631276857506 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1744660642 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/3.lc_ctrl_state_post_trans.1744660642 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_state_post_trans.1744660642 -covoverwrite' seed=101076723367662033873671434374796663178519257102011715865360905808631276857506 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101076723367662033873671434374796663178519257102011715865360905808631276857506 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 106721750161194735572671274008162432205195478675890538416745529099322306127165 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1425597757 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/3.lc_ctrl_prog_failure.1425597757 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_prog_failure.1425597757 -covoverwrite' seed=106721750161194735572671274008162432205195478675890538416745529099322306127165 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106721750161194735572671274008162432205195478675890538416745529099322306127165 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 38568912808685947472745107529357652041263187838342647321947102470379153753031 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=167871431 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/3.lc_ctrl_errors.167871431 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_errors.167871431 -covoverwrite' seed=38568912808685947472745107529357652041263187838342647321947102470379153753031 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38568912808685947472745107529357652041263187838342647321947102470379153753031 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 1627862321774939195396738713852374965645192461865913392101707745388257319249 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2465438033 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/3.lc_ctrl_security_escalation.2465438033 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_security_escalation.2465438033 -covoverwrite' seed=1627862321774939195396738713852374965645192461865913392101707745388257319249 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1627862321774939195396738713852374965645192461865913392101707745388257319249 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_regwen_during_op 82039395553533138562423580776470348255020156619909808330992834975196518484709 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_regwen_during_op/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3195996901 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/3.lc_ctrl_regwen_during_op.3195996901 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_regwen_during_op.3195996901 -covoverwrite' seed=82039395553533138562423580776470348255020156619909808330992834975196518484709 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82039395553533138562423580776470348255020156619909808330992834975196518484709 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_claim_transition_if 38289541543213835539793263361650313137756960210548252654131777162283684150106 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_claim_transition_if/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3166649178 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/3.lc_ctrl_claim_transition_if.3166649178 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_claim_transition_if.3166649178 -covoverwrite' seed=38289541543213835539793263361650313137756960210548252654131777162283684150106 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38289541543213835539793263361650313137756960210548252654131777162283684150106 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_claim_transition_if/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_claim_transition_if_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 92302010457597526379548786574085642158071337423725955657714714183807918998715 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1205929147 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/3.lc_ctrl_jtag_smoke.1205929147 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_jtag_smoke.1205929147 -covoverwrite' seed=92302010457597526379548786574085642158071337423725955657714714183807918998715 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92302010457597526379548786574085642158071337423725955657714714183807918998715 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 8652062802033963154857984836874127374209567982009606116019746025967888266195 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1545499603 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/3.lc_ctrl_jtag_state_failure.1545499603 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_jtag_state_failure.1545499603 -covoverwrite' seed=8652062802033963154857984836874127374209567982009606116019746025967888266195 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8652062802033963154857984836874127374209567982009606116019746025967888266195 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 71865984933546558543174896817111121431730601218696395085715508099681052572192 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3792484896 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/3.lc_ctrl_jtag_state_post_trans.3792484896 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_jtag_state_post_trans.3792484896 -covoverwrite' seed=71865984933546558543174896817111121431730601218696395085715508099681052572192 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71865984933546558543174896817111121431730601218696395085715508099681052572192 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 4460892106624381624409045951745261849304552339750174185361461254441929020352 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1709446080 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/3.lc_ctrl_jtag_prog_failure.1709446080 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_jtag_prog_failure.1709446080 -covoverwrite' seed=4460892106624381624409045951745261849304552339750174185361461254441929020352 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4460892106624381624409045951745261849304552339750174185361461254441929020352 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 93360381023205899934230472886619551695813439970874983519757272938450755725937 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1122708081 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/3.lc_ctrl_jtag_errors.1122708081 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_jtag_errors.1122708081 -covoverwrite' seed=93360381023205899934230472886619551695813439970874983519757272938450755725937 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93360381023205899934230472886619551695813439970874983519757272938450755725937 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 17055846932218779253949507290401426936426457312184529985259299782617010818833 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=227561233 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/3.lc_ctrl_jtag_access.227561233 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_jtag_access.227561233 -covoverwrite' seed=17055846932218779253949507290401426936426457312184529985259299782617010818833 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17055846932218779253949507290401426936426457312184529985259299782617010818833 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_priority 104409789195083348614435830468681150872899780415149454460873038813409077266276 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_jtag_priority/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=773228388 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/3.lc_ctrl_jtag_priority.773228388 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_jtag_priority.773228388 -covoverwrite' seed=104409789195083348614435830468681150872899780415149454460873038813409077266276 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104409789195083348614435830468681150872899780415149454460873038813409077266276 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_jtag_priority/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_priority_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_regwen_during_op 27035045515305056077042735065148561870304392691848773420423587130498608546113 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_jtag_regwen_during_op/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=538460481 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/3.lc_ctrl_jtag_regwen_during_op.538460481 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_jtag_regwen_during_op.538460481 -covoverwrite' seed=27035045515305056077042735065148561870304392691848773420423587130498608546113 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27035045515305056077042735065148561870304392691848773420423587130498608546113 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_jtag_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_hw_reset 59573796129932007667468466816784843616266538128879728560431957271758015396777 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_jtag_csr_hw_reset/latest run_opts='+csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3512826793 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.3512826793 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.lc_ctrl_jtag_csr_hw_reset.3512826793 -covoverwrite' seed=59573796129932007667468466816784843616266538128879728560431957271758015396777 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=59573796129932007667468466816784843616266538128879728560431957271758015396777 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_jtag_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_rw 100131741984792899678781348800737427741614245677936574134331198429432181901839 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_jtag_csr_rw/latest run_opts='+csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3728427535 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.3728427535 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.lc_ctrl_jtag_csr_rw.3728427535 -covoverwrite' seed=100131741984792899678781348800737427741614245677936574134331198429432181901839 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100131741984792899678781348800737427741614245677936574134331198429432181901839 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_jtag_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_bit_bash 50900649241345540158471486747304677631701403365557175742924102368955486234387 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_jtag_csr_bit_bash/latest run_opts='+csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1400432403 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.1400432403 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.lc_ctrl_jtag_csr_bit_bash.1400432403 -covoverwrite' seed=50900649241345540158471486747304677631701403365557175742924102368955486234387 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50900649241345540158471486747304677631701403365557175742924102368955486234387 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_jtag_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_aliasing 81322757048679776702896800725558214624553168780382038440680271071927940678631 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_jtag_csr_aliasing/latest run_opts='+csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3491496935 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3491496935 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.lc_ctrl_jtag_csr_aliasing.3491496935 -covoverwrite' seed=81322757048679776702896800725558214624553168780382038440680271071927940678631 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81322757048679776702896800725558214624553168780382038440680271071927940678631 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_jtag_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_same_csr_outstanding 66270954923618629976816161397082412856692870355681002901931605528528420276806 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_jtag_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2040990278 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.2040990278 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.lc_ctrl_jtag_same_csr_outstanding.2040990278 -covoverwrite' seed=66270954923618629976816161397082412856692870355681002901931605528528420276806 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66270954923618629976816161397082412856692870355681002901931605528528420276806 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_jtag_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 88552838219039521457477361326916933714310792202967193105386202580717458107026 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3285658258 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3285658258 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3285658258 -covoverwrite' seed=88552838219039521457477361326916933714310792202967193105386202580717458107026 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88552838219039521457477361326916933714310792202967193105386202580717458107026 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_alert_test 6945645593744595997663061510621122357853049321602411582347968722884648612826 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_jtag_alert_test/latest run_opts='+run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=277984218 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.277984218 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.lc_ctrl_jtag_alert_test.277984218 -covoverwrite' seed=6945645593744595997663061510621122357853049321602411582347968722884648612826 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6945645593744595997663061510621122357853049321602411582347968722884648612826 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_jtag_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_mubi 79792926214038337882707312981502647388997010680252537594450572769526022643804 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_sec_mubi/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1321705564 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/3.lc_ctrl_sec_mubi.1321705564 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_sec_mubi.1321705564 -covoverwrite' seed=79792926214038337882707312981502647388997010680252537594450572769526022643804 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79792926214038337882707312981502647388997010680252537594450572769526022643804 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_sec_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_mubi_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_mux 25071734618462314871054503931738450297955668996218982369199813430848887355298 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_sec_token_mux/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1185052578 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/3.lc_ctrl_sec_token_mux.1185052578 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_sec_token_mux.1185052578 -covoverwrite' seed=25071734618462314871054503931738450297955668996218982369199813430848887355298 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25071734618462314871054503931738450297955668996218982369199813430848887355298 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_sec_token_mux/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_mux_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_digest 71063206017753901829169174891106021426691601955968523941433896020715433825831 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_sec_token_digest/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1142363687 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/3.lc_ctrl_sec_token_digest.1142363687 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_sec_token_digest.1142363687 -covoverwrite' seed=71063206017753901829169174891106021426691601955968523941433896020715433825831 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71063206017753901829169174891106021426691601955968523941433896020715433825831 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_sec_token_digest/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_digest_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_stress_all_with_rand_reset 38860675112191841021735792074554428583088012982619465909338603965255098050622 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_stress_all_with_rand_reset/latest run_opts='+create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2146707518 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.2146707518 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_stress_all_with_rand_reset.2146707518 -covoverwrite' seed=38860675112191841021735792074554428583088012982619465909338603965255098050622 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38860675112191841021735792074554428583088012982619465909338603965255098050622 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_cm 103099432894680805837920930045390320229558494963562083790092310734143666085627 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=427646715 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/3.lc_ctrl_sec_cm.427646715 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_sec_cm.427646715 -covoverwrite' seed=103099432894680805837920930045390320229558494963562083790092310734143666085627 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103099432894680805837920930045390320229558494963562083790092310734143666085627 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 100642661469730551666672342731339067366564971484975123612934366917791825284467 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2212253043 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2212253043 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.lc_ctrl_tl_errors.2212253043 -covoverwrite' seed=100642661469730551666672342731339067366564971484975123612934366917791825284467 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100642661469730551666672342731339067366564971484975123612934366917791825284467 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 104931339987832488855029582641300124034957041769931895375582479066711760172032 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1525019648 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.1525019648 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.lc_ctrl_tl_intg_err.1525019648 -covoverwrite' seed=104931339987832488855029582641300124034957041769931895375582479066711760172032 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104931339987832488855029582641300124034957041769931895375582479066711760172032 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_alert_test 113170771782963432052486491618764522897279000254503450918632983043653986560344 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2637310296 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/3.lc_ctrl_alert_test.2637310296 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_alert_test.2637310296 -covoverwrite' seed=113170771782963432052486491618764522897279000254503450918632983043653986560344 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113170771782963432052486491618764522897279000254503450918632983043653986560344 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_csr_rw 38831829239692249793830309091012462008783825314739917427323309745317543343882 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=470742794 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/3.lc_ctrl_csr_rw.470742794 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.lc_ctrl_csr_rw.470742794 -covoverwrite' seed=38831829239692249793830309091012462008783825314739917427323309745317543343882 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38831829239692249793830309091012462008783825314739917427323309745317543343882 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_same_csr_outstanding 32556009098284362182034754997856554309784843045642378473519889199122071003876 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1761452772 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.1761452772 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.lc_ctrl_same_csr_outstanding.1761452772 -covoverwrite' seed=32556009098284362182034754997856554309784843045642378473519889199122071003876 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32556009098284362182034754997856554309784843045642378473519889199122071003876 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_csr_mem_rw_with_rand_reset 34253316273966546551257891039794930411054004388778641132750504218141446749578 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3434462602 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.3434462602 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.lc_ctrl_csr_mem_rw_with_rand_reset.3434462602 -covoverwrite' seed=34253316273966546551257891039794930411054004388778641132750504218141446749578 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34253316273966546551257891039794930411054004388778641132750504218141446749578 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 49251587710738394138535586630024979705616972771236758471768509057973093663023 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2729705775 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/4.lc_ctrl_smoke.2729705775 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_smoke.2729705775 -covoverwrite' seed=49251587710738394138535586630024979705616972771236758471768509057973093663023 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49251587710738394138535586630024979705616972771236758471768509057973093663023 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_volatile_unlock_smoke 65345101328060238294081629157739191112032481640635368341777788004859474346728 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_volatile_unlock_smoke/latest run_opts='+en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=602145512 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/4.lc_ctrl_volatile_unlock_smoke.602145512 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_volatile_unlock_smoke.602145512 -covoverwrite' seed=65345101328060238294081629157739191112032481640635368341777788004859474346728 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65345101328060238294081629157739191112032481640635368341777788004859474346728 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_volatile_unlock_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_volatile_unlock_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 36955281385007575933808785014768838881985063929509831474764554733120542718658 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1825028802 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/4.lc_ctrl_state_failure.1825028802 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_state_failure.1825028802 -covoverwrite' seed=36955281385007575933808785014768838881985063929509831474764554733120542718658 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36955281385007575933808785014768838881985063929509831474764554733120542718658 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 107911472378144138024025089433595271592941432999172357202530021625807339416400 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=12217168 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/4.lc_ctrl_state_post_trans.12217168 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_state_post_trans.12217168 -covoverwrite' seed=107911472378144138024025089433595271592941432999172357202530021625807339416400 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107911472378144138024025089433595271592941432999172357202530021625807339416400 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 79753769931310592793873407843404518048680805785410575687231460275106577982988 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1009067532 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/4.lc_ctrl_prog_failure.1009067532 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_prog_failure.1009067532 -covoverwrite' seed=79753769931310592793873407843404518048680805785410575687231460275106577982988 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79753769931310592793873407843404518048680805785410575687231460275106577982988 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 41496152689527316649454040693467150978460157692199992809014005681037025232412 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1760577052 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/4.lc_ctrl_errors.1760577052 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_errors.1760577052 -covoverwrite' seed=41496152689527316649454040693467150978460157692199992809014005681037025232412 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41496152689527316649454040693467150978460157692199992809014005681037025232412 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 62752219868563557415852936881333232777560858821036851606182915009271296790 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3494638358 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/4.lc_ctrl_security_escalation.3494638358 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_security_escalation.3494638358 -covoverwrite' seed=62752219868563557415852936881333232777560858821036851606182915009271296790 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62752219868563557415852936881333232777560858821036851606182915009271296790 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_regwen_during_op 503548867603601114802383355970524600932005471945011885929223218286269996881 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_regwen_during_op/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1753390929 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/4.lc_ctrl_regwen_during_op.1753390929 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_regwen_during_op.1753390929 -covoverwrite' seed=503548867603601114802383355970524600932005471945011885929223218286269996881 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=503548867603601114802383355970524600932005471945011885929223218286269996881 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_claim_transition_if 55394022726452963392481587461419851202727130525241657306534376142395959872735 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_claim_transition_if/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1191120095 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/4.lc_ctrl_claim_transition_if.1191120095 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_claim_transition_if.1191120095 -covoverwrite' seed=55394022726452963392481587461419851202727130525241657306534376142395959872735 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55394022726452963392481587461419851202727130525241657306534376142395959872735 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_claim_transition_if/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_claim_transition_if_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 97362802957740903608172647641409441821783363371415357429031969015891406560179 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1765481395 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/4.lc_ctrl_jtag_smoke.1765481395 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_jtag_smoke.1765481395 -covoverwrite' seed=97362802957740903608172647641409441821783363371415357429031969015891406560179 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97362802957740903608172647641409441821783363371415357429031969015891406560179 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 85218434573174580683256768024769293733153991941977945199672958734189065969214 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3274481214 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/4.lc_ctrl_jtag_state_failure.3274481214 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_jtag_state_failure.3274481214 -covoverwrite' seed=85218434573174580683256768024769293733153991941977945199672958734189065969214 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85218434573174580683256768024769293733153991941977945199672958734189065969214 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 75646810165442613002450280140405852414878794510532676884346061436109013488259 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2412352131 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/4.lc_ctrl_jtag_state_post_trans.2412352131 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_jtag_state_post_trans.2412352131 -covoverwrite' seed=75646810165442613002450280140405852414878794510532676884346061436109013488259 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75646810165442613002450280140405852414878794510532676884346061436109013488259 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 16362402718013153807081093296274360554987243055361449820153471812204752230967 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3174521399 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/4.lc_ctrl_jtag_prog_failure.3174521399 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_jtag_prog_failure.3174521399 -covoverwrite' seed=16362402718013153807081093296274360554987243055361449820153471812204752230967 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16362402718013153807081093296274360554987243055361449820153471812204752230967 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 94293641100238347294346593697825800319669501598964534188611755550868258386782 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4017320798 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/4.lc_ctrl_jtag_errors.4017320798 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_jtag_errors.4017320798 -covoverwrite' seed=94293641100238347294346593697825800319669501598964534188611755550868258386782 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94293641100238347294346593697825800319669501598964534188611755550868258386782 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 15148849449864904463832506117686392920539538218028932416885433070843590873438 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3078885726 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/4.lc_ctrl_jtag_access.3078885726 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_jtag_access.3078885726 -covoverwrite' seed=15148849449864904463832506117686392920539538218028932416885433070843590873438 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15148849449864904463832506117686392920539538218028932416885433070843590873438 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_priority 41400361245993963031888472008605397403504371045391025626594244448264284765656 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_jtag_priority/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3505356248 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/4.lc_ctrl_jtag_priority.3505356248 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_jtag_priority.3505356248 -covoverwrite' seed=41400361245993963031888472008605397403504371045391025626594244448264284765656 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41400361245993963031888472008605397403504371045391025626594244448264284765656 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_jtag_priority/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_priority_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_regwen_during_op 98441818682039834998507909349822778612876871897864454828454416155210929600408 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_jtag_regwen_during_op/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1304098712 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/4.lc_ctrl_jtag_regwen_during_op.1304098712 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_jtag_regwen_during_op.1304098712 -covoverwrite' seed=98441818682039834998507909349822778612876871897864454828454416155210929600408 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98441818682039834998507909349822778612876871897864454828454416155210929600408 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_jtag_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_hw_reset 63090451024252643516732768649801704795075918835154172017026605513112778824724 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_jtag_csr_hw_reset/latest run_opts='+csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=248372244 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.248372244 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.lc_ctrl_jtag_csr_hw_reset.248372244 -covoverwrite' seed=63090451024252643516732768649801704795075918835154172017026605513112778824724 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63090451024252643516732768649801704795075918835154172017026605513112778824724 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_jtag_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_rw 84560089660304079384940285439771181461706081464227844034293406124560890834901 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_jtag_csr_rw/latest run_opts='+csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2502537173 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2502537173 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.lc_ctrl_jtag_csr_rw.2502537173 -covoverwrite' seed=84560089660304079384940285439771181461706081464227844034293406124560890834901 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84560089660304079384940285439771181461706081464227844034293406124560890834901 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_jtag_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_bit_bash 64514860046768975546688507824520193202544277872502807897984084014429236146054 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_jtag_csr_bit_bash/latest run_opts='+csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2426449798 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.2426449798 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.lc_ctrl_jtag_csr_bit_bash.2426449798 -covoverwrite' seed=64514860046768975546688507824520193202544277872502807897984084014429236146054 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64514860046768975546688507824520193202544277872502807897984084014429236146054 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_jtag_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_aliasing 7479051342013830527990476295770813182525164045491034629242993213768049851150 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_jtag_csr_aliasing/latest run_opts='+csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3159063310 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.3159063310 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.lc_ctrl_jtag_csr_aliasing.3159063310 -covoverwrite' seed=7479051342013830527990476295770813182525164045491034629242993213768049851150 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7479051342013830527990476295770813182525164045491034629242993213768049851150 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_jtag_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_same_csr_outstanding 63926118884081936387963490466228112185502991171878766646980464629430427785874 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_jtag_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=426187410 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.426187410 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.lc_ctrl_jtag_same_csr_outstanding.426187410 -covoverwrite' seed=63926118884081936387963490466228112185502991171878766646980464629430427785874 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63926118884081936387963490466228112185502991171878766646980464629430427785874 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_jtag_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 37729545072350259499726838258386296347640544411469873421491564089207406503788 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=939829100 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.939829100 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.939829100 -covoverwrite' seed=37729545072350259499726838258386296347640544411469873421491564089207406503788 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37729545072350259499726838258386296347640544411469873421491564089207406503788 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_alert_test 95253419592787294909118534464381589283312689952501877376677578479482513958542 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_jtag_alert_test/latest run_opts='+run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2089592462 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.2089592462 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.lc_ctrl_jtag_alert_test.2089592462 -covoverwrite' seed=95253419592787294909118534464381589283312689952501877376677578479482513958542 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95253419592787294909118534464381589283312689952501877376677578479482513958542 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_jtag_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_mubi 24603113752581135990409170342235365686482577217181436554500302287595529787479 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_sec_mubi/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2703186007 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/4.lc_ctrl_sec_mubi.2703186007 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_sec_mubi.2703186007 -covoverwrite' seed=24603113752581135990409170342235365686482577217181436554500302287595529787479 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24603113752581135990409170342235365686482577217181436554500302287595529787479 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_sec_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_mubi_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_mux 15142585377188462003970148406881181612950113179857096972506539022155189283648 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_sec_token_mux/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1095199552 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/4.lc_ctrl_sec_token_mux.1095199552 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_sec_token_mux.1095199552 -covoverwrite' seed=15142585377188462003970148406881181612950113179857096972506539022155189283648 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15142585377188462003970148406881181612950113179857096972506539022155189283648 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_sec_token_mux/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_mux_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_digest 68275071760191839758163597878896152668510218688214672295200760173225100560969 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_sec_token_digest/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=711051849 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/4.lc_ctrl_sec_token_digest.711051849 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_sec_token_digest.711051849 -covoverwrite' seed=68275071760191839758163597878896152668510218688214672295200760173225100560969 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68275071760191839758163597878896152668510218688214672295200760173225100560969 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_sec_token_digest/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_digest_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_stress_all_with_rand_reset 10336077848178147048086730320882664504532352072044360759421511140738640482997 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_stress_all_with_rand_reset/latest run_opts='+create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3367604917 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.3367604917 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_stress_all_with_rand_reset.3367604917 -covoverwrite' seed=10336077848178147048086730320882664504532352072044360759421511140738640482997 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10336077848178147048086730320882664504532352072044360759421511140738640482997 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_cm 41040933848384392240597187459886798559697864678875405416351015517140130125372 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=746509884 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/4.lc_ctrl_sec_cm.746509884 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_sec_cm.746509884 -covoverwrite' seed=41040933848384392240597187459886798559697864678875405416351015517140130125372 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41040933848384392240597187459886798559697864678875405416351015517140130125372 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 113356784365137811953538596012576888683985500055415180133788929796340938393958 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2080852326 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/4.lc_ctrl_tl_errors.2080852326 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.lc_ctrl_tl_errors.2080852326 -covoverwrite' seed=113356784365137811953538596012576888683985500055415180133788929796340938393958 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113356784365137811953538596012576888683985500055415180133788929796340938393958 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 64379104346269425281342293193808648272963456731801950216160492271442136025784 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1293306552 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.1293306552 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.lc_ctrl_tl_intg_err.1293306552 -covoverwrite' seed=64379104346269425281342293193808648272963456731801950216160492271442136025784 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64379104346269425281342293193808648272963456731801950216160492271442136025784 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_alert_test 85862491295660563291922565774114457686115004506927054709417038688235970240833 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2869043521 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/4.lc_ctrl_alert_test.2869043521 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_alert_test.2869043521 -covoverwrite' seed=85862491295660563291922565774114457686115004506927054709417038688235970240833 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85862491295660563291922565774114457686115004506927054709417038688235970240833 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_csr_rw 110189664465780789056820247111808719293491224223549445337792013419644803364018 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2625909938 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2625909938 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.lc_ctrl_csr_rw.2625909938 -covoverwrite' seed=110189664465780789056820247111808719293491224223549445337792013419644803364018 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110189664465780789056820247111808719293491224223549445337792013419644803364018 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_same_csr_outstanding 82738213090279653185146107356962225817812647706749925534707005138034577945545 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2512958409 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2512958409 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.lc_ctrl_same_csr_outstanding.2512958409 -covoverwrite' seed=82738213090279653185146107356962225817812647706749925534707005138034577945545 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82738213090279653185146107356962225817812647706749925534707005138034577945545 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_csr_mem_rw_with_rand_reset 80689318475578186346842748896264340635061385882750915502859967050521287242589 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=779793245 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.779793245 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.lc_ctrl_csr_mem_rw_with_rand_reset.779793245 -covoverwrite' seed=80689318475578186346842748896264340635061385882750915502859967050521287242589 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80689318475578186346842748896264340635061385882750915502859967050521287242589 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 23168194484974335446523468222560464025035036238577922960909238299330501492138 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4174724522 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/5.lc_ctrl_smoke.4174724522 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_smoke.4174724522 -covoverwrite' seed=23168194484974335446523468222560464025035036238577922960909238299330501492138 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23168194484974335446523468222560464025035036238577922960909238299330501492138 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_volatile_unlock_smoke 106079117340857338123135705138115826866305397846326352682337466920685511066945 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_volatile_unlock_smoke/latest run_opts='+en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2131707201 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/5.lc_ctrl_volatile_unlock_smoke.2131707201 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_volatile_unlock_smoke.2131707201 -covoverwrite' seed=106079117340857338123135705138115826866305397846326352682337466920685511066945 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106079117340857338123135705138115826866305397846326352682337466920685511066945 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_volatile_unlock_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_volatile_unlock_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 80647485307481299166385129569106944997446643840036714231797921455222920652598 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1431381814 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/5.lc_ctrl_state_failure.1431381814 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_state_failure.1431381814 -covoverwrite' seed=80647485307481299166385129569106944997446643840036714231797921455222920652598 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80647485307481299166385129569106944997446643840036714231797921455222920652598 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 21368203733564154145355006795344759660110623235460409764474978097113166947824 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2546902512 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/5.lc_ctrl_state_post_trans.2546902512 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_state_post_trans.2546902512 -covoverwrite' seed=21368203733564154145355006795344759660110623235460409764474978097113166947824 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21368203733564154145355006795344759660110623235460409764474978097113166947824 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 29669970385236747202956251198381931422870080915368701008877541081509058128040 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2307205288 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/5.lc_ctrl_prog_failure.2307205288 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_prog_failure.2307205288 -covoverwrite' seed=29669970385236747202956251198381931422870080915368701008877541081509058128040 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29669970385236747202956251198381931422870080915368701008877541081509058128040 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 27852620884371507990160768608978850969151013371259206086213726804774180900832 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2014334944 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/5.lc_ctrl_errors.2014334944 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_errors.2014334944 -covoverwrite' seed=27852620884371507990160768608978850969151013371259206086213726804774180900832 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27852620884371507990160768608978850969151013371259206086213726804774180900832 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 28639749005689057078644167608474310512244253923332428999386964989081273785029 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3701234373 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/5.lc_ctrl_security_escalation.3701234373 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_security_escalation.3701234373 -covoverwrite' seed=28639749005689057078644167608474310512244253923332428999386964989081273785029 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28639749005689057078644167608474310512244253923332428999386964989081273785029 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_regwen_during_op 60601104996448807773380642561150029323722060469560195607130713386497410835573 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_regwen_during_op/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2665718901 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/5.lc_ctrl_regwen_during_op.2665718901 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_regwen_during_op.2665718901 -covoverwrite' seed=60601104996448807773380642561150029323722060469560195607130713386497410835573 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60601104996448807773380642561150029323722060469560195607130713386497410835573 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_claim_transition_if 88273139807381299859645155758021181418020240509495904272228325295196027963267 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_claim_transition_if/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3715319683 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/5.lc_ctrl_claim_transition_if.3715319683 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_claim_transition_if.3715319683 -covoverwrite' seed=88273139807381299859645155758021181418020240509495904272228325295196027963267 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88273139807381299859645155758021181418020240509495904272228325295196027963267 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_claim_transition_if/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_claim_transition_if_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 16191508948847950844896584563051386653296286328263180573086018455865088033274 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=105923066 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/5.lc_ctrl_jtag_smoke.105923066 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_jtag_smoke.105923066 -covoverwrite' seed=16191508948847950844896584563051386653296286328263180573086018455865088033274 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16191508948847950844896584563051386653296286328263180573086018455865088033274 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 76631544557043194505454289286898419118739035925843762736159230122453760843716 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2086510532 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/5.lc_ctrl_jtag_state_failure.2086510532 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_jtag_state_failure.2086510532 -covoverwrite' seed=76631544557043194505454289286898419118739035925843762736159230122453760843716 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76631544557043194505454289286898419118739035925843762736159230122453760843716 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 105868102192269577736040246934318314040179036294027521229455972602888145525307 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3226131003 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/5.lc_ctrl_jtag_state_post_trans.3226131003 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_jtag_state_post_trans.3226131003 -covoverwrite' seed=105868102192269577736040246934318314040179036294027521229455972602888145525307 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105868102192269577736040246934318314040179036294027521229455972602888145525307 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 97303414995372227051023956339005376700697684662125126414414632220156265240228 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2860521124 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/5.lc_ctrl_jtag_prog_failure.2860521124 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_jtag_prog_failure.2860521124 -covoverwrite' seed=97303414995372227051023956339005376700697684662125126414414632220156265240228 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97303414995372227051023956339005376700697684662125126414414632220156265240228 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 33674636053957355507884685918910931602057245016170662393707951587290366190056 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3252265448 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/5.lc_ctrl_jtag_errors.3252265448 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_jtag_errors.3252265448 -covoverwrite' seed=33674636053957355507884685918910931602057245016170662393707951587290366190056 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33674636053957355507884685918910931602057245016170662393707951587290366190056 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 82552962598930486710178093375874328582285521292760311894360658518270077916575 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3698939295 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/5.lc_ctrl_jtag_access.3698939295 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_jtag_access.3698939295 -covoverwrite' seed=82552962598930486710178093375874328582285521292760311894360658518270077916575 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82552962598930486710178093375874328582285521292760311894360658518270077916575 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_priority 23085204495056188492490767956681193453020902386058698177397612210659920020941 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_jtag_priority/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2364638669 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/5.lc_ctrl_jtag_priority.2364638669 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_jtag_priority.2364638669 -covoverwrite' seed=23085204495056188492490767956681193453020902386058698177397612210659920020941 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23085204495056188492490767956681193453020902386058698177397612210659920020941 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_jtag_priority/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_priority_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_regwen_during_op 67955325966952285224864224203822545682528466168754441067265236420792894049321 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_jtag_regwen_during_op/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2505788457 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/5.lc_ctrl_jtag_regwen_during_op.2505788457 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_jtag_regwen_during_op.2505788457 -covoverwrite' seed=67955325966952285224864224203822545682528466168754441067265236420792894049321 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67955325966952285224864224203822545682528466168754441067265236420792894049321 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_jtag_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_hw_reset 16437754661488220714690031451381015670595526509419727933897462095917071853299 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_jtag_csr_hw_reset/latest run_opts='+csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3736987379 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.3736987379 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.lc_ctrl_jtag_csr_hw_reset.3736987379 -covoverwrite' seed=16437754661488220714690031451381015670595526509419727933897462095917071853299 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16437754661488220714690031451381015670595526509419727933897462095917071853299 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_jtag_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_rw 61799254691172642035481752470863967240113354706431971811562078096120273169765 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_jtag_csr_rw/latest run_opts='+csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1956638053 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.1956638053 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.lc_ctrl_jtag_csr_rw.1956638053 -covoverwrite' seed=61799254691172642035481752470863967240113354706431971811562078096120273169765 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61799254691172642035481752470863967240113354706431971811562078096120273169765 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_jtag_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_bit_bash 100088789725711173111153518782464811752833302332080123853082813592498817740543 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_jtag_csr_bit_bash/latest run_opts='+csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1880895231 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.1880895231 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.lc_ctrl_jtag_csr_bit_bash.1880895231 -covoverwrite' seed=100088789725711173111153518782464811752833302332080123853082813592498817740543 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100088789725711173111153518782464811752833302332080123853082813592498817740543 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_jtag_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_aliasing 38630214747360422646431199577508573199655341417119279114475270583282767345719 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_jtag_csr_aliasing/latest run_opts='+csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=743290935 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.743290935 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.lc_ctrl_jtag_csr_aliasing.743290935 -covoverwrite' seed=38630214747360422646431199577508573199655341417119279114475270583282767345719 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38630214747360422646431199577508573199655341417119279114475270583282767345719 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_jtag_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_same_csr_outstanding 112107562627719619639640623221052323785604704217566263938974349153672441292745 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_jtag_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1973086153 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.1973086153 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.lc_ctrl_jtag_same_csr_outstanding.1973086153 -covoverwrite' seed=112107562627719619639640623221052323785604704217566263938974349153672441292745 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112107562627719619639640623221052323785604704217566263938974349153672441292745 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_jtag_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 70693429607607676521941694522055273599706554078294493568572022939107068142543 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=62055375 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.62055375 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.62055375 -covoverwrite' seed=70693429607607676521941694522055273599706554078294493568572022939107068142543 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70693429607607676521941694522055273599706554078294493568572022939107068142543 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_alert_test 114849764001090449651347477773115041154120919440120313696817086099221272302556 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_jtag_alert_test/latest run_opts='+run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=763597788 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.763597788 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.lc_ctrl_jtag_alert_test.763597788 -covoverwrite' seed=114849764001090449651347477773115041154120919440120313696817086099221272302556 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114849764001090449651347477773115041154120919440120313696817086099221272302556 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_jtag_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_mubi 106455948226632964927937235580317167420584443544086513277592084195060901841182 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_sec_mubi/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3292891422 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/5.lc_ctrl_sec_mubi.3292891422 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_sec_mubi.3292891422 -covoverwrite' seed=106455948226632964927937235580317167420584443544086513277592084195060901841182 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106455948226632964927937235580317167420584443544086513277592084195060901841182 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_sec_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_mubi_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_mux 77106927670592102491039541307748353803561251247739000766873619745424608759005 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_sec_token_mux/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2344520925 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/5.lc_ctrl_sec_token_mux.2344520925 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_sec_token_mux.2344520925 -covoverwrite' seed=77106927670592102491039541307748353803561251247739000766873619745424608759005 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77106927670592102491039541307748353803561251247739000766873619745424608759005 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_sec_token_mux/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_mux_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_digest 98519732018984930443838439490344317050574388804716073402110894858813753174272 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_sec_token_digest/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3810175232 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/5.lc_ctrl_sec_token_digest.3810175232 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_sec_token_digest.3810175232 -covoverwrite' seed=98519732018984930443838439490344317050574388804716073402110894858813753174272 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98519732018984930443838439490344317050574388804716073402110894858813753174272 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_sec_token_digest/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_digest_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_stress_all_with_rand_reset 113164714174224756589727570730258540896446180014231049539251776436215850809169 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_stress_all_with_rand_reset/latest run_opts='+create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1735735121 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.1735735121 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_stress_all_with_rand_reset.1735735121 -covoverwrite' seed=113164714174224756589727570730258540896446180014231049539251776436215850809169 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113164714174224756589727570730258540896446180014231049539251776436215850809169 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 17837793512866037784418146477334625407816195107054374606421573827129749441066 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=593922602 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/5.lc_ctrl_tl_errors.593922602 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.lc_ctrl_tl_errors.593922602 -covoverwrite' seed=17837793512866037784418146477334625407816195107054374606421573827129749441066 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17837793512866037784418146477334625407816195107054374606421573827129749441066 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 5621851464365618618465574978571313244111408161351818099182471639204827830655 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2229344639 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.2229344639 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.lc_ctrl_tl_intg_err.2229344639 -covoverwrite' seed=5621851464365618618465574978571313244111408161351818099182471639204827830655 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5621851464365618618465574978571313244111408161351818099182471639204827830655 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_alert_test 11305862625487867807860411365002846542276566404889124331890647642032853864490 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3429224490 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/5.lc_ctrl_alert_test.3429224490 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_alert_test.3429224490 -covoverwrite' seed=11305862625487867807860411365002846542276566404889124331890647642032853864490 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11305862625487867807860411365002846542276566404889124331890647642032853864490 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/5.lc_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 100987055915749361542066969584870934549708185759131134476632222376202862186580 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1618595924 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/6.lc_ctrl_smoke.1618595924 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_smoke.1618595924 -covoverwrite' seed=100987055915749361542066969584870934549708185759131134476632222376202862186580 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100987055915749361542066969584870934549708185759131134476632222376202862186580 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_volatile_unlock_smoke 43893385858440907938802558044787500416281144180981725810374671466869411686808 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_volatile_unlock_smoke/latest run_opts='+en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1427253656 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1427253656 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_volatile_unlock_smoke.1427253656 -covoverwrite' seed=43893385858440907938802558044787500416281144180981725810374671466869411686808 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43893385858440907938802558044787500416281144180981725810374671466869411686808 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_volatile_unlock_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_volatile_unlock_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 94273374960796292477200453081250097786594344012661781457595994309031781844965 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2321401829 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/6.lc_ctrl_state_failure.2321401829 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_state_failure.2321401829 -covoverwrite' seed=94273374960796292477200453081250097786594344012661781457595994309031781844965 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94273374960796292477200453081250097786594344012661781457595994309031781844965 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 6719569567026155372262878513312384337388451305901954043007768791333862705549 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3555002765 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/6.lc_ctrl_state_post_trans.3555002765 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_state_post_trans.3555002765 -covoverwrite' seed=6719569567026155372262878513312384337388451305901954043007768791333862705549 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6719569567026155372262878513312384337388451305901954043007768791333862705549 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 72136199455740098052935003468270083463543599099106879053837600195303326016702 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3400459454 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/6.lc_ctrl_prog_failure.3400459454 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_prog_failure.3400459454 -covoverwrite' seed=72136199455740098052935003468270083463543599099106879053837600195303326016702 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72136199455740098052935003468270083463543599099106879053837600195303326016702 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 87279433351457387917104819722709317927908471291025299354441289328765166356011 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1183778347 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/6.lc_ctrl_errors.1183778347 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_errors.1183778347 -covoverwrite' seed=87279433351457387917104819722709317927908471291025299354441289328765166356011 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87279433351457387917104819722709317927908471291025299354441289328765166356011 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 25130110019292197039224299416548074983551865589986116477454584710538344762197 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1844415317 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/6.lc_ctrl_security_escalation.1844415317 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_security_escalation.1844415317 -covoverwrite' seed=25130110019292197039224299416548074983551865589986116477454584710538344762197 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25130110019292197039224299416548074983551865589986116477454584710538344762197 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_regwen_during_op 63965721556117160591841316989603772554611498737574112787910899338852301163043 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_regwen_during_op/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=594954787 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/6.lc_ctrl_regwen_during_op.594954787 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_regwen_during_op.594954787 -covoverwrite' seed=63965721556117160591841316989603772554611498737574112787910899338852301163043 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63965721556117160591841316989603772554611498737574112787910899338852301163043 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_claim_transition_if 66932260953034340996956080460654275965099084166332967210240057278506182933055 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_claim_transition_if/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2320267839 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/6.lc_ctrl_claim_transition_if.2320267839 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_claim_transition_if.2320267839 -covoverwrite' seed=66932260953034340996956080460654275965099084166332967210240057278506182933055 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66932260953034340996956080460654275965099084166332967210240057278506182933055 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_claim_transition_if/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_claim_transition_if_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 65835291281400574965457502981172113971581524180190681764789737462673890091196 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3456639164 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/6.lc_ctrl_jtag_smoke.3456639164 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_jtag_smoke.3456639164 -covoverwrite' seed=65835291281400574965457502981172113971581524180190681764789737462673890091196 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65835291281400574965457502981172113971581524180190681764789737462673890091196 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 49558996029304623644975284342307297330712238294633916680913665900310166291078 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1676460678 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/6.lc_ctrl_jtag_state_failure.1676460678 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_jtag_state_failure.1676460678 -covoverwrite' seed=49558996029304623644975284342307297330712238294633916680913665900310166291078 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49558996029304623644975284342307297330712238294633916680913665900310166291078 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 112014103931647128358495389280318191778401133872224167272496365777625214225864 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3429764552 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/6.lc_ctrl_jtag_state_post_trans.3429764552 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_jtag_state_post_trans.3429764552 -covoverwrite' seed=112014103931647128358495389280318191778401133872224167272496365777625214225864 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112014103931647128358495389280318191778401133872224167272496365777625214225864 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 66511850810778416327460093851074222747298903049526679777915715308198656858404 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1122621732 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/6.lc_ctrl_jtag_prog_failure.1122621732 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_jtag_prog_failure.1122621732 -covoverwrite' seed=66511850810778416327460093851074222747298903049526679777915715308198656858404 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66511850810778416327460093851074222747298903049526679777915715308198656858404 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 106328384322031238971445818327717890594195971950162256676519123474348612358332 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2586153148 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/6.lc_ctrl_jtag_errors.2586153148 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_jtag_errors.2586153148 -covoverwrite' seed=106328384322031238971445818327717890594195971950162256676519123474348612358332 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106328384322031238971445818327717890594195971950162256676519123474348612358332 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 100057205250376236088901725181104001381557450342324692104652907773245931177458 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1006945778 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/6.lc_ctrl_jtag_access.1006945778 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_jtag_access.1006945778 -covoverwrite' seed=100057205250376236088901725181104001381557450342324692104652907773245931177458 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100057205250376236088901725181104001381557450342324692104652907773245931177458 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_priority 51806677892476397814249189827274245655097676350341712189747396616275535019972 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_jtag_priority/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3562225604 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/6.lc_ctrl_jtag_priority.3562225604 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_jtag_priority.3562225604 -covoverwrite' seed=51806677892476397814249189827274245655097676350341712189747396616275535019972 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51806677892476397814249189827274245655097676350341712189747396616275535019972 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_jtag_priority/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_priority_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_regwen_during_op 76166117331611074833312059824657592164427413478037168516317270552021036448137 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_jtag_regwen_during_op/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3833084297 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/6.lc_ctrl_jtag_regwen_during_op.3833084297 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_jtag_regwen_during_op.3833084297 -covoverwrite' seed=76166117331611074833312059824657592164427413478037168516317270552021036448137 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76166117331611074833312059824657592164427413478037168516317270552021036448137 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_jtag_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_hw_reset 17660610963237237944054926460268664531770337871032710190298786339267753419895 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_jtag_csr_hw_reset/latest run_opts='+csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=847914103 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.847914103 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.lc_ctrl_jtag_csr_hw_reset.847914103 -covoverwrite' seed=17660610963237237944054926460268664531770337871032710190298786339267753419895 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17660610963237237944054926460268664531770337871032710190298786339267753419895 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_jtag_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_rw 48832765862052542659248674918143178382511166750084667667098451875240142797956 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_jtag_csr_rw/latest run_opts='+csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1034517636 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1034517636 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.lc_ctrl_jtag_csr_rw.1034517636 -covoverwrite' seed=48832765862052542659248674918143178382511166750084667667098451875240142797956 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48832765862052542659248674918143178382511166750084667667098451875240142797956 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_jtag_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_bit_bash 97384481719426696372130659914345115636096893260756317194839777968455441687953 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_jtag_csr_bit_bash/latest run_opts='+csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=67872145 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.67872145 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.lc_ctrl_jtag_csr_bit_bash.67872145 -covoverwrite' seed=97384481719426696372130659914345115636096893260756317194839777968455441687953 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97384481719426696372130659914345115636096893260756317194839777968455441687953 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_jtag_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_aliasing 64339433929381779597358204182012510967635731811544822154633085481528628437754 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_jtag_csr_aliasing/latest run_opts='+csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3712312058 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.3712312058 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.lc_ctrl_jtag_csr_aliasing.3712312058 -covoverwrite' seed=64339433929381779597358204182012510967635731811544822154633085481528628437754 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64339433929381779597358204182012510967635731811544822154633085481528628437754 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_jtag_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_same_csr_outstanding 77340108371734337041607516990414827748543221301880055915435520672707404219795 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_jtag_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=350078355 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.350078355 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.lc_ctrl_jtag_same_csr_outstanding.350078355 -covoverwrite' seed=77340108371734337041607516990414827748543221301880055915435520672707404219795 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77340108371734337041607516990414827748543221301880055915435520672707404219795 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_jtag_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4360327921506929355032424528391549286304307446087673674798671551162385080176 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3866009456 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3866009456 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3866009456 -covoverwrite' seed=4360327921506929355032424528391549286304307446087673674798671551162385080176 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4360327921506929355032424528391549286304307446087673674798671551162385080176 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_alert_test 92846695323464623782734449913332486344549475808457629225190252303420164324055 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_jtag_alert_test/latest run_opts='+run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1515895511 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.1515895511 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.lc_ctrl_jtag_alert_test.1515895511 -covoverwrite' seed=92846695323464623782734449913332486344549475808457629225190252303420164324055 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92846695323464623782734449913332486344549475808457629225190252303420164324055 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_jtag_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_mubi 47242791193204521911754190195546521199897761903476309703315723376174435462454 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_sec_mubi/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=312536374 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/6.lc_ctrl_sec_mubi.312536374 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_sec_mubi.312536374 -covoverwrite' seed=47242791193204521911754190195546521199897761903476309703315723376174435462454 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47242791193204521911754190195546521199897761903476309703315723376174435462454 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_sec_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_mubi_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_mux 115141822328837501892099675361967056771760502020315909415400286505711434280010 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_sec_token_mux/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3402181706 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/6.lc_ctrl_sec_token_mux.3402181706 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_sec_token_mux.3402181706 -covoverwrite' seed=115141822328837501892099675361967056771760502020315909415400286505711434280010 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115141822328837501892099675361967056771760502020315909415400286505711434280010 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_sec_token_mux/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_mux_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_digest 49296629963053228228015325773693706428752219709276813663846353621766020274477 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_sec_token_digest/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3461617965 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/6.lc_ctrl_sec_token_digest.3461617965 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_sec_token_digest.3461617965 -covoverwrite' seed=49296629963053228228015325773693706428752219709276813663846353621766020274477 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49296629963053228228015325773693706428752219709276813663846353621766020274477 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_sec_token_digest/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_digest_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_stress_all_with_rand_reset 74337759598460108472741105955488942321960467026078043530761775307498935920544 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_stress_all_with_rand_reset/latest run_opts='+create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3158943648 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.3158943648 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_stress_all_with_rand_reset.3158943648 -covoverwrite' seed=74337759598460108472741105955488942321960467026078043530761775307498935920544 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74337759598460108472741105955488942321960467026078043530761775307498935920544 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 103410339388846132475253685195553883484975246421557494784562876923199861444703 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=143806559 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/6.lc_ctrl_tl_errors.143806559 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.lc_ctrl_tl_errors.143806559 -covoverwrite' seed=103410339388846132475253685195553883484975246421557494784562876923199861444703 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103410339388846132475253685195553883484975246421557494784562876923199861444703 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 104566400349712925144306673360376936412885167637679466055471758520497746153806 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=777982286 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.777982286 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.lc_ctrl_tl_intg_err.777982286 -covoverwrite' seed=104566400349712925144306673360376936412885167637679466055471758520497746153806 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104566400349712925144306673360376936412885167637679466055471758520497746153806 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_alert_test 26151836094443885625345828790844325701122213526313090560790648486619385547326 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1286195774 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/6.lc_ctrl_alert_test.1286195774 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_alert_test.1286195774 -covoverwrite' seed=26151836094443885625345828790844325701122213526313090560790648486619385547326 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26151836094443885625345828790844325701122213526313090560790648486619385547326 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/6.lc_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 7856155624024795565259961155380818712169732698210572550201711423522243185793 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3714944129 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/7.lc_ctrl_smoke.3714944129 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_smoke.3714944129 -covoverwrite' seed=7856155624024795565259961155380818712169732698210572550201711423522243185793 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7856155624024795565259961155380818712169732698210572550201711423522243185793 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_volatile_unlock_smoke 9153927707510766051839395574235939360432411930845088463060754721514589140443 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_volatile_unlock_smoke/latest run_opts='+en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2218669531 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/7.lc_ctrl_volatile_unlock_smoke.2218669531 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_volatile_unlock_smoke.2218669531 -covoverwrite' seed=9153927707510766051839395574235939360432411930845088463060754721514589140443 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9153927707510766051839395574235939360432411930845088463060754721514589140443 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_volatile_unlock_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_volatile_unlock_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 104761183965264325794831477410711510695248332655545909216620404407037044738867 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1307069235 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/7.lc_ctrl_state_failure.1307069235 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_state_failure.1307069235 -covoverwrite' seed=104761183965264325794831477410711510695248332655545909216620404407037044738867 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104761183965264325794831477410711510695248332655545909216620404407037044738867 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 62817437925257362875174023270403962776126070738826076853634900867102092609081 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1859700281 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/7.lc_ctrl_state_post_trans.1859700281 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_state_post_trans.1859700281 -covoverwrite' seed=62817437925257362875174023270403962776126070738826076853634900867102092609081 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62817437925257362875174023270403962776126070738826076853634900867102092609081 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 89460697679359779477528722092620580029594853637592111113610946636604568984917 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2728353109 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/7.lc_ctrl_prog_failure.2728353109 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_prog_failure.2728353109 -covoverwrite' seed=89460697679359779477528722092620580029594853637592111113610946636604568984917 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89460697679359779477528722092620580029594853637592111113610946636604568984917 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 67599967846731069470415417667597999279626398796814429161171402736673904324781 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1367535789 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/7.lc_ctrl_errors.1367535789 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_errors.1367535789 -covoverwrite' seed=67599967846731069470415417667597999279626398796814429161171402736673904324781 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67599967846731069470415417667597999279626398796814429161171402736673904324781 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 36488882452227921222446194059774591978309978656552195229028758329204338364586 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=376737962 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/7.lc_ctrl_security_escalation.376737962 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_security_escalation.376737962 -covoverwrite' seed=36488882452227921222446194059774591978309978656552195229028758329204338364586 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36488882452227921222446194059774591978309978656552195229028758329204338364586 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_regwen_during_op 69013833132483390399641421660797890275961432178229410980981094826675236761221 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_regwen_during_op/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1701572229 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/7.lc_ctrl_regwen_during_op.1701572229 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_regwen_during_op.1701572229 -covoverwrite' seed=69013833132483390399641421660797890275961432178229410980981094826675236761221 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69013833132483390399641421660797890275961432178229410980981094826675236761221 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_claim_transition_if 1091323056072198810658711408332022386869242553640007836872166823155458930626 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_claim_transition_if/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2140174274 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/7.lc_ctrl_claim_transition_if.2140174274 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_claim_transition_if.2140174274 -covoverwrite' seed=1091323056072198810658711408332022386869242553640007836872166823155458930626 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1091323056072198810658711408332022386869242553640007836872166823155458930626 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_claim_transition_if/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_claim_transition_if_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 92311234432830928001606128447764303788562122192364323398527808785979383409150 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3742558718 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/7.lc_ctrl_jtag_smoke.3742558718 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_jtag_smoke.3742558718 -covoverwrite' seed=92311234432830928001606128447764303788562122192364323398527808785979383409150 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92311234432830928001606128447764303788562122192364323398527808785979383409150 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 39380118150371512131054011675883569942156415726427762821936413965209727359473 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3924515313 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/7.lc_ctrl_jtag_state_failure.3924515313 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_jtag_state_failure.3924515313 -covoverwrite' seed=39380118150371512131054011675883569942156415726427762821936413965209727359473 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39380118150371512131054011675883569942156415726427762821936413965209727359473 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 44173073430116074350316567174112401885862166176500674041823254673190652364358 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2999076422 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/7.lc_ctrl_jtag_state_post_trans.2999076422 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_jtag_state_post_trans.2999076422 -covoverwrite' seed=44173073430116074350316567174112401885862166176500674041823254673190652364358 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44173073430116074350316567174112401885862166176500674041823254673190652364358 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 38796388688182705298670242581383769075402324081697098622020312270337822164525 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1180173869 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/7.lc_ctrl_jtag_prog_failure.1180173869 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_jtag_prog_failure.1180173869 -covoverwrite' seed=38796388688182705298670242581383769075402324081697098622020312270337822164525 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38796388688182705298670242581383769075402324081697098622020312270337822164525 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 100684173023586487985650414766283651913746180712967718552082359883332030973441 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1666336257 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/7.lc_ctrl_jtag_errors.1666336257 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_jtag_errors.1666336257 -covoverwrite' seed=100684173023586487985650414766283651913746180712967718552082359883332030973441 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100684173023586487985650414766283651913746180712967718552082359883332030973441 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 113388287591083457108600340463125158830202164035646791450309863749402678052409 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1770571321 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/7.lc_ctrl_jtag_access.1770571321 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_jtag_access.1770571321 -covoverwrite' seed=113388287591083457108600340463125158830202164035646791450309863749402678052409 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113388287591083457108600340463125158830202164035646791450309863749402678052409 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_priority 106965167096050375495656107858364003783979034199728799268583597226679960248610 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_jtag_priority/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2426839330 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/7.lc_ctrl_jtag_priority.2426839330 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_jtag_priority.2426839330 -covoverwrite' seed=106965167096050375495656107858364003783979034199728799268583597226679960248610 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106965167096050375495656107858364003783979034199728799268583597226679960248610 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_jtag_priority/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_priority_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_regwen_during_op 100240949604636375566391817238499897946336942468404451940592586750508126252450 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_jtag_regwen_during_op/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3328519586 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/7.lc_ctrl_jtag_regwen_during_op.3328519586 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_jtag_regwen_during_op.3328519586 -covoverwrite' seed=100240949604636375566391817238499897946336942468404451940592586750508126252450 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100240949604636375566391817238499897946336942468404451940592586750508126252450 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_jtag_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_hw_reset 89084683028857643847249400396115597861859919904424100729336590478530919895356 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_jtag_csr_hw_reset/latest run_opts='+csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=937005372 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.937005372 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.lc_ctrl_jtag_csr_hw_reset.937005372 -covoverwrite' seed=89084683028857643847249400396115597861859919904424100729336590478530919895356 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89084683028857643847249400396115597861859919904424100729336590478530919895356 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_jtag_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_rw 60990249095243585437772866886099333769352766361898809041948251778287889505409 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_jtag_csr_rw/latest run_opts='+csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=851401857 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.851401857 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.lc_ctrl_jtag_csr_rw.851401857 -covoverwrite' seed=60990249095243585437772866886099333769352766361898809041948251778287889505409 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60990249095243585437772866886099333769352766361898809041948251778287889505409 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_jtag_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_bit_bash 50236489970793344964413503496826587447893117763043803163052586900654462730241 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_jtag_csr_bit_bash/latest run_opts='+csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2665611265 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.2665611265 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.lc_ctrl_jtag_csr_bit_bash.2665611265 -covoverwrite' seed=50236489970793344964413503496826587447893117763043803163052586900654462730241 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50236489970793344964413503496826587447893117763043803163052586900654462730241 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_jtag_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_aliasing 33821468535891479596829581489439808147046674388524869798943892350218619845077 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_jtag_csr_aliasing/latest run_opts='+csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3106929109 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.3106929109 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.lc_ctrl_jtag_csr_aliasing.3106929109 -covoverwrite' seed=33821468535891479596829581489439808147046674388524869798943892350218619845077 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33821468535891479596829581489439808147046674388524869798943892350218619845077 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_jtag_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_same_csr_outstanding 103987710727742314112530936649616364694025072385529740885087814426674641406104 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_jtag_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1807124632 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.1807124632 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.lc_ctrl_jtag_same_csr_outstanding.1807124632 -covoverwrite' seed=103987710727742314112530936649616364694025072385529740885087814426674641406104 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103987710727742314112530936649616364694025072385529740885087814426674641406104 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_jtag_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 29422061699146509653331462097525068980536899273554842291192146172816676556531 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1924337395 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1924337395 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1924337395 -covoverwrite' seed=29422061699146509653331462097525068980536899273554842291192146172816676556531 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29422061699146509653331462097525068980536899273554842291192146172816676556531 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_alert_test 87478478233522682944674717205959417779285554432629933669613526687926955557816 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_jtag_alert_test/latest run_opts='+run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1900037048 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.1900037048 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.lc_ctrl_jtag_alert_test.1900037048 -covoverwrite' seed=87478478233522682944674717205959417779285554432629933669613526687926955557816 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87478478233522682944674717205959417779285554432629933669613526687926955557816 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_jtag_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_mubi 46773240528775939153837528813361861990564606588370414424815569350305123722177 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_sec_mubi/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1342497729 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/7.lc_ctrl_sec_mubi.1342497729 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_sec_mubi.1342497729 -covoverwrite' seed=46773240528775939153837528813361861990564606588370414424815569350305123722177 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46773240528775939153837528813361861990564606588370414424815569350305123722177 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_sec_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_mubi_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_mux 13295233440295534640022415700123030726674376032660338055443579852918360161081 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_sec_token_mux/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1698741049 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/7.lc_ctrl_sec_token_mux.1698741049 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_sec_token_mux.1698741049 -covoverwrite' seed=13295233440295534640022415700123030726674376032660338055443579852918360161081 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13295233440295534640022415700123030726674376032660338055443579852918360161081 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_sec_token_mux/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_mux_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_digest 75688773058834395091334275390773327600975773176517748827624928217974869928247 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_sec_token_digest/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2967546167 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/7.lc_ctrl_sec_token_digest.2967546167 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_sec_token_digest.2967546167 -covoverwrite' seed=75688773058834395091334275390773327600975773176517748827624928217974869928247 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75688773058834395091334275390773327600975773176517748827624928217974869928247 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_sec_token_digest/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_digest_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_stress_all_with_rand_reset 23060335072551274404776382810505634104159990628745763528593290062434528031023 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_stress_all_with_rand_reset/latest run_opts='+create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1079931183 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.1079931183 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_stress_all_with_rand_reset.1079931183 -covoverwrite' seed=23060335072551274404776382810505634104159990628745763528593290062434528031023 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23060335072551274404776382810505634104159990628745763528593290062434528031023 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 62476155071353554307500477511937492703441840822499537455399484490838757091569 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3645384945 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3645384945 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.lc_ctrl_tl_errors.3645384945 -covoverwrite' seed=62476155071353554307500477511937492703441840822499537455399484490838757091569 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62476155071353554307500477511937492703441840822499537455399484490838757091569 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 59508494942261700108820774599304080560987653990108462487573346892290204317556 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1344747380 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1344747380 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.lc_ctrl_tl_intg_err.1344747380 -covoverwrite' seed=59508494942261700108820774599304080560987653990108462487573346892290204317556 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=59508494942261700108820774599304080560987653990108462487573346892290204317556 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_alert_test 71292952007677921471217998893953276796535318159702666349945531268035155277572 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3325507332 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/7.lc_ctrl_alert_test.3325507332 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_alert_test.3325507332 -covoverwrite' seed=71292952007677921471217998893953276796535318159702666349945531268035155277572 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71292952007677921471217998893953276796535318159702666349945531268035155277572 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/7.lc_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 18018802439202072058279816347048592293515384174470054198217136290262108235678 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3973212062 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/8.lc_ctrl_smoke.3973212062 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_smoke.3973212062 -covoverwrite' seed=18018802439202072058279816347048592293515384174470054198217136290262108235678 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18018802439202072058279816347048592293515384174470054198217136290262108235678 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_volatile_unlock_smoke 92787221576243866316628251659937820239322652757850460489715390592638965913797 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_volatile_unlock_smoke/latest run_opts='+en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=694032581 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/8.lc_ctrl_volatile_unlock_smoke.694032581 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_volatile_unlock_smoke.694032581 -covoverwrite' seed=92787221576243866316628251659937820239322652757850460489715390592638965913797 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92787221576243866316628251659937820239322652757850460489715390592638965913797 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_volatile_unlock_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_volatile_unlock_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 112855010723099226450634433582715509783006172772340049980815830353806397797037 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1226306221 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/8.lc_ctrl_state_failure.1226306221 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_state_failure.1226306221 -covoverwrite' seed=112855010723099226450634433582715509783006172772340049980815830353806397797037 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112855010723099226450634433582715509783006172772340049980815830353806397797037 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 69508103284215436512715115077226092923002814158321587837386623619947618263227 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2777309371 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/8.lc_ctrl_state_post_trans.2777309371 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_state_post_trans.2777309371 -covoverwrite' seed=69508103284215436512715115077226092923002814158321587837386623619947618263227 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69508103284215436512715115077226092923002814158321587837386623619947618263227 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 58338973178066040317511540456795016126321206652870527216373680433898522927827 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=692839123 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/8.lc_ctrl_prog_failure.692839123 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_prog_failure.692839123 -covoverwrite' seed=58338973178066040317511540456795016126321206652870527216373680433898522927827 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58338973178066040317511540456795016126321206652870527216373680433898522927827 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 26009916001415190886503989524920165732432833012374485674725149642275121458172 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1618144252 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/8.lc_ctrl_errors.1618144252 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_errors.1618144252 -covoverwrite' seed=26009916001415190886503989524920165732432833012374485674725149642275121458172 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26009916001415190886503989524920165732432833012374485674725149642275121458172 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 57384905621821787831408477454144111003267625039088001053706763905644153601389 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2878930285 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/8.lc_ctrl_security_escalation.2878930285 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_security_escalation.2878930285 -covoverwrite' seed=57384905621821787831408477454144111003267625039088001053706763905644153601389 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57384905621821787831408477454144111003267625039088001053706763905644153601389 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_regwen_during_op 88068008636960349551858485722904049741476775622337098624755507424215702401091 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_regwen_during_op/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2605412419 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/8.lc_ctrl_regwen_during_op.2605412419 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_regwen_during_op.2605412419 -covoverwrite' seed=88068008636960349551858485722904049741476775622337098624755507424215702401091 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88068008636960349551858485722904049741476775622337098624755507424215702401091 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_claim_transition_if 83276171223028086962286831639523952763288467901057150644073998140103314111901 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_claim_transition_if/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3122658717 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/8.lc_ctrl_claim_transition_if.3122658717 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_claim_transition_if.3122658717 -covoverwrite' seed=83276171223028086962286831639523952763288467901057150644073998140103314111901 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83276171223028086962286831639523952763288467901057150644073998140103314111901 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_claim_transition_if/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_claim_transition_if_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 64549850770412264173005095991443182408484310241196433346157256417497640348573 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3265276829 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/8.lc_ctrl_jtag_smoke.3265276829 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_jtag_smoke.3265276829 -covoverwrite' seed=64549850770412264173005095991443182408484310241196433346157256417497640348573 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64549850770412264173005095991443182408484310241196433346157256417497640348573 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 61887349599663654707384000911814286351034015159207229094117532675697189371346 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=199802322 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/8.lc_ctrl_jtag_state_failure.199802322 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_jtag_state_failure.199802322 -covoverwrite' seed=61887349599663654707384000911814286351034015159207229094117532675697189371346 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61887349599663654707384000911814286351034015159207229094117532675697189371346 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 29298132592455951361268263867025864436007753496557164107051382747555834623302 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=435680582 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/8.lc_ctrl_jtag_state_post_trans.435680582 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_jtag_state_post_trans.435680582 -covoverwrite' seed=29298132592455951361268263867025864436007753496557164107051382747555834623302 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29298132592455951361268263867025864436007753496557164107051382747555834623302 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 102844839892495936823896274589462834519828920300153900337256424333097054780077 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1023687341 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/8.lc_ctrl_jtag_prog_failure.1023687341 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_jtag_prog_failure.1023687341 -covoverwrite' seed=102844839892495936823896274589462834519828920300153900337256424333097054780077 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102844839892495936823896274589462834519828920300153900337256424333097054780077 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 98793426285023242229204538655353696434238722712150045339604830573072695848046 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=416967790 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/8.lc_ctrl_jtag_errors.416967790 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_jtag_errors.416967790 -covoverwrite' seed=98793426285023242229204538655353696434238722712150045339604830573072695848046 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98793426285023242229204538655353696434238722712150045339604830573072695848046 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 12648647986456599181977311949236891385523269912964863854843144131923353783720 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3143093672 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/8.lc_ctrl_jtag_access.3143093672 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_jtag_access.3143093672 -covoverwrite' seed=12648647986456599181977311949236891385523269912964863854843144131923353783720 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12648647986456599181977311949236891385523269912964863854843144131923353783720 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_priority 69778029759956822874539640264289772297179121978699653633546788184304440191522 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_jtag_priority/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=228207138 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/8.lc_ctrl_jtag_priority.228207138 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_jtag_priority.228207138 -covoverwrite' seed=69778029759956822874539640264289772297179121978699653633546788184304440191522 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69778029759956822874539640264289772297179121978699653633546788184304440191522 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_jtag_priority/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_priority_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_regwen_during_op 73356011483798491095960890270697100808078980459863389925067020610000629392242 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_jtag_regwen_during_op/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1788994418 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/8.lc_ctrl_jtag_regwen_during_op.1788994418 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_jtag_regwen_during_op.1788994418 -covoverwrite' seed=73356011483798491095960890270697100808078980459863389925067020610000629392242 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73356011483798491095960890270697100808078980459863389925067020610000629392242 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_jtag_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_hw_reset 11248076024375405427391168709816860056772141455116297361501276059910181612585 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_jtag_csr_hw_reset/latest run_opts='+csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3261983785 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3261983785 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.lc_ctrl_jtag_csr_hw_reset.3261983785 -covoverwrite' seed=11248076024375405427391168709816860056772141455116297361501276059910181612585 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11248076024375405427391168709816860056772141455116297361501276059910181612585 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_jtag_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_rw 40272730784293639660065641374933763263144844591493459058250234016342929224304 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_jtag_csr_rw/latest run_opts='+csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3671503472 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3671503472 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.lc_ctrl_jtag_csr_rw.3671503472 -covoverwrite' seed=40272730784293639660065641374933763263144844591493459058250234016342929224304 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40272730784293639660065641374933763263144844591493459058250234016342929224304 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_jtag_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_bit_bash 54782020880691658212707812345956010814510611175289200256108826530205382559903 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_jtag_csr_bit_bash/latest run_opts='+csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1713719455 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.1713719455 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.lc_ctrl_jtag_csr_bit_bash.1713719455 -covoverwrite' seed=54782020880691658212707812345956010814510611175289200256108826530205382559903 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54782020880691658212707812345956010814510611175289200256108826530205382559903 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_jtag_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_aliasing 50302544723098044526612362478289883463772891465272310678707526319441594573381 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_jtag_csr_aliasing/latest run_opts='+csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4119618117 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.4119618117 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.lc_ctrl_jtag_csr_aliasing.4119618117 -covoverwrite' seed=50302544723098044526612362478289883463772891465272310678707526319441594573381 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50302544723098044526612362478289883463772891465272310678707526319441594573381 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_jtag_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_same_csr_outstanding 24261727425646843514306045995372850366518473868460094875144526831737561949276 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_jtag_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2699568220 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.2699568220 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.lc_ctrl_jtag_same_csr_outstanding.2699568220 -covoverwrite' seed=24261727425646843514306045995372850366518473868460094875144526831737561949276 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24261727425646843514306045995372850366518473868460094875144526831737561949276 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_jtag_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 78798070395340951197957889601722574789901045888340221235127177576888149920871 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2935671911 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2935671911 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2935671911 -covoverwrite' seed=78798070395340951197957889601722574789901045888340221235127177576888149920871 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78798070395340951197957889601722574789901045888340221235127177576888149920871 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_alert_test 107839125953484228339661200437609221708821785709382118727128438398293393770126 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_jtag_alert_test/latest run_opts='+run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1681884814 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.1681884814 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.lc_ctrl_jtag_alert_test.1681884814 -covoverwrite' seed=107839125953484228339661200437609221708821785709382118727128438398293393770126 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107839125953484228339661200437609221708821785709382118727128438398293393770126 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_jtag_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_mubi 102781155852510004435263593701248485664787515276672191990874280577397487638799 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_sec_mubi/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2523470095 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/8.lc_ctrl_sec_mubi.2523470095 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_sec_mubi.2523470095 -covoverwrite' seed=102781155852510004435263593701248485664787515276672191990874280577397487638799 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102781155852510004435263593701248485664787515276672191990874280577397487638799 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_sec_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_mubi_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_mux 24398881768401811314120004737422134395114316568933156240750113921306484454662 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_sec_token_mux/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3729962246 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/8.lc_ctrl_sec_token_mux.3729962246 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_sec_token_mux.3729962246 -covoverwrite' seed=24398881768401811314120004737422134395114316568933156240750113921306484454662 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24398881768401811314120004737422134395114316568933156240750113921306484454662 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_sec_token_mux/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_mux_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_digest 15393633220475570491890879941201732445132697112953351625926248564817838504372 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_sec_token_digest/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3997465012 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/8.lc_ctrl_sec_token_digest.3997465012 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_sec_token_digest.3997465012 -covoverwrite' seed=15393633220475570491890879941201732445132697112953351625926248564817838504372 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15393633220475570491890879941201732445132697112953351625926248564817838504372 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_sec_token_digest/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_digest_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_stress_all_with_rand_reset 10920958899644529708197446510929902783925753475370438381252377201327714901972 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_stress_all_with_rand_reset/latest run_opts='+create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2345705428 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.2345705428 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_stress_all_with_rand_reset.2345705428 -covoverwrite' seed=10920958899644529708197446510929902783925753475370438381252377201327714901972 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10920958899644529708197446510929902783925753475370438381252377201327714901972 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 76984999962364015180168288969302475622312497262176270175621358589018753634174 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=371101566 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/8.lc_ctrl_tl_errors.371101566 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.lc_ctrl_tl_errors.371101566 -covoverwrite' seed=76984999962364015180168288969302475622312497262176270175621358589018753634174 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76984999962364015180168288969302475622312497262176270175621358589018753634174 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 94802561804980636106821682152755318610053931816063208064516768808996433287963 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1914166043 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1914166043 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.lc_ctrl_tl_intg_err.1914166043 -covoverwrite' seed=94802561804980636106821682152755318610053931816063208064516768808996433287963 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94802561804980636106821682152755318610053931816063208064516768808996433287963 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_alert_test 113977291765090132164396840835678717592097732625629703528348327333004773288562 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1303767666 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/8.lc_ctrl_alert_test.1303767666 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_alert_test.1303767666 -covoverwrite' seed=113977291765090132164396840835678717592097732625629703528348327333004773288562 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113977291765090132164396840835678717592097732625629703528348327333004773288562 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/8.lc_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 73851927899589287574211136596187773932452634705687518584914542575832116835371 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1460745259 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/9.lc_ctrl_smoke.1460745259 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_smoke.1460745259 -covoverwrite' seed=73851927899589287574211136596187773932452634705687518584914542575832116835371 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73851927899589287574211136596187773932452634705687518584914542575832116835371 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_volatile_unlock_smoke 104443776385254669086285145798320287977801813536358246662399582945707370742789 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_volatile_unlock_smoke/latest run_opts='+en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4291298309 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/9.lc_ctrl_volatile_unlock_smoke.4291298309 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_volatile_unlock_smoke.4291298309 -covoverwrite' seed=104443776385254669086285145798320287977801813536358246662399582945707370742789 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104443776385254669086285145798320287977801813536358246662399582945707370742789 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_volatile_unlock_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_volatile_unlock_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 112043148752417418932185890871311935988676699297346166580939127991463979705493 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2232870037 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/9.lc_ctrl_state_failure.2232870037 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_state_failure.2232870037 -covoverwrite' seed=112043148752417418932185890871311935988676699297346166580939127991463979705493 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112043148752417418932185890871311935988676699297346166580939127991463979705493 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 2111304278131293654596912751201518591581629826518471923050562572079256057225 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3557045641 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/9.lc_ctrl_state_post_trans.3557045641 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_state_post_trans.3557045641 -covoverwrite' seed=2111304278131293654596912751201518591581629826518471923050562572079256057225 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2111304278131293654596912751201518591581629826518471923050562572079256057225 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 13318602110299877609498777869584946315233888769726615937909476736639135057380 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3083011556 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/9.lc_ctrl_prog_failure.3083011556 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_prog_failure.3083011556 -covoverwrite' seed=13318602110299877609498777869584946315233888769726615937909476736639135057380 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13318602110299877609498777869584946315233888769726615937909476736639135057380 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 3644145832005742488582593848685362982137139638443459434875290319374132728824 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4020524024 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/9.lc_ctrl_errors.4020524024 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_errors.4020524024 -covoverwrite' seed=3644145832005742488582593848685362982137139638443459434875290319374132728824 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3644145832005742488582593848685362982137139638443459434875290319374132728824 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 102997255121972728609780018460211454248351666939903165079656257932608896275448 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3655373816 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/9.lc_ctrl_security_escalation.3655373816 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_security_escalation.3655373816 -covoverwrite' seed=102997255121972728609780018460211454248351666939903165079656257932608896275448 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102997255121972728609780018460211454248351666939903165079656257932608896275448 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_regwen_during_op 74845489087716641703617465143667537873637100233224531092263513573934551990159 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_regwen_during_op/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3944415119 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/9.lc_ctrl_regwen_during_op.3944415119 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_regwen_during_op.3944415119 -covoverwrite' seed=74845489087716641703617465143667537873637100233224531092263513573934551990159 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74845489087716641703617465143667537873637100233224531092263513573934551990159 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_claim_transition_if 106222893143401774378484607166528841031159026601724229110779641808053476932523 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_claim_transition_if/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2626042795 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/9.lc_ctrl_claim_transition_if.2626042795 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_claim_transition_if.2626042795 -covoverwrite' seed=106222893143401774378484607166528841031159026601724229110779641808053476932523 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106222893143401774378484607166528841031159026601724229110779641808053476932523 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_claim_transition_if/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_claim_transition_if_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 86635980000823165078526455931683049866416833213289037412556137346995900858865 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3109241329 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/9.lc_ctrl_jtag_smoke.3109241329 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_jtag_smoke.3109241329 -covoverwrite' seed=86635980000823165078526455931683049866416833213289037412556137346995900858865 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86635980000823165078526455931683049866416833213289037412556137346995900858865 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 105003089864202778075222328572749153998036919666527985389207898541185386392435 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3204426611 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/9.lc_ctrl_jtag_state_failure.3204426611 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_jtag_state_failure.3204426611 -covoverwrite' seed=105003089864202778075222328572749153998036919666527985389207898541185386392435 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105003089864202778075222328572749153998036919666527985389207898541185386392435 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 113080847681335030767760177086046126914233936016730365601376910170904691034397 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=813779229 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/9.lc_ctrl_jtag_state_post_trans.813779229 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_jtag_state_post_trans.813779229 -covoverwrite' seed=113080847681335030767760177086046126914233936016730365601376910170904691034397 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113080847681335030767760177086046126914233936016730365601376910170904691034397 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 81774413105038463309486247833335506745799672114284324587712267568420729909942 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1236791990 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/9.lc_ctrl_jtag_prog_failure.1236791990 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_jtag_prog_failure.1236791990 -covoverwrite' seed=81774413105038463309486247833335506745799672114284324587712267568420729909942 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81774413105038463309486247833335506745799672114284324587712267568420729909942 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 55753120920249621056649278610372780771293229242671595542084379565792210094516 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3290597812 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/9.lc_ctrl_jtag_errors.3290597812 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_jtag_errors.3290597812 -covoverwrite' seed=55753120920249621056649278610372780771293229242671595542084379565792210094516 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55753120920249621056649278610372780771293229242671595542084379565792210094516 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 104210551492319128591280006300417667570745159242719420622573116670262833314616 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=865860408 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/9.lc_ctrl_jtag_access.865860408 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_jtag_access.865860408 -covoverwrite' seed=104210551492319128591280006300417667570745159242719420622573116670262833314616 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104210551492319128591280006300417667570745159242719420622573116670262833314616 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_priority 93794145339227892416386819009256179585657615770669647413973310454727121872642 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_jtag_priority/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4280592130 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/9.lc_ctrl_jtag_priority.4280592130 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_jtag_priority.4280592130 -covoverwrite' seed=93794145339227892416386819009256179585657615770669647413973310454727121872642 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93794145339227892416386819009256179585657615770669647413973310454727121872642 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_jtag_priority/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_priority_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_regwen_during_op 36315816899904893643782245953410539339595371563225680006275184233234375109050 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_jtag_regwen_during_op/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3807111610 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/9.lc_ctrl_jtag_regwen_during_op.3807111610 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_jtag_regwen_during_op.3807111610 -covoverwrite' seed=36315816899904893643782245953410539339595371563225680006275184233234375109050 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36315816899904893643782245953410539339595371563225680006275184233234375109050 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_jtag_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_hw_reset 7076089478969430560880593380428624111338201782642566481379727523705957656812 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_jtag_csr_hw_reset/latest run_opts='+csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=485763308 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.485763308 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.lc_ctrl_jtag_csr_hw_reset.485763308 -covoverwrite' seed=7076089478969430560880593380428624111338201782642566481379727523705957656812 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7076089478969430560880593380428624111338201782642566481379727523705957656812 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_jtag_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_rw 22737166427018149650888873707833157181807688710842685179113224016784561787760 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_jtag_csr_rw/latest run_opts='+csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=227267440 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.227267440 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.lc_ctrl_jtag_csr_rw.227267440 -covoverwrite' seed=22737166427018149650888873707833157181807688710842685179113224016784561787760 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22737166427018149650888873707833157181807688710842685179113224016784561787760 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_jtag_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_bit_bash 50386628935324982865179096719528196961943477040049017699409545827638210288374 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_jtag_csr_bit_bash/latest run_opts='+csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3133233910 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3133233910 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.lc_ctrl_jtag_csr_bit_bash.3133233910 -covoverwrite' seed=50386628935324982865179096719528196961943477040049017699409545827638210288374 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50386628935324982865179096719528196961943477040049017699409545827638210288374 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_jtag_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_aliasing 115277570179073243697019721702295362628174653608534013276377448705931260445782 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_jtag_csr_aliasing/latest run_opts='+csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1831322710 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.1831322710 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.lc_ctrl_jtag_csr_aliasing.1831322710 -covoverwrite' seed=115277570179073243697019721702295362628174653608534013276377448705931260445782 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115277570179073243697019721702295362628174653608534013276377448705931260445782 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_jtag_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_same_csr_outstanding 87606916081882026399716869073391635043424121958905242092553919583431446332040 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_jtag_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2939519624 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.2939519624 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.lc_ctrl_jtag_same_csr_outstanding.2939519624 -covoverwrite' seed=87606916081882026399716869073391635043424121958905242092553919583431446332040 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87606916081882026399716869073391635043424121958905242092553919583431446332040 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_jtag_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 49528860243142979996753365762195992043764563636786128863851448591838227256016 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=762893008 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.762893008 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.762893008 -covoverwrite' seed=49528860243142979996753365762195992043764563636786128863851448591838227256016 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49528860243142979996753365762195992043764563636786128863851448591838227256016 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_alert_test 77218690776848416418006042487624877112391462389101910772975573774918244865508 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_jtag_alert_test/latest run_opts='+run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2103416292 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2103416292 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.lc_ctrl_jtag_alert_test.2103416292 -covoverwrite' seed=77218690776848416418006042487624877112391462389101910772975573774918244865508 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77218690776848416418006042487624877112391462389101910772975573774918244865508 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_jtag_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_mubi 26122376455358495311966252663873226825635780505709191405485856916123441103047 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_sec_mubi/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3466002631 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/9.lc_ctrl_sec_mubi.3466002631 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_sec_mubi.3466002631 -covoverwrite' seed=26122376455358495311966252663873226825635780505709191405485856916123441103047 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26122376455358495311966252663873226825635780505709191405485856916123441103047 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_sec_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_mubi_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_mux 32734910440518886295567099823582050887873326709584450583690059772025515426027 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_sec_token_mux/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3628220651 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/9.lc_ctrl_sec_token_mux.3628220651 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_sec_token_mux.3628220651 -covoverwrite' seed=32734910440518886295567099823582050887873326709584450583690059772025515426027 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32734910440518886295567099823582050887873326709584450583690059772025515426027 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_sec_token_mux/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_mux_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_digest 65629784930627748888688110950879444389706206741836064522449520238062479257553 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_sec_token_digest/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2572857297 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/9.lc_ctrl_sec_token_digest.2572857297 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_sec_token_digest.2572857297 -covoverwrite' seed=65629784930627748888688110950879444389706206741836064522449520238062479257553 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65629784930627748888688110950879444389706206741836064522449520238062479257553 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_sec_token_digest/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_digest_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_stress_all_with_rand_reset 112817486586024662453915767513407693967569724876468354216720422654993205687794 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_stress_all_with_rand_reset/latest run_opts='+create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2127689202 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.2127689202 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_stress_all_with_rand_reset.2127689202 -covoverwrite' seed=112817486586024662453915767513407693967569724876468354216720422654993205687794 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112817486586024662453915767513407693967569724876468354216720422654993205687794 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 33925100087565668289408957462176705639803077857288296485151018536295601585785 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2347023993 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/9.lc_ctrl_tl_errors.2347023993 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.lc_ctrl_tl_errors.2347023993 -covoverwrite' seed=33925100087565668289408957462176705639803077857288296485151018536295601585785 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33925100087565668289408957462176705639803077857288296485151018536295601585785 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 49079276325805507721889549583467571125411467156775130565938359173484161815074 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1169969698 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.1169969698 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.lc_ctrl_tl_intg_err.1169969698 -covoverwrite' seed=49079276325805507721889549583467571125411467156775130565938359173484161815074 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49079276325805507721889549583467571125411467156775130565938359173484161815074 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_alert_test 107589918319639064399904874291007467105312673040754070897225176528604541414705 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=568782129 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/9.lc_ctrl_alert_test.568782129 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_alert_test.568782129 -covoverwrite' seed=107589918319639064399904874291007467105312673040754070897225176528604541414705 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107589918319639064399904874291007467105312673040754070897225176528604541414705 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/9.lc_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 43204580344357245298958646499298211306776974263072001766152243600060978396907 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/10.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=620855019 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/10.lc_ctrl_smoke.620855019 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 10.lc_ctrl_smoke.620855019 -covoverwrite' seed=43204580344357245298958646499298211306776974263072001766152243600060978396907 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43204580344357245298958646499298211306776974263072001766152243600060978396907 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/10.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 88141657320086967201565164087928070505451058340431968489453615936137482612122 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/10.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=713960858 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/10.lc_ctrl_state_failure.713960858 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 10.lc_ctrl_state_failure.713960858 -covoverwrite' seed=88141657320086967201565164087928070505451058340431968489453615936137482612122 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88141657320086967201565164087928070505451058340431968489453615936137482612122 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/10.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 3168742862964799537713859988428083817617463670971662263051682122322313410818 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/10.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=942078210 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/10.lc_ctrl_state_post_trans.942078210 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 10.lc_ctrl_state_post_trans.942078210 -covoverwrite' seed=3168742862964799537713859988428083817617463670971662263051682122322313410818 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3168742862964799537713859988428083817617463670971662263051682122322313410818 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/10.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 58203443912701140209140234169059605747982711545262612688543457306862111801066 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/10.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4238458602 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/10.lc_ctrl_prog_failure.4238458602 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 10.lc_ctrl_prog_failure.4238458602 -covoverwrite' seed=58203443912701140209140234169059605747982711545262612688543457306862111801066 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58203443912701140209140234169059605747982711545262612688543457306862111801066 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/10.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 76838606068084767872408934006541704448289327199979354705904708644999337083134 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/10.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=454557950 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/10.lc_ctrl_errors.454557950 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 10.lc_ctrl_errors.454557950 -covoverwrite' seed=76838606068084767872408934006541704448289327199979354705904708644999337083134 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76838606068084767872408934006541704448289327199979354705904708644999337083134 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/10.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 111585540989644281123743253618668925735534949978522225732028330694346328570082 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/10.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1939142882 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/10.lc_ctrl_security_escalation.1939142882 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 10.lc_ctrl_security_escalation.1939142882 -covoverwrite' seed=111585540989644281123743253618668925735534949978522225732028330694346328570082 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111585540989644281123743253618668925735534949978522225732028330694346328570082 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/10.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 35627688897252428869117638320413119836816793846172965694361873130078476632763 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/10.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=18023099 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/10.lc_ctrl_jtag_smoke.18023099 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 10.lc_ctrl_jtag_smoke.18023099 -covoverwrite' seed=35627688897252428869117638320413119836816793846172965694361873130078476632763 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35627688897252428869117638320413119836816793846172965694361873130078476632763 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/10.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 113395742602269999757012323945125256534289274928236856016529860743736372878031 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/10.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=818535119 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/10.lc_ctrl_jtag_state_failure.818535119 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 10.lc_ctrl_jtag_state_failure.818535119 -covoverwrite' seed=113395742602269999757012323945125256534289274928236856016529860743736372878031 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113395742602269999757012323945125256534289274928236856016529860743736372878031 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/10.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 3392098683249278878857265085173124272675506461714316820749928199295241688989 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/10.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1035605917 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/10.lc_ctrl_jtag_state_post_trans.1035605917 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 10.lc_ctrl_jtag_state_post_trans.1035605917 -covoverwrite' seed=3392098683249278878857265085173124272675506461714316820749928199295241688989 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3392098683249278878857265085173124272675506461714316820749928199295241688989 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/10.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 107145181442606705276223981457249173406297047460870336748378095803663660126870 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/10.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=298619542 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/10.lc_ctrl_jtag_prog_failure.298619542 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 10.lc_ctrl_jtag_prog_failure.298619542 -covoverwrite' seed=107145181442606705276223981457249173406297047460870336748378095803663660126870 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107145181442606705276223981457249173406297047460870336748378095803663660126870 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/10.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 96117288653778025726374813175780805302884129338568264989662173643847945899808 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/10.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=385306400 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/10.lc_ctrl_jtag_errors.385306400 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 10.lc_ctrl_jtag_errors.385306400 -covoverwrite' seed=96117288653778025726374813175780805302884129338568264989662173643847945899808 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96117288653778025726374813175780805302884129338568264989662173643847945899808 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/10.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 49063361636637050522090652859972494322662833727029616306205634757988139138548 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/10.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2276720116 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/10.lc_ctrl_jtag_access.2276720116 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 10.lc_ctrl_jtag_access.2276720116 -covoverwrite' seed=49063361636637050522090652859972494322662833727029616306205634757988139138548 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49063361636637050522090652859972494322662833727029616306205634757988139138548 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/10.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 81599988343301457018717016830789835182482598101340199270056820370599881530227 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/10.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3216825203 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/10.lc_ctrl_tl_errors.3216825203 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 10.lc_ctrl_tl_errors.3216825203 -covoverwrite' seed=81599988343301457018717016830789835182482598101340199270056820370599881530227 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81599988343301457018717016830789835182482598101340199270056820370599881530227 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/10.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 61860342678172010572737371855575653720840819108275463724294103962867207607777 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/10.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2316670433 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2316670433 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 10.lc_ctrl_tl_intg_err.2316670433 -covoverwrite' seed=61860342678172010572737371855575653720840819108275463724294103962867207607777 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61860342678172010572737371855575653720840819108275463724294103962867207607777 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/10.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 52753314299919102618611626463721837261275807514841044219205796165840769237251 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/11.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4216176899 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/11.lc_ctrl_smoke.4216176899 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 11.lc_ctrl_smoke.4216176899 -covoverwrite' seed=52753314299919102618611626463721837261275807514841044219205796165840769237251 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=52753314299919102618611626463721837261275807514841044219205796165840769237251 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/11.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 20008646739524145296200761110484852095232946000286570921044752891135612520156 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/11.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=294225628 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/11.lc_ctrl_state_failure.294225628 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 11.lc_ctrl_state_failure.294225628 -covoverwrite' seed=20008646739524145296200761110484852095232946000286570921044752891135612520156 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20008646739524145296200761110484852095232946000286570921044752891135612520156 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/11.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 15627546927393618718729280449587415225945476488362379826837631560952140159743 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/11.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=59136767 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/11.lc_ctrl_state_post_trans.59136767 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 11.lc_ctrl_state_post_trans.59136767 -covoverwrite' seed=15627546927393618718729280449587415225945476488362379826837631560952140159743 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15627546927393618718729280449587415225945476488362379826837631560952140159743 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/11.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 22157347533714120838188401948838036518525884189599442262324231686678520030831 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/11.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1085302383 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/11.lc_ctrl_prog_failure.1085302383 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 11.lc_ctrl_prog_failure.1085302383 -covoverwrite' seed=22157347533714120838188401948838036518525884189599442262324231686678520030831 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22157347533714120838188401948838036518525884189599442262324231686678520030831 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/11.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 18328706589984664280608376254952332599055636506218711842439669234378242694744 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/11.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2287902296 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/11.lc_ctrl_errors.2287902296 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 11.lc_ctrl_errors.2287902296 -covoverwrite' seed=18328706589984664280608376254952332599055636506218711842439669234378242694744 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18328706589984664280608376254952332599055636506218711842439669234378242694744 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/11.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 111220749694774378470331589240597622491843874253954087377232154911968696533982 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/11.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1960641502 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/11.lc_ctrl_security_escalation.1960641502 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 11.lc_ctrl_security_escalation.1960641502 -covoverwrite' seed=111220749694774378470331589240597622491843874253954087377232154911968696533982 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111220749694774378470331589240597622491843874253954087377232154911968696533982 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/11.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 76577291074939420830945145648519015073452166270054481174148610945226322556669 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/11.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1337800445 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/11.lc_ctrl_jtag_smoke.1337800445 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 11.lc_ctrl_jtag_smoke.1337800445 -covoverwrite' seed=76577291074939420830945145648519015073452166270054481174148610945226322556669 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76577291074939420830945145648519015073452166270054481174148610945226322556669 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/11.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 90803173302778751066628919134686653183764162707661678114421702890491378838295 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/11.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=525773591 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/11.lc_ctrl_jtag_state_failure.525773591 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 11.lc_ctrl_jtag_state_failure.525773591 -covoverwrite' seed=90803173302778751066628919134686653183764162707661678114421702890491378838295 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90803173302778751066628919134686653183764162707661678114421702890491378838295 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/11.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 40902267851185267572681648749030832999977367980546054442667786839474748242231 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/11.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2741745975 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/11.lc_ctrl_jtag_state_post_trans.2741745975 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 11.lc_ctrl_jtag_state_post_trans.2741745975 -covoverwrite' seed=40902267851185267572681648749030832999977367980546054442667786839474748242231 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40902267851185267572681648749030832999977367980546054442667786839474748242231 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/11.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 33336318716829567805152886641096103323334576405142183489073970996338827209391 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/11.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2418289327 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/11.lc_ctrl_jtag_prog_failure.2418289327 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 11.lc_ctrl_jtag_prog_failure.2418289327 -covoverwrite' seed=33336318716829567805152886641096103323334576405142183489073970996338827209391 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33336318716829567805152886641096103323334576405142183489073970996338827209391 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/11.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 46789645887369136043730888541014783805445307167310780284656079938717431584215 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/11.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=772756951 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/11.lc_ctrl_jtag_errors.772756951 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 11.lc_ctrl_jtag_errors.772756951 -covoverwrite' seed=46789645887369136043730888541014783805445307167310780284656079938717431584215 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46789645887369136043730888541014783805445307167310780284656079938717431584215 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/11.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 113446386402672645209757569459270360747163407353769459288099061702211482245460 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/11.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2683132244 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/11.lc_ctrl_jtag_access.2683132244 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 11.lc_ctrl_jtag_access.2683132244 -covoverwrite' seed=113446386402672645209757569459270360747163407353769459288099061702211482245460 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113446386402672645209757569459270360747163407353769459288099061702211482245460 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/11.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 88459269893278517955984167344390532103110568799260529150899788357529269993485 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/11.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1326481421 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/11.lc_ctrl_tl_errors.1326481421 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 11.lc_ctrl_tl_errors.1326481421 -covoverwrite' seed=88459269893278517955984167344390532103110568799260529150899788357529269993485 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88459269893278517955984167344390532103110568799260529150899788357529269993485 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/11.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 32560666355775895090819510030366475427235744572420213550026467096666301791528 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/11.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1469578536 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1469578536 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 11.lc_ctrl_tl_intg_err.1469578536 -covoverwrite' seed=32560666355775895090819510030366475427235744572420213550026467096666301791528 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32560666355775895090819510030366475427235744572420213550026467096666301791528 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/11.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 106330674823528052201303477614548838346463459950715136381285536925056562579217 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/12.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=836716305 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/12.lc_ctrl_smoke.836716305 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 12.lc_ctrl_smoke.836716305 -covoverwrite' seed=106330674823528052201303477614548838346463459950715136381285536925056562579217 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106330674823528052201303477614548838346463459950715136381285536925056562579217 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/12.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 86432021438687109190675782639179653567859106588451004701885137530960884131246 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/12.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2851202478 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/12.lc_ctrl_state_failure.2851202478 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 12.lc_ctrl_state_failure.2851202478 -covoverwrite' seed=86432021438687109190675782639179653567859106588451004701885137530960884131246 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86432021438687109190675782639179653567859106588451004701885137530960884131246 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/12.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 34627961335816864688945981995279727284211735782153594265895548723921442761165 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/12.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=899082701 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/12.lc_ctrl_state_post_trans.899082701 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 12.lc_ctrl_state_post_trans.899082701 -covoverwrite' seed=34627961335816864688945981995279727284211735782153594265895548723921442761165 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34627961335816864688945981995279727284211735782153594265895548723921442761165 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/12.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 16508498564453675977968223832264929078679598169192110549370067029284136752733 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/12.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=674043485 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/12.lc_ctrl_prog_failure.674043485 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 12.lc_ctrl_prog_failure.674043485 -covoverwrite' seed=16508498564453675977968223832264929078679598169192110549370067029284136752733 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16508498564453675977968223832264929078679598169192110549370067029284136752733 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/12.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 17961182834217439363778624845594809846272627144017078177781229392710829521089 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/12.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2445457601 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/12.lc_ctrl_errors.2445457601 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 12.lc_ctrl_errors.2445457601 -covoverwrite' seed=17961182834217439363778624845594809846272627144017078177781229392710829521089 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17961182834217439363778624845594809846272627144017078177781229392710829521089 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/12.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 107712610680069340424172639359758011730777443492200012023687129629516826779308 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/12.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3633946284 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/12.lc_ctrl_security_escalation.3633946284 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 12.lc_ctrl_security_escalation.3633946284 -covoverwrite' seed=107712610680069340424172639359758011730777443492200012023687129629516826779308 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107712610680069340424172639359758011730777443492200012023687129629516826779308 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/12.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 38594179609541889839970460028543656871261867971365695373978139616723982999499 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/12.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=803069899 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/12.lc_ctrl_jtag_smoke.803069899 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 12.lc_ctrl_jtag_smoke.803069899 -covoverwrite' seed=38594179609541889839970460028543656871261867971365695373978139616723982999499 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38594179609541889839970460028543656871261867971365695373978139616723982999499 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/12.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 97897335574701117754912167941414976309448420372724973370163429349196749456893 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/12.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=969262589 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/12.lc_ctrl_jtag_state_failure.969262589 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 12.lc_ctrl_jtag_state_failure.969262589 -covoverwrite' seed=97897335574701117754912167941414976309448420372724973370163429349196749456893 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97897335574701117754912167941414976309448420372724973370163429349196749456893 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/12.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 78584589216026842855292110919512236697596132745638814997000268444576568067079 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/12.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4015539207 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/12.lc_ctrl_jtag_state_post_trans.4015539207 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 12.lc_ctrl_jtag_state_post_trans.4015539207 -covoverwrite' seed=78584589216026842855292110919512236697596132745638814997000268444576568067079 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78584589216026842855292110919512236697596132745638814997000268444576568067079 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/12.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 35363215822193423392542275511360092043191255212065332438950023160791133176642 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/12.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2936914754 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/12.lc_ctrl_jtag_prog_failure.2936914754 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 12.lc_ctrl_jtag_prog_failure.2936914754 -covoverwrite' seed=35363215822193423392542275511360092043191255212065332438950023160791133176642 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35363215822193423392542275511360092043191255212065332438950023160791133176642 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/12.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 26047441220383930509722293650705199581421450303789486485215488564142476206225 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/12.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2321916049 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/12.lc_ctrl_jtag_errors.2321916049 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 12.lc_ctrl_jtag_errors.2321916049 -covoverwrite' seed=26047441220383930509722293650705199581421450303789486485215488564142476206225 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26047441220383930509722293650705199581421450303789486485215488564142476206225 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/12.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 71879059946831713778344538427595398038287459645156509203430652739524978088106 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/12.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=755308714 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/12.lc_ctrl_jtag_access.755308714 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 12.lc_ctrl_jtag_access.755308714 -covoverwrite' seed=71879059946831713778344538427595398038287459645156509203430652739524978088106 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71879059946831713778344538427595398038287459645156509203430652739524978088106 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/12.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 100385061063588488899582201118675868623727153084090975720744569478056015323731 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/12.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2949407315 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/12.lc_ctrl_tl_errors.2949407315 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 12.lc_ctrl_tl_errors.2949407315 -covoverwrite' seed=100385061063588488899582201118675868623727153084090975720744569478056015323731 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100385061063588488899582201118675868623727153084090975720744569478056015323731 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/12.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 27729003484495055773383829688238633842567517304271967623149700356554127490106 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/12.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1014414394 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.1014414394 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 12.lc_ctrl_tl_intg_err.1014414394 -covoverwrite' seed=27729003484495055773383829688238633842567517304271967623149700356554127490106 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27729003484495055773383829688238633842567517304271967623149700356554127490106 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/12.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 19988323671145554687609456466697860252399790081926356154089863271973888020561 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/13.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3324596305 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/13.lc_ctrl_smoke.3324596305 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 13.lc_ctrl_smoke.3324596305 -covoverwrite' seed=19988323671145554687609456466697860252399790081926356154089863271973888020561 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19988323671145554687609456466697860252399790081926356154089863271973888020561 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/13.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 94924463366018162974567454722520406795591299064966161501172703261932269381985 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/13.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=810068321 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/13.lc_ctrl_state_failure.810068321 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 13.lc_ctrl_state_failure.810068321 -covoverwrite' seed=94924463366018162974567454722520406795591299064966161501172703261932269381985 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94924463366018162974567454722520406795591299064966161501172703261932269381985 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/13.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 17540869806524118799069573534958276227349508713850953930055491369537306407505 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/13.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1163178577 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/13.lc_ctrl_state_post_trans.1163178577 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 13.lc_ctrl_state_post_trans.1163178577 -covoverwrite' seed=17540869806524118799069573534958276227349508713850953930055491369537306407505 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17540869806524118799069573534958276227349508713850953930055491369537306407505 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/13.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 32894177773962855562777614578413800199290819962864297008898810966055080527043 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/13.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=12682435 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/13.lc_ctrl_prog_failure.12682435 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 13.lc_ctrl_prog_failure.12682435 -covoverwrite' seed=32894177773962855562777614578413800199290819962864297008898810966055080527043 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32894177773962855562777614578413800199290819962864297008898810966055080527043 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/13.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 89637631684954335990236973194802437899802284693701102567948721369247571791964 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/13.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3659026524 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/13.lc_ctrl_errors.3659026524 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 13.lc_ctrl_errors.3659026524 -covoverwrite' seed=89637631684954335990236973194802437899802284693701102567948721369247571791964 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89637631684954335990236973194802437899802284693701102567948721369247571791964 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/13.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 96502267404941057614273439645356019466826818040455897309574571589900581859871 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/13.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4156158495 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/13.lc_ctrl_security_escalation.4156158495 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 13.lc_ctrl_security_escalation.4156158495 -covoverwrite' seed=96502267404941057614273439645356019466826818040455897309574571589900581859871 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96502267404941057614273439645356019466826818040455897309574571589900581859871 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/13.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 103968863631803546410479872963314354681468331483252219303216331110090548383723 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/13.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=393154539 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/13.lc_ctrl_jtag_smoke.393154539 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 13.lc_ctrl_jtag_smoke.393154539 -covoverwrite' seed=103968863631803546410479872963314354681468331483252219303216331110090548383723 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103968863631803546410479872963314354681468331483252219303216331110090548383723 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/13.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 16422737077603061114174901270628980574948494235703581478782348569212949864508 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/13.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1958453308 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/13.lc_ctrl_jtag_state_failure.1958453308 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 13.lc_ctrl_jtag_state_failure.1958453308 -covoverwrite' seed=16422737077603061114174901270628980574948494235703581478782348569212949864508 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16422737077603061114174901270628980574948494235703581478782348569212949864508 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/13.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 9013559213844025303801243228290173099671109421264730826278129941997730286371 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/13.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2834713379 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/13.lc_ctrl_jtag_state_post_trans.2834713379 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 13.lc_ctrl_jtag_state_post_trans.2834713379 -covoverwrite' seed=9013559213844025303801243228290173099671109421264730826278129941997730286371 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9013559213844025303801243228290173099671109421264730826278129941997730286371 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/13.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 59418891735249458674253353749253556290006890379753268277103604794243746717306 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/13.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4246036090 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/13.lc_ctrl_jtag_prog_failure.4246036090 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 13.lc_ctrl_jtag_prog_failure.4246036090 -covoverwrite' seed=59418891735249458674253353749253556290006890379753268277103604794243746717306 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=59418891735249458674253353749253556290006890379753268277103604794243746717306 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/13.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 62963438631838903981148915418378497290367090398365759280156441246381806973740 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/13.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=888664876 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/13.lc_ctrl_jtag_errors.888664876 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 13.lc_ctrl_jtag_errors.888664876 -covoverwrite' seed=62963438631838903981148915418378497290367090398365759280156441246381806973740 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62963438631838903981148915418378497290367090398365759280156441246381806973740 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/13.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 48902862735046732877403930992004330048893095658576300669550429742176119230355 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/13.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=227479443 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/13.lc_ctrl_jtag_access.227479443 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 13.lc_ctrl_jtag_access.227479443 -covoverwrite' seed=48902862735046732877403930992004330048893095658576300669550429742176119230355 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48902862735046732877403930992004330048893095658576300669550429742176119230355 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/13.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 87238795863675972599341007653027596610559406851031879350090882511125925919902 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/13.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1510800542 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/13.lc_ctrl_tl_errors.1510800542 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 13.lc_ctrl_tl_errors.1510800542 -covoverwrite' seed=87238795863675972599341007653027596610559406851031879350090882511125925919902 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87238795863675972599341007653027596610559406851031879350090882511125925919902 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/13.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 54956637537933664283205941105102813803911033054101332529910344500504517056586 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/13.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=382113866 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.382113866 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 13.lc_ctrl_tl_intg_err.382113866 -covoverwrite' seed=54956637537933664283205941105102813803911033054101332529910344500504517056586 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54956637537933664283205941105102813803911033054101332529910344500504517056586 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/13.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 17266912007982487648693071944738231583363201141781141929531282976998737091042 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/14.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2371918306 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/14.lc_ctrl_smoke.2371918306 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 14.lc_ctrl_smoke.2371918306 -covoverwrite' seed=17266912007982487648693071944738231583363201141781141929531282976998737091042 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17266912007982487648693071944738231583363201141781141929531282976998737091042 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/14.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 26030120551141163135393060752844953066406606236386654746297508701403821076526 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/14.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1455648814 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/14.lc_ctrl_state_failure.1455648814 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 14.lc_ctrl_state_failure.1455648814 -covoverwrite' seed=26030120551141163135393060752844953066406606236386654746297508701403821076526 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26030120551141163135393060752844953066406606236386654746297508701403821076526 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/14.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 82344822651847312709882272870654512279378379963427000351988813582989398881330 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/14.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=297514034 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/14.lc_ctrl_state_post_trans.297514034 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 14.lc_ctrl_state_post_trans.297514034 -covoverwrite' seed=82344822651847312709882272870654512279378379963427000351988813582989398881330 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82344822651847312709882272870654512279378379963427000351988813582989398881330 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/14.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 72179584195346138568910109741866218124374109308878973152346071819291187753960 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/14.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3563860968 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/14.lc_ctrl_prog_failure.3563860968 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 14.lc_ctrl_prog_failure.3563860968 -covoverwrite' seed=72179584195346138568910109741866218124374109308878973152346071819291187753960 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72179584195346138568910109741866218124374109308878973152346071819291187753960 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/14.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 6121319540711023587071610254982034920749336046970428675762114005672994512018 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/14.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=884972690 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/14.lc_ctrl_errors.884972690 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 14.lc_ctrl_errors.884972690 -covoverwrite' seed=6121319540711023587071610254982034920749336046970428675762114005672994512018 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6121319540711023587071610254982034920749336046970428675762114005672994512018 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/14.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 27578403871261050050676799521114029053872073788165080916349977635796185574881 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/14.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1328344545 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/14.lc_ctrl_security_escalation.1328344545 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 14.lc_ctrl_security_escalation.1328344545 -covoverwrite' seed=27578403871261050050676799521114029053872073788165080916349977635796185574881 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27578403871261050050676799521114029053872073788165080916349977635796185574881 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/14.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 38233508796692618418772538001143113593801206648967627667712771830722025625382 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/14.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=286398246 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/14.lc_ctrl_jtag_smoke.286398246 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 14.lc_ctrl_jtag_smoke.286398246 -covoverwrite' seed=38233508796692618418772538001143113593801206648967627667712771830722025625382 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38233508796692618418772538001143113593801206648967627667712771830722025625382 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/14.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 67888357172482508775054396947069464864502235635923683104582407358960225796175 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/14.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2846670927 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/14.lc_ctrl_jtag_state_failure.2846670927 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 14.lc_ctrl_jtag_state_failure.2846670927 -covoverwrite' seed=67888357172482508775054396947069464864502235635923683104582407358960225796175 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67888357172482508775054396947069464864502235635923683104582407358960225796175 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/14.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 43125490136657794360066986181389507065860757677832967038028590543812070525086 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/14.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2692008094 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/14.lc_ctrl_jtag_state_post_trans.2692008094 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 14.lc_ctrl_jtag_state_post_trans.2692008094 -covoverwrite' seed=43125490136657794360066986181389507065860757677832967038028590543812070525086 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43125490136657794360066986181389507065860757677832967038028590543812070525086 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/14.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 114799141900293079840824579913341346243968704058964466876008222738841597612564 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/14.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=331059732 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/14.lc_ctrl_jtag_prog_failure.331059732 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 14.lc_ctrl_jtag_prog_failure.331059732 -covoverwrite' seed=114799141900293079840824579913341346243968704058964466876008222738841597612564 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114799141900293079840824579913341346243968704058964466876008222738841597612564 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/14.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 83295949852787728889814132131121210675193431165687541331901168317586517353507 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/14.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=312828963 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/14.lc_ctrl_jtag_errors.312828963 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 14.lc_ctrl_jtag_errors.312828963 -covoverwrite' seed=83295949852787728889814132131121210675193431165687541331901168317586517353507 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83295949852787728889814132131121210675193431165687541331901168317586517353507 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/14.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 65871277044266358284944491636971449650392878115279280042817950638935799256674 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/14.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3126613602 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/14.lc_ctrl_jtag_access.3126613602 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 14.lc_ctrl_jtag_access.3126613602 -covoverwrite' seed=65871277044266358284944491636971449650392878115279280042817950638935799256674 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65871277044266358284944491636971449650392878115279280042817950638935799256674 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/14.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 90274395855644177209423824440069436232129779660043792387732734296656207418148 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/14.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1456476964 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/14.lc_ctrl_tl_errors.1456476964 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 14.lc_ctrl_tl_errors.1456476964 -covoverwrite' seed=90274395855644177209423824440069436232129779660043792387732734296656207418148 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90274395855644177209423824440069436232129779660043792387732734296656207418148 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/14.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 2174126262735375270189143042858711431656824642500861862173424597016038141077 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/14.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1677257877 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.1677257877 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 14.lc_ctrl_tl_intg_err.1677257877 -covoverwrite' seed=2174126262735375270189143042858711431656824642500861862173424597016038141077 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2174126262735375270189143042858711431656824642500861862173424597016038141077 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/14.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 105929094678310746487522378109943953673764913897797999647501241368692719108321 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/15.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=562053345 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/15.lc_ctrl_smoke.562053345 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 15.lc_ctrl_smoke.562053345 -covoverwrite' seed=105929094678310746487522378109943953673764913897797999647501241368692719108321 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105929094678310746487522378109943953673764913897797999647501241368692719108321 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/15.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 10759237606660073089819646732397042060553465089497850615382659773175652919936 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/15.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4206340736 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/15.lc_ctrl_state_failure.4206340736 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 15.lc_ctrl_state_failure.4206340736 -covoverwrite' seed=10759237606660073089819646732397042060553465089497850615382659773175652919936 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10759237606660073089819646732397042060553465089497850615382659773175652919936 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/15.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 48676840957649129620446577095520384730108285363921623012432897612417150731170 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/15.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4118791074 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/15.lc_ctrl_state_post_trans.4118791074 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 15.lc_ctrl_state_post_trans.4118791074 -covoverwrite' seed=48676840957649129620446577095520384730108285363921623012432897612417150731170 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48676840957649129620446577095520384730108285363921623012432897612417150731170 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/15.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 97059355449742498130792545613982510420924478372329984047224551134513797199174 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/15.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3979801926 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/15.lc_ctrl_prog_failure.3979801926 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 15.lc_ctrl_prog_failure.3979801926 -covoverwrite' seed=97059355449742498130792545613982510420924478372329984047224551134513797199174 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97059355449742498130792545613982510420924478372329984047224551134513797199174 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/15.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 39329495414416344862637828723274483485702185083908912758377470283231157235711 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/15.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1224159231 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/15.lc_ctrl_errors.1224159231 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 15.lc_ctrl_errors.1224159231 -covoverwrite' seed=39329495414416344862637828723274483485702185083908912758377470283231157235711 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39329495414416344862637828723274483485702185083908912758377470283231157235711 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/15.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 43607306948746766033296338150331045430657240246271496728020257133052997879559 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/15.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1858291463 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/15.lc_ctrl_security_escalation.1858291463 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 15.lc_ctrl_security_escalation.1858291463 -covoverwrite' seed=43607306948746766033296338150331045430657240246271496728020257133052997879559 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43607306948746766033296338150331045430657240246271496728020257133052997879559 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/15.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 35235293165466398887693789404117337202106123769127328986271598994736895854550 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/15.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1780320214 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/15.lc_ctrl_jtag_smoke.1780320214 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 15.lc_ctrl_jtag_smoke.1780320214 -covoverwrite' seed=35235293165466398887693789404117337202106123769127328986271598994736895854550 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35235293165466398887693789404117337202106123769127328986271598994736895854550 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/15.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 60648316016711544916584142882127454934696108592558653260147432062357426582464 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/15.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1562817472 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/15.lc_ctrl_jtag_state_failure.1562817472 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 15.lc_ctrl_jtag_state_failure.1562817472 -covoverwrite' seed=60648316016711544916584142882127454934696108592558653260147432062357426582464 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60648316016711544916584142882127454934696108592558653260147432062357426582464 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/15.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 94999621237636838960180749392945271544723952780547948782422899033074619699499 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/15.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1436602667 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/15.lc_ctrl_jtag_state_post_trans.1436602667 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 15.lc_ctrl_jtag_state_post_trans.1436602667 -covoverwrite' seed=94999621237636838960180749392945271544723952780547948782422899033074619699499 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94999621237636838960180749392945271544723952780547948782422899033074619699499 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/15.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 73946593813515795636854328347633283565537929651438647634015333344120023385009 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/15.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3289482161 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/15.lc_ctrl_jtag_prog_failure.3289482161 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 15.lc_ctrl_jtag_prog_failure.3289482161 -covoverwrite' seed=73946593813515795636854328347633283565537929651438647634015333344120023385009 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73946593813515795636854328347633283565537929651438647634015333344120023385009 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/15.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 95981989567429646434293564516563430940623895573391369452149646738141423379403 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/15.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3874530251 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/15.lc_ctrl_jtag_errors.3874530251 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 15.lc_ctrl_jtag_errors.3874530251 -covoverwrite' seed=95981989567429646434293564516563430940623895573391369452149646738141423379403 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95981989567429646434293564516563430940623895573391369452149646738141423379403 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/15.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 93887802406129521945390114708910662742017128261501576222320996376511744097542 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/15.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1624030470 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/15.lc_ctrl_jtag_access.1624030470 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 15.lc_ctrl_jtag_access.1624030470 -covoverwrite' seed=93887802406129521945390114708910662742017128261501576222320996376511744097542 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93887802406129521945390114708910662742017128261501576222320996376511744097542 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/15.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 25110515303804647044155269762199481832598242355831291387422711801511010292555 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/15.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1276302155 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/15.lc_ctrl_tl_errors.1276302155 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 15.lc_ctrl_tl_errors.1276302155 -covoverwrite' seed=25110515303804647044155269762199481832598242355831291387422711801511010292555 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25110515303804647044155269762199481832598242355831291387422711801511010292555 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/15.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 20434932517069032628789901486945132407862421854023327999677567523904367235840 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/15.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1580077824 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1580077824 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 15.lc_ctrl_tl_intg_err.1580077824 -covoverwrite' seed=20434932517069032628789901486945132407862421854023327999677567523904367235840 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20434932517069032628789901486945132407862421854023327999677567523904367235840 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/15.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 107736022853937150547703787592061143576453585500384655031341124339675824725627 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/16.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2644057723 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/16.lc_ctrl_smoke.2644057723 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 16.lc_ctrl_smoke.2644057723 -covoverwrite' seed=107736022853937150547703787592061143576453585500384655031341124339675824725627 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107736022853937150547703787592061143576453585500384655031341124339675824725627 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/16.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 87673136395059301621312546461774496459566192524262748638254341638505512706659 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/16.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3869647459 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/16.lc_ctrl_state_failure.3869647459 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 16.lc_ctrl_state_failure.3869647459 -covoverwrite' seed=87673136395059301621312546461774496459566192524262748638254341638505512706659 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87673136395059301621312546461774496459566192524262748638254341638505512706659 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/16.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 74191915288899106388144286302969996842639682463010366095108830097229019040158 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/16.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1514621342 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/16.lc_ctrl_state_post_trans.1514621342 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 16.lc_ctrl_state_post_trans.1514621342 -covoverwrite' seed=74191915288899106388144286302969996842639682463010366095108830097229019040158 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74191915288899106388144286302969996842639682463010366095108830097229019040158 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/16.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 96984843223254550931120582083354758647357737433257409049453242756038341565467 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/16.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3657571355 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/16.lc_ctrl_prog_failure.3657571355 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 16.lc_ctrl_prog_failure.3657571355 -covoverwrite' seed=96984843223254550931120582083354758647357737433257409049453242756038341565467 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96984843223254550931120582083354758647357737433257409049453242756038341565467 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/16.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 77635889505353770998232554116406878452030383730703563011750180779190129629066 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/16.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3578632074 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/16.lc_ctrl_errors.3578632074 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 16.lc_ctrl_errors.3578632074 -covoverwrite' seed=77635889505353770998232554116406878452030383730703563011750180779190129629066 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77635889505353770998232554116406878452030383730703563011750180779190129629066 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/16.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 13898796711906009200850591949809198747693115994481113904079596152345997108676 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/16.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3037226436 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/16.lc_ctrl_security_escalation.3037226436 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 16.lc_ctrl_security_escalation.3037226436 -covoverwrite' seed=13898796711906009200850591949809198747693115994481113904079596152345997108676 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13898796711906009200850591949809198747693115994481113904079596152345997108676 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/16.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 67205872521414824502496735294907781976069150109184509045201242539547878257308 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/16.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3085464220 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/16.lc_ctrl_jtag_smoke.3085464220 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 16.lc_ctrl_jtag_smoke.3085464220 -covoverwrite' seed=67205872521414824502496735294907781976069150109184509045201242539547878257308 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67205872521414824502496735294907781976069150109184509045201242539547878257308 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/16.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 2986603816283769743956254397835739342541328416129606240500548367063562311057 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/16.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=158848401 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/16.lc_ctrl_jtag_state_failure.158848401 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 16.lc_ctrl_jtag_state_failure.158848401 -covoverwrite' seed=2986603816283769743956254397835739342541328416129606240500548367063562311057 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2986603816283769743956254397835739342541328416129606240500548367063562311057 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/16.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 16504438010765622656091310827019362397315334955714124768221163364698302970585 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/16.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=142867161 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/16.lc_ctrl_jtag_state_post_trans.142867161 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 16.lc_ctrl_jtag_state_post_trans.142867161 -covoverwrite' seed=16504438010765622656091310827019362397315334955714124768221163364698302970585 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16504438010765622656091310827019362397315334955714124768221163364698302970585 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/16.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 103356052711445774649527273538849292315803801337269618198760066890310062429367 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/16.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3301954743 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/16.lc_ctrl_jtag_prog_failure.3301954743 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 16.lc_ctrl_jtag_prog_failure.3301954743 -covoverwrite' seed=103356052711445774649527273538849292315803801337269618198760066890310062429367 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103356052711445774649527273538849292315803801337269618198760066890310062429367 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/16.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 16050153335754456636307475650993471744070023482883864543739101852762456120109 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/16.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3231898413 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/16.lc_ctrl_jtag_errors.3231898413 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 16.lc_ctrl_jtag_errors.3231898413 -covoverwrite' seed=16050153335754456636307475650993471744070023482883864543739101852762456120109 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16050153335754456636307475650993471744070023482883864543739101852762456120109 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/16.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 51807608324413611861734403038872042582526290436505969086240405933191468102791 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/16.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=142554247 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/16.lc_ctrl_jtag_access.142554247 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 16.lc_ctrl_jtag_access.142554247 -covoverwrite' seed=51807608324413611861734403038872042582526290436505969086240405933191468102791 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51807608324413611861734403038872042582526290436505969086240405933191468102791 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/16.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 54651125757737040089176898681058448390452212265911192435442641821517817175904 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/16.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4281982816 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/16.lc_ctrl_tl_errors.4281982816 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 16.lc_ctrl_tl_errors.4281982816 -covoverwrite' seed=54651125757737040089176898681058448390452212265911192435442641821517817175904 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54651125757737040089176898681058448390452212265911192435442641821517817175904 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/16.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 8358176518747303711841199086108568581794323076927973687732119564680918081224 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/16.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3021872840 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.3021872840 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 16.lc_ctrl_tl_intg_err.3021872840 -covoverwrite' seed=8358176518747303711841199086108568581794323076927973687732119564680918081224 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8358176518747303711841199086108568581794323076927973687732119564680918081224 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/16.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 25529742092726296798897969275992628276680067634612535725587454031380611829962 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/17.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2058064074 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/17.lc_ctrl_smoke.2058064074 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 17.lc_ctrl_smoke.2058064074 -covoverwrite' seed=25529742092726296798897969275992628276680067634612535725587454031380611829962 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25529742092726296798897969275992628276680067634612535725587454031380611829962 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/17.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 27310797401142893859638615257042410257825616881025606014473162154423561760704 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/17.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1236021184 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/17.lc_ctrl_state_failure.1236021184 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 17.lc_ctrl_state_failure.1236021184 -covoverwrite' seed=27310797401142893859638615257042410257825616881025606014473162154423561760704 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27310797401142893859638615257042410257825616881025606014473162154423561760704 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/17.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 4744338160501579922841625608440726530136985635935282105732374826632373716220 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/17.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1989002492 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/17.lc_ctrl_state_post_trans.1989002492 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 17.lc_ctrl_state_post_trans.1989002492 -covoverwrite' seed=4744338160501579922841625608440726530136985635935282105732374826632373716220 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4744338160501579922841625608440726530136985635935282105732374826632373716220 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/17.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 86356620712582517322560257684207892335648049407856984173599714087289514097837 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/17.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3006790829 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/17.lc_ctrl_prog_failure.3006790829 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 17.lc_ctrl_prog_failure.3006790829 -covoverwrite' seed=86356620712582517322560257684207892335648049407856984173599714087289514097837 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86356620712582517322560257684207892335648049407856984173599714087289514097837 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/17.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 38056825967183131031713700554798072462370026625918042271120873280595359637911 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/17.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3622248855 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/17.lc_ctrl_errors.3622248855 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 17.lc_ctrl_errors.3622248855 -covoverwrite' seed=38056825967183131031713700554798072462370026625918042271120873280595359637911 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38056825967183131031713700554798072462370026625918042271120873280595359637911 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/17.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 26302853777420514901977472871269563723601609415004236568991399061030304843042 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/17.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1176601890 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/17.lc_ctrl_security_escalation.1176601890 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 17.lc_ctrl_security_escalation.1176601890 -covoverwrite' seed=26302853777420514901977472871269563723601609415004236568991399061030304843042 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26302853777420514901977472871269563723601609415004236568991399061030304843042 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/17.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 104900246554265130045621315235675857122930114862543328050064029101323004385363 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/17.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4167800915 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/17.lc_ctrl_jtag_smoke.4167800915 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 17.lc_ctrl_jtag_smoke.4167800915 -covoverwrite' seed=104900246554265130045621315235675857122930114862543328050064029101323004385363 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104900246554265130045621315235675857122930114862543328050064029101323004385363 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/17.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 12434009786587506849303724882157274072627321488641099043833654797124461981747 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/17.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=801435699 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/17.lc_ctrl_jtag_state_failure.801435699 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 17.lc_ctrl_jtag_state_failure.801435699 -covoverwrite' seed=12434009786587506849303724882157274072627321488641099043833654797124461981747 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12434009786587506849303724882157274072627321488641099043833654797124461981747 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/17.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 104517733212756572852927865251214469140118830390640210305359834347172042039567 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/17.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2764497167 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/17.lc_ctrl_jtag_state_post_trans.2764497167 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 17.lc_ctrl_jtag_state_post_trans.2764497167 -covoverwrite' seed=104517733212756572852927865251214469140118830390640210305359834347172042039567 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104517733212756572852927865251214469140118830390640210305359834347172042039567 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/17.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 104950506198452879528905491753766894101400674443992871781639300345481990324879 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/17.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1806254735 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/17.lc_ctrl_jtag_prog_failure.1806254735 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 17.lc_ctrl_jtag_prog_failure.1806254735 -covoverwrite' seed=104950506198452879528905491753766894101400674443992871781639300345481990324879 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104950506198452879528905491753766894101400674443992871781639300345481990324879 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/17.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 4298539669606999823740938906128483350686264161503457443703391986211783738605 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/17.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1773438189 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/17.lc_ctrl_jtag_errors.1773438189 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 17.lc_ctrl_jtag_errors.1773438189 -covoverwrite' seed=4298539669606999823740938906128483350686264161503457443703391986211783738605 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4298539669606999823740938906128483350686264161503457443703391986211783738605 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/17.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 106326502872726436676848773368074734097944999895710607602934863789340314000375 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/17.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1078418423 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/17.lc_ctrl_jtag_access.1078418423 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 17.lc_ctrl_jtag_access.1078418423 -covoverwrite' seed=106326502872726436676848773368074734097944999895710607602934863789340314000375 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106326502872726436676848773368074734097944999895710607602934863789340314000375 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/17.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 34797111232812945160264937654334563310218755420018357639487349129165872236128 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/17.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1579615840 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1579615840 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 17.lc_ctrl_tl_errors.1579615840 -covoverwrite' seed=34797111232812945160264937654334563310218755420018357639487349129165872236128 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34797111232812945160264937654334563310218755420018357639487349129165872236128 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/17.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 74563314757401557565425456116074509451964747209884979754800024124372789375317 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/17.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=491401557 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.491401557 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 17.lc_ctrl_tl_intg_err.491401557 -covoverwrite' seed=74563314757401557565425456116074509451964747209884979754800024124372789375317 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74563314757401557565425456116074509451964747209884979754800024124372789375317 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/17.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 17367874129981924060733428350089835031902232966993627632088705735748803498970 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/18.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2233078746 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/18.lc_ctrl_smoke.2233078746 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 18.lc_ctrl_smoke.2233078746 -covoverwrite' seed=17367874129981924060733428350089835031902232966993627632088705735748803498970 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17367874129981924060733428350089835031902232966993627632088705735748803498970 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/18.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 115065941440497854210695306892076671345952492267061606037762952619084822731371 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/18.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1072028267 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/18.lc_ctrl_state_failure.1072028267 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 18.lc_ctrl_state_failure.1072028267 -covoverwrite' seed=115065941440497854210695306892076671345952492267061606037762952619084822731371 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115065941440497854210695306892076671345952492267061606037762952619084822731371 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/18.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 4423548031538168361714464319766776070832812947981268060002455992310694071366 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/18.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=58903622 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/18.lc_ctrl_state_post_trans.58903622 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 18.lc_ctrl_state_post_trans.58903622 -covoverwrite' seed=4423548031538168361714464319766776070832812947981268060002455992310694071366 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4423548031538168361714464319766776070832812947981268060002455992310694071366 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/18.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 48057949748554265928225405018836854067212722424000775993238541259628479064482 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/18.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1062807970 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/18.lc_ctrl_prog_failure.1062807970 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 18.lc_ctrl_prog_failure.1062807970 -covoverwrite' seed=48057949748554265928225405018836854067212722424000775993238541259628479064482 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48057949748554265928225405018836854067212722424000775993238541259628479064482 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/18.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 77469985476219342509735433086862925215942464323059982402908106471515509576828 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/18.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2559923324 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/18.lc_ctrl_errors.2559923324 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 18.lc_ctrl_errors.2559923324 -covoverwrite' seed=77469985476219342509735433086862925215942464323059982402908106471515509576828 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77469985476219342509735433086862925215942464323059982402908106471515509576828 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/18.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 105560419831606080730272432520107817744982296367549864020379233486974087539616 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/18.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1404513184 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/18.lc_ctrl_security_escalation.1404513184 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 18.lc_ctrl_security_escalation.1404513184 -covoverwrite' seed=105560419831606080730272432520107817744982296367549864020379233486974087539616 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105560419831606080730272432520107817744982296367549864020379233486974087539616 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/18.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 10431984846691981756269428718896951289367312114264970029871014173147463265613 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/18.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2470554957 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/18.lc_ctrl_jtag_smoke.2470554957 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 18.lc_ctrl_jtag_smoke.2470554957 -covoverwrite' seed=10431984846691981756269428718896951289367312114264970029871014173147463265613 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10431984846691981756269428718896951289367312114264970029871014173147463265613 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/18.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 36006840055828990716570469258451109950944051110267713724448110764865280538545 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/18.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1294202801 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/18.lc_ctrl_jtag_state_failure.1294202801 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 18.lc_ctrl_jtag_state_failure.1294202801 -covoverwrite' seed=36006840055828990716570469258451109950944051110267713724448110764865280538545 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36006840055828990716570469258451109950944051110267713724448110764865280538545 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/18.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 46532928490263359077844701900016096570993830892614404966641333009018423400953 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/18.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3477395961 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/18.lc_ctrl_jtag_state_post_trans.3477395961 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 18.lc_ctrl_jtag_state_post_trans.3477395961 -covoverwrite' seed=46532928490263359077844701900016096570993830892614404966641333009018423400953 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46532928490263359077844701900016096570993830892614404966641333009018423400953 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/18.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 77478399922478864049358119979816668968601924617203279611353586518434903344758 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/18.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2389034614 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/18.lc_ctrl_jtag_prog_failure.2389034614 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 18.lc_ctrl_jtag_prog_failure.2389034614 -covoverwrite' seed=77478399922478864049358119979816668968601924617203279611353586518434903344758 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77478399922478864049358119979816668968601924617203279611353586518434903344758 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/18.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 367752982782119105961424316663406128503404310334843233573816306211320223562 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/18.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1059313482 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/18.lc_ctrl_jtag_errors.1059313482 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 18.lc_ctrl_jtag_errors.1059313482 -covoverwrite' seed=367752982782119105961424316663406128503404310334843233573816306211320223562 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=367752982782119105961424316663406128503404310334843233573816306211320223562 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/18.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 24838668828798385601555314853773688577254411285321916459218195953558126299395 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/18.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=10455299 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/18.lc_ctrl_jtag_access.10455299 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 18.lc_ctrl_jtag_access.10455299 -covoverwrite' seed=24838668828798385601555314853773688577254411285321916459218195953558126299395 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24838668828798385601555314853773688577254411285321916459218195953558126299395 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/18.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 41854241097376084795814454648611413101410150985421489718226634089807627413151 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/18.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2270946975 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/18.lc_ctrl_tl_errors.2270946975 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 18.lc_ctrl_tl_errors.2270946975 -covoverwrite' seed=41854241097376084795814454648611413101410150985421489718226634089807627413151 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41854241097376084795814454648611413101410150985421489718226634089807627413151 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/18.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 78786025080028637151096301962659597285218259943586592608854418369001290013004 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/18.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=512039244 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.512039244 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 18.lc_ctrl_tl_intg_err.512039244 -covoverwrite' seed=78786025080028637151096301962659597285218259943586592608854418369001290013004 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78786025080028637151096301962659597285218259943586592608854418369001290013004 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/18.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 33313347848262581991307607196730011215276955646273422280778895401408372496477 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/19.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3226818653 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/19.lc_ctrl_smoke.3226818653 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 19.lc_ctrl_smoke.3226818653 -covoverwrite' seed=33313347848262581991307607196730011215276955646273422280778895401408372496477 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33313347848262581991307607196730011215276955646273422280778895401408372496477 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/19.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 38058922853669936825596935101958166897545282302552220729108443206937098602519 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/19.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=529549335 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/19.lc_ctrl_state_failure.529549335 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 19.lc_ctrl_state_failure.529549335 -covoverwrite' seed=38058922853669936825596935101958166897545282302552220729108443206937098602519 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38058922853669936825596935101958166897545282302552220729108443206937098602519 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/19.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 16243239443095549663373819419436158186187572974061348359828977818809501964773 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/19.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=148855269 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/19.lc_ctrl_state_post_trans.148855269 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 19.lc_ctrl_state_post_trans.148855269 -covoverwrite' seed=16243239443095549663373819419436158186187572974061348359828977818809501964773 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16243239443095549663373819419436158186187572974061348359828977818809501964773 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/19.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 61863878095822100010700932430923377274859697689501441729814928617821417626071 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/19.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3897154007 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/19.lc_ctrl_prog_failure.3897154007 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 19.lc_ctrl_prog_failure.3897154007 -covoverwrite' seed=61863878095822100010700932430923377274859697689501441729814928617821417626071 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61863878095822100010700932430923377274859697689501441729814928617821417626071 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/19.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 110677737415546103336566366695777591704378152490782370166833139265054206180939 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/19.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=532266571 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/19.lc_ctrl_errors.532266571 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 19.lc_ctrl_errors.532266571 -covoverwrite' seed=110677737415546103336566366695777591704378152490782370166833139265054206180939 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110677737415546103336566366695777591704378152490782370166833139265054206180939 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/19.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 72473288315015265756882358890749076122258191680748636072957639116790225152070 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/19.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3710888006 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/19.lc_ctrl_security_escalation.3710888006 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 19.lc_ctrl_security_escalation.3710888006 -covoverwrite' seed=72473288315015265756882358890749076122258191680748636072957639116790225152070 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72473288315015265756882358890749076122258191680748636072957639116790225152070 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/19.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 77188757326613180335162057412495037961172916188407263714498668364249092477724 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/19.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=427971356 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/19.lc_ctrl_jtag_smoke.427971356 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 19.lc_ctrl_jtag_smoke.427971356 -covoverwrite' seed=77188757326613180335162057412495037961172916188407263714498668364249092477724 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77188757326613180335162057412495037961172916188407263714498668364249092477724 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/19.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 36909246518714276921537385518466164623528506695942325883792807226506245799962 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/19.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2588901402 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/19.lc_ctrl_jtag_state_failure.2588901402 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 19.lc_ctrl_jtag_state_failure.2588901402 -covoverwrite' seed=36909246518714276921537385518466164623528506695942325883792807226506245799962 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36909246518714276921537385518466164623528506695942325883792807226506245799962 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/19.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 112320231519740711336252967017280061826571666400500212415503566887106606181375 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/19.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=668904447 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/19.lc_ctrl_jtag_state_post_trans.668904447 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 19.lc_ctrl_jtag_state_post_trans.668904447 -covoverwrite' seed=112320231519740711336252967017280061826571666400500212415503566887106606181375 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112320231519740711336252967017280061826571666400500212415503566887106606181375 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/19.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 53155892902050148568524593110327741229114795498233000261249622351968718858561 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/19.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3861162305 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/19.lc_ctrl_jtag_prog_failure.3861162305 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 19.lc_ctrl_jtag_prog_failure.3861162305 -covoverwrite' seed=53155892902050148568524593110327741229114795498233000261249622351968718858561 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53155892902050148568524593110327741229114795498233000261249622351968718858561 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/19.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 80496011223129304120895642656995803328631911753617007584865454511870962292672 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/19.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3150698432 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/19.lc_ctrl_jtag_errors.3150698432 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 19.lc_ctrl_jtag_errors.3150698432 -covoverwrite' seed=80496011223129304120895642656995803328631911753617007584865454511870962292672 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80496011223129304120895642656995803328631911753617007584865454511870962292672 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/19.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 82761458419481571260388946582244350182428949887347413596830790517110563817189 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/19.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2747156197 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/19.lc_ctrl_jtag_access.2747156197 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 19.lc_ctrl_jtag_access.2747156197 -covoverwrite' seed=82761458419481571260388946582244350182428949887347413596830790517110563817189 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82761458419481571260388946582244350182428949887347413596830790517110563817189 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/19.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 27927424108884264165063510697703920065388894091297054505036379429625021526223 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/19.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1650127055 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/19.lc_ctrl_tl_errors.1650127055 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 19.lc_ctrl_tl_errors.1650127055 -covoverwrite' seed=27927424108884264165063510697703920065388894091297054505036379429625021526223 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27927424108884264165063510697703920065388894091297054505036379429625021526223 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/19.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 2300138188199062241094984748587913724629647606285380007675910213796884541000 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/19.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1744989768 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.1744989768 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 19.lc_ctrl_tl_intg_err.1744989768 -covoverwrite' seed=2300138188199062241094984748587913724629647606285380007675910213796884541000 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2300138188199062241094984748587913724629647606285380007675910213796884541000 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/19.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 88534666542249641736286322848408186952493967403731501939700241938304267903102 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/20.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2999115902 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/20.lc_ctrl_jtag_access.2999115902 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 20.lc_ctrl_jtag_access.2999115902 -covoverwrite' seed=88534666542249641736286322848408186952493967403731501939700241938304267903102 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88534666542249641736286322848408186952493967403731501939700241938304267903102 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/20.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 89611180490146295091225978095521337074047441652329250386728302727712773205100 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/20.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1260612716 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/20.lc_ctrl_tl_errors.1260612716 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 20.lc_ctrl_tl_errors.1260612716 -covoverwrite' seed=89611180490146295091225978095521337074047441652329250386728302727712773205100 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89611180490146295091225978095521337074047441652329250386728302727712773205100 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/20.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 99960350723977295309622328932814945143569911128638330257596885766404128990486 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/20.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3984942358 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/20.lc_ctrl_tl_intg_err.3984942358 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 20.lc_ctrl_tl_intg_err.3984942358 -covoverwrite' seed=99960350723977295309622328932814945143569911128638330257596885766404128990486 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99960350723977295309622328932814945143569911128638330257596885766404128990486 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/20.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 17983448574987532371257130394027616304809543498117577522623215721052916167359 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/21.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1363161791 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/21.lc_ctrl_jtag_access.1363161791 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 21.lc_ctrl_jtag_access.1363161791 -covoverwrite' seed=17983448574987532371257130394027616304809543498117577522623215721052916167359 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17983448574987532371257130394027616304809543498117577522623215721052916167359 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/21.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 41421372237094894079867597808715336466447105053207052531321902946184354525211 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/21.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2147676187 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/21.lc_ctrl_tl_errors.2147676187 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 21.lc_ctrl_tl_errors.2147676187 -covoverwrite' seed=41421372237094894079867597808715336466447105053207052531321902946184354525211 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41421372237094894079867597808715336466447105053207052531321902946184354525211 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/21.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 79967669142505027047827963528020802613645021316796743097129160826810589483883 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/21.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=781161323 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/21.lc_ctrl_tl_intg_err.781161323 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 21.lc_ctrl_tl_intg_err.781161323 -covoverwrite' seed=79967669142505027047827963528020802613645021316796743097129160826810589483883 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79967669142505027047827963528020802613645021316796743097129160826810589483883 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/21.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 61447931870389697679020876408499409589222939491625419064289690842611709702840 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/22.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1032647352 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/22.lc_ctrl_jtag_access.1032647352 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 22.lc_ctrl_jtag_access.1032647352 -covoverwrite' seed=61447931870389697679020876408499409589222939491625419064289690842611709702840 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61447931870389697679020876408499409589222939491625419064289690842611709702840 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/22.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 18190710464030682459118557933415463758706042838748094466177890151766215909893 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/22.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=652239365 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/22.lc_ctrl_tl_errors.652239365 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 22.lc_ctrl_tl_errors.652239365 -covoverwrite' seed=18190710464030682459118557933415463758706042838748094466177890151766215909893 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18190710464030682459118557933415463758706042838748094466177890151766215909893 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/22.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 7022562202039651263363293983145887584159228300460943599272150395617690449607 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/22.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=701953735 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/22.lc_ctrl_tl_intg_err.701953735 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 22.lc_ctrl_tl_intg_err.701953735 -covoverwrite' seed=7022562202039651263363293983145887584159228300460943599272150395617690449607 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7022562202039651263363293983145887584159228300460943599272150395617690449607 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/22.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 8679155832344829827529542121795560082373551674124680205014252197264592069721 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/23.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1726866521 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/23.lc_ctrl_jtag_access.1726866521 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 23.lc_ctrl_jtag_access.1726866521 -covoverwrite' seed=8679155832344829827529542121795560082373551674124680205014252197264592069721 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8679155832344829827529542121795560082373551674124680205014252197264592069721 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/23.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 89642788534619242802261381459943751700010543509045016492230312289620940605027 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/23.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3398223459 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/23.lc_ctrl_tl_errors.3398223459 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 23.lc_ctrl_tl_errors.3398223459 -covoverwrite' seed=89642788534619242802261381459943751700010543509045016492230312289620940605027 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89642788534619242802261381459943751700010543509045016492230312289620940605027 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/23.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 18274827727134602550537747258552986157845270480205738455268439158145977248601 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/23.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2688641881 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/23.lc_ctrl_tl_intg_err.2688641881 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 23.lc_ctrl_tl_intg_err.2688641881 -covoverwrite' seed=18274827727134602550537747258552986157845270480205738455268439158145977248601 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18274827727134602550537747258552986157845270480205738455268439158145977248601 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/23.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 112920898035830781833755484932279456417211744126886254823230625720060522034100 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/24.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3061347252 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/24.lc_ctrl_jtag_access.3061347252 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 24.lc_ctrl_jtag_access.3061347252 -covoverwrite' seed=112920898035830781833755484932279456417211744126886254823230625720060522034100 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112920898035830781833755484932279456417211744126886254823230625720060522034100 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/24.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 62436883908316402668721340544484859695649788011664768129235611539916597410410 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/24.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3190733418 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/24.lc_ctrl_tl_errors.3190733418 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 24.lc_ctrl_tl_errors.3190733418 -covoverwrite' seed=62436883908316402668721340544484859695649788011664768129235611539916597410410 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62436883908316402668721340544484859695649788011664768129235611539916597410410 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/24.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 32390652342893993796372062889201220267003974526486550196372102038172024808551 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/24.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3403785319 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/cover_reg_top/24.lc_ctrl_tl_intg_err.3403785319 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 24.lc_ctrl_tl_intg_err.3403785319 -covoverwrite' seed=32390652342893993796372062889201220267003974526486550196372102038172024808551 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32390652342893993796372062889201220267003974526486550196372102038172024808551 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/24.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 100542370611882104556051776006594769206483633894269672433844582623588663363324 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/25.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2052785916 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/25.lc_ctrl_jtag_access.2052785916 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 25.lc_ctrl_jtag_access.2052785916 -covoverwrite' seed=100542370611882104556051776006594769206483633894269672433844582623588663363324 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100542370611882104556051776006594769206483633894269672433844582623588663363324 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/25.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 13094890544944468684114344421253227931923690797014215782423233499302560051042 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/26.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2992680802 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/26.lc_ctrl_jtag_access.2992680802 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 26.lc_ctrl_jtag_access.2992680802 -covoverwrite' seed=13094890544944468684114344421253227931923690797014215782423233499302560051042 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13094890544944468684114344421253227931923690797014215782423233499302560051042 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/26.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 110115935367383391371607924721651812499406568961652330769604370079417239653587 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/27.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1137757395 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/27.lc_ctrl_jtag_access.1137757395 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 27.lc_ctrl_jtag_access.1137757395 -covoverwrite' seed=110115935367383391371607924721651812499406568961652330769604370079417239653587 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110115935367383391371607924721651812499406568961652330769604370079417239653587 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/27.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 44346330366200219895017015228020983447865133344959191073896297661921779083577 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/28.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1735223609 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/28.lc_ctrl_jtag_access.1735223609 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 28.lc_ctrl_jtag_access.1735223609 -covoverwrite' seed=44346330366200219895017015228020983447865133344959191073896297661921779083577 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44346330366200219895017015228020983447865133344959191073896297661921779083577 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/28.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 91324989677522033818616275201080024551112190791713700941205278685838238556443 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/29.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2572689691 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/29.lc_ctrl_jtag_access.2572689691 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 29.lc_ctrl_jtag_access.2572689691 -covoverwrite' seed=91324989677522033818616275201080024551112190791713700941205278685838238556443 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91324989677522033818616275201080024551112190791713700941205278685838238556443 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/29.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 11945092935368699336982624113049570520351888743425248029923770753199705244973 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/30.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=865682733 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/30.lc_ctrl_jtag_access.865682733 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 30.lc_ctrl_jtag_access.865682733 -covoverwrite' seed=11945092935368699336982624113049570520351888743425248029923770753199705244973 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11945092935368699336982624113049570520351888743425248029923770753199705244973 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/30.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 103347395123561556689347176460537017470938718791044242984787746795266204185220 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/31.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2742497924 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/31.lc_ctrl_jtag_access.2742497924 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 31.lc_ctrl_jtag_access.2742497924 -covoverwrite' seed=103347395123561556689347176460537017470938718791044242984787746795266204185220 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103347395123561556689347176460537017470938718791044242984787746795266204185220 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/31.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 32146038309335210846422820886850349439094653826607262392587651520509201232990 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/32.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2552116318 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/32.lc_ctrl_jtag_access.2552116318 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 32.lc_ctrl_jtag_access.2552116318 -covoverwrite' seed=32146038309335210846422820886850349439094653826607262392587651520509201232990 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32146038309335210846422820886850349439094653826607262392587651520509201232990 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/32.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 20090818118857622875126104504397027149596819253681049483717159912048180158753 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/33.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=789143841 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/33.lc_ctrl_jtag_access.789143841 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 33.lc_ctrl_jtag_access.789143841 -covoverwrite' seed=20090818118857622875126104504397027149596819253681049483717159912048180158753 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20090818118857622875126104504397027149596819253681049483717159912048180158753 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/33.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 79197887523206710259336741467129130227553877509013298468663580596760865857960 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/34.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2074272168 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/34.lc_ctrl_jtag_access.2074272168 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 34.lc_ctrl_jtag_access.2074272168 -covoverwrite' seed=79197887523206710259336741467129130227553877509013298468663580596760865857960 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79197887523206710259336741467129130227553877509013298468663580596760865857960 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/34.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 52326982140855340629026685324356658020579624311219138835709791918122832943150 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/35.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=8050734 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/35.lc_ctrl_jtag_access.8050734 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 35.lc_ctrl_jtag_access.8050734 -covoverwrite' seed=52326982140855340629026685324356658020579624311219138835709791918122832943150 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=52326982140855340629026685324356658020579624311219138835709791918122832943150 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/35.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 80153962646886846090409334917713550632560019563202323089571080482893478536724 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/36.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2566170132 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/36.lc_ctrl_jtag_access.2566170132 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 36.lc_ctrl_jtag_access.2566170132 -covoverwrite' seed=80153962646886846090409334917713550632560019563202323089571080482893478536724 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80153962646886846090409334917713550632560019563202323089571080482893478536724 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/36.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 19945168530852763253067482626548878289926351389573080054111977202530168906122 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/37.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1987092874 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/37.lc_ctrl_jtag_access.1987092874 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 37.lc_ctrl_jtag_access.1987092874 -covoverwrite' seed=19945168530852763253067482626548878289926351389573080054111977202530168906122 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19945168530852763253067482626548878289926351389573080054111977202530168906122 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/37.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 43298901654819527183748970328867155995770176217261599539378994533620981453810 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/38.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2135970802 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/38.lc_ctrl_jtag_access.2135970802 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 38.lc_ctrl_jtag_access.2135970802 -covoverwrite' seed=43298901654819527183748970328867155995770176217261599539378994533620981453810 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43298901654819527183748970328867155995770176217261599539378994533620981453810 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/38.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 9777178685679216634488295339465652549165461271635235321732597985326027822938 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/39.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=643356506 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/39.lc_ctrl_jtag_access.643356506 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 39.lc_ctrl_jtag_access.643356506 -covoverwrite' seed=9777178685679216634488295339465652549165461271635235321732597985326027822938 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9777178685679216634488295339465652549165461271635235321732597985326027822938 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/39.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 82676939193841029617572598518142405397784878951954745130312606404416366062272 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/40.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2077895360 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/40.lc_ctrl_jtag_access.2077895360 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 40.lc_ctrl_jtag_access.2077895360 -covoverwrite' seed=82676939193841029617572598518142405397784878951954745130312606404416366062272 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82676939193841029617572598518142405397784878951954745130312606404416366062272 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/40.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 32743652704014387123441378253721770801808385864035110570873684392929259104232 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/41.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2777360360 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/41.lc_ctrl_jtag_access.2777360360 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 41.lc_ctrl_jtag_access.2777360360 -covoverwrite' seed=32743652704014387123441378253721770801808385864035110570873684392929259104232 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32743652704014387123441378253721770801808385864035110570873684392929259104232 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/41.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 90645297155549886944869536139858211591413599143403008183166810120594953411340 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/42.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1051007756 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/42.lc_ctrl_jtag_access.1051007756 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 42.lc_ctrl_jtag_access.1051007756 -covoverwrite' seed=90645297155549886944869536139858211591413599143403008183166810120594953411340 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90645297155549886944869536139858211591413599143403008183166810120594953411340 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/42.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 57431274215766945150142591565187735405012482460539152067048141672244811316696 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/43.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2837626328 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/43.lc_ctrl_jtag_access.2837626328 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 43.lc_ctrl_jtag_access.2837626328 -covoverwrite' seed=57431274215766945150142591565187735405012482460539152067048141672244811316696 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57431274215766945150142591565187735405012482460539152067048141672244811316696 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/43.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 3920445018750513456277049527056702774554532144596257755400363243653247187100 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/44.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1977006236 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/44.lc_ctrl_jtag_access.1977006236 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 44.lc_ctrl_jtag_access.1977006236 -covoverwrite' seed=3920445018750513456277049527056702774554532144596257755400363243653247187100 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3920445018750513456277049527056702774554532144596257755400363243653247187100 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/44.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 113662661155075098439426867624010733852671885559983974807628780752573244017559 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/45.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3143535511 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/45.lc_ctrl_jtag_access.3143535511 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 45.lc_ctrl_jtag_access.3143535511 -covoverwrite' seed=113662661155075098439426867624010733852671885559983974807628780752573244017559 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113662661155075098439426867624010733852671885559983974807628780752573244017559 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/45.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 41569963889464361408030115648502146631721716162937532590417531858360828693043 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/46.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1990724147 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/46.lc_ctrl_jtag_access.1990724147 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 46.lc_ctrl_jtag_access.1990724147 -covoverwrite' seed=41569963889464361408030115648502146631721716162937532590417531858360828693043 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41569963889464361408030115648502146631721716162937532590417531858360828693043 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/46.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 41046046008023189364397021981423907907231678070495549401934032341349359778165 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/47.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4238178677 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/47.lc_ctrl_jtag_access.4238178677 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 47.lc_ctrl_jtag_access.4238178677 -covoverwrite' seed=41046046008023189364397021981423907907231678070495549401934032341349359778165 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41046046008023189364397021981423907907231678070495549401934032341349359778165 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/47.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 51543664794357846550890846729068589836238786745629367831544962814093959729332 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/48.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2887094452 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/48.lc_ctrl_jtag_access.2887094452 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 48.lc_ctrl_jtag_access.2887094452 -covoverwrite' seed=51543664794357846550890846729068589836238786745629367831544962814093959729332 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51543664794357846550890846729068589836238786745629367831544962814093959729332 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/48.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 113147457149447770998884505580555922094647865269529151572448466279771295884566 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/49.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1099605270 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage/default/49.lc_ctrl_jtag_access.1099605270 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/coverage -covscope default -covtest 49.lc_ctrl_jtag_access.1099605270 -covoverwrite' seed=113147457149447770998884505580555922094647865269529151572448466279771295884566 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113147457149447770998884505580555922094647865269529151572448466279771295884566 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_disabled-sim-xcelium/49.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
Job timed out after * minutes 10 test runs
lc_ctrl_stress_all 55034364506750126376086629881815859033048436793665199612084783738359786766096 None
lc_ctrl_stress_all 34759750346289435753974737756747533904318476103624218322713071626093825685484 None
lc_ctrl_stress_all 40841209474221303726057480412961709311462692650470550539237261012794048715713 None
lc_ctrl_stress_all 60847995549342610264124919874581860469251649436241744063014391887342624321358 None
lc_ctrl_stress_all 13966885428724282376125639826706617557912776256657320685707835003029424635675 None
lc_ctrl_stress_all 71834621270015281551580225014639959271827213779680459929700196851952614952421 None
lc_ctrl_stress_all 95824813680391297677548526294832244403793619769314549734601087986618727496417 None
lc_ctrl_stress_all 867463203274859764946221604737048297247005374890842004815801802646506879384 None
lc_ctrl_stress_all 68530633298599085609755457617253853664630247997013255107976768991472179077991 None
lc_ctrl_stress_all 113641446272465969527712142777238994500704603830676900674468460735875406510781 None
Job cancelled because all of its dependencies failed or were killed. 1 test run
lc_ctrl None None
Job cancelled because one of its dependencies failed or was killed. 1 test run
lc_ctrl None None