Simulation Results: lc_ctrl/volatile_unlock_enabled

 
28/08/2026 21:54:34 DVSim: v1.49.0 sha: a099412 json Branch: master Tool: xcelium [unknown]
Validation stages
V1
0.00%
V2
0.00%
V2S
0.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 0 20 0.00
lc_ctrl_smoke 1.620s 0.000us 0 20 0.00
csr_hw_reset 0 1 0.00
lc_ctrl_csr_hw_reset 0.912s 0.000us 0 1 0.00
csr_rw 0 5 0.00
lc_ctrl_csr_rw 1.373s 0.000us 0 5 0.00
csr_bit_bash 0 1 0.00
lc_ctrl_csr_bit_bash 0.911s 0.000us 0 1 0.00
csr_aliasing 0 1 0.00
lc_ctrl_csr_aliasing 1.341s 0.000us 0 1 0.00
csr_mem_rw_with_rand_reset 0 5 0.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.895s 0.000us 0 5 0.00
regwen_csr_and_corresponding_lockable_csr 0 6 0.00
lc_ctrl_csr_rw 1.373s 0.000us 0 5 0.00
lc_ctrl_csr_aliasing 1.341s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 0 20 0.00
lc_ctrl_state_post_trans 1.612s 0.000us 0 20 0.00
regwen_during_op 0 10 0.00
lc_ctrl_regwen_during_op 0.938s 0.000us 0 10 0.00
rand_wr_claim_transition_if 0 10 0.00
lc_ctrl_claim_transition_if 0.916s 0.000us 0 10 0.00
lc_prog_failure 0 20 0.00
lc_ctrl_prog_failure 0.927s 0.000us 0 20 0.00
lc_state_failure 0 20 0.00
lc_ctrl_state_failure 0.959s 0.000us 0 20 0.00
lc_errors 0 20 0.00
lc_ctrl_errors 1.637s 0.000us 0 20 0.00
security_escalation 0 140 0.00
lc_ctrl_state_failure 0.959s 0.000us 0 20 0.00
lc_ctrl_prog_failure 0.927s 0.000us 0 20 0.00
lc_ctrl_errors 1.637s 0.000us 0 20 0.00
lc_ctrl_security_escalation 1.611s 0.000us 0 20 0.00
lc_ctrl_jtag_state_failure 1.620s 0.000us 0 20 0.00
lc_ctrl_jtag_prog_failure 1.721s 0.000us 0 20 0.00
lc_ctrl_jtag_errors 1.701s 0.000us 0 20 0.00
jtag_access 0 210 0.00
lc_ctrl_jtag_smoke 1.658s 0.000us 0 20 0.00
lc_ctrl_jtag_state_post_trans 0.946s 0.000us 0 20 0.00
lc_ctrl_jtag_prog_failure 1.721s 0.000us 0 20 0.00
lc_ctrl_jtag_errors 1.701s 0.000us 0 20 0.00
lc_ctrl_jtag_access 1.620s 0.000us 0 50 0.00
lc_ctrl_jtag_regwen_during_op 1.659s 0.000us 0 10 0.00
lc_ctrl_jtag_csr_hw_reset 0.916s 0.000us 0 10 0.00
lc_ctrl_jtag_csr_rw 1.494s 0.000us 0 10 0.00
lc_ctrl_jtag_csr_bit_bash 0.943s 0.000us 0 10 0.00
lc_ctrl_jtag_csr_aliasing 1.636s 0.000us 0 10 0.00
lc_ctrl_jtag_same_csr_outstanding 1.645s 0.000us 0 10 0.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 0.910s 0.000us 0 10 0.00
lc_ctrl_jtag_alert_test 1.601s 0.000us 0 10 0.00
jtag_priority 0 10 0.00
lc_ctrl_jtag_priority 0.932s 0.000us 0 10 0.00
lc_ctrl_volatile_unlock 0 10 0.00
lc_ctrl_volatile_unlock_smoke 0.929s 0.000us 0 10 0.00
stress_all 0 10 0.00
lc_ctrl_stress_all 10803.000s 0.000us 0 10 0.00
alert_test 0 10 0.00
lc_ctrl_alert_test 0.917s 0.000us 0 10 0.00
tl_d_oob_addr_access 0 25 0.00
lc_ctrl_tl_errors 1.647s 0.000us 0 25 0.00
tl_d_illegal_access 0 25 0.00
lc_ctrl_tl_errors 1.647s 0.000us 0 25 0.00
tl_d_outstanding_access 0 12 0.00
lc_ctrl_csr_hw_reset 0.912s 0.000us 0 1 0.00
lc_ctrl_csr_rw 1.373s 0.000us 0 5 0.00
lc_ctrl_csr_aliasing 1.341s 0.000us 0 1 0.00
lc_ctrl_same_csr_outstanding 0.950s 0.000us 0 5 0.00
tl_d_partial_access 0 12 0.00
lc_ctrl_csr_hw_reset 0.912s 0.000us 0 1 0.00
lc_ctrl_csr_rw 1.373s 0.000us 0 5 0.00
lc_ctrl_csr_aliasing 1.341s 0.000us 0 1 0.00
lc_ctrl_same_csr_outstanding 0.950s 0.000us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 30 0.00
lc_ctrl_sec_cm 0.926s 0.000us 0 5 0.00
lc_ctrl_tl_intg_err 1.608s 0.000us 0 25 0.00
sec_cm_bus_integrity 0 25 0.00
lc_ctrl_tl_intg_err 1.608s 0.000us 0 25 0.00
sec_cm_transition_config_regwen 0 10 0.00
lc_ctrl_regwen_during_op 0.938s 0.000us 0 10 0.00
sec_cm_manuf_state_sparse 0 25 0.00
lc_ctrl_state_failure 0.959s 0.000us 0 20 0.00
lc_ctrl_sec_cm 0.926s 0.000us 0 5 0.00
sec_cm_transition_ctr_sparse 0 25 0.00
lc_ctrl_state_failure 0.959s 0.000us 0 20 0.00
lc_ctrl_sec_cm 0.926s 0.000us 0 5 0.00
sec_cm_manuf_state_bkgn_chk 0 25 0.00
lc_ctrl_state_failure 0.959s 0.000us 0 20 0.00
lc_ctrl_sec_cm 0.926s 0.000us 0 5 0.00
sec_cm_transition_ctr_bkgn_chk 0 25 0.00
lc_ctrl_state_failure 0.959s 0.000us 0 20 0.00
lc_ctrl_sec_cm 0.926s 0.000us 0 5 0.00
sec_cm_state_config_sparse 0 25 0.00
lc_ctrl_state_failure 0.959s 0.000us 0 20 0.00
lc_ctrl_sec_cm 0.926s 0.000us 0 5 0.00
sec_cm_main_fsm_sparse 0 25 0.00
lc_ctrl_state_failure 0.959s 0.000us 0 20 0.00
lc_ctrl_sec_cm 0.926s 0.000us 0 5 0.00
sec_cm_kmac_fsm_sparse 0 25 0.00
lc_ctrl_state_failure 0.959s 0.000us 0 20 0.00
lc_ctrl_sec_cm 0.926s 0.000us 0 5 0.00
sec_cm_main_fsm_local_esc 0 25 0.00
lc_ctrl_state_failure 0.959s 0.000us 0 20 0.00
lc_ctrl_sec_cm 0.926s 0.000us 0 5 0.00
sec_cm_main_fsm_global_esc 0 20 0.00
lc_ctrl_security_escalation 1.611s 0.000us 0 20 0.00
sec_cm_main_ctrl_flow_consistency 0 40 0.00
lc_ctrl_state_post_trans 1.612s 0.000us 0 20 0.00
lc_ctrl_jtag_state_post_trans 0.946s 0.000us 0 20 0.00
sec_cm_intersig_mubi 0 10 0.00
lc_ctrl_sec_mubi 0.913s 0.000us 0 10 0.00
sec_cm_token_valid_ctrl_mubi 0 10 0.00
lc_ctrl_sec_mubi 0.913s 0.000us 0 10 0.00
sec_cm_token_digest 0 10 0.00
lc_ctrl_sec_token_digest 0.932s 0.000us 0 10 0.00
sec_cm_token_mux_ctrl_redun 0 10 0.00
lc_ctrl_sec_token_mux 1.592s 0.000us 0 10 0.00
sec_cm_token_valid_mux_redun 0 10 0.00
lc_ctrl_sec_token_mux 1.592s 0.000us 0 10 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 10 0.00
lc_ctrl_stress_all_with_rand_reset 0.923s 0.000us 0 10 0.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 513 test runs
lc_ctrl_smoke 78072353197739769864473477923341561665222755469998877759844950595811061960510 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2992803646 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/0.lc_ctrl_smoke.2992803646 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_smoke.2992803646 -covoverwrite' seed=78072353197739769864473477923341561665222755469998877759844950595811061960510 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78072353197739769864473477923341561665222755469998877759844950595811061960510 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_volatile_unlock_smoke 69949343004373456121777211461157489005198046503645532071875085311399713360288 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_volatile_unlock_smoke/latest run_opts='+en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3630221728 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/0.lc_ctrl_volatile_unlock_smoke.3630221728 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_volatile_unlock_smoke.3630221728 -covoverwrite' seed=69949343004373456121777211461157489005198046503645532071875085311399713360288 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69949343004373456121777211461157489005198046503645532071875085311399713360288 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_volatile_unlock_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_volatile_unlock_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 54684335992424814904176532144621354813283988416368109953584014350794112486738 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1276235090 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/0.lc_ctrl_state_failure.1276235090 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_state_failure.1276235090 -covoverwrite' seed=54684335992424814904176532144621354813283988416368109953584014350794112486738 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54684335992424814904176532144621354813283988416368109953584014350794112486738 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 17617402971111056499703815314123407156470728711943940239701077976004604855679 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=263062911 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/0.lc_ctrl_state_post_trans.263062911 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_state_post_trans.263062911 -covoverwrite' seed=17617402971111056499703815314123407156470728711943940239701077976004604855679 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17617402971111056499703815314123407156470728711943940239701077976004604855679 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 98799583932374749341289347318291137224770332855917140920334642952952713894558 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=423942814 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/0.lc_ctrl_prog_failure.423942814 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_prog_failure.423942814 -covoverwrite' seed=98799583932374749341289347318291137224770332855917140920334642952952713894558 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98799583932374749341289347318291137224770332855917140920334642952952713894558 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 95353717434603739426321769344044950336429473110301007282498817901100043810791 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=491468775 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/0.lc_ctrl_errors.491468775 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_errors.491468775 -covoverwrite' seed=95353717434603739426321769344044950336429473110301007282498817901100043810791 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95353717434603739426321769344044950336429473110301007282498817901100043810791 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 10594162218803909109637246261942040889811277578226951967850303569985231211248 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=764758768 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/0.lc_ctrl_security_escalation.764758768 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_security_escalation.764758768 -covoverwrite' seed=10594162218803909109637246261942040889811277578226951967850303569985231211248 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10594162218803909109637246261942040889811277578226951967850303569985231211248 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_regwen_during_op 15431343497631138177077191938445866834340997512727268223752672731515877407540 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_regwen_during_op/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3761584948 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/0.lc_ctrl_regwen_during_op.3761584948 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_regwen_during_op.3761584948 -covoverwrite' seed=15431343497631138177077191938445866834340997512727268223752672731515877407540 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15431343497631138177077191938445866834340997512727268223752672731515877407540 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_claim_transition_if 66270792439760440617777711259770169833164309328557201326265610736379053187728 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_claim_transition_if/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=874750608 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/0.lc_ctrl_claim_transition_if.874750608 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_claim_transition_if.874750608 -covoverwrite' seed=66270792439760440617777711259770169833164309328557201326265610736379053187728 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66270792439760440617777711259770169833164309328557201326265610736379053187728 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_claim_transition_if/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_claim_transition_if_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 88857221266770858937911464091297149253093818004883327299901937368773740228027 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4113067451 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/0.lc_ctrl_jtag_smoke.4113067451 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_jtag_smoke.4113067451 -covoverwrite' seed=88857221266770858937911464091297149253093818004883327299901937368773740228027 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88857221266770858937911464091297149253093818004883327299901937368773740228027 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 114589354767912138230379723396425034429519064868298953119681024811815599591237 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=762302277 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/0.lc_ctrl_jtag_state_failure.762302277 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_jtag_state_failure.762302277 -covoverwrite' seed=114589354767912138230379723396425034429519064868298953119681024811815599591237 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114589354767912138230379723396425034429519064868298953119681024811815599591237 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 24337163143830555709569228645594681080026076069966327413746798733232637734536 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4063489672 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/0.lc_ctrl_jtag_state_post_trans.4063489672 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_jtag_state_post_trans.4063489672 -covoverwrite' seed=24337163143830555709569228645594681080026076069966327413746798733232637734536 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24337163143830555709569228645594681080026076069966327413746798733232637734536 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 38105973068736538587770390303174038981432342352320733010638853480501151757222 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1213690790 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/0.lc_ctrl_jtag_prog_failure.1213690790 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_jtag_prog_failure.1213690790 -covoverwrite' seed=38105973068736538587770390303174038981432342352320733010638853480501151757222 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38105973068736538587770390303174038981432342352320733010638853480501151757222 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 85267067013178732716168676968070873609185131313269936213674968096203072846184 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3036133736 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/0.lc_ctrl_jtag_errors.3036133736 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_jtag_errors.3036133736 -covoverwrite' seed=85267067013178732716168676968070873609185131313269936213674968096203072846184 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85267067013178732716168676968070873609185131313269936213674968096203072846184 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 23670213290520684404665191383731279358783556407420887913203691549376570867285 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1662139989 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/0.lc_ctrl_jtag_access.1662139989 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_jtag_access.1662139989 -covoverwrite' seed=23670213290520684404665191383731279358783556407420887913203691549376570867285 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23670213290520684404665191383731279358783556407420887913203691549376570867285 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_priority 106007874376027375643347434235784226578298282080718446923356298826256023908296 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_jtag_priority/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=667774920 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/0.lc_ctrl_jtag_priority.667774920 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_jtag_priority.667774920 -covoverwrite' seed=106007874376027375643347434235784226578298282080718446923356298826256023908296 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106007874376027375643347434235784226578298282080718446923356298826256023908296 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_jtag_priority/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_priority_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_regwen_during_op 103111507258947969942482321350720378263166747401551298843225952457804714444792 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_jtag_regwen_during_op/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4082206712 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/0.lc_ctrl_jtag_regwen_during_op.4082206712 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_jtag_regwen_during_op.4082206712 -covoverwrite' seed=103111507258947969942482321350720378263166747401551298843225952457804714444792 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103111507258947969942482321350720378263166747401551298843225952457804714444792 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_jtag_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_hw_reset 113831963296068902285664016953257545106170061634538346486183728429222235417972 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_jtag_csr_hw_reset/latest run_opts='+csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2711039348 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.2711039348 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.lc_ctrl_jtag_csr_hw_reset.2711039348 -covoverwrite' seed=113831963296068902285664016953257545106170061634538346486183728429222235417972 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113831963296068902285664016953257545106170061634538346486183728429222235417972 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_jtag_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_rw 75733833742562393962630996513093914555187033171977303530304156076076363754537 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_jtag_csr_rw/latest run_opts='+csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3063491625 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3063491625 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.lc_ctrl_jtag_csr_rw.3063491625 -covoverwrite' seed=75733833742562393962630996513093914555187033171977303530304156076076363754537 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75733833742562393962630996513093914555187033171977303530304156076076363754537 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_jtag_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_bit_bash 31333620961170469675790441778954328242468255518511564235701600563279256771306 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_jtag_csr_bit_bash/latest run_opts='+csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3807533802 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.3807533802 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.lc_ctrl_jtag_csr_bit_bash.3807533802 -covoverwrite' seed=31333620961170469675790441778954328242468255518511564235701600563279256771306 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31333620961170469675790441778954328242468255518511564235701600563279256771306 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_jtag_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_aliasing 70819504784005265158888888224518280727563614741728332537639234039879362622515 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_jtag_csr_aliasing/latest run_opts='+csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1558918195 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.1558918195 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.lc_ctrl_jtag_csr_aliasing.1558918195 -covoverwrite' seed=70819504784005265158888888224518280727563614741728332537639234039879362622515 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70819504784005265158888888224518280727563614741728332537639234039879362622515 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_jtag_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_same_csr_outstanding 86460636313396319743887395844999941408584242406993920359400810139361544278468 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_jtag_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3188232644 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.3188232644 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.lc_ctrl_jtag_same_csr_outstanding.3188232644 -covoverwrite' seed=86460636313396319743887395844999941408584242406993920359400810139361544278468 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86460636313396319743887395844999941408584242406993920359400810139361544278468 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_jtag_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 65721017326428412617863411925946640420298933482194418019992721691661043349408 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1362737056 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1362737056 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1362737056 -covoverwrite' seed=65721017326428412617863411925946640420298933482194418019992721691661043349408 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65721017326428412617863411925946640420298933482194418019992721691661043349408 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_alert_test 81942889759592610706283719312590107129655860989018874255594039186815107137178 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_jtag_alert_test/latest run_opts='+run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3284074138 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.3284074138 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.lc_ctrl_jtag_alert_test.3284074138 -covoverwrite' seed=81942889759592610706283719312590107129655860989018874255594039186815107137178 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81942889759592610706283719312590107129655860989018874255594039186815107137178 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_jtag_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_mubi 2188757110188444339901868130506273118496159879498574642958422568912499248774 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_sec_mubi/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2786856582 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/0.lc_ctrl_sec_mubi.2786856582 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_sec_mubi.2786856582 -covoverwrite' seed=2188757110188444339901868130506273118496159879498574642958422568912499248774 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2188757110188444339901868130506273118496159879498574642958422568912499248774 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_sec_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_mubi_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_mux 87783891264986473979301704882395646925960480548764848157132339654531219071942 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_sec_token_mux/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2807702470 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/0.lc_ctrl_sec_token_mux.2807702470 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_sec_token_mux.2807702470 -covoverwrite' seed=87783891264986473979301704882395646925960480548764848157132339654531219071942 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87783891264986473979301704882395646925960480548764848157132339654531219071942 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_sec_token_mux/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_mux_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_digest 58604147571207207360162974020586071362394776384129037571341940774810381642865 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_sec_token_digest/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1451420785 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/0.lc_ctrl_sec_token_digest.1451420785 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_sec_token_digest.1451420785 -covoverwrite' seed=58604147571207207360162974020586071362394776384129037571341940774810381642865 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58604147571207207360162974020586071362394776384129037571341940774810381642865 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_sec_token_digest/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_digest_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_stress_all_with_rand_reset 93358890619499651118200528932242331194749230474244979724193181535166950782007 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_stress_all_with_rand_reset/latest run_opts='+create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3862672439 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/0.lc_ctrl_stress_all_with_rand_reset.3862672439 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_stress_all_with_rand_reset.3862672439 -covoverwrite' seed=93358890619499651118200528932242331194749230474244979724193181535166950782007 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93358890619499651118200528932242331194749230474244979724193181535166950782007 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_cm 56488788717650416936081396296163529746615738857515081875215872863789851169451 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1849512619 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/0.lc_ctrl_sec_cm.1849512619 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_sec_cm.1849512619 -covoverwrite' seed=56488788717650416936081396296163529746615738857515081875215872863789851169451 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56488788717650416936081396296163529746615738857515081875215872863789851169451 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 6773744394867178946762760772356196225333471849448003430208977148300284402546 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3360955250 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3360955250 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.lc_ctrl_tl_errors.3360955250 -covoverwrite' seed=6773744394867178946762760772356196225333471849448003430208977148300284402546 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6773744394867178946762760772356196225333471849448003430208977148300284402546 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 12964590185596980984307444992211531406215447470563474823326396456853052603639 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4138745079 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.4138745079 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.lc_ctrl_tl_intg_err.4138745079 -covoverwrite' seed=12964590185596980984307444992211531406215447470563474823326396456853052603639 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12964590185596980984307444992211531406215447470563474823326396456853052603639 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_alert_test 18696478293229423924185945394039086670954007642516288009329191745742997801476 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4122462724 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/0.lc_ctrl_alert_test.4122462724 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 0.lc_ctrl_alert_test.4122462724 -covoverwrite' seed=18696478293229423924185945394039086670954007642516288009329191745742997801476 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18696478293229423924185945394039086670954007642516288009329191745742997801476 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_csr_hw_reset 709640108650125389007436476225967097236727367494853274430025742950503425216 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_csr_hw_reset/latest run_opts='+csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=309470400 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.309470400 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.lc_ctrl_csr_hw_reset.309470400 -covoverwrite' seed=709640108650125389007436476225967097236727367494853274430025742950503425216 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=709640108650125389007436476225967097236727367494853274430025742950503425216 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_csr_rw 72005021433151188047537255028800433145620247289363088513585832912423537758619 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3760083355 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/0.lc_ctrl_csr_rw.3760083355 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.lc_ctrl_csr_rw.3760083355 -covoverwrite' seed=72005021433151188047537255028800433145620247289363088513585832912423537758619 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72005021433151188047537255028800433145620247289363088513585832912423537758619 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_csr_bit_bash 109916045233145541924262120692927642682910974720913815773036260260320000818437 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_csr_bit_bash/latest run_opts='+csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2365013253 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2365013253 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.lc_ctrl_csr_bit_bash.2365013253 -covoverwrite' seed=109916045233145541924262120692927642682910974720913815773036260260320000818437 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109916045233145541924262120692927642682910974720913815773036260260320000818437 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_csr_aliasing 103572880343068055537993067447313305335567876986198748916314214984414284398304 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_csr_aliasing/latest run_opts='+csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3469917920 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.3469917920 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.lc_ctrl_csr_aliasing.3469917920 -covoverwrite' seed=103572880343068055537993067447313305335567876986198748916314214984414284398304 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103572880343068055537993067447313305335567876986198748916314214984414284398304 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_same_csr_outstanding 47192544051268769292086482590550825017216194918214555619915388500254356344240 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1515916720 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.1515916720 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.lc_ctrl_same_csr_outstanding.1515916720 -covoverwrite' seed=47192544051268769292086482590550825017216194918214555619915388500254356344240 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47192544051268769292086482590550825017216194918214555619915388500254356344240 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_csr_mem_rw_with_rand_reset 77289078168648518239565029706812866129871243451603714040055189211083168047018 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1229479850 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1229479850 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.lc_ctrl_csr_mem_rw_with_rand_reset.1229479850 -covoverwrite' seed=77289078168648518239565029706812866129871243451603714040055189211083168047018 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77289078168648518239565029706812866129871243451603714040055189211083168047018 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 101531713906431570662649749904581292977327649210282673520128568727752422794845 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3775997533 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/1.lc_ctrl_smoke.3775997533 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_smoke.3775997533 -covoverwrite' seed=101531713906431570662649749904581292977327649210282673520128568727752422794845 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101531713906431570662649749904581292977327649210282673520128568727752422794845 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_volatile_unlock_smoke 49457608091771570106079473386576474550350419095908786807461429449714663118846 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_volatile_unlock_smoke/latest run_opts='+en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2799130622 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/1.lc_ctrl_volatile_unlock_smoke.2799130622 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_volatile_unlock_smoke.2799130622 -covoverwrite' seed=49457608091771570106079473386576474550350419095908786807461429449714663118846 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49457608091771570106079473386576474550350419095908786807461429449714663118846 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_volatile_unlock_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_volatile_unlock_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 28779067429673219099324825370062644840177122652798566543500436385485108403419 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2880822491 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/1.lc_ctrl_state_failure.2880822491 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_state_failure.2880822491 -covoverwrite' seed=28779067429673219099324825370062644840177122652798566543500436385485108403419 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28779067429673219099324825370062644840177122652798566543500436385485108403419 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 56989187265184398632300340713086659774464157715680558822648924557750943000537 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3089803225 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/1.lc_ctrl_state_post_trans.3089803225 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_state_post_trans.3089803225 -covoverwrite' seed=56989187265184398632300340713086659774464157715680558822648924557750943000537 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56989187265184398632300340713086659774464157715680558822648924557750943000537 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 13350068215047499137179260554756850147568049752206634717961739548382613460348 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1046992252 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/1.lc_ctrl_prog_failure.1046992252 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_prog_failure.1046992252 -covoverwrite' seed=13350068215047499137179260554756850147568049752206634717961739548382613460348 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13350068215047499137179260554756850147568049752206634717961739548382613460348 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 95926662784175978148825104057174470080716271339472481486916333058101061247806 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2715968318 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/1.lc_ctrl_errors.2715968318 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_errors.2715968318 -covoverwrite' seed=95926662784175978148825104057174470080716271339472481486916333058101061247806 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95926662784175978148825104057174470080716271339472481486916333058101061247806 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 57453352311722921791421838427765948205301868315768213604322149973982049257896 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1205914024 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/1.lc_ctrl_security_escalation.1205914024 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_security_escalation.1205914024 -covoverwrite' seed=57453352311722921791421838427765948205301868315768213604322149973982049257896 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57453352311722921791421838427765948205301868315768213604322149973982049257896 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_regwen_during_op 15813763593724638966200506809759396355802077877083876160806644546470175535422 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_regwen_during_op/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=283341118 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/1.lc_ctrl_regwen_during_op.283341118 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_regwen_during_op.283341118 -covoverwrite' seed=15813763593724638966200506809759396355802077877083876160806644546470175535422 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15813763593724638966200506809759396355802077877083876160806644546470175535422 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_claim_transition_if 67481717418221353415562883085496304122886679870231361951087195511033462135587 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_claim_transition_if/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2341083939 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/1.lc_ctrl_claim_transition_if.2341083939 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_claim_transition_if.2341083939 -covoverwrite' seed=67481717418221353415562883085496304122886679870231361951087195511033462135587 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67481717418221353415562883085496304122886679870231361951087195511033462135587 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_claim_transition_if/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_claim_transition_if_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 83106221423659206362718683501769203296805494419163049375094057906611991100710 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2583182630 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/1.lc_ctrl_jtag_smoke.2583182630 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_jtag_smoke.2583182630 -covoverwrite' seed=83106221423659206362718683501769203296805494419163049375094057906611991100710 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83106221423659206362718683501769203296805494419163049375094057906611991100710 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 6225490429321578790843760817755248445111040812457630900725937232119678996239 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3292630799 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/1.lc_ctrl_jtag_state_failure.3292630799 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_jtag_state_failure.3292630799 -covoverwrite' seed=6225490429321578790843760817755248445111040812457630900725937232119678996239 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6225490429321578790843760817755248445111040812457630900725937232119678996239 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 40626944907228493519630573000591138151175133395555219508534948023212059701439 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=213692607 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/1.lc_ctrl_jtag_state_post_trans.213692607 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_jtag_state_post_trans.213692607 -covoverwrite' seed=40626944907228493519630573000591138151175133395555219508534948023212059701439 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40626944907228493519630573000591138151175133395555219508534948023212059701439 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 66196588370279513762592764780175107401035116674776770893800837565382329280557 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3230050349 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/1.lc_ctrl_jtag_prog_failure.3230050349 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_jtag_prog_failure.3230050349 -covoverwrite' seed=66196588370279513762592764780175107401035116674776770893800837565382329280557 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66196588370279513762592764780175107401035116674776770893800837565382329280557 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 56713890906753261138320667240935244232893473553644183425636497484823474688662 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=325800598 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/1.lc_ctrl_jtag_errors.325800598 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_jtag_errors.325800598 -covoverwrite' seed=56713890906753261138320667240935244232893473553644183425636497484823474688662 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56713890906753261138320667240935244232893473553644183425636497484823474688662 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 55208571328952394437267975189208505172174212353501955790638204421830240425332 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1606997364 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/1.lc_ctrl_jtag_access.1606997364 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_jtag_access.1606997364 -covoverwrite' seed=55208571328952394437267975189208505172174212353501955790638204421830240425332 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55208571328952394437267975189208505172174212353501955790638204421830240425332 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_priority 67786632065228293624714628050962405871108984277014652530400244337867115653182 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_jtag_priority/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1310386238 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/1.lc_ctrl_jtag_priority.1310386238 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_jtag_priority.1310386238 -covoverwrite' seed=67786632065228293624714628050962405871108984277014652530400244337867115653182 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67786632065228293624714628050962405871108984277014652530400244337867115653182 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_jtag_priority/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_priority_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_regwen_during_op 113273085717515234535801752902276436461861781012182789063422259387659722464085 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_jtag_regwen_during_op/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2719521621 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/1.lc_ctrl_jtag_regwen_during_op.2719521621 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_jtag_regwen_during_op.2719521621 -covoverwrite' seed=113273085717515234535801752902276436461861781012182789063422259387659722464085 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113273085717515234535801752902276436461861781012182789063422259387659722464085 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_jtag_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_hw_reset 22607366054987219764720140515431638449134469961333711162719344582598107614645 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_jtag_csr_hw_reset/latest run_opts='+csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1310215605 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.1310215605 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.lc_ctrl_jtag_csr_hw_reset.1310215605 -covoverwrite' seed=22607366054987219764720140515431638449134469961333711162719344582598107614645 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22607366054987219764720140515431638449134469961333711162719344582598107614645 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_jtag_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_rw 111021348944742863906535537775915088946575153620546154434988681271960212131577 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_jtag_csr_rw/latest run_opts='+csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=454086393 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.454086393 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.lc_ctrl_jtag_csr_rw.454086393 -covoverwrite' seed=111021348944742863906535537775915088946575153620546154434988681271960212131577 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111021348944742863906535537775915088946575153620546154434988681271960212131577 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_jtag_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_bit_bash 14542452088027491335296057937638299448180617274997506896897247479523106684215 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_jtag_csr_bit_bash/latest run_opts='+csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2673409335 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.2673409335 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.lc_ctrl_jtag_csr_bit_bash.2673409335 -covoverwrite' seed=14542452088027491335296057937638299448180617274997506896897247479523106684215 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=14542452088027491335296057937638299448180617274997506896897247479523106684215 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_jtag_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_aliasing 16940254363369374554279139651205110911236473869990772083639108341801434310152 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_jtag_csr_aliasing/latest run_opts='+csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1364026888 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.1364026888 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.lc_ctrl_jtag_csr_aliasing.1364026888 -covoverwrite' seed=16940254363369374554279139651205110911236473869990772083639108341801434310152 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16940254363369374554279139651205110911236473869990772083639108341801434310152 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_jtag_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_same_csr_outstanding 29738726318174226759593847528103904622246889280406733127926470323125169483837 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_jtag_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3480809533 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.3480809533 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.lc_ctrl_jtag_same_csr_outstanding.3480809533 -covoverwrite' seed=29738726318174226759593847528103904622246889280406733127926470323125169483837 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29738726318174226759593847528103904622246889280406733127926470323125169483837 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_jtag_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 8944793464589284992276444712107969242765000496463793008215448618273901079111 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1385916999 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1385916999 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1385916999 -covoverwrite' seed=8944793464589284992276444712107969242765000496463793008215448618273901079111 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8944793464589284992276444712107969242765000496463793008215448618273901079111 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_alert_test 80095342213951260299676702424115953178563067153740381149731824157881110612547 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_jtag_alert_test/latest run_opts='+run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4179348035 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.4179348035 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.lc_ctrl_jtag_alert_test.4179348035 -covoverwrite' seed=80095342213951260299676702424115953178563067153740381149731824157881110612547 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80095342213951260299676702424115953178563067153740381149731824157881110612547 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_jtag_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_mubi 22832377896143174318519020348325778125902846909781922742721074798094230925349 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_sec_mubi/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=48672805 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/1.lc_ctrl_sec_mubi.48672805 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_sec_mubi.48672805 -covoverwrite' seed=22832377896143174318519020348325778125902846909781922742721074798094230925349 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22832377896143174318519020348325778125902846909781922742721074798094230925349 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_sec_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_mubi_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_mux 72116113141848626439986782845464991465074156496792062138806115058265279632608 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_sec_token_mux/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3146716384 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/1.lc_ctrl_sec_token_mux.3146716384 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_sec_token_mux.3146716384 -covoverwrite' seed=72116113141848626439986782845464991465074156496792062138806115058265279632608 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72116113141848626439986782845464991465074156496792062138806115058265279632608 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_sec_token_mux/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_mux_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_digest 109156425584127107622890449429950266081509985168586746985802088025912480845438 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_sec_token_digest/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=324750974 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/1.lc_ctrl_sec_token_digest.324750974 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_sec_token_digest.324750974 -covoverwrite' seed=109156425584127107622890449429950266081509985168586746985802088025912480845438 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109156425584127107622890449429950266081509985168586746985802088025912480845438 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_sec_token_digest/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_digest_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_stress_all_with_rand_reset 44599270051787623787351771402568776044473847756025900869816479950764692902727 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_stress_all_with_rand_reset/latest run_opts='+create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1729270599 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/1.lc_ctrl_stress_all_with_rand_reset.1729270599 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_stress_all_with_rand_reset.1729270599 -covoverwrite' seed=44599270051787623787351771402568776044473847756025900869816479950764692902727 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44599270051787623787351771402568776044473847756025900869816479950764692902727 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_cm 65543345487028812327127894287423077643954337564479172485336472962990876864062 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1400843838 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/1.lc_ctrl_sec_cm.1400843838 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_sec_cm.1400843838 -covoverwrite' seed=65543345487028812327127894287423077643954337564479172485336472962990876864062 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65543345487028812327127894287423077643954337564479172485336472962990876864062 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 94906380979631661600099161904764779253171666821731218227410246179668870541212 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=301707164 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/1.lc_ctrl_tl_errors.301707164 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.lc_ctrl_tl_errors.301707164 -covoverwrite' seed=94906380979631661600099161904764779253171666821731218227410246179668870541212 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94906380979631661600099161904764779253171666821731218227410246179668870541212 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 2009787845032676426097455228657808206933828636323944006444290894949814607256 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1473748376 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.1473748376 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.lc_ctrl_tl_intg_err.1473748376 -covoverwrite' seed=2009787845032676426097455228657808206933828636323944006444290894949814607256 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2009787845032676426097455228657808206933828636323944006444290894949814607256 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_alert_test 60382191074356171702245605420027760631509630342383036842510972575564501867570 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2664684594 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/1.lc_ctrl_alert_test.2664684594 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 1.lc_ctrl_alert_test.2664684594 -covoverwrite' seed=60382191074356171702245605420027760631509630342383036842510972575564501867570 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60382191074356171702245605420027760631509630342383036842510972575564501867570 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_csr_rw 63385698165736829405968991396044496809226413574588404219936346350624144297250 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2891648290 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2891648290 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.lc_ctrl_csr_rw.2891648290 -covoverwrite' seed=63385698165736829405968991396044496809226413574588404219936346350624144297250 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63385698165736829405968991396044496809226413574588404219936346350624144297250 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_same_csr_outstanding 88383960013179631251139508327961450200737893695026641910296741689930423858057 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1036383113 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.1036383113 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.lc_ctrl_same_csr_outstanding.1036383113 -covoverwrite' seed=88383960013179631251139508327961450200737893695026641910296741689930423858057 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88383960013179631251139508327961450200737893695026641910296741689930423858057 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_csr_mem_rw_with_rand_reset 33486212356447306887236354782580050507145603171302851531893111929175029316979 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=777256307 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.777256307 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.lc_ctrl_csr_mem_rw_with_rand_reset.777256307 -covoverwrite' seed=33486212356447306887236354782580050507145603171302851531893111929175029316979 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33486212356447306887236354782580050507145603171302851531893111929175029316979 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 107998196600490056578339846363136775290804278453963936496880782541540542717941 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4022935541 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/2.lc_ctrl_smoke.4022935541 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_smoke.4022935541 -covoverwrite' seed=107998196600490056578339846363136775290804278453963936496880782541540542717941 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107998196600490056578339846363136775290804278453963936496880782541540542717941 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_volatile_unlock_smoke 44520106302620806549641109983068241717403502677512862486843341554168902521070 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_volatile_unlock_smoke/latest run_opts='+en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=889786606 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/2.lc_ctrl_volatile_unlock_smoke.889786606 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_volatile_unlock_smoke.889786606 -covoverwrite' seed=44520106302620806549641109983068241717403502677512862486843341554168902521070 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44520106302620806549641109983068241717403502677512862486843341554168902521070 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_volatile_unlock_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_volatile_unlock_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 19296684734175773418629242030900676010729658750744758243370520758287209959730 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3915747634 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/2.lc_ctrl_state_failure.3915747634 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_state_failure.3915747634 -covoverwrite' seed=19296684734175773418629242030900676010729658750744758243370520758287209959730 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19296684734175773418629242030900676010729658750744758243370520758287209959730 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 81826936760811100523787675844543337186817977374472027314772573723809277362357 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3757654197 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/2.lc_ctrl_state_post_trans.3757654197 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_state_post_trans.3757654197 -covoverwrite' seed=81826936760811100523787675844543337186817977374472027314772573723809277362357 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81826936760811100523787675844543337186817977374472027314772573723809277362357 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 92350603333943925246134070190207020174627064477587115463483542690332990693478 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2298404966 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/2.lc_ctrl_prog_failure.2298404966 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_prog_failure.2298404966 -covoverwrite' seed=92350603333943925246134070190207020174627064477587115463483542690332990693478 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92350603333943925246134070190207020174627064477587115463483542690332990693478 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 21634058404896396197520242798853174786591496985409884263244184796083376333529 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=657957593 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/2.lc_ctrl_errors.657957593 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_errors.657957593 -covoverwrite' seed=21634058404896396197520242798853174786591496985409884263244184796083376333529 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21634058404896396197520242798853174786591496985409884263244184796083376333529 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 86080121617401240620155000948492955751845793926456407754389129593095134886159 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2249177359 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/2.lc_ctrl_security_escalation.2249177359 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_security_escalation.2249177359 -covoverwrite' seed=86080121617401240620155000948492955751845793926456407754389129593095134886159 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86080121617401240620155000948492955751845793926456407754389129593095134886159 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_regwen_during_op 104898798941814047621914610221741770706350768231919977336457033234603879662594 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_regwen_during_op/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1124303874 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/2.lc_ctrl_regwen_during_op.1124303874 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_regwen_during_op.1124303874 -covoverwrite' seed=104898798941814047621914610221741770706350768231919977336457033234603879662594 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104898798941814047621914610221741770706350768231919977336457033234603879662594 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_claim_transition_if 63807628222141296305766536734556214837855613793862846921030796910522814944904 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_claim_transition_if/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4286568072 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/2.lc_ctrl_claim_transition_if.4286568072 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_claim_transition_if.4286568072 -covoverwrite' seed=63807628222141296305766536734556214837855613793862846921030796910522814944904 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63807628222141296305766536734556214837855613793862846921030796910522814944904 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_claim_transition_if/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_claim_transition_if_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 98320394885427710417093618788430009566991965897435089042303702289284477484972 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=963903404 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/2.lc_ctrl_jtag_smoke.963903404 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_jtag_smoke.963903404 -covoverwrite' seed=98320394885427710417093618788430009566991965897435089042303702289284477484972 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98320394885427710417093618788430009566991965897435089042303702289284477484972 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 8636412707021175995313963680019317010954349842971798772961809845311792685637 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1129259589 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/2.lc_ctrl_jtag_state_failure.1129259589 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_jtag_state_failure.1129259589 -covoverwrite' seed=8636412707021175995313963680019317010954349842971798772961809845311792685637 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8636412707021175995313963680019317010954349842971798772961809845311792685637 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 89151604936561069791404631676303895856838505497502145182520532852593667131577 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=84723897 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/2.lc_ctrl_jtag_state_post_trans.84723897 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_jtag_state_post_trans.84723897 -covoverwrite' seed=89151604936561069791404631676303895856838505497502145182520532852593667131577 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89151604936561069791404631676303895856838505497502145182520532852593667131577 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 89684249830123877990413372889034087459258835571304101494942600918770763522294 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2112970998 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/2.lc_ctrl_jtag_prog_failure.2112970998 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_jtag_prog_failure.2112970998 -covoverwrite' seed=89684249830123877990413372889034087459258835571304101494942600918770763522294 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89684249830123877990413372889034087459258835571304101494942600918770763522294 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 112795678972326422542344695535222966893829298039963680000652792823046009414478 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2379375438 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/2.lc_ctrl_jtag_errors.2379375438 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_jtag_errors.2379375438 -covoverwrite' seed=112795678972326422542344695535222966893829298039963680000652792823046009414478 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112795678972326422542344695535222966893829298039963680000652792823046009414478 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 88502884469347819266019130195631846002978412338529324145265036602821875541172 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2664375476 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/2.lc_ctrl_jtag_access.2664375476 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_jtag_access.2664375476 -covoverwrite' seed=88502884469347819266019130195631846002978412338529324145265036602821875541172 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88502884469347819266019130195631846002978412338529324145265036602821875541172 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_priority 72487518030999607437937875900409404401557857260525121756161037456909410564292 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_jtag_priority/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3945855172 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/2.lc_ctrl_jtag_priority.3945855172 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_jtag_priority.3945855172 -covoverwrite' seed=72487518030999607437937875900409404401557857260525121756161037456909410564292 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72487518030999607437937875900409404401557857260525121756161037456909410564292 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_jtag_priority/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_priority_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_regwen_during_op 18524834279432225780442717274804833327667847436604613606018494955890039571799 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_jtag_regwen_during_op/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=504612183 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/2.lc_ctrl_jtag_regwen_during_op.504612183 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_jtag_regwen_during_op.504612183 -covoverwrite' seed=18524834279432225780442717274804833327667847436604613606018494955890039571799 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18524834279432225780442717274804833327667847436604613606018494955890039571799 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_jtag_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_hw_reset 56318483210524517491091530962987506426297560523649243064185618399048476571721 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_jtag_csr_hw_reset/latest run_opts='+csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3626416201 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.3626416201 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.lc_ctrl_jtag_csr_hw_reset.3626416201 -covoverwrite' seed=56318483210524517491091530962987506426297560523649243064185618399048476571721 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56318483210524517491091530962987506426297560523649243064185618399048476571721 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_jtag_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_rw 105468083335164539278955476446329299612075847872453845499687400516969877270780 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_jtag_csr_rw/latest run_opts='+csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4780284 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.4780284 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.lc_ctrl_jtag_csr_rw.4780284 -covoverwrite' seed=105468083335164539278955476446329299612075847872453845499687400516969877270780 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105468083335164539278955476446329299612075847872453845499687400516969877270780 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_jtag_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_bit_bash 6824072152093099906353259654191370950000109792120066808807336169525887588871 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_jtag_csr_bit_bash/latest run_opts='+csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2920503815 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.2920503815 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.lc_ctrl_jtag_csr_bit_bash.2920503815 -covoverwrite' seed=6824072152093099906353259654191370950000109792120066808807336169525887588871 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6824072152093099906353259654191370950000109792120066808807336169525887588871 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_jtag_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_aliasing 18403312510333599314868056018475158314388525905236409715771799130819488187561 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_jtag_csr_aliasing/latest run_opts='+csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1421149353 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.1421149353 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.lc_ctrl_jtag_csr_aliasing.1421149353 -covoverwrite' seed=18403312510333599314868056018475158314388525905236409715771799130819488187561 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18403312510333599314868056018475158314388525905236409715771799130819488187561 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_jtag_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_same_csr_outstanding 78947573851854522127989555693565018007435924216378052014198355999216194702082 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_jtag_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2377272066 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.2377272066 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.lc_ctrl_jtag_same_csr_outstanding.2377272066 -covoverwrite' seed=78947573851854522127989555693565018007435924216378052014198355999216194702082 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78947573851854522127989555693565018007435924216378052014198355999216194702082 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_jtag_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 26340193612175561593504123819364206119783072104267288496130752977698200960272 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2413247760 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2413247760 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2413247760 -covoverwrite' seed=26340193612175561593504123819364206119783072104267288496130752977698200960272 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26340193612175561593504123819364206119783072104267288496130752977698200960272 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_alert_test 73358597314083159065863009778879846039914974372381716596908757996960688258922 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_jtag_alert_test/latest run_opts='+run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3587587946 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.3587587946 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.lc_ctrl_jtag_alert_test.3587587946 -covoverwrite' seed=73358597314083159065863009778879846039914974372381716596908757996960688258922 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73358597314083159065863009778879846039914974372381716596908757996960688258922 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_jtag_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_mubi 107784027692978865641752857119894550232734370355551852099159468396313074216569 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_sec_mubi/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=165686905 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/2.lc_ctrl_sec_mubi.165686905 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_sec_mubi.165686905 -covoverwrite' seed=107784027692978865641752857119894550232734370355551852099159468396313074216569 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107784027692978865641752857119894550232734370355551852099159468396313074216569 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_sec_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_mubi_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_mux 20848180462246363296682306642449653387812403772733006130332684304220364097808 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_sec_token_mux/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1175079184 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/2.lc_ctrl_sec_token_mux.1175079184 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_sec_token_mux.1175079184 -covoverwrite' seed=20848180462246363296682306642449653387812403772733006130332684304220364097808 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20848180462246363296682306642449653387812403772733006130332684304220364097808 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_sec_token_mux/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_mux_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_digest 84610673207535910918875867001365402587156445654990634475292182240939164446826 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_sec_token_digest/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2505977962 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/2.lc_ctrl_sec_token_digest.2505977962 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_sec_token_digest.2505977962 -covoverwrite' seed=84610673207535910918875867001365402587156445654990634475292182240939164446826 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84610673207535910918875867001365402587156445654990634475292182240939164446826 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_sec_token_digest/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_digest_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_stress_all_with_rand_reset 72460644188185643951834363370635471567213667392494162550103261837740179804767 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_stress_all_with_rand_reset/latest run_opts='+create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3409007199 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/2.lc_ctrl_stress_all_with_rand_reset.3409007199 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_stress_all_with_rand_reset.3409007199 -covoverwrite' seed=72460644188185643951834363370635471567213667392494162550103261837740179804767 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72460644188185643951834363370635471567213667392494162550103261837740179804767 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_cm 34130690470659479703091836068451821164788588013580438251414186560328546800474 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2966311770 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/2.lc_ctrl_sec_cm.2966311770 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_sec_cm.2966311770 -covoverwrite' seed=34130690470659479703091836068451821164788588013580438251414186560328546800474 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34130690470659479703091836068451821164788588013580438251414186560328546800474 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 105115540080955286583994097067899537669100728826084782123845223510415859707964 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3873370172 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/2.lc_ctrl_tl_errors.3873370172 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.lc_ctrl_tl_errors.3873370172 -covoverwrite' seed=105115540080955286583994097067899537669100728826084782123845223510415859707964 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105115540080955286583994097067899537669100728826084782123845223510415859707964 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 62950854062968633618311925651605588971656039509281750532577076283478451927428 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3862935940 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.3862935940 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.lc_ctrl_tl_intg_err.3862935940 -covoverwrite' seed=62950854062968633618311925651605588971656039509281750532577076283478451927428 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62950854062968633618311925651605588971656039509281750532577076283478451927428 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_alert_test 42974082083555354999888747149723186861492767399674338059214643037568250979686 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1196205414 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/2.lc_ctrl_alert_test.1196205414 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 2.lc_ctrl_alert_test.1196205414 -covoverwrite' seed=42974082083555354999888747149723186861492767399674338059214643037568250979686 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42974082083555354999888747149723186861492767399674338059214643037568250979686 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_csr_rw 109890999521018655973777359660812300228362277201858482237297907639356906773202 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3954940626 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/2.lc_ctrl_csr_rw.3954940626 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.lc_ctrl_csr_rw.3954940626 -covoverwrite' seed=109890999521018655973777359660812300228362277201858482237297907639356906773202 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109890999521018655973777359660812300228362277201858482237297907639356906773202 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_same_csr_outstanding 15352732434680394048220829712186552289091673463308150621820823695818708590688 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=294232160 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.294232160 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.lc_ctrl_same_csr_outstanding.294232160 -covoverwrite' seed=15352732434680394048220829712186552289091673463308150621820823695818708590688 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15352732434680394048220829712186552289091673463308150621820823695818708590688 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_csr_mem_rw_with_rand_reset 37332896249276768538427813580872309919784637156083826683689652688426543781053 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2687145149 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.2687145149 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.lc_ctrl_csr_mem_rw_with_rand_reset.2687145149 -covoverwrite' seed=37332896249276768538427813580872309919784637156083826683689652688426543781053 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37332896249276768538427813580872309919784637156083826683689652688426543781053 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 74048798381918784059569224462797032802347480906141222076592388916139691900244 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=914390356 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/3.lc_ctrl_smoke.914390356 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_smoke.914390356 -covoverwrite' seed=74048798381918784059569224462797032802347480906141222076592388916139691900244 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74048798381918784059569224462797032802347480906141222076592388916139691900244 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_volatile_unlock_smoke 90097171175800635949427515931954062673840709829581385453958804189023025730013 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_volatile_unlock_smoke/latest run_opts='+en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=470782429 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/3.lc_ctrl_volatile_unlock_smoke.470782429 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_volatile_unlock_smoke.470782429 -covoverwrite' seed=90097171175800635949427515931954062673840709829581385453958804189023025730013 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90097171175800635949427515931954062673840709829581385453958804189023025730013 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_volatile_unlock_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_volatile_unlock_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 49268253008602920799228306622688735443361849397245390287316945617023192330196 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3955290068 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/3.lc_ctrl_state_failure.3955290068 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_state_failure.3955290068 -covoverwrite' seed=49268253008602920799228306622688735443361849397245390287316945617023192330196 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49268253008602920799228306622688735443361849397245390287316945617023192330196 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 20816598380390830415081739634435249090168192150442230131288705276168959974229 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1372085077 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/3.lc_ctrl_state_post_trans.1372085077 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_state_post_trans.1372085077 -covoverwrite' seed=20816598380390830415081739634435249090168192150442230131288705276168959974229 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20816598380390830415081739634435249090168192150442230131288705276168959974229 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 35699002717249796370856233695216556758421801100307935612108097989088707422030 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2884970318 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/3.lc_ctrl_prog_failure.2884970318 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_prog_failure.2884970318 -covoverwrite' seed=35699002717249796370856233695216556758421801100307935612108097989088707422030 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35699002717249796370856233695216556758421801100307935612108097989088707422030 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 67654954253033370422848444663663595461349512982369455726918089933939227103194 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2654605274 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/3.lc_ctrl_errors.2654605274 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_errors.2654605274 -covoverwrite' seed=67654954253033370422848444663663595461349512982369455726918089933939227103194 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67654954253033370422848444663663595461349512982369455726918089933939227103194 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 90653145018698588884664069607369730417944008541447802287739372747453600892206 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=266077486 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/3.lc_ctrl_security_escalation.266077486 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_security_escalation.266077486 -covoverwrite' seed=90653145018698588884664069607369730417944008541447802287739372747453600892206 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90653145018698588884664069607369730417944008541447802287739372747453600892206 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_regwen_during_op 71840687353789481180032044759175087716343370651173987769708998734166439036626 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_regwen_during_op/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3251963602 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/3.lc_ctrl_regwen_during_op.3251963602 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_regwen_during_op.3251963602 -covoverwrite' seed=71840687353789481180032044759175087716343370651173987769708998734166439036626 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71840687353789481180032044759175087716343370651173987769708998734166439036626 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_claim_transition_if 6134616138710678839026649707551694926219329498682122009978634365134013713281 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_claim_transition_if/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=275762049 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/3.lc_ctrl_claim_transition_if.275762049 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_claim_transition_if.275762049 -covoverwrite' seed=6134616138710678839026649707551694926219329498682122009978634365134013713281 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6134616138710678839026649707551694926219329498682122009978634365134013713281 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_claim_transition_if/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_claim_transition_if_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 74191453368683859503778116830940594828884082566166402650997487278560094330320 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3049922000 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/3.lc_ctrl_jtag_smoke.3049922000 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_jtag_smoke.3049922000 -covoverwrite' seed=74191453368683859503778116830940594828884082566166402650997487278560094330320 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74191453368683859503778116830940594828884082566166402650997487278560094330320 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 58085464975978313991758470262816829862370393276279836664061277803596665367130 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=644131418 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/3.lc_ctrl_jtag_state_failure.644131418 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_jtag_state_failure.644131418 -covoverwrite' seed=58085464975978313991758470262816829862370393276279836664061277803596665367130 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58085464975978313991758470262816829862370393276279836664061277803596665367130 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 84529102835595148327741097496015897107250686373470002399391849972133125289317 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4010145125 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/3.lc_ctrl_jtag_state_post_trans.4010145125 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_jtag_state_post_trans.4010145125 -covoverwrite' seed=84529102835595148327741097496015897107250686373470002399391849972133125289317 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84529102835595148327741097496015897107250686373470002399391849972133125289317 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 51650354185018121163251874661800962596682971007100056091186578638910813076058 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1707309658 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/3.lc_ctrl_jtag_prog_failure.1707309658 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_jtag_prog_failure.1707309658 -covoverwrite' seed=51650354185018121163251874661800962596682971007100056091186578638910813076058 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51650354185018121163251874661800962596682971007100056091186578638910813076058 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 83321972564351769359450231095971552917186444173004425449653144294718180776088 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3050657944 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/3.lc_ctrl_jtag_errors.3050657944 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_jtag_errors.3050657944 -covoverwrite' seed=83321972564351769359450231095971552917186444173004425449653144294718180776088 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83321972564351769359450231095971552917186444173004425449653144294718180776088 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 61301900016420717168512978372191060622431322874443461285273118955719640778382 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=66356878 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/3.lc_ctrl_jtag_access.66356878 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_jtag_access.66356878 -covoverwrite' seed=61301900016420717168512978372191060622431322874443461285273118955719640778382 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61301900016420717168512978372191060622431322874443461285273118955719640778382 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_priority 11973933873034968276823533090072583820403296082126675898959447195478409505160 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_jtag_priority/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1134455176 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/3.lc_ctrl_jtag_priority.1134455176 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_jtag_priority.1134455176 -covoverwrite' seed=11973933873034968276823533090072583820403296082126675898959447195478409505160 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11973933873034968276823533090072583820403296082126675898959447195478409505160 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_jtag_priority/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_priority_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_regwen_during_op 111743436369863602168960173599714384530625549708941496876509755486640297991986 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_jtag_regwen_during_op/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=282582834 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/3.lc_ctrl_jtag_regwen_during_op.282582834 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_jtag_regwen_during_op.282582834 -covoverwrite' seed=111743436369863602168960173599714384530625549708941496876509755486640297991986 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111743436369863602168960173599714384530625549708941496876509755486640297991986 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_jtag_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_hw_reset 46743728500075386956518784917665645125204056907129497715139849114354351517250 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_jtag_csr_hw_reset/latest run_opts='+csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2382016066 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.2382016066 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.lc_ctrl_jtag_csr_hw_reset.2382016066 -covoverwrite' seed=46743728500075386956518784917665645125204056907129497715139849114354351517250 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46743728500075386956518784917665645125204056907129497715139849114354351517250 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_jtag_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_rw 25596905849268060349671126210945291678895703066057002616335237023375201463916 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_jtag_csr_rw/latest run_opts='+csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=691334764 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.691334764 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.lc_ctrl_jtag_csr_rw.691334764 -covoverwrite' seed=25596905849268060349671126210945291678895703066057002616335237023375201463916 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25596905849268060349671126210945291678895703066057002616335237023375201463916 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_jtag_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_bit_bash 1627795936918493090356724172090872807439677506358750348299110579490854739852 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_jtag_csr_bit_bash/latest run_opts='+csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3374522252 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.3374522252 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.lc_ctrl_jtag_csr_bit_bash.3374522252 -covoverwrite' seed=1627795936918493090356724172090872807439677506358750348299110579490854739852 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1627795936918493090356724172090872807439677506358750348299110579490854739852 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_jtag_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_aliasing 82598167428986886494459135640394930249015365529171556835359962050141320905687 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_jtag_csr_aliasing/latest run_opts='+csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1722287063 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.1722287063 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.lc_ctrl_jtag_csr_aliasing.1722287063 -covoverwrite' seed=82598167428986886494459135640394930249015365529171556835359962050141320905687 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82598167428986886494459135640394930249015365529171556835359962050141320905687 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_jtag_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_same_csr_outstanding 63433876455092914304219453384626100931226995895578782397602452599004704376623 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_jtag_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3529606959 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3529606959 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.lc_ctrl_jtag_same_csr_outstanding.3529606959 -covoverwrite' seed=63433876455092914304219453384626100931226995895578782397602452599004704376623 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63433876455092914304219453384626100931226995895578782397602452599004704376623 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_jtag_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 111220985350413084500997392584959807843886204561097038365363099051023168303377 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1300361489 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1300361489 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1300361489 -covoverwrite' seed=111220985350413084500997392584959807843886204561097038365363099051023168303377 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111220985350413084500997392584959807843886204561097038365363099051023168303377 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_alert_test 19744628985870765414399864453305950524899516804275840221728323026410966897661 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_jtag_alert_test/latest run_opts='+run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3812643837 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3812643837 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.lc_ctrl_jtag_alert_test.3812643837 -covoverwrite' seed=19744628985870765414399864453305950524899516804275840221728323026410966897661 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19744628985870765414399864453305950524899516804275840221728323026410966897661 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_jtag_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_mubi 108779571754642640526259160906206532832957834249872534557662867318322266768803 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_sec_mubi/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3466462627 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/3.lc_ctrl_sec_mubi.3466462627 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_sec_mubi.3466462627 -covoverwrite' seed=108779571754642640526259160906206532832957834249872534557662867318322266768803 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108779571754642640526259160906206532832957834249872534557662867318322266768803 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_sec_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_mubi_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_mux 104950872469379680160583674125685253843044578269962978412878097512870542367240 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_sec_token_mux/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3995916808 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/3.lc_ctrl_sec_token_mux.3995916808 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_sec_token_mux.3995916808 -covoverwrite' seed=104950872469379680160583674125685253843044578269962978412878097512870542367240 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104950872469379680160583674125685253843044578269962978412878097512870542367240 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_sec_token_mux/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_mux_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_digest 104687100604824620334828900560689099792970812234104856796528937615618383513030 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_sec_token_digest/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2103150022 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/3.lc_ctrl_sec_token_digest.2103150022 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_sec_token_digest.2103150022 -covoverwrite' seed=104687100604824620334828900560689099792970812234104856796528937615618383513030 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104687100604824620334828900560689099792970812234104856796528937615618383513030 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_sec_token_digest/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_digest_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_stress_all_with_rand_reset 91220853393507369293180195727627835791622053415667817059839328529778981347949 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_stress_all_with_rand_reset/latest run_opts='+create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3605930605 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/3.lc_ctrl_stress_all_with_rand_reset.3605930605 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_stress_all_with_rand_reset.3605930605 -covoverwrite' seed=91220853393507369293180195727627835791622053415667817059839328529778981347949 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91220853393507369293180195727627835791622053415667817059839328529778981347949 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_cm 23829037432728680501097560838214377235015089523083717097231590636245613056723 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2249757395 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/3.lc_ctrl_sec_cm.2249757395 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_sec_cm.2249757395 -covoverwrite' seed=23829037432728680501097560838214377235015089523083717097231590636245613056723 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23829037432728680501097560838214377235015089523083717097231590636245613056723 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 103835713377296714334104951947127977823738593067975335945392072678042505735365 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2403757253 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/3.lc_ctrl_tl_errors.2403757253 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.lc_ctrl_tl_errors.2403757253 -covoverwrite' seed=103835713377296714334104951947127977823738593067975335945392072678042505735365 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103835713377296714334104951947127977823738593067975335945392072678042505735365 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 39999567834550551273934862141642735759480618162852154134822621029427196935822 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3220913806 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.3220913806 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.lc_ctrl_tl_intg_err.3220913806 -covoverwrite' seed=39999567834550551273934862141642735759480618162852154134822621029427196935822 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39999567834550551273934862141642735759480618162852154134822621029427196935822 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_alert_test 63933195373930016821283309262669144131706231207824566068802784482434242121435 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=424742619 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/3.lc_ctrl_alert_test.424742619 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 3.lc_ctrl_alert_test.424742619 -covoverwrite' seed=63933195373930016821283309262669144131706231207824566068802784482434242121435 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63933195373930016821283309262669144131706231207824566068802784482434242121435 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_csr_rw 46294139679194949543906202603076535103392515655129745161809657204878388012164 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=127706244 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/3.lc_ctrl_csr_rw.127706244 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.lc_ctrl_csr_rw.127706244 -covoverwrite' seed=46294139679194949543906202603076535103392515655129745161809657204878388012164 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46294139679194949543906202603076535103392515655129745161809657204878388012164 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_same_csr_outstanding 16575614607402469641988984665450510147776006129316843348813822607207085949527 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2233254487 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.2233254487 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.lc_ctrl_same_csr_outstanding.2233254487 -covoverwrite' seed=16575614607402469641988984665450510147776006129316843348813822607207085949527 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16575614607402469641988984665450510147776006129316843348813822607207085949527 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_csr_mem_rw_with_rand_reset 39930194985615226564524371830478857741696247752107573583364519310774718143983 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1152097775 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.1152097775 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.lc_ctrl_csr_mem_rw_with_rand_reset.1152097775 -covoverwrite' seed=39930194985615226564524371830478857741696247752107573583364519310774718143983 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39930194985615226564524371830478857741696247752107573583364519310774718143983 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 6161314160930582500553103565361632255125658908472236939962841694504464309680 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=44457392 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/4.lc_ctrl_smoke.44457392 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_smoke.44457392 -covoverwrite' seed=6161314160930582500553103565361632255125658908472236939962841694504464309680 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6161314160930582500553103565361632255125658908472236939962841694504464309680 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_volatile_unlock_smoke 80123043582443374562140314327810570707948223018997527397320093731594974349871 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_volatile_unlock_smoke/latest run_opts='+en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2295155247 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/4.lc_ctrl_volatile_unlock_smoke.2295155247 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_volatile_unlock_smoke.2295155247 -covoverwrite' seed=80123043582443374562140314327810570707948223018997527397320093731594974349871 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80123043582443374562140314327810570707948223018997527397320093731594974349871 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_volatile_unlock_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_volatile_unlock_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 82390926729751774212759731911028535508220816881094878766585508256383759590214 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1024762694 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/4.lc_ctrl_state_failure.1024762694 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_state_failure.1024762694 -covoverwrite' seed=82390926729751774212759731911028535508220816881094878766585508256383759590214 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82390926729751774212759731911028535508220816881094878766585508256383759590214 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 85434009450259657662684220734739479896155972923397361436215082241894509348511 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2321450655 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/4.lc_ctrl_state_post_trans.2321450655 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_state_post_trans.2321450655 -covoverwrite' seed=85434009450259657662684220734739479896155972923397361436215082241894509348511 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85434009450259657662684220734739479896155972923397361436215082241894509348511 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 60442525375966272900503535103451188091369354544058840419224932117819758726928 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2665991952 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/4.lc_ctrl_prog_failure.2665991952 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_prog_failure.2665991952 -covoverwrite' seed=60442525375966272900503535103451188091369354544058840419224932117819758726928 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60442525375966272900503535103451188091369354544058840419224932117819758726928 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 83856130984185315793074229941688155794112371552789838068516527118990614925603 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1946620195 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/4.lc_ctrl_errors.1946620195 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_errors.1946620195 -covoverwrite' seed=83856130984185315793074229941688155794112371552789838068516527118990614925603 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83856130984185315793074229941688155794112371552789838068516527118990614925603 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 33787278547095556762835210407913000375083146774996801305460028481999973406923 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1211652299 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/4.lc_ctrl_security_escalation.1211652299 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_security_escalation.1211652299 -covoverwrite' seed=33787278547095556762835210407913000375083146774996801305460028481999973406923 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33787278547095556762835210407913000375083146774996801305460028481999973406923 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_regwen_during_op 84258754264118318327675818116402003340609733140429831714848511634244694944847 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_regwen_during_op/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1316465743 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/4.lc_ctrl_regwen_during_op.1316465743 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_regwen_during_op.1316465743 -covoverwrite' seed=84258754264118318327675818116402003340609733140429831714848511634244694944847 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84258754264118318327675818116402003340609733140429831714848511634244694944847 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_claim_transition_if 18785924729781577661991060148769159460454541450456109719704326205247905684560 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_claim_transition_if/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3098106960 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/4.lc_ctrl_claim_transition_if.3098106960 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_claim_transition_if.3098106960 -covoverwrite' seed=18785924729781577661991060148769159460454541450456109719704326205247905684560 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18785924729781577661991060148769159460454541450456109719704326205247905684560 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_claim_transition_if/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_claim_transition_if_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 12642791186965769619848959124736306131862371801746337368367914967169765706080 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1315146080 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/4.lc_ctrl_jtag_smoke.1315146080 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_jtag_smoke.1315146080 -covoverwrite' seed=12642791186965769619848959124736306131862371801746337368367914967169765706080 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12642791186965769619848959124736306131862371801746337368367914967169765706080 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 58390173578797966674354379670942125985186494134221957323833625697609392211038 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1441154142 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/4.lc_ctrl_jtag_state_failure.1441154142 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_jtag_state_failure.1441154142 -covoverwrite' seed=58390173578797966674354379670942125985186494134221957323833625697609392211038 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58390173578797966674354379670942125985186494134221957323833625697609392211038 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 100117897140257625420879572549981146194597898692898566877874040797052478419617 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3898864289 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/4.lc_ctrl_jtag_state_post_trans.3898864289 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_jtag_state_post_trans.3898864289 -covoverwrite' seed=100117897140257625420879572549981146194597898692898566877874040797052478419617 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100117897140257625420879572549981146194597898692898566877874040797052478419617 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 72958426585848869843387576967954567746577666445377750583682635711312752584911 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2769856719 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/4.lc_ctrl_jtag_prog_failure.2769856719 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_jtag_prog_failure.2769856719 -covoverwrite' seed=72958426585848869843387576967954567746577666445377750583682635711312752584911 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72958426585848869843387576967954567746577666445377750583682635711312752584911 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 3415021647436777904885947335096875907699829672794202150646074965714057758785 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3872852033 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/4.lc_ctrl_jtag_errors.3872852033 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_jtag_errors.3872852033 -covoverwrite' seed=3415021647436777904885947335096875907699829672794202150646074965714057758785 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3415021647436777904885947335096875907699829672794202150646074965714057758785 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 82971373507902205945180348562536813860930198996153354770486274748150810778635 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2061343755 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/4.lc_ctrl_jtag_access.2061343755 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_jtag_access.2061343755 -covoverwrite' seed=82971373507902205945180348562536813860930198996153354770486274748150810778635 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82971373507902205945180348562536813860930198996153354770486274748150810778635 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_priority 15459049659764034330870761914898382269943464114974688627878507098937618028618 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_jtag_priority/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1166760010 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/4.lc_ctrl_jtag_priority.1166760010 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_jtag_priority.1166760010 -covoverwrite' seed=15459049659764034330870761914898382269943464114974688627878507098937618028618 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15459049659764034330870761914898382269943464114974688627878507098937618028618 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_jtag_priority/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_priority_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_regwen_during_op 60164323498214248984690108121030200981260408849478121040682304612771458436745 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_jtag_regwen_during_op/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3879456393 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/4.lc_ctrl_jtag_regwen_during_op.3879456393 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_jtag_regwen_during_op.3879456393 -covoverwrite' seed=60164323498214248984690108121030200981260408849478121040682304612771458436745 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60164323498214248984690108121030200981260408849478121040682304612771458436745 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_jtag_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_hw_reset 48933919500006391848574438184815608809872140875587920351151677273207391364627 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_jtag_csr_hw_reset/latest run_opts='+csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=399484435 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.399484435 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.lc_ctrl_jtag_csr_hw_reset.399484435 -covoverwrite' seed=48933919500006391848574438184815608809872140875587920351151677273207391364627 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48933919500006391848574438184815608809872140875587920351151677273207391364627 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_jtag_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_rw 74885338172186759471034972528104549673346323819624992970571420578560971644672 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_jtag_csr_rw/latest run_opts='+csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=354950912 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.354950912 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.lc_ctrl_jtag_csr_rw.354950912 -covoverwrite' seed=74885338172186759471034972528104549673346323819624992970571420578560971644672 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74885338172186759471034972528104549673346323819624992970571420578560971644672 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_jtag_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_bit_bash 8512983605254124034544792533862855229433856231452619276218427392320820561971 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_jtag_csr_bit_bash/latest run_opts='+csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1625638963 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.1625638963 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.lc_ctrl_jtag_csr_bit_bash.1625638963 -covoverwrite' seed=8512983605254124034544792533862855229433856231452619276218427392320820561971 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8512983605254124034544792533862855229433856231452619276218427392320820561971 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_jtag_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_aliasing 56467141692892684371426567536694271947583066689628658597419824732692858377358 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_jtag_csr_aliasing/latest run_opts='+csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=239441038 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.239441038 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.lc_ctrl_jtag_csr_aliasing.239441038 -covoverwrite' seed=56467141692892684371426567536694271947583066689628658597419824732692858377358 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56467141692892684371426567536694271947583066689628658597419824732692858377358 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_jtag_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_same_csr_outstanding 34558776612596612414526848093723286578535307588708510282949644824520239696008 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_jtag_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=927811720 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.927811720 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.lc_ctrl_jtag_same_csr_outstanding.927811720 -covoverwrite' seed=34558776612596612414526848093723286578535307588708510282949644824520239696008 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34558776612596612414526848093723286578535307588708510282949644824520239696008 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_jtag_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 105191221542802633758306539104322685771384734406463719603431925939526670611116 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1978528428 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1978528428 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1978528428 -covoverwrite' seed=105191221542802633758306539104322685771384734406463719603431925939526670611116 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105191221542802633758306539104322685771384734406463719603431925939526670611116 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_alert_test 55857204016371557295301477930229109473015563922983511320004301839320455543913 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_jtag_alert_test/latest run_opts='+run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3750722665 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.3750722665 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.lc_ctrl_jtag_alert_test.3750722665 -covoverwrite' seed=55857204016371557295301477930229109473015563922983511320004301839320455543913 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55857204016371557295301477930229109473015563922983511320004301839320455543913 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_jtag_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_mubi 33585652562913210407235269944023096142729935371695340687051557717629992764104 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_sec_mubi/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4177330888 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/4.lc_ctrl_sec_mubi.4177330888 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_sec_mubi.4177330888 -covoverwrite' seed=33585652562913210407235269944023096142729935371695340687051557717629992764104 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33585652562913210407235269944023096142729935371695340687051557717629992764104 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_sec_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_mubi_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_mux 79188930605773211459578353606481971219460350382520771070880913957642375985753 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_sec_token_mux/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=269679193 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/4.lc_ctrl_sec_token_mux.269679193 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_sec_token_mux.269679193 -covoverwrite' seed=79188930605773211459578353606481971219460350382520771070880913957642375985753 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79188930605773211459578353606481971219460350382520771070880913957642375985753 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_sec_token_mux/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_mux_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_digest 24121373181956226992954958826837998603482824637163305113549345288077221257353 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_sec_token_digest/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1258774665 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/4.lc_ctrl_sec_token_digest.1258774665 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_sec_token_digest.1258774665 -covoverwrite' seed=24121373181956226992954958826837998603482824637163305113549345288077221257353 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24121373181956226992954958826837998603482824637163305113549345288077221257353 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_sec_token_digest/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_digest_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_stress_all_with_rand_reset 66232251689665532608229634430147062925938476705643394951697972738034587842721 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_stress_all_with_rand_reset/latest run_opts='+create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=952285345 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/4.lc_ctrl_stress_all_with_rand_reset.952285345 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_stress_all_with_rand_reset.952285345 -covoverwrite' seed=66232251689665532608229634430147062925938476705643394951697972738034587842721 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66232251689665532608229634430147062925938476705643394951697972738034587842721 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_cm 27720704396334197277468985510005004511905940398774274223145551493021972195776 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1170631104 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/4.lc_ctrl_sec_cm.1170631104 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_sec_cm.1170631104 -covoverwrite' seed=27720704396334197277468985510005004511905940398774274223145551493021972195776 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27720704396334197277468985510005004511905940398774274223145551493021972195776 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 95514588065790568188751173886564466576676638599692789537225479043446552136458 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=826018570 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/4.lc_ctrl_tl_errors.826018570 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.lc_ctrl_tl_errors.826018570 -covoverwrite' seed=95514588065790568188751173886564466576676638599692789537225479043446552136458 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95514588065790568188751173886564466576676638599692789537225479043446552136458 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 79911212175527893861282079809753380034365559963587966524810043329649467577534 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3165246654 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.3165246654 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.lc_ctrl_tl_intg_err.3165246654 -covoverwrite' seed=79911212175527893861282079809753380034365559963587966524810043329649467577534 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79911212175527893861282079809753380034365559963587966524810043329649467577534 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_alert_test 77773828781239202234379997760016378064671008189863655494381809183873830093151 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=758251871 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/4.lc_ctrl_alert_test.758251871 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 4.lc_ctrl_alert_test.758251871 -covoverwrite' seed=77773828781239202234379997760016378064671008189863655494381809183873830093151 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77773828781239202234379997760016378064671008189863655494381809183873830093151 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_csr_rw 60763676937851945719332874231608715188785325488032778216950570857939564307513 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3473482809 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/4.lc_ctrl_csr_rw.3473482809 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.lc_ctrl_csr_rw.3473482809 -covoverwrite' seed=60763676937851945719332874231608715188785325488032778216950570857939564307513 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60763676937851945719332874231608715188785325488032778216950570857939564307513 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_same_csr_outstanding 16549506842590583491073203761781514424083103704899219703252259425681057140339 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3755363955 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.3755363955 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.lc_ctrl_same_csr_outstanding.3755363955 -covoverwrite' seed=16549506842590583491073203761781514424083103704899219703252259425681057140339 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16549506842590583491073203761781514424083103704899219703252259425681057140339 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_csr_mem_rw_with_rand_reset 114381253024315887093583605103626579948202651764578859191219878116505663169773 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2388780269 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.2388780269 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.lc_ctrl_csr_mem_rw_with_rand_reset.2388780269 -covoverwrite' seed=114381253024315887093583605103626579948202651764578859191219878116505663169773 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114381253024315887093583605103626579948202651764578859191219878116505663169773 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 94690697007732698351672719345919862567480480405352593895747314901561734437189 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1100060997 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/5.lc_ctrl_smoke.1100060997 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_smoke.1100060997 -covoverwrite' seed=94690697007732698351672719345919862567480480405352593895747314901561734437189 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94690697007732698351672719345919862567480480405352593895747314901561734437189 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_volatile_unlock_smoke 76243334899149589683316532963124313178982861783436430181435196752794711151409 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_volatile_unlock_smoke/latest run_opts='+en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4183741233 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/5.lc_ctrl_volatile_unlock_smoke.4183741233 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_volatile_unlock_smoke.4183741233 -covoverwrite' seed=76243334899149589683316532963124313178982861783436430181435196752794711151409 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76243334899149589683316532963124313178982861783436430181435196752794711151409 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_volatile_unlock_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_volatile_unlock_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 49809831345211302382171715816686961277364794494336178825388807924258088272505 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=536199801 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/5.lc_ctrl_state_failure.536199801 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_state_failure.536199801 -covoverwrite' seed=49809831345211302382171715816686961277364794494336178825388807924258088272505 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49809831345211302382171715816686961277364794494336178825388807924258088272505 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 26743503395905484996507471139355951465560174406158318710374645193398116855234 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3557207490 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/5.lc_ctrl_state_post_trans.3557207490 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_state_post_trans.3557207490 -covoverwrite' seed=26743503395905484996507471139355951465560174406158318710374645193398116855234 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26743503395905484996507471139355951465560174406158318710374645193398116855234 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 79648391600225401158304556280739442251152777885960325490616349810551571226345 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1828069097 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/5.lc_ctrl_prog_failure.1828069097 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_prog_failure.1828069097 -covoverwrite' seed=79648391600225401158304556280739442251152777885960325490616349810551571226345 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79648391600225401158304556280739442251152777885960325490616349810551571226345 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 50457748160961518576125823473906201549119774351271261675833406199396092300753 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=22236625 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/5.lc_ctrl_errors.22236625 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_errors.22236625 -covoverwrite' seed=50457748160961518576125823473906201549119774351271261675833406199396092300753 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50457748160961518576125823473906201549119774351271261675833406199396092300753 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 113370660033463548353794971486472073817336613975802585222650296529389534986343 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=744112231 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/5.lc_ctrl_security_escalation.744112231 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_security_escalation.744112231 -covoverwrite' seed=113370660033463548353794971486472073817336613975802585222650296529389534986343 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113370660033463548353794971486472073817336613975802585222650296529389534986343 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_regwen_during_op 36433052313436120752007367647549323770274755573570630118134706961625886254043 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_regwen_during_op/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2799723483 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/5.lc_ctrl_regwen_during_op.2799723483 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_regwen_during_op.2799723483 -covoverwrite' seed=36433052313436120752007367647549323770274755573570630118134706961625886254043 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36433052313436120752007367647549323770274755573570630118134706961625886254043 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_claim_transition_if 36778222638442165760587810845169463384103192783380479284328418356400563046705 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_claim_transition_if/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3585231153 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/5.lc_ctrl_claim_transition_if.3585231153 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_claim_transition_if.3585231153 -covoverwrite' seed=36778222638442165760587810845169463384103192783380479284328418356400563046705 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36778222638442165760587810845169463384103192783380479284328418356400563046705 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_claim_transition_if/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_claim_transition_if_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 40048693950717453382566918464637113677266016927520436630511194528761344592868 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3907423204 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/5.lc_ctrl_jtag_smoke.3907423204 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_jtag_smoke.3907423204 -covoverwrite' seed=40048693950717453382566918464637113677266016927520436630511194528761344592868 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40048693950717453382566918464637113677266016927520436630511194528761344592868 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 105604021250917797039530108848514795030049596660617140482574776203251192101747 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1145502579 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/5.lc_ctrl_jtag_state_failure.1145502579 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_jtag_state_failure.1145502579 -covoverwrite' seed=105604021250917797039530108848514795030049596660617140482574776203251192101747 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105604021250917797039530108848514795030049596660617140482574776203251192101747 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 178193296810454922240588906136744991188201292174257944879141484604621070736 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2398888336 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/5.lc_ctrl_jtag_state_post_trans.2398888336 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_jtag_state_post_trans.2398888336 -covoverwrite' seed=178193296810454922240588906136744991188201292174257944879141484604621070736 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=178193296810454922240588906136744991188201292174257944879141484604621070736 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 114200722265849601102054309938268788479561377398169547383819094900492656922037 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=186600885 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/5.lc_ctrl_jtag_prog_failure.186600885 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_jtag_prog_failure.186600885 -covoverwrite' seed=114200722265849601102054309938268788479561377398169547383819094900492656922037 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114200722265849601102054309938268788479561377398169547383819094900492656922037 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 92819991875590370496731314192046564224996396302716449328757243781198752597641 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1665484425 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/5.lc_ctrl_jtag_errors.1665484425 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_jtag_errors.1665484425 -covoverwrite' seed=92819991875590370496731314192046564224996396302716449328757243781198752597641 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92819991875590370496731314192046564224996396302716449328757243781198752597641 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 79094982384154075233885449995909121300394507764740251993807581698578593698495 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=692671167 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/5.lc_ctrl_jtag_access.692671167 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_jtag_access.692671167 -covoverwrite' seed=79094982384154075233885449995909121300394507764740251993807581698578593698495 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79094982384154075233885449995909121300394507764740251993807581698578593698495 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_priority 4541115062100017943872185890364531437692950505742055828731255104153429687993 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_jtag_priority/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2364751545 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/5.lc_ctrl_jtag_priority.2364751545 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_jtag_priority.2364751545 -covoverwrite' seed=4541115062100017943872185890364531437692950505742055828731255104153429687993 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4541115062100017943872185890364531437692950505742055828731255104153429687993 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_jtag_priority/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_priority_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_regwen_during_op 107811506645625639765658966324796740788857450373445379776164334584757184385242 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_jtag_regwen_during_op/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1397510362 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/5.lc_ctrl_jtag_regwen_during_op.1397510362 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_jtag_regwen_during_op.1397510362 -covoverwrite' seed=107811506645625639765658966324796740788857450373445379776164334584757184385242 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107811506645625639765658966324796740788857450373445379776164334584757184385242 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_jtag_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_hw_reset 65073476899661379438310928000592120277168080876734549412794063684605757861022 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_jtag_csr_hw_reset/latest run_opts='+csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2860756126 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.2860756126 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.lc_ctrl_jtag_csr_hw_reset.2860756126 -covoverwrite' seed=65073476899661379438310928000592120277168080876734549412794063684605757861022 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65073476899661379438310928000592120277168080876734549412794063684605757861022 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_jtag_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_rw 79057396395122631141443311429449901308978135385812535633121701313389844165773 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_jtag_csr_rw/latest run_opts='+csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=617018509 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.617018509 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.lc_ctrl_jtag_csr_rw.617018509 -covoverwrite' seed=79057396395122631141443311429449901308978135385812535633121701313389844165773 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79057396395122631141443311429449901308978135385812535633121701313389844165773 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_jtag_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_bit_bash 857127369342463797157009347905984481248436174815145576340794352103472399482 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_jtag_csr_bit_bash/latest run_opts='+csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=199132282 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.199132282 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.lc_ctrl_jtag_csr_bit_bash.199132282 -covoverwrite' seed=857127369342463797157009347905984481248436174815145576340794352103472399482 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=857127369342463797157009347905984481248436174815145576340794352103472399482 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_jtag_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_aliasing 71342119850223657011491853774403004574599519683710433944373016615218497230072 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_jtag_csr_aliasing/latest run_opts='+csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1478006008 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.1478006008 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.lc_ctrl_jtag_csr_aliasing.1478006008 -covoverwrite' seed=71342119850223657011491853774403004574599519683710433944373016615218497230072 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71342119850223657011491853774403004574599519683710433944373016615218497230072 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_jtag_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_same_csr_outstanding 108953875399082206002284639333756718903417657372870039031274353229663183586372 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_jtag_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3952624708 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.3952624708 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.lc_ctrl_jtag_same_csr_outstanding.3952624708 -covoverwrite' seed=108953875399082206002284639333756718903417657372870039031274353229663183586372 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108953875399082206002284639333756718903417657372870039031274353229663183586372 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_jtag_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 54348270218030653905657695281719803621915894280190363297044716602566909758904 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1838812600 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1838812600 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1838812600 -covoverwrite' seed=54348270218030653905657695281719803621915894280190363297044716602566909758904 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54348270218030653905657695281719803621915894280190363297044716602566909758904 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_alert_test 52748463575430175105097957701005154515928273834830776939758697205512691856446 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_jtag_alert_test/latest run_opts='+run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=912864318 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.912864318 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.lc_ctrl_jtag_alert_test.912864318 -covoverwrite' seed=52748463575430175105097957701005154515928273834830776939758697205512691856446 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=52748463575430175105097957701005154515928273834830776939758697205512691856446 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_jtag_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_mubi 87925279587179006146762683355923093021897207193969336777417111694829209731002 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_sec_mubi/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=265240506 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/5.lc_ctrl_sec_mubi.265240506 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_sec_mubi.265240506 -covoverwrite' seed=87925279587179006146762683355923093021897207193969336777417111694829209731002 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87925279587179006146762683355923093021897207193969336777417111694829209731002 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_sec_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_mubi_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_mux 19932389633125542588794843982948035078374081069116438146826764251059373098992 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_sec_token_mux/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4144908272 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/5.lc_ctrl_sec_token_mux.4144908272 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_sec_token_mux.4144908272 -covoverwrite' seed=19932389633125542588794843982948035078374081069116438146826764251059373098992 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19932389633125542588794843982948035078374081069116438146826764251059373098992 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_sec_token_mux/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_mux_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_digest 42238446389377878762032454443645874834227651076798976887971034528577071962133 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_sec_token_digest/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=396711957 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/5.lc_ctrl_sec_token_digest.396711957 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_sec_token_digest.396711957 -covoverwrite' seed=42238446389377878762032454443645874834227651076798976887971034528577071962133 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42238446389377878762032454443645874834227651076798976887971034528577071962133 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_sec_token_digest/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_digest_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_stress_all_with_rand_reset 24400415632690625699746109721642481230490257383712444397015400561254062553563 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_stress_all_with_rand_reset/latest run_opts='+create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3828021723 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/5.lc_ctrl_stress_all_with_rand_reset.3828021723 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_stress_all_with_rand_reset.3828021723 -covoverwrite' seed=24400415632690625699746109721642481230490257383712444397015400561254062553563 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24400415632690625699746109721642481230490257383712444397015400561254062553563 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 18541564533457029206794838745181686406746876513750770703967208748918770338239 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4104751551 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/5.lc_ctrl_tl_errors.4104751551 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.lc_ctrl_tl_errors.4104751551 -covoverwrite' seed=18541564533457029206794838745181686406746876513750770703967208748918770338239 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18541564533457029206794838745181686406746876513750770703967208748918770338239 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 46933072711604644587453564817635327771819089047102213992949451150599409748524 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3367619116 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.3367619116 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.lc_ctrl_tl_intg_err.3367619116 -covoverwrite' seed=46933072711604644587453564817635327771819089047102213992949451150599409748524 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46933072711604644587453564817635327771819089047102213992949451150599409748524 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_alert_test 61138088940026754399938665072660209784220261075888905000048734547276294674988 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=772168236 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/5.lc_ctrl_alert_test.772168236 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 5.lc_ctrl_alert_test.772168236 -covoverwrite' seed=61138088940026754399938665072660209784220261075888905000048734547276294674988 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61138088940026754399938665072660209784220261075888905000048734547276294674988 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/5.lc_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 62283647735766362131037483572840368272624469773464031826765801264486169353381 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3528891557 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/6.lc_ctrl_smoke.3528891557 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_smoke.3528891557 -covoverwrite' seed=62283647735766362131037483572840368272624469773464031826765801264486169353381 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62283647735766362131037483572840368272624469773464031826765801264486169353381 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_volatile_unlock_smoke 5997159490688455944077180158600342146707660564388918883739705075288575274827 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_volatile_unlock_smoke/latest run_opts='+en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1358655307 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/6.lc_ctrl_volatile_unlock_smoke.1358655307 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_volatile_unlock_smoke.1358655307 -covoverwrite' seed=5997159490688455944077180158600342146707660564388918883739705075288575274827 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5997159490688455944077180158600342146707660564388918883739705075288575274827 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_volatile_unlock_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_volatile_unlock_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 93809882118279537736735053481764346406834573059292233451271852909526075842636 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1057497164 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/6.lc_ctrl_state_failure.1057497164 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_state_failure.1057497164 -covoverwrite' seed=93809882118279537736735053481764346406834573059292233451271852909526075842636 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93809882118279537736735053481764346406834573059292233451271852909526075842636 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 110317825998950371804610576440933319533564586464585493622894552383049847316287 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3071319871 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/6.lc_ctrl_state_post_trans.3071319871 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_state_post_trans.3071319871 -covoverwrite' seed=110317825998950371804610576440933319533564586464585493622894552383049847316287 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110317825998950371804610576440933319533564586464585493622894552383049847316287 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 85518753542356645825333290529429993068919724462971964645621583264446062140885 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=408559061 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/6.lc_ctrl_prog_failure.408559061 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_prog_failure.408559061 -covoverwrite' seed=85518753542356645825333290529429993068919724462971964645621583264446062140885 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85518753542356645825333290529429993068919724462971964645621583264446062140885 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 91979001125426220836975841769938725489633410826561143364196062819601426524653 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3339037165 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/6.lc_ctrl_errors.3339037165 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_errors.3339037165 -covoverwrite' seed=91979001125426220836975841769938725489633410826561143364196062819601426524653 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91979001125426220836975841769938725489633410826561143364196062819601426524653 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 96789707540071272952671091923136311256334279147141046699489628422234180799864 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1479658872 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/6.lc_ctrl_security_escalation.1479658872 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_security_escalation.1479658872 -covoverwrite' seed=96789707540071272952671091923136311256334279147141046699489628422234180799864 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96789707540071272952671091923136311256334279147141046699489628422234180799864 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_regwen_during_op 45868368371187617263962796940871584385829175647731282360434462933026813804918 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_regwen_during_op/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=76579190 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/6.lc_ctrl_regwen_during_op.76579190 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_regwen_during_op.76579190 -covoverwrite' seed=45868368371187617263962796940871584385829175647731282360434462933026813804918 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45868368371187617263962796940871584385829175647731282360434462933026813804918 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_claim_transition_if 27631384396138280843142044977544421866071658185416244405719141325627154628829 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_claim_transition_if/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3308388573 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/6.lc_ctrl_claim_transition_if.3308388573 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_claim_transition_if.3308388573 -covoverwrite' seed=27631384396138280843142044977544421866071658185416244405719141325627154628829 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27631384396138280843142044977544421866071658185416244405719141325627154628829 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_claim_transition_if/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_claim_transition_if_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 13777896529140389373876539555761752647690384579276416950227386089157582478506 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=616651946 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/6.lc_ctrl_jtag_smoke.616651946 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_jtag_smoke.616651946 -covoverwrite' seed=13777896529140389373876539555761752647690384579276416950227386089157582478506 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13777896529140389373876539555761752647690384579276416950227386089157582478506 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 19242853073606004637890769390056049516384751272151597303619738639135857848217 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4180553625 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/6.lc_ctrl_jtag_state_failure.4180553625 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_jtag_state_failure.4180553625 -covoverwrite' seed=19242853073606004637890769390056049516384751272151597303619738639135857848217 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19242853073606004637890769390056049516384751272151597303619738639135857848217 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 96690783561792000874889449463691348107544219832691895343365302497156680131839 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3127911679 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/6.lc_ctrl_jtag_state_post_trans.3127911679 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_jtag_state_post_trans.3127911679 -covoverwrite' seed=96690783561792000874889449463691348107544219832691895343365302497156680131839 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96690783561792000874889449463691348107544219832691895343365302497156680131839 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 10972409485045121194810134928431472191484002469977303549722458261725825823611 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1378448251 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/6.lc_ctrl_jtag_prog_failure.1378448251 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_jtag_prog_failure.1378448251 -covoverwrite' seed=10972409485045121194810134928431472191484002469977303549722458261725825823611 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10972409485045121194810134928431472191484002469977303549722458261725825823611 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 35769250822475728036077620212405878554752151394305771261205934862079279069716 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1956477460 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/6.lc_ctrl_jtag_errors.1956477460 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_jtag_errors.1956477460 -covoverwrite' seed=35769250822475728036077620212405878554752151394305771261205934862079279069716 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35769250822475728036077620212405878554752151394305771261205934862079279069716 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 44293356396613797233259573632690212904773572810081348902213243381062853291227 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4133579995 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/6.lc_ctrl_jtag_access.4133579995 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_jtag_access.4133579995 -covoverwrite' seed=44293356396613797233259573632690212904773572810081348902213243381062853291227 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44293356396613797233259573632690212904773572810081348902213243381062853291227 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_priority 50519668820285916699543994951379205667192139668398831004913267697840503463549 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_jtag_priority/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1199382141 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/6.lc_ctrl_jtag_priority.1199382141 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_jtag_priority.1199382141 -covoverwrite' seed=50519668820285916699543994951379205667192139668398831004913267697840503463549 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50519668820285916699543994951379205667192139668398831004913267697840503463549 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_jtag_priority/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_priority_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_regwen_during_op 48655389934250989256903222279168630907811169951211974709171023932474212052995 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_jtag_regwen_during_op/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1189965827 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/6.lc_ctrl_jtag_regwen_during_op.1189965827 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_jtag_regwen_during_op.1189965827 -covoverwrite' seed=48655389934250989256903222279168630907811169951211974709171023932474212052995 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48655389934250989256903222279168630907811169951211974709171023932474212052995 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_jtag_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_hw_reset 12621012429516589627779864161936908536608740369288702155743629231904811920281 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_jtag_csr_hw_reset/latest run_opts='+csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3284413337 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.3284413337 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.lc_ctrl_jtag_csr_hw_reset.3284413337 -covoverwrite' seed=12621012429516589627779864161936908536608740369288702155743629231904811920281 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12621012429516589627779864161936908536608740369288702155743629231904811920281 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_jtag_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_rw 40872405897204502266534124084428156239886613563285286663357063563222949722455 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_jtag_csr_rw/latest run_opts='+csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=25590103 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.25590103 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.lc_ctrl_jtag_csr_rw.25590103 -covoverwrite' seed=40872405897204502266534124084428156239886613563285286663357063563222949722455 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40872405897204502266534124084428156239886613563285286663357063563222949722455 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_jtag_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_bit_bash 61349041083907640455560216924368021012563601138206814197845838417775396649641 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_jtag_csr_bit_bash/latest run_opts='+csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1075313321 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.1075313321 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.lc_ctrl_jtag_csr_bit_bash.1075313321 -covoverwrite' seed=61349041083907640455560216924368021012563601138206814197845838417775396649641 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61349041083907640455560216924368021012563601138206814197845838417775396649641 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_jtag_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_aliasing 52699775109053275222641023382102443932677662448685325286042982963184888945509 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_jtag_csr_aliasing/latest run_opts='+csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1623169893 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.1623169893 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.lc_ctrl_jtag_csr_aliasing.1623169893 -covoverwrite' seed=52699775109053275222641023382102443932677662448685325286042982963184888945509 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=52699775109053275222641023382102443932677662448685325286042982963184888945509 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_jtag_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_same_csr_outstanding 93297587533103748875908649484272177343244529947452584169383666795484543715009 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_jtag_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3897296577 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3897296577 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.lc_ctrl_jtag_same_csr_outstanding.3897296577 -covoverwrite' seed=93297587533103748875908649484272177343244529947452584169383666795484543715009 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93297587533103748875908649484272177343244529947452584169383666795484543715009 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_jtag_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 111409378710735383575472046720411797881426294997516040534616959187342126569948 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1927371228 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1927371228 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1927371228 -covoverwrite' seed=111409378710735383575472046720411797881426294997516040534616959187342126569948 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111409378710735383575472046720411797881426294997516040534616959187342126569948 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_alert_test 25436316028066593115737492989766772329306375880603458360120587595757740867358 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_jtag_alert_test/latest run_opts='+run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2240528158 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.2240528158 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.lc_ctrl_jtag_alert_test.2240528158 -covoverwrite' seed=25436316028066593115737492989766772329306375880603458360120587595757740867358 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25436316028066593115737492989766772329306375880603458360120587595757740867358 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_jtag_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_mubi 5930894298621292935759798790291668690004061621545102214397784449741166089350 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_sec_mubi/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=606999686 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/6.lc_ctrl_sec_mubi.606999686 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_sec_mubi.606999686 -covoverwrite' seed=5930894298621292935759798790291668690004061621545102214397784449741166089350 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5930894298621292935759798790291668690004061621545102214397784449741166089350 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_sec_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_mubi_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_mux 86629837369611832433622954639015286113024385313146730965542839830809281225936 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_sec_token_mux/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=595256528 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/6.lc_ctrl_sec_token_mux.595256528 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_sec_token_mux.595256528 -covoverwrite' seed=86629837369611832433622954639015286113024385313146730965542839830809281225936 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86629837369611832433622954639015286113024385313146730965542839830809281225936 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_sec_token_mux/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_mux_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_digest 104567068858689002628574925071421227816953701616494504746209230326350895886184 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_sec_token_digest/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2524163944 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/6.lc_ctrl_sec_token_digest.2524163944 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_sec_token_digest.2524163944 -covoverwrite' seed=104567068858689002628574925071421227816953701616494504746209230326350895886184 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104567068858689002628574925071421227816953701616494504746209230326350895886184 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_sec_token_digest/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_digest_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_stress_all_with_rand_reset 102639183682578868809047650479616002686599421141543131486554019235334937107955 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_stress_all_with_rand_reset/latest run_opts='+create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=121101811 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/6.lc_ctrl_stress_all_with_rand_reset.121101811 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_stress_all_with_rand_reset.121101811 -covoverwrite' seed=102639183682578868809047650479616002686599421141543131486554019235334937107955 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102639183682578868809047650479616002686599421141543131486554019235334937107955 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 8083110790083864559103760467107253779445023358537006315251743910057525994416 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2140758960 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/6.lc_ctrl_tl_errors.2140758960 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.lc_ctrl_tl_errors.2140758960 -covoverwrite' seed=8083110790083864559103760467107253779445023358537006315251743910057525994416 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8083110790083864559103760467107253779445023358537006315251743910057525994416 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 22428121039608425813842748519209219844313118520721277324718705639460210461953 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2404371713 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2404371713 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.lc_ctrl_tl_intg_err.2404371713 -covoverwrite' seed=22428121039608425813842748519209219844313118520721277324718705639460210461953 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22428121039608425813842748519209219844313118520721277324718705639460210461953 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_alert_test 108942141979283774134889574130770861108649601373493686876875476001979191717952 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2523328576 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/6.lc_ctrl_alert_test.2523328576 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 6.lc_ctrl_alert_test.2523328576 -covoverwrite' seed=108942141979283774134889574130770861108649601373493686876875476001979191717952 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108942141979283774134889574130770861108649601373493686876875476001979191717952 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/6.lc_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 26978251763331540866418855596575028778770812036975766183354463491195073535415 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=965287351 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/7.lc_ctrl_smoke.965287351 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_smoke.965287351 -covoverwrite' seed=26978251763331540866418855596575028778770812036975766183354463491195073535415 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26978251763331540866418855596575028778770812036975766183354463491195073535415 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_volatile_unlock_smoke 96244916427721014784544081615178881984354593381273310458910670929196501231714 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_volatile_unlock_smoke/latest run_opts='+en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2560419938 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/7.lc_ctrl_volatile_unlock_smoke.2560419938 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_volatile_unlock_smoke.2560419938 -covoverwrite' seed=96244916427721014784544081615178881984354593381273310458910670929196501231714 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96244916427721014784544081615178881984354593381273310458910670929196501231714 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_volatile_unlock_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_volatile_unlock_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 84771741860841893359172724628030125331231825940529513244605360972194633005080 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1001961496 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/7.lc_ctrl_state_failure.1001961496 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_state_failure.1001961496 -covoverwrite' seed=84771741860841893359172724628030125331231825940529513244605360972194633005080 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84771741860841893359172724628030125331231825940529513244605360972194633005080 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 18900012511577178821003268930685206635834382177524919899490659226475676550925 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3984836365 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/7.lc_ctrl_state_post_trans.3984836365 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_state_post_trans.3984836365 -covoverwrite' seed=18900012511577178821003268930685206635834382177524919899490659226475676550925 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18900012511577178821003268930685206635834382177524919899490659226475676550925 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 84345589523586070612329869733929789888318483763857246617383642464848275262205 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1113279229 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/7.lc_ctrl_prog_failure.1113279229 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_prog_failure.1113279229 -covoverwrite' seed=84345589523586070612329869733929789888318483763857246617383642464848275262205 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84345589523586070612329869733929789888318483763857246617383642464848275262205 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 37881787634343812062317279917384051551206701944820724861706907196018429397972 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3121220564 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/7.lc_ctrl_errors.3121220564 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_errors.3121220564 -covoverwrite' seed=37881787634343812062317279917384051551206701944820724861706907196018429397972 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37881787634343812062317279917384051551206701944820724861706907196018429397972 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 52886202646390618389644471023374449024892522761878231299392394708151628503707 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2361694875 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/7.lc_ctrl_security_escalation.2361694875 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_security_escalation.2361694875 -covoverwrite' seed=52886202646390618389644471023374449024892522761878231299392394708151628503707 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=52886202646390618389644471023374449024892522761878231299392394708151628503707 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_regwen_during_op 79312782415779679629200012535287756532761379070171694230732480423358197165789 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_regwen_during_op/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1255435997 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/7.lc_ctrl_regwen_during_op.1255435997 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_regwen_during_op.1255435997 -covoverwrite' seed=79312782415779679629200012535287756532761379070171694230732480423358197165789 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79312782415779679629200012535287756532761379070171694230732480423358197165789 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_claim_transition_if 1379579797189929801417627922105358719559582510495065531428725714985693844446 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_claim_transition_if/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3565523934 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/7.lc_ctrl_claim_transition_if.3565523934 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_claim_transition_if.3565523934 -covoverwrite' seed=1379579797189929801417627922105358719559582510495065531428725714985693844446 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1379579797189929801417627922105358719559582510495065531428725714985693844446 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_claim_transition_if/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_claim_transition_if_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 87632259998612730308659322010052250158439780672513509963034325305968871330941 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3523990653 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/7.lc_ctrl_jtag_smoke.3523990653 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_jtag_smoke.3523990653 -covoverwrite' seed=87632259998612730308659322010052250158439780672513509963034325305968871330941 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87632259998612730308659322010052250158439780672513509963034325305968871330941 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 59707692847963645735506043470548949063598105442577780408203039465874022652886 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1495981014 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/7.lc_ctrl_jtag_state_failure.1495981014 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_jtag_state_failure.1495981014 -covoverwrite' seed=59707692847963645735506043470548949063598105442577780408203039465874022652886 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=59707692847963645735506043470548949063598105442577780408203039465874022652886 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 28899226616268286038937490104727768534291585084883454518744758567292056962704 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2376664720 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/7.lc_ctrl_jtag_state_post_trans.2376664720 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_jtag_state_post_trans.2376664720 -covoverwrite' seed=28899226616268286038937490104727768534291585084883454518744758567292056962704 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28899226616268286038937490104727768534291585084883454518744758567292056962704 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 91447933905936962796366799272326246680816049308848435011738116109661824546790 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2117269478 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/7.lc_ctrl_jtag_prog_failure.2117269478 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_jtag_prog_failure.2117269478 -covoverwrite' seed=91447933905936962796366799272326246680816049308848435011738116109661824546790 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91447933905936962796366799272326246680816049308848435011738116109661824546790 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 114684829559275429860130643215440127225116576317443655018047619813358896672868 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1437593700 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/7.lc_ctrl_jtag_errors.1437593700 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_jtag_errors.1437593700 -covoverwrite' seed=114684829559275429860130643215440127225116576317443655018047619813358896672868 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114684829559275429860130643215440127225116576317443655018047619813358896672868 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 25850413091677212131037240534527725993752386981060298677074981341382553464651 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3901058891 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/7.lc_ctrl_jtag_access.3901058891 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_jtag_access.3901058891 -covoverwrite' seed=25850413091677212131037240534527725993752386981060298677074981341382553464651 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25850413091677212131037240534527725993752386981060298677074981341382553464651 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_priority 92893600802148342927294684226379433199891818370567891877662775932010929516715 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_jtag_priority/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3272011947 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/7.lc_ctrl_jtag_priority.3272011947 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_jtag_priority.3272011947 -covoverwrite' seed=92893600802148342927294684226379433199891818370567891877662775932010929516715 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92893600802148342927294684226379433199891818370567891877662775932010929516715 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_jtag_priority/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_priority_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_regwen_during_op 65568065180831090073567224758554623277903148440701304165134768587893675220156 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_jtag_regwen_during_op/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2426756284 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/7.lc_ctrl_jtag_regwen_during_op.2426756284 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_jtag_regwen_during_op.2426756284 -covoverwrite' seed=65568065180831090073567224758554623277903148440701304165134768587893675220156 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65568065180831090073567224758554623277903148440701304165134768587893675220156 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_jtag_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_hw_reset 24765685271895427664555803757498932770284635040278074824204896962999776611614 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_jtag_csr_hw_reset/latest run_opts='+csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=51023134 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.51023134 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.lc_ctrl_jtag_csr_hw_reset.51023134 -covoverwrite' seed=24765685271895427664555803757498932770284635040278074824204896962999776611614 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24765685271895427664555803757498932770284635040278074824204896962999776611614 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_jtag_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_rw 50072465213721539982555360480034987940530367559279042782477064646874074497844 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_jtag_csr_rw/latest run_opts='+csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1092666164 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1092666164 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.lc_ctrl_jtag_csr_rw.1092666164 -covoverwrite' seed=50072465213721539982555360480034987940530367559279042782477064646874074497844 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50072465213721539982555360480034987940530367559279042782477064646874074497844 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_jtag_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_bit_bash 36888908679928696797338120190447697410889266351453678374068378256676172170258 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_jtag_csr_bit_bash/latest run_opts='+csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3279520786 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.3279520786 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.lc_ctrl_jtag_csr_bit_bash.3279520786 -covoverwrite' seed=36888908679928696797338120190447697410889266351453678374068378256676172170258 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36888908679928696797338120190447697410889266351453678374068378256676172170258 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_jtag_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_aliasing 54540883210566017227343556053019507615285241858082369011978494481188945109593 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_jtag_csr_aliasing/latest run_opts='+csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1830265433 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.1830265433 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.lc_ctrl_jtag_csr_aliasing.1830265433 -covoverwrite' seed=54540883210566017227343556053019507615285241858082369011978494481188945109593 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54540883210566017227343556053019507615285241858082369011978494481188945109593 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_jtag_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_same_csr_outstanding 685122125469153032079574946949349322289601705080934025990488454212230224251 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_jtag_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3646855547 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.3646855547 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.lc_ctrl_jtag_same_csr_outstanding.3646855547 -covoverwrite' seed=685122125469153032079574946949349322289601705080934025990488454212230224251 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=685122125469153032079574946949349322289601705080934025990488454212230224251 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_jtag_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 103451007231240250803269634695928706700163677499203437569366689528971270756542 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3800504510 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3800504510 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3800504510 -covoverwrite' seed=103451007231240250803269634695928706700163677499203437569366689528971270756542 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103451007231240250803269634695928706700163677499203437569366689528971270756542 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_alert_test 115545299945253688292702080973745222466238598724152743244456412513442311614125 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_jtag_alert_test/latest run_opts='+run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2880351917 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.2880351917 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.lc_ctrl_jtag_alert_test.2880351917 -covoverwrite' seed=115545299945253688292702080973745222466238598724152743244456412513442311614125 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115545299945253688292702080973745222466238598724152743244456412513442311614125 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_jtag_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_mubi 95364749105758712287802562924045267227946107149463814761444039905439976907180 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_sec_mubi/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=662561196 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/7.lc_ctrl_sec_mubi.662561196 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_sec_mubi.662561196 -covoverwrite' seed=95364749105758712287802562924045267227946107149463814761444039905439976907180 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95364749105758712287802562924045267227946107149463814761444039905439976907180 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_sec_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_mubi_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_mux 74588178221219809169766260561115253997535190270767378469013082156559029053263 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_sec_token_mux/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=840509263 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/7.lc_ctrl_sec_token_mux.840509263 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_sec_token_mux.840509263 -covoverwrite' seed=74588178221219809169766260561115253997535190270767378469013082156559029053263 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74588178221219809169766260561115253997535190270767378469013082156559029053263 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_sec_token_mux/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_mux_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_digest 7821866713153131689013686960817073430485787096123711779697021631755615224972 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_sec_token_digest/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1685341324 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/7.lc_ctrl_sec_token_digest.1685341324 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_sec_token_digest.1685341324 -covoverwrite' seed=7821866713153131689013686960817073430485787096123711779697021631755615224972 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7821866713153131689013686960817073430485787096123711779697021631755615224972 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_sec_token_digest/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_digest_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_stress_all_with_rand_reset 35035861172809112098885360359027783761124119781155298026811918650848681463984 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_stress_all_with_rand_reset/latest run_opts='+create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1817252016 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.1817252016 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_stress_all_with_rand_reset.1817252016 -covoverwrite' seed=35035861172809112098885360359027783761124119781155298026811918650848681463984 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35035861172809112098885360359027783761124119781155298026811918650848681463984 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 23417675118540889601443788973237443345629978243053724660127722202767771062115 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1609060195 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/7.lc_ctrl_tl_errors.1609060195 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.lc_ctrl_tl_errors.1609060195 -covoverwrite' seed=23417675118540889601443788973237443345629978243053724660127722202767771062115 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23417675118540889601443788973237443345629978243053724660127722202767771062115 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 110851825024977788563187355303478263557346353626280313672058662353195825626516 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1387265428 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.1387265428 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.lc_ctrl_tl_intg_err.1387265428 -covoverwrite' seed=110851825024977788563187355303478263557346353626280313672058662353195825626516 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110851825024977788563187355303478263557346353626280313672058662353195825626516 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_alert_test 90034209063386576259818596304024345898615912447087490778167073809838670299983 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3311092559 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/7.lc_ctrl_alert_test.3311092559 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 7.lc_ctrl_alert_test.3311092559 -covoverwrite' seed=90034209063386576259818596304024345898615912447087490778167073809838670299983 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90034209063386576259818596304024345898615912447087490778167073809838670299983 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/7.lc_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 88803031447951914405775239409482970864322484453817612684285893484078375149647 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3386417231 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/8.lc_ctrl_smoke.3386417231 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_smoke.3386417231 -covoverwrite' seed=88803031447951914405775239409482970864322484453817612684285893484078375149647 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88803031447951914405775239409482970864322484453817612684285893484078375149647 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_volatile_unlock_smoke 60669656329365817060914113334505906684536576230802306251081815437164411385097 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_volatile_unlock_smoke/latest run_opts='+en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3639112969 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/8.lc_ctrl_volatile_unlock_smoke.3639112969 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_volatile_unlock_smoke.3639112969 -covoverwrite' seed=60669656329365817060914113334505906684536576230802306251081815437164411385097 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60669656329365817060914113334505906684536576230802306251081815437164411385097 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_volatile_unlock_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_volatile_unlock_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 17298797119947252874954723864398156337593865312561467343358426356635173953246 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1147444958 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/8.lc_ctrl_state_failure.1147444958 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_state_failure.1147444958 -covoverwrite' seed=17298797119947252874954723864398156337593865312561467343358426356635173953246 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17298797119947252874954723864398156337593865312561467343358426356635173953246 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 77202170653629470865630999165482053820108844359010034735415808050721231489405 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1107052925 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/8.lc_ctrl_state_post_trans.1107052925 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_state_post_trans.1107052925 -covoverwrite' seed=77202170653629470865630999165482053820108844359010034735415808050721231489405 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77202170653629470865630999165482053820108844359010034735415808050721231489405 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 65286049229957065250442793769474574892081247907487339709762973763592386767063 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=389277911 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/8.lc_ctrl_prog_failure.389277911 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_prog_failure.389277911 -covoverwrite' seed=65286049229957065250442793769474574892081247907487339709762973763592386767063 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65286049229957065250442793769474574892081247907487339709762973763592386767063 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 18444394550479651523496998321150225346482535034897123669031876184352463883102 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2392427358 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/8.lc_ctrl_errors.2392427358 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_errors.2392427358 -covoverwrite' seed=18444394550479651523496998321150225346482535034897123669031876184352463883102 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18444394550479651523496998321150225346482535034897123669031876184352463883102 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 103350025974459057386562661008865242637907494207553717784609518963147095413258 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1711804938 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/8.lc_ctrl_security_escalation.1711804938 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_security_escalation.1711804938 -covoverwrite' seed=103350025974459057386562661008865242637907494207553717784609518963147095413258 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103350025974459057386562661008865242637907494207553717784609518963147095413258 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_regwen_during_op 74304984721699381173400293764866887795896372759544208504368371858216014665567 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_regwen_during_op/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1125996383 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/8.lc_ctrl_regwen_during_op.1125996383 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_regwen_during_op.1125996383 -covoverwrite' seed=74304984721699381173400293764866887795896372759544208504368371858216014665567 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74304984721699381173400293764866887795896372759544208504368371858216014665567 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_claim_transition_if 98530195715570177542922335465528456210021373876641525564562777068923926746841 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_claim_transition_if/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3215857369 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/8.lc_ctrl_claim_transition_if.3215857369 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_claim_transition_if.3215857369 -covoverwrite' seed=98530195715570177542922335465528456210021373876641525564562777068923926746841 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98530195715570177542922335465528456210021373876641525564562777068923926746841 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_claim_transition_if/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_claim_transition_if_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 54049318982335332126721620845105572961262167251219085890270562567333999006749 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2851591197 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/8.lc_ctrl_jtag_smoke.2851591197 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_jtag_smoke.2851591197 -covoverwrite' seed=54049318982335332126721620845105572961262167251219085890270562567333999006749 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54049318982335332126721620845105572961262167251219085890270562567333999006749 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 100418558504911666384857807224260256272539998930382545427316775355347023143028 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3881017460 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/8.lc_ctrl_jtag_state_failure.3881017460 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_jtag_state_failure.3881017460 -covoverwrite' seed=100418558504911666384857807224260256272539998930382545427316775355347023143028 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100418558504911666384857807224260256272539998930382545427316775355347023143028 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 58531236811388874304055708837891452424023649373999740294588005506113624568784 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=471823312 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/8.lc_ctrl_jtag_state_post_trans.471823312 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_jtag_state_post_trans.471823312 -covoverwrite' seed=58531236811388874304055708837891452424023649373999740294588005506113624568784 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58531236811388874304055708837891452424023649373999740294588005506113624568784 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 34630202286738788060214227675179544820864394133619799348685131781065980316039 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2834631047 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/8.lc_ctrl_jtag_prog_failure.2834631047 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_jtag_prog_failure.2834631047 -covoverwrite' seed=34630202286738788060214227675179544820864394133619799348685131781065980316039 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34630202286738788060214227675179544820864394133619799348685131781065980316039 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 53517710834697955864492619258485936460365720475530135756600039791784095977069 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1843727981 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/8.lc_ctrl_jtag_errors.1843727981 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_jtag_errors.1843727981 -covoverwrite' seed=53517710834697955864492619258485936460365720475530135756600039791784095977069 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53517710834697955864492619258485936460365720475530135756600039791784095977069 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 59477724415066418280290800179414177184909039162750020554981598285889073641204 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2698049268 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/8.lc_ctrl_jtag_access.2698049268 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_jtag_access.2698049268 -covoverwrite' seed=59477724415066418280290800179414177184909039162750020554981598285889073641204 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=59477724415066418280290800179414177184909039162750020554981598285889073641204 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_priority 72161947914895638685952008324166835498236639039889324035287139001915788507464 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_jtag_priority/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3400022344 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/8.lc_ctrl_jtag_priority.3400022344 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_jtag_priority.3400022344 -covoverwrite' seed=72161947914895638685952008324166835498236639039889324035287139001915788507464 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72161947914895638685952008324166835498236639039889324035287139001915788507464 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_jtag_priority/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_priority_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_regwen_during_op 21163853982755769811630189405279389019238387166045231682664595496250939822947 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_jtag_regwen_during_op/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=922243939 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/8.lc_ctrl_jtag_regwen_during_op.922243939 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_jtag_regwen_during_op.922243939 -covoverwrite' seed=21163853982755769811630189405279389019238387166045231682664595496250939822947 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21163853982755769811630189405279389019238387166045231682664595496250939822947 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_jtag_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_hw_reset 95272805784115418553377874097171392108230431723301642289316862898836731039898 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_jtag_csr_hw_reset/latest run_opts='+csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3431174298 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.3431174298 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.lc_ctrl_jtag_csr_hw_reset.3431174298 -covoverwrite' seed=95272805784115418553377874097171392108230431723301642289316862898836731039898 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95272805784115418553377874097171392108230431723301642289316862898836731039898 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_jtag_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_rw 26619216464804131607750284951272591509109860502831478597838472914405371738330 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_jtag_csr_rw/latest run_opts='+csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3083925722 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.3083925722 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.lc_ctrl_jtag_csr_rw.3083925722 -covoverwrite' seed=26619216464804131607750284951272591509109860502831478597838472914405371738330 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26619216464804131607750284951272591509109860502831478597838472914405371738330 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_jtag_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_bit_bash 16134701839360049794794945511883604567974792045147587419504807261405449323529 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_jtag_csr_bit_bash/latest run_opts='+csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=812680201 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.812680201 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.lc_ctrl_jtag_csr_bit_bash.812680201 -covoverwrite' seed=16134701839360049794794945511883604567974792045147587419504807261405449323529 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16134701839360049794794945511883604567974792045147587419504807261405449323529 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_jtag_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_aliasing 42810803319326786015752470378686981513260569476354940449045175547418565106865 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_jtag_csr_aliasing/latest run_opts='+csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1409506481 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.1409506481 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.lc_ctrl_jtag_csr_aliasing.1409506481 -covoverwrite' seed=42810803319326786015752470378686981513260569476354940449045175547418565106865 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42810803319326786015752470378686981513260569476354940449045175547418565106865 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_jtag_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_same_csr_outstanding 89804400277766326069184372926308519927297756939197775380902233077174018219266 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_jtag_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1634966786 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.1634966786 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.lc_ctrl_jtag_same_csr_outstanding.1634966786 -covoverwrite' seed=89804400277766326069184372926308519927297756939197775380902233077174018219266 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89804400277766326069184372926308519927297756939197775380902233077174018219266 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_jtag_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 27348730881281932006505152756839270906153094977200541127244018473468136791739 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=868228795 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.868228795 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.868228795 -covoverwrite' seed=27348730881281932006505152756839270906153094977200541127244018473468136791739 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27348730881281932006505152756839270906153094977200541127244018473468136791739 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_alert_test 68052265633630336366648179614053993647871286932461054534674894966558355138050 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_jtag_alert_test/latest run_opts='+run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2846139906 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.2846139906 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.lc_ctrl_jtag_alert_test.2846139906 -covoverwrite' seed=68052265633630336366648179614053993647871286932461054534674894966558355138050 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68052265633630336366648179614053993647871286932461054534674894966558355138050 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_jtag_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_mubi 11682002798602289589581353048644857667628846753628826840577359966720170632172 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_sec_mubi/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3323962348 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/8.lc_ctrl_sec_mubi.3323962348 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_sec_mubi.3323962348 -covoverwrite' seed=11682002798602289589581353048644857667628846753628826840577359966720170632172 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11682002798602289589581353048644857667628846753628826840577359966720170632172 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_sec_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_mubi_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_mux 104942621429961820104238853977915385119196161899301447334021439749680498080763 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_sec_token_mux/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4280417275 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/8.lc_ctrl_sec_token_mux.4280417275 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_sec_token_mux.4280417275 -covoverwrite' seed=104942621429961820104238853977915385119196161899301447334021439749680498080763 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104942621429961820104238853977915385119196161899301447334021439749680498080763 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_sec_token_mux/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_mux_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_digest 85191344068535144031023909005394755249053116251105695899061526540276015620483 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_sec_token_digest/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=227336579 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/8.lc_ctrl_sec_token_digest.227336579 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_sec_token_digest.227336579 -covoverwrite' seed=85191344068535144031023909005394755249053116251105695899061526540276015620483 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85191344068535144031023909005394755249053116251105695899061526540276015620483 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_sec_token_digest/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_digest_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_stress_all_with_rand_reset 15726549986036356689998199908414926694284836972167323922189450390888370269383 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_stress_all_with_rand_reset/latest run_opts='+create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1266019527 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/8.lc_ctrl_stress_all_with_rand_reset.1266019527 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_stress_all_with_rand_reset.1266019527 -covoverwrite' seed=15726549986036356689998199908414926694284836972167323922189450390888370269383 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15726549986036356689998199908414926694284836972167323922189450390888370269383 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 97377065796668964593116031565944042031590130490692546039409936707166479154411 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3618733291 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/8.lc_ctrl_tl_errors.3618733291 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.lc_ctrl_tl_errors.3618733291 -covoverwrite' seed=97377065796668964593116031565944042031590130490692546039409936707166479154411 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97377065796668964593116031565944042031590130490692546039409936707166479154411 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 114379768163884305512774402726064463925536454027574467385801286521384087774105 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2023678873 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.2023678873 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.lc_ctrl_tl_intg_err.2023678873 -covoverwrite' seed=114379768163884305512774402726064463925536454027574467385801286521384087774105 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114379768163884305512774402726064463925536454027574467385801286521384087774105 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_alert_test 34426070455972792283135679464210639421972091367710916731415644860591476204406 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3868353398 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/8.lc_ctrl_alert_test.3868353398 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 8.lc_ctrl_alert_test.3868353398 -covoverwrite' seed=34426070455972792283135679464210639421972091367710916731415644860591476204406 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34426070455972792283135679464210639421972091367710916731415644860591476204406 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/8.lc_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 98319093314417025585197198112737555964894861758471697894812803671298404678749 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3330702429 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/9.lc_ctrl_smoke.3330702429 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_smoke.3330702429 -covoverwrite' seed=98319093314417025585197198112737555964894861758471697894812803671298404678749 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98319093314417025585197198112737555964894861758471697894812803671298404678749 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_volatile_unlock_smoke 10708009696652415512853534137492031339098679661026792246785074059090676922633 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_volatile_unlock_smoke/latest run_opts='+en_scb=0 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3751000329 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_volatile_unlock_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/9.lc_ctrl_volatile_unlock_smoke.3751000329 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_volatile_unlock_smoke.3751000329 -covoverwrite' seed=10708009696652415512853534137492031339098679661026792246785074059090676922633 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10708009696652415512853534137492031339098679661026792246785074059090676922633 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_volatile_unlock_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_volatile_unlock_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 32514268723507305823005005189849809658285047648222739715153856936313524705406 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=963238014 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/9.lc_ctrl_state_failure.963238014 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_state_failure.963238014 -covoverwrite' seed=32514268723507305823005005189849809658285047648222739715153856936313524705406 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32514268723507305823005005189849809658285047648222739715153856936313524705406 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 16765165538536511626928254753450218322027627019149831927941300471428830852097 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=59896833 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/9.lc_ctrl_state_post_trans.59896833 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_state_post_trans.59896833 -covoverwrite' seed=16765165538536511626928254753450218322027627019149831927941300471428830852097 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16765165538536511626928254753450218322027627019149831927941300471428830852097 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 55491797389295107338357396344009593036058655972686611055956946290844067085065 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=799193865 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/9.lc_ctrl_prog_failure.799193865 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_prog_failure.799193865 -covoverwrite' seed=55491797389295107338357396344009593036058655972686611055956946290844067085065 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55491797389295107338357396344009593036058655972686611055956946290844067085065 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 80599997239356386467124060779358673880513702465505357846037153801712792048639 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=470094847 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/9.lc_ctrl_errors.470094847 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_errors.470094847 -covoverwrite' seed=80599997239356386467124060779358673880513702465505357846037153801712792048639 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80599997239356386467124060779358673880513702465505357846037153801712792048639 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 48939418967248380963816873974278431480388299895464760537298287026443583930188 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2868821836 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/9.lc_ctrl_security_escalation.2868821836 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_security_escalation.2868821836 -covoverwrite' seed=48939418967248380963816873974278431480388299895464760537298287026443583930188 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48939418967248380963816873974278431480388299895464760537298287026443583930188 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_regwen_during_op 66680888899892286072676459048876349582163882719943055733250799116657546796229 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_regwen_during_op/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2448727237 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/9.lc_ctrl_regwen_during_op.2448727237 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_regwen_during_op.2448727237 -covoverwrite' seed=66680888899892286072676459048876349582163882719943055733250799116657546796229 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66680888899892286072676459048876349582163882719943055733250799116657546796229 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_claim_transition_if 113877779194459730391796670975676957055851626770260977745390471161753831480294 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_claim_transition_if/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3688373222 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_claim_transition_if_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/9.lc_ctrl_claim_transition_if.3688373222 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_claim_transition_if.3688373222 -covoverwrite' seed=113877779194459730391796670975676957055851626770260977745390471161753831480294 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113877779194459730391796670975676957055851626770260977745390471161753831480294 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_claim_transition_if/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_claim_transition_if_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 53115450873322272904356712431665375521264339215006067978795968255729004433647 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1087885551 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/9.lc_ctrl_jtag_smoke.1087885551 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_jtag_smoke.1087885551 -covoverwrite' seed=53115450873322272904356712431665375521264339215006067978795968255729004433647 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53115450873322272904356712431665375521264339215006067978795968255729004433647 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 11672637542766272419900573622050493676245530767473660032117363560338431430527 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1800687487 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/9.lc_ctrl_jtag_state_failure.1800687487 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_jtag_state_failure.1800687487 -covoverwrite' seed=11672637542766272419900573622050493676245530767473660032117363560338431430527 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11672637542766272419900573622050493676245530767473660032117363560338431430527 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 47350816797345329243186424713823207642377975674780842608189674702915823390950 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1701236966 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/9.lc_ctrl_jtag_state_post_trans.1701236966 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_jtag_state_post_trans.1701236966 -covoverwrite' seed=47350816797345329243186424713823207642377975674780842608189674702915823390950 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47350816797345329243186424713823207642377975674780842608189674702915823390950 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 24372867059528229517861913786555036197509300572482937904109961336116256434026 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=986441578 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/9.lc_ctrl_jtag_prog_failure.986441578 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_jtag_prog_failure.986441578 -covoverwrite' seed=24372867059528229517861913786555036197509300572482937904109961336116256434026 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24372867059528229517861913786555036197509300572482937904109961336116256434026 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 15952968706174232701624829778725683062151988222941956928962355760118347114778 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3843860762 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/9.lc_ctrl_jtag_errors.3843860762 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_jtag_errors.3843860762 -covoverwrite' seed=15952968706174232701624829778725683062151988222941956928962355760118347114778 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15952968706174232701624829778725683062151988222941956928962355760118347114778 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 65250005209769141291579217748351895946926822050884086150451461273472752059128 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2627633912 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/9.lc_ctrl_jtag_access.2627633912 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_jtag_access.2627633912 -covoverwrite' seed=65250005209769141291579217748351895946926822050884086150451461273472752059128 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65250005209769141291579217748351895946926822050884086150451461273472752059128 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_priority 87588153697737106851585584348509074669951683258190156737232676735979929532697 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_jtag_priority/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=866973977 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_priority_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/9.lc_ctrl_jtag_priority.866973977 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_jtag_priority.866973977 -covoverwrite' seed=87588153697737106851585584348509074669951683258190156737232676735979929532697 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87588153697737106851585584348509074669951683258190156737232676735979929532697 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_jtag_priority/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_priority_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_regwen_during_op 18278121175507390044719676688428117592552981778929483102002203384239552491907 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_jtag_regwen_during_op/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2499309955 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_regwen_during_op_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/9.lc_ctrl_jtag_regwen_during_op.2499309955 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_jtag_regwen_during_op.2499309955 -covoverwrite' seed=18278121175507390044719676688428117592552981778929483102002203384239552491907 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18278121175507390044719676688428117592552981778929483102002203384239552491907 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_jtag_regwen_during_op/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_regwen_during_op_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_hw_reset 79461091642174091916622959559074326423118600873561745546954610397247049603048 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_jtag_csr_hw_reset/latest run_opts='+csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3073153000 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3073153000 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.lc_ctrl_jtag_csr_hw_reset.3073153000 -covoverwrite' seed=79461091642174091916622959559074326423118600873561745546954610397247049603048 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79461091642174091916622959559074326423118600873561745546954610397247049603048 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_jtag_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_rw 7039549725115466760504714486631323843854579926724576054090169041539638079871 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_jtag_csr_rw/latest run_opts='+csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=693219711 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.693219711 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.lc_ctrl_jtag_csr_rw.693219711 -covoverwrite' seed=7039549725115466760504714486631323843854579926724576054090169041539638079871 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7039549725115466760504714486631323843854579926724576054090169041539638079871 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_jtag_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_bit_bash 110490049909886770795473760186500731572986690193612752420081760286084033650563 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_jtag_csr_bit_bash/latest run_opts='+csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1403232131 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.1403232131 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.lc_ctrl_jtag_csr_bit_bash.1403232131 -covoverwrite' seed=110490049909886770795473760186500731572986690193612752420081760286084033650563 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110490049909886770795473760186500731572986690193612752420081760286084033650563 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_jtag_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_aliasing 104015284559324460832322004509084060679615627982859742309096404450459185513127 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_jtag_csr_aliasing/latest run_opts='+csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3617522343 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.3617522343 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.lc_ctrl_jtag_csr_aliasing.3617522343 -covoverwrite' seed=104015284559324460832322004509084060679615627982859742309096404450459185513127 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104015284559324460832322004509084060679615627982859742309096404450459185513127 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_jtag_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_same_csr_outstanding 1513680094396143135845582385769454490757259870083798310545996016872394909581 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_jtag_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=84469645 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.84469645 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.lc_ctrl_jtag_same_csr_outstanding.84469645 -covoverwrite' seed=1513680094396143135845582385769454490757259870083798310545996016872394909581 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1513680094396143135845582385769454490757259870083798310545996016872394909581 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_jtag_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 89111767976933849671711764119655566572809264720596086331841067317310541441603 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3027413571 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3027413571 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3027413571 -covoverwrite' seed=89111767976933849671711764119655566572809264720596086331841067317310541441603 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89111767976933849671711764119655566572809264720596086331841067317310541441603 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_alert_test 49298145423333092693867107307282607374948336688390774865934436163414434477990 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_jtag_alert_test/latest run_opts='+run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2900064166 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2900064166 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.lc_ctrl_jtag_alert_test.2900064166 -covoverwrite' seed=49298145423333092693867107307282607374948336688390774865934436163414434477990 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49298145423333092693867107307282607374948336688390774865934436163414434477990 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_jtag_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_mubi 63226385560062305599614955576361907958248832127964720718183608961822019504126 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_sec_mubi/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=947603454 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_mubi_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/9.lc_ctrl_sec_mubi.947603454 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_sec_mubi.947603454 -covoverwrite' seed=63226385560062305599614955576361907958248832127964720718183608961822019504126 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63226385560062305599614955576361907958248832127964720718183608961822019504126 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_sec_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_mubi_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_mux 14930896046231288138188491668411607279716145686686079708270134569027807441336 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_sec_token_mux/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2033414584 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_mux_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/9.lc_ctrl_sec_token_mux.2033414584 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_sec_token_mux.2033414584 -covoverwrite' seed=14930896046231288138188491668411607279716145686686079708270134569027807441336 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=14930896046231288138188491668411607279716145686686079708270134569027807441336 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_sec_token_mux/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_mux_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_sec_token_digest 23503835609915861035624478390959683183428689613704209585960292769900131638182 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_sec_token_digest/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1843780518 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_sec_token_digest_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/9.lc_ctrl_sec_token_digest.1843780518 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_sec_token_digest.1843780518 -covoverwrite' seed=23503835609915861035624478390959683183428689613704209585960292769900131638182 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23503835609915861035624478390959683183428689613704209585960292769900131638182 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_sec_token_digest/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_sec_token_digest_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_stress_all_with_rand_reset 64443025537518788606458611862627093772437053091599669763649823462085770249413 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_stress_all_with_rand_reset/latest run_opts='+create_jtag_riscv_map=1 +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=lc_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2897904837 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.2897904837 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_stress_all_with_rand_reset.2897904837 -covoverwrite' seed=64443025537518788606458611862627093772437053091599669763649823462085770249413 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64443025537518788606458611862627093772437053091599669763649823462085770249413 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 59398296878768696505429537586056388234080222435710261547206009550474284247253 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3397265621 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3397265621 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.lc_ctrl_tl_errors.3397265621 -covoverwrite' seed=59398296878768696505429537586056388234080222435710261547206009550474284247253 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=59398296878768696505429537586056388234080222435710261547206009550474284247253 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 9709314262486836692748969495852142887136811202980447159850840960230496826210 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2405856098 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.2405856098 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.lc_ctrl_tl_intg_err.2405856098 -covoverwrite' seed=9709314262486836692748969495852142887136811202980447159850840960230496826210 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9709314262486836692748969495852142887136811202980447159850840960230496826210 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_alert_test 57959192593316687444148479137941358170271666684243923301864107229892360081922 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1108152834 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/9.lc_ctrl_alert_test.1108152834 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 9.lc_ctrl_alert_test.1108152834 -covoverwrite' seed=57959192593316687444148479137941358170271666684243923301864107229892360081922 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57959192593316687444148479137941358170271666684243923301864107229892360081922 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/9.lc_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 18015467560797261908744695329942226751859079617242285548367973878155328776155 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/10.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=314468315 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/10.lc_ctrl_smoke.314468315 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 10.lc_ctrl_smoke.314468315 -covoverwrite' seed=18015467560797261908744695329942226751859079617242285548367973878155328776155 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18015467560797261908744695329942226751859079617242285548367973878155328776155 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/10.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 37542456784380194975855495278915109196977233089106454413774318418349827933025 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/10.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1844298593 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/10.lc_ctrl_state_failure.1844298593 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 10.lc_ctrl_state_failure.1844298593 -covoverwrite' seed=37542456784380194975855495278915109196977233089106454413774318418349827933025 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37542456784380194975855495278915109196977233089106454413774318418349827933025 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/10.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 75033380200493027482451602646532506685332073033149963090708529698094781654563 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/10.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2037999139 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/10.lc_ctrl_state_post_trans.2037999139 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 10.lc_ctrl_state_post_trans.2037999139 -covoverwrite' seed=75033380200493027482451602646532506685332073033149963090708529698094781654563 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75033380200493027482451602646532506685332073033149963090708529698094781654563 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/10.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 14520738321392552931668157127443767264282033249117795293391335137269274578786 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/10.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3623292770 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/10.lc_ctrl_prog_failure.3623292770 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 10.lc_ctrl_prog_failure.3623292770 -covoverwrite' seed=14520738321392552931668157127443767264282033249117795293391335137269274578786 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=14520738321392552931668157127443767264282033249117795293391335137269274578786 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/10.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 19878841990490339832435088116947220106150956736910478392329618189264750811312 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/10.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3153238192 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/10.lc_ctrl_errors.3153238192 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 10.lc_ctrl_errors.3153238192 -covoverwrite' seed=19878841990490339832435088116947220106150956736910478392329618189264750811312 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19878841990490339832435088116947220106150956736910478392329618189264750811312 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/10.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 7995671319655806472800276171384500816073455026398182230214783769217940910953 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/10.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=345568105 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/10.lc_ctrl_security_escalation.345568105 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 10.lc_ctrl_security_escalation.345568105 -covoverwrite' seed=7995671319655806472800276171384500816073455026398182230214783769217940910953 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7995671319655806472800276171384500816073455026398182230214783769217940910953 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/10.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 25860639954479294576897684290578191059078632219008594469554676626769667119567 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/10.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4144978383 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/10.lc_ctrl_jtag_smoke.4144978383 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 10.lc_ctrl_jtag_smoke.4144978383 -covoverwrite' seed=25860639954479294576897684290578191059078632219008594469554676626769667119567 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25860639954479294576897684290578191059078632219008594469554676626769667119567 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/10.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 21602531960657428735822834507046429540481196827878542321742820742030742116984 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/10.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3944077944 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/10.lc_ctrl_jtag_state_failure.3944077944 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 10.lc_ctrl_jtag_state_failure.3944077944 -covoverwrite' seed=21602531960657428735822834507046429540481196827878542321742820742030742116984 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21602531960657428735822834507046429540481196827878542321742820742030742116984 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/10.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 27256159802981538532053650469461713460032086941990538560149723361289265992050 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/10.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3358314866 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/10.lc_ctrl_jtag_state_post_trans.3358314866 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 10.lc_ctrl_jtag_state_post_trans.3358314866 -covoverwrite' seed=27256159802981538532053650469461713460032086941990538560149723361289265992050 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27256159802981538532053650469461713460032086941990538560149723361289265992050 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/10.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 62393894915277646921464628376074211089878050676953802246012680737760983803620 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/10.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3708970724 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/10.lc_ctrl_jtag_prog_failure.3708970724 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 10.lc_ctrl_jtag_prog_failure.3708970724 -covoverwrite' seed=62393894915277646921464628376074211089878050676953802246012680737760983803620 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62393894915277646921464628376074211089878050676953802246012680737760983803620 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/10.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 45627327375182517076440112885066181094151804218459151407985431561676394661687 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/10.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1397819191 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/10.lc_ctrl_jtag_errors.1397819191 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 10.lc_ctrl_jtag_errors.1397819191 -covoverwrite' seed=45627327375182517076440112885066181094151804218459151407985431561676394661687 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45627327375182517076440112885066181094151804218459151407985431561676394661687 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/10.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 16576144267936639812892252098157008299520058449281817778236387702744474807270 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/10.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=642608102 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/10.lc_ctrl_jtag_access.642608102 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 10.lc_ctrl_jtag_access.642608102 -covoverwrite' seed=16576144267936639812892252098157008299520058449281817778236387702744474807270 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16576144267936639812892252098157008299520058449281817778236387702744474807270 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/10.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 83756890100000512232820694578624946953396415680520630661134313364186701600504 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/10.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=824547064 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/10.lc_ctrl_tl_errors.824547064 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 10.lc_ctrl_tl_errors.824547064 -covoverwrite' seed=83756890100000512232820694578624946953396415680520630661134313364186701600504 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83756890100000512232820694578624946953396415680520630661134313364186701600504 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/10.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 8081175000181066147850877390855413296821747920332063167147398132314340383599 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/10.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3651722095 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.3651722095 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 10.lc_ctrl_tl_intg_err.3651722095 -covoverwrite' seed=8081175000181066147850877390855413296821747920332063167147398132314340383599 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8081175000181066147850877390855413296821747920332063167147398132314340383599 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/10.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 72083971070815139446110695231575860023733447181394693519707138966230342675381 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/11.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2682629045 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/11.lc_ctrl_smoke.2682629045 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 11.lc_ctrl_smoke.2682629045 -covoverwrite' seed=72083971070815139446110695231575860023733447181394693519707138966230342675381 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72083971070815139446110695231575860023733447181394693519707138966230342675381 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/11.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 72161723540495061875459104134982311535412108700292586390107225569249992677858 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/11.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4070349282 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/11.lc_ctrl_state_failure.4070349282 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 11.lc_ctrl_state_failure.4070349282 -covoverwrite' seed=72161723540495061875459104134982311535412108700292586390107225569249992677858 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72161723540495061875459104134982311535412108700292586390107225569249992677858 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/11.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 5966995245807457691442742849500044281193281926223407082586902983048967088137 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/11.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2299127817 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/11.lc_ctrl_state_post_trans.2299127817 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 11.lc_ctrl_state_post_trans.2299127817 -covoverwrite' seed=5966995245807457691442742849500044281193281926223407082586902983048967088137 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5966995245807457691442742849500044281193281926223407082586902983048967088137 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/11.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 75371921532882658793699804382160503712349300586939724974568333046114596511160 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/11.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1895390648 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/11.lc_ctrl_prog_failure.1895390648 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 11.lc_ctrl_prog_failure.1895390648 -covoverwrite' seed=75371921532882658793699804382160503712349300586939724974568333046114596511160 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75371921532882658793699804382160503712349300586939724974568333046114596511160 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/11.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 100592218267457482676761642986969315931912725418365266539252615182948109619359 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/11.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3645083807 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/11.lc_ctrl_errors.3645083807 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 11.lc_ctrl_errors.3645083807 -covoverwrite' seed=100592218267457482676761642986969315931912725418365266539252615182948109619359 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100592218267457482676761642986969315931912725418365266539252615182948109619359 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/11.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 27189018634663743255382606863652000513779418109633219329692810343254102774500 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/11.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2816348900 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/11.lc_ctrl_security_escalation.2816348900 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 11.lc_ctrl_security_escalation.2816348900 -covoverwrite' seed=27189018634663743255382606863652000513779418109633219329692810343254102774500 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27189018634663743255382606863652000513779418109633219329692810343254102774500 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/11.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 8914249694946067850829838674818347285239749761586336063851195178043260542056 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/11.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1263279208 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/11.lc_ctrl_jtag_smoke.1263279208 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 11.lc_ctrl_jtag_smoke.1263279208 -covoverwrite' seed=8914249694946067850829838674818347285239749761586336063851195178043260542056 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8914249694946067850829838674818347285239749761586336063851195178043260542056 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/11.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 55223861134813667114996736448952101691807253172485968966370900060122686721860 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/11.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4286877508 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/11.lc_ctrl_jtag_state_failure.4286877508 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 11.lc_ctrl_jtag_state_failure.4286877508 -covoverwrite' seed=55223861134813667114996736448952101691807253172485968966370900060122686721860 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55223861134813667114996736448952101691807253172485968966370900060122686721860 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/11.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 50024568536627241751673788314033679897889884640561451906251274238661018544552 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/11.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=33319336 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/11.lc_ctrl_jtag_state_post_trans.33319336 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 11.lc_ctrl_jtag_state_post_trans.33319336 -covoverwrite' seed=50024568536627241751673788314033679897889884640561451906251274238661018544552 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50024568536627241751673788314033679897889884640561451906251274238661018544552 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/11.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 73520609628093787364929603017566311523337167900016582254614108538333497249829 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/11.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4013281317 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/11.lc_ctrl_jtag_prog_failure.4013281317 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 11.lc_ctrl_jtag_prog_failure.4013281317 -covoverwrite' seed=73520609628093787364929603017566311523337167900016582254614108538333497249829 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73520609628093787364929603017566311523337167900016582254614108538333497249829 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/11.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 82022354793945494271518605819378798840575830088776593120092130079406446073161 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/11.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2713703753 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/11.lc_ctrl_jtag_errors.2713703753 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 11.lc_ctrl_jtag_errors.2713703753 -covoverwrite' seed=82022354793945494271518605819378798840575830088776593120092130079406446073161 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82022354793945494271518605819378798840575830088776593120092130079406446073161 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/11.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 32916905111657067636129856834303166957865891332830442886399613073966583002346 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/11.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3419682026 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/11.lc_ctrl_jtag_access.3419682026 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 11.lc_ctrl_jtag_access.3419682026 -covoverwrite' seed=32916905111657067636129856834303166957865891332830442886399613073966583002346 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32916905111657067636129856834303166957865891332830442886399613073966583002346 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/11.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 27693146862875243549822594969136549887020124610937891737410471158088445858244 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/11.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=44437956 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/11.lc_ctrl_tl_errors.44437956 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 11.lc_ctrl_tl_errors.44437956 -covoverwrite' seed=27693146862875243549822594969136549887020124610937891737410471158088445858244 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27693146862875243549822594969136549887020124610937891737410471158088445858244 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/11.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 38867055616200577722885628124005402988327358813332484013742181846082978462953 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/11.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2310159593 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.2310159593 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 11.lc_ctrl_tl_intg_err.2310159593 -covoverwrite' seed=38867055616200577722885628124005402988327358813332484013742181846082978462953 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38867055616200577722885628124005402988327358813332484013742181846082978462953 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/11.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 82094606046203401601749235298467185822297778267507088811234525251184551180458 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/12.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=927905962 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/12.lc_ctrl_smoke.927905962 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 12.lc_ctrl_smoke.927905962 -covoverwrite' seed=82094606046203401601749235298467185822297778267507088811234525251184551180458 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82094606046203401601749235298467185822297778267507088811234525251184551180458 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/12.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 69171364207527147023072533684963229382609998419274693548208423160045923720833 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/12.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1361829505 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/12.lc_ctrl_state_failure.1361829505 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 12.lc_ctrl_state_failure.1361829505 -covoverwrite' seed=69171364207527147023072533684963229382609998419274693548208423160045923720833 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69171364207527147023072533684963229382609998419274693548208423160045923720833 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/12.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 32044986103890190705944547688032901768697634290854811249291982164891494063247 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/12.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=665394319 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/12.lc_ctrl_state_post_trans.665394319 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 12.lc_ctrl_state_post_trans.665394319 -covoverwrite' seed=32044986103890190705944547688032901768697634290854811249291982164891494063247 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32044986103890190705944547688032901768697634290854811249291982164891494063247 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/12.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 40564194387851270267616912958199490993034774608328786822494888280967652851319 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/12.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3697819255 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/12.lc_ctrl_prog_failure.3697819255 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 12.lc_ctrl_prog_failure.3697819255 -covoverwrite' seed=40564194387851270267616912958199490993034774608328786822494888280967652851319 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40564194387851270267616912958199490993034774608328786822494888280967652851319 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/12.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 48585262910300914997213514246743608987378673388432112977653205459645457726042 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/12.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=165902938 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/12.lc_ctrl_errors.165902938 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 12.lc_ctrl_errors.165902938 -covoverwrite' seed=48585262910300914997213514246743608987378673388432112977653205459645457726042 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48585262910300914997213514246743608987378673388432112977653205459645457726042 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/12.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 30228600197016029026278487168293694881143367748691934955032700139367444032189 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/12.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2602871485 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/12.lc_ctrl_security_escalation.2602871485 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 12.lc_ctrl_security_escalation.2602871485 -covoverwrite' seed=30228600197016029026278487168293694881143367748691934955032700139367444032189 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30228600197016029026278487168293694881143367748691934955032700139367444032189 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/12.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 50125639357648032952980521838828759632475747546110591811263466141181349972596 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/12.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1697106548 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/12.lc_ctrl_jtag_smoke.1697106548 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 12.lc_ctrl_jtag_smoke.1697106548 -covoverwrite' seed=50125639357648032952980521838828759632475747546110591811263466141181349972596 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50125639357648032952980521838828759632475747546110591811263466141181349972596 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/12.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 89348880697828203606559104085681682344079272685287050100280877046710591942751 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/12.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4196528223 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/12.lc_ctrl_jtag_state_failure.4196528223 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 12.lc_ctrl_jtag_state_failure.4196528223 -covoverwrite' seed=89348880697828203606559104085681682344079272685287050100280877046710591942751 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89348880697828203606559104085681682344079272685287050100280877046710591942751 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/12.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 57254947297694063409140409769187083172368452059078552106591216977747824257770 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/12.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3847662314 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/12.lc_ctrl_jtag_state_post_trans.3847662314 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 12.lc_ctrl_jtag_state_post_trans.3847662314 -covoverwrite' seed=57254947297694063409140409769187083172368452059078552106591216977747824257770 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57254947297694063409140409769187083172368452059078552106591216977747824257770 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/12.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 56260193990346768318410290019347413641622438761848977636408300357744558464557 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/12.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=198303277 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/12.lc_ctrl_jtag_prog_failure.198303277 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 12.lc_ctrl_jtag_prog_failure.198303277 -covoverwrite' seed=56260193990346768318410290019347413641622438761848977636408300357744558464557 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56260193990346768318410290019347413641622438761848977636408300357744558464557 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/12.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 35471002444897907967829184242627770274770282001042546669948514737331699634130 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/12.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2567360466 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/12.lc_ctrl_jtag_errors.2567360466 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 12.lc_ctrl_jtag_errors.2567360466 -covoverwrite' seed=35471002444897907967829184242627770274770282001042546669948514737331699634130 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35471002444897907967829184242627770274770282001042546669948514737331699634130 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/12.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 2431510817241415033402217283112195744563587446648565718528782698832461761917 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/12.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2868841853 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/12.lc_ctrl_jtag_access.2868841853 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 12.lc_ctrl_jtag_access.2868841853 -covoverwrite' seed=2431510817241415033402217283112195744563587446648565718528782698832461761917 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2431510817241415033402217283112195744563587446648565718528782698832461761917 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/12.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 113882360314757404105514515318858366714436023628543996943468834801782109637157 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/12.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3467774501 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/12.lc_ctrl_tl_errors.3467774501 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 12.lc_ctrl_tl_errors.3467774501 -covoverwrite' seed=113882360314757404105514515318858366714436023628543996943468834801782109637157 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113882360314757404105514515318858366714436023628543996943468834801782109637157 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/12.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 114076113421083607096549111065107012543132986791290488090788237897141829183174 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/12.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2749310662 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.2749310662 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 12.lc_ctrl_tl_intg_err.2749310662 -covoverwrite' seed=114076113421083607096549111065107012543132986791290488090788237897141829183174 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114076113421083607096549111065107012543132986791290488090788237897141829183174 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/12.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 64573617100993551501650660199479135102749010110144530224263092705740761474877 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/13.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1618356029 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/13.lc_ctrl_smoke.1618356029 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 13.lc_ctrl_smoke.1618356029 -covoverwrite' seed=64573617100993551501650660199479135102749010110144530224263092705740761474877 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64573617100993551501650660199479135102749010110144530224263092705740761474877 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/13.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 105727310166000644199456919177736322853911817732544474767946363088595715569656 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/13.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=478623736 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/13.lc_ctrl_state_failure.478623736 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 13.lc_ctrl_state_failure.478623736 -covoverwrite' seed=105727310166000644199456919177736322853911817732544474767946363088595715569656 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105727310166000644199456919177736322853911817732544474767946363088595715569656 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/13.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 79367004221232104839714425563591061340981292380079114148303819715922562983491 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/13.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4210370115 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/13.lc_ctrl_state_post_trans.4210370115 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 13.lc_ctrl_state_post_trans.4210370115 -covoverwrite' seed=79367004221232104839714425563591061340981292380079114148303819715922562983491 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79367004221232104839714425563591061340981292380079114148303819715922562983491 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/13.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 46530060886916511780220122690706284390742028980824378501835916198866643885472 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/13.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4198014368 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/13.lc_ctrl_prog_failure.4198014368 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 13.lc_ctrl_prog_failure.4198014368 -covoverwrite' seed=46530060886916511780220122690706284390742028980824378501835916198866643885472 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46530060886916511780220122690706284390742028980824378501835916198866643885472 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/13.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 87649456025688537134107948096347318005852957753130789733538162856213927366977 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/13.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2581795137 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/13.lc_ctrl_errors.2581795137 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 13.lc_ctrl_errors.2581795137 -covoverwrite' seed=87649456025688537134107948096347318005852957753130789733538162856213927366977 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87649456025688537134107948096347318005852957753130789733538162856213927366977 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/13.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 72365059011893057509225921748162458219766057583585230418797046689673450295797 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/13.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3930264053 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/13.lc_ctrl_security_escalation.3930264053 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 13.lc_ctrl_security_escalation.3930264053 -covoverwrite' seed=72365059011893057509225921748162458219766057583585230418797046689673450295797 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72365059011893057509225921748162458219766057583585230418797046689673450295797 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/13.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 22712573181967356482500116714432840909851038069388368496054280353992663749274 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/13.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2234372762 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/13.lc_ctrl_jtag_smoke.2234372762 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 13.lc_ctrl_jtag_smoke.2234372762 -covoverwrite' seed=22712573181967356482500116714432840909851038069388368496054280353992663749274 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22712573181967356482500116714432840909851038069388368496054280353992663749274 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/13.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 9775068854094673772336959041058122848761146019223950833365004744226940587892 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/13.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3350925172 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/13.lc_ctrl_jtag_state_failure.3350925172 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 13.lc_ctrl_jtag_state_failure.3350925172 -covoverwrite' seed=9775068854094673772336959041058122848761146019223950833365004744226940587892 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9775068854094673772336959041058122848761146019223950833365004744226940587892 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/13.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 55674000203277036631640452123905929975443920607072402617512592700349362103849 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/13.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4288308777 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/13.lc_ctrl_jtag_state_post_trans.4288308777 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 13.lc_ctrl_jtag_state_post_trans.4288308777 -covoverwrite' seed=55674000203277036631640452123905929975443920607072402617512592700349362103849 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55674000203277036631640452123905929975443920607072402617512592700349362103849 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/13.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 95454971722525866904166054095694000142955055658283918984065433441059177091441 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/13.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1354092913 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/13.lc_ctrl_jtag_prog_failure.1354092913 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 13.lc_ctrl_jtag_prog_failure.1354092913 -covoverwrite' seed=95454971722525866904166054095694000142955055658283918984065433441059177091441 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95454971722525866904166054095694000142955055658283918984065433441059177091441 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/13.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 66234548871688775302667381321304727691672698451869269720119997648089915190920 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/13.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1354362504 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/13.lc_ctrl_jtag_errors.1354362504 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 13.lc_ctrl_jtag_errors.1354362504 -covoverwrite' seed=66234548871688775302667381321304727691672698451869269720119997648089915190920 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66234548871688775302667381321304727691672698451869269720119997648089915190920 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/13.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 33209658191448650449162659424429526112844523888294106580796218450813684583237 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/13.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2248182597 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/13.lc_ctrl_jtag_access.2248182597 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 13.lc_ctrl_jtag_access.2248182597 -covoverwrite' seed=33209658191448650449162659424429526112844523888294106580796218450813684583237 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33209658191448650449162659424429526112844523888294106580796218450813684583237 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/13.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 11970672807597885846971907655326813670395256845315566245151804424083763785664 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/13.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2862510016 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/13.lc_ctrl_tl_errors.2862510016 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 13.lc_ctrl_tl_errors.2862510016 -covoverwrite' seed=11970672807597885846971907655326813670395256845315566245151804424083763785664 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11970672807597885846971907655326813670395256845315566245151804424083763785664 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/13.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 100609499749819006786805841632687438324737998303042778740980922396559558748273 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/13.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=366651505 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.366651505 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 13.lc_ctrl_tl_intg_err.366651505 -covoverwrite' seed=100609499749819006786805841632687438324737998303042778740980922396559558748273 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100609499749819006786805841632687438324737998303042778740980922396559558748273 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/13.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 18578302437833435481267654958017072126564036522033827879964786100705205672259 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/14.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1785190723 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/14.lc_ctrl_smoke.1785190723 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 14.lc_ctrl_smoke.1785190723 -covoverwrite' seed=18578302437833435481267654958017072126564036522033827879964786100705205672259 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18578302437833435481267654958017072126564036522033827879964786100705205672259 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/14.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 92965959456445415089858178212943810885470171608756175071228137587612620815291 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/14.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1781660603 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/14.lc_ctrl_state_failure.1781660603 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 14.lc_ctrl_state_failure.1781660603 -covoverwrite' seed=92965959456445415089858178212943810885470171608756175071228137587612620815291 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92965959456445415089858178212943810885470171608756175071228137587612620815291 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/14.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 29189720595409326774998201541119705104845266099404022479577575531057481290451 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/14.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=438604499 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/14.lc_ctrl_state_post_trans.438604499 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 14.lc_ctrl_state_post_trans.438604499 -covoverwrite' seed=29189720595409326774998201541119705104845266099404022479577575531057481290451 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29189720595409326774998201541119705104845266099404022479577575531057481290451 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/14.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 83769482129958747497494177033663593962064422685696443306090826371319910767763 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/14.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3745651859 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/14.lc_ctrl_prog_failure.3745651859 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 14.lc_ctrl_prog_failure.3745651859 -covoverwrite' seed=83769482129958747497494177033663593962064422685696443306090826371319910767763 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83769482129958747497494177033663593962064422685696443306090826371319910767763 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/14.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 69305327681333521925074677210219797989372150938352719628365100118051436184087 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/14.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3565765143 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/14.lc_ctrl_errors.3565765143 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 14.lc_ctrl_errors.3565765143 -covoverwrite' seed=69305327681333521925074677210219797989372150938352719628365100118051436184087 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69305327681333521925074677210219797989372150938352719628365100118051436184087 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/14.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 88017033379095901349833620797979862610743041215454662710556674381890324693753 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/14.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=447906553 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/14.lc_ctrl_security_escalation.447906553 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 14.lc_ctrl_security_escalation.447906553 -covoverwrite' seed=88017033379095901349833620797979862610743041215454662710556674381890324693753 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88017033379095901349833620797979862610743041215454662710556674381890324693753 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/14.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 75328677606491082027473055684864651762244445414243289461351502532429036559672 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/14.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3390217528 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/14.lc_ctrl_jtag_smoke.3390217528 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 14.lc_ctrl_jtag_smoke.3390217528 -covoverwrite' seed=75328677606491082027473055684864651762244445414243289461351502532429036559672 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75328677606491082027473055684864651762244445414243289461351502532429036559672 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/14.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 11948917838159375372953739199609718138209958704596320981984260485814172275238 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/14.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2856604198 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/14.lc_ctrl_jtag_state_failure.2856604198 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 14.lc_ctrl_jtag_state_failure.2856604198 -covoverwrite' seed=11948917838159375372953739199609718138209958704596320981984260485814172275238 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11948917838159375372953739199609718138209958704596320981984260485814172275238 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/14.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 98032286247214668596354888579246791825547580435197553933287034714191906381396 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/14.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3162152532 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/14.lc_ctrl_jtag_state_post_trans.3162152532 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 14.lc_ctrl_jtag_state_post_trans.3162152532 -covoverwrite' seed=98032286247214668596354888579246791825547580435197553933287034714191906381396 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98032286247214668596354888579246791825547580435197553933287034714191906381396 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/14.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 29220417202606235757207822564476478154578612315695655661356834051769385362791 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/14.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1873814887 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/14.lc_ctrl_jtag_prog_failure.1873814887 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 14.lc_ctrl_jtag_prog_failure.1873814887 -covoverwrite' seed=29220417202606235757207822564476478154578612315695655661356834051769385362791 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29220417202606235757207822564476478154578612315695655661356834051769385362791 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/14.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 74866269568033866020788846261431003098290072801272875549382393969413903583680 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/14.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2003798464 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/14.lc_ctrl_jtag_errors.2003798464 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 14.lc_ctrl_jtag_errors.2003798464 -covoverwrite' seed=74866269568033866020788846261431003098290072801272875549382393969413903583680 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74866269568033866020788846261431003098290072801272875549382393969413903583680 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/14.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 109785471429662934052754115971929912100242861641803291763778982335163241440022 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/14.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2401870614 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/14.lc_ctrl_jtag_access.2401870614 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 14.lc_ctrl_jtag_access.2401870614 -covoverwrite' seed=109785471429662934052754115971929912100242861641803291763778982335163241440022 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109785471429662934052754115971929912100242861641803291763778982335163241440022 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/14.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 30842379312937730074364689256716623089418447852947583075302265474395770838127 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/14.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=12180591 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/14.lc_ctrl_tl_errors.12180591 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 14.lc_ctrl_tl_errors.12180591 -covoverwrite' seed=30842379312937730074364689256716623089418447852947583075302265474395770838127 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30842379312937730074364689256716623089418447852947583075302265474395770838127 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/14.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 46626641455087588000516052128241504882135174833076929546812373380073327030903 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/14.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4031640183 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.4031640183 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 14.lc_ctrl_tl_intg_err.4031640183 -covoverwrite' seed=46626641455087588000516052128241504882135174833076929546812373380073327030903 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46626641455087588000516052128241504882135174833076929546812373380073327030903 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/14.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 104687202767238038702065537427887975692207502461878137914700194628815080805122 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/15.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4020392706 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/15.lc_ctrl_smoke.4020392706 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 15.lc_ctrl_smoke.4020392706 -covoverwrite' seed=104687202767238038702065537427887975692207502461878137914700194628815080805122 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104687202767238038702065537427887975692207502461878137914700194628815080805122 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/15.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 73776240581804901794570989702944533075581293388180568148804801650751364292693 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/15.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=797859925 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/15.lc_ctrl_state_failure.797859925 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 15.lc_ctrl_state_failure.797859925 -covoverwrite' seed=73776240581804901794570989702944533075581293388180568148804801650751364292693 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73776240581804901794570989702944533075581293388180568148804801650751364292693 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/15.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 56075103176212115130756899429822075310411262164182899777252954540028412608042 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/15.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=41729578 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/15.lc_ctrl_state_post_trans.41729578 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 15.lc_ctrl_state_post_trans.41729578 -covoverwrite' seed=56075103176212115130756899429822075310411262164182899777252954540028412608042 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56075103176212115130756899429822075310411262164182899777252954540028412608042 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/15.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 76840185388808287466380284580325846954894446236760099268047794530950456518243 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/15.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1725933155 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/15.lc_ctrl_prog_failure.1725933155 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 15.lc_ctrl_prog_failure.1725933155 -covoverwrite' seed=76840185388808287466380284580325846954894446236760099268047794530950456518243 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76840185388808287466380284580325846954894446236760099268047794530950456518243 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/15.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 40707080261685329825121862914053186932749164068666231155048192160879009458464 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/15.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=699787552 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/15.lc_ctrl_errors.699787552 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 15.lc_ctrl_errors.699787552 -covoverwrite' seed=40707080261685329825121862914053186932749164068666231155048192160879009458464 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40707080261685329825121862914053186932749164068666231155048192160879009458464 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/15.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 82507576722149064977869754504196397657342942466117918941288938573540744963828 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/15.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=474949364 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/15.lc_ctrl_security_escalation.474949364 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 15.lc_ctrl_security_escalation.474949364 -covoverwrite' seed=82507576722149064977869754504196397657342942466117918941288938573540744963828 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82507576722149064977869754504196397657342942466117918941288938573540744963828 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/15.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 113915336883821539529665745743154159614294971656053229687746261658421119962921 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/15.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3776991017 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/15.lc_ctrl_jtag_smoke.3776991017 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 15.lc_ctrl_jtag_smoke.3776991017 -covoverwrite' seed=113915336883821539529665745743154159614294971656053229687746261658421119962921 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113915336883821539529665745743154159614294971656053229687746261658421119962921 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/15.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 86919450644127059557387501995051704110243998675614453806076258768490335185125 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/15.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3689818341 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/15.lc_ctrl_jtag_state_failure.3689818341 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 15.lc_ctrl_jtag_state_failure.3689818341 -covoverwrite' seed=86919450644127059557387501995051704110243998675614453806076258768490335185125 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86919450644127059557387501995051704110243998675614453806076258768490335185125 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/15.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 66232471746371364417103806183856021626296978117092016893066279951168033555552 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/15.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=285246560 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/15.lc_ctrl_jtag_state_post_trans.285246560 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 15.lc_ctrl_jtag_state_post_trans.285246560 -covoverwrite' seed=66232471746371364417103806183856021626296978117092016893066279951168033555552 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66232471746371364417103806183856021626296978117092016893066279951168033555552 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/15.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 1264598330014340748659453759285220380727690713699066744050385205267396425890 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/15.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1162737826 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/15.lc_ctrl_jtag_prog_failure.1162737826 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 15.lc_ctrl_jtag_prog_failure.1162737826 -covoverwrite' seed=1264598330014340748659453759285220380727690713699066744050385205267396425890 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1264598330014340748659453759285220380727690713699066744050385205267396425890 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/15.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 18896191506363378604129212491302718063064785197113850556764946719670441631501 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/15.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2256297741 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/15.lc_ctrl_jtag_errors.2256297741 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 15.lc_ctrl_jtag_errors.2256297741 -covoverwrite' seed=18896191506363378604129212491302718063064785197113850556764946719670441631501 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18896191506363378604129212491302718063064785197113850556764946719670441631501 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/15.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 1840967258170178910775556580991050593615581719368000771519256505174892984317 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/15.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=271038461 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/15.lc_ctrl_jtag_access.271038461 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 15.lc_ctrl_jtag_access.271038461 -covoverwrite' seed=1840967258170178910775556580991050593615581719368000771519256505174892984317 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1840967258170178910775556580991050593615581719368000771519256505174892984317 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/15.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 26849353287116015131676922135605794115518056533562712037944141766979976287707 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/15.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4164802011 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/15.lc_ctrl_tl_errors.4164802011 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 15.lc_ctrl_tl_errors.4164802011 -covoverwrite' seed=26849353287116015131676922135605794115518056533562712037944141766979976287707 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26849353287116015131676922135605794115518056533562712037944141766979976287707 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/15.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 75623804150007607455532671828633627641822808055885834697864300614865450613507 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/15.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4202871555 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.4202871555 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 15.lc_ctrl_tl_intg_err.4202871555 -covoverwrite' seed=75623804150007607455532671828633627641822808055885834697864300614865450613507 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75623804150007607455532671828633627641822808055885834697864300614865450613507 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/15.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 5008777879516389585009175691723154701247506405500123520872519439477841575693 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/16.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=330284813 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/16.lc_ctrl_smoke.330284813 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 16.lc_ctrl_smoke.330284813 -covoverwrite' seed=5008777879516389585009175691723154701247506405500123520872519439477841575693 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5008777879516389585009175691723154701247506405500123520872519439477841575693 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/16.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 96567131048362834192244430916109375718228726816583634524514351413040840795865 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/16.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1426679513 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/16.lc_ctrl_state_failure.1426679513 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 16.lc_ctrl_state_failure.1426679513 -covoverwrite' seed=96567131048362834192244430916109375718228726816583634524514351413040840795865 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96567131048362834192244430916109375718228726816583634524514351413040840795865 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/16.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 78113486426796733737266547616937991952595424893623064607545735934851793958290 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/16.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2353411474 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/16.lc_ctrl_state_post_trans.2353411474 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 16.lc_ctrl_state_post_trans.2353411474 -covoverwrite' seed=78113486426796733737266547616937991952595424893623064607545735934851793958290 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78113486426796733737266547616937991952595424893623064607545735934851793958290 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/16.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 17947524380270081648254715033229368686615227378458542601076547626340853585381 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/16.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=831100389 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/16.lc_ctrl_prog_failure.831100389 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 16.lc_ctrl_prog_failure.831100389 -covoverwrite' seed=17947524380270081648254715033229368686615227378458542601076547626340853585381 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17947524380270081648254715033229368686615227378458542601076547626340853585381 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/16.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 22444854841030036635683348998000766026721307206486748064120268734764735210630 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/16.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3115787398 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/16.lc_ctrl_errors.3115787398 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 16.lc_ctrl_errors.3115787398 -covoverwrite' seed=22444854841030036635683348998000766026721307206486748064120268734764735210630 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22444854841030036635683348998000766026721307206486748064120268734764735210630 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/16.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 104068607786108697695016362260225275322784666362848487300923110935583256013237 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/16.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4042844597 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/16.lc_ctrl_security_escalation.4042844597 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 16.lc_ctrl_security_escalation.4042844597 -covoverwrite' seed=104068607786108697695016362260225275322784666362848487300923110935583256013237 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104068607786108697695016362260225275322784666362848487300923110935583256013237 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/16.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 3267662258314781838140274122861483670966753740768982539835828456412477686860 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/16.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=229409868 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/16.lc_ctrl_jtag_smoke.229409868 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 16.lc_ctrl_jtag_smoke.229409868 -covoverwrite' seed=3267662258314781838140274122861483670966753740768982539835828456412477686860 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3267662258314781838140274122861483670966753740768982539835828456412477686860 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/16.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 12042941700750761165695150426180390187350137990328611806593200391417476470666 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/16.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1679611786 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/16.lc_ctrl_jtag_state_failure.1679611786 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 16.lc_ctrl_jtag_state_failure.1679611786 -covoverwrite' seed=12042941700750761165695150426180390187350137990328611806593200391417476470666 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12042941700750761165695150426180390187350137990328611806593200391417476470666 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/16.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 13670338903024273198625368847708280938279050163063957345947088083735736593193 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/16.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3567102761 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/16.lc_ctrl_jtag_state_post_trans.3567102761 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 16.lc_ctrl_jtag_state_post_trans.3567102761 -covoverwrite' seed=13670338903024273198625368847708280938279050163063957345947088083735736593193 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13670338903024273198625368847708280938279050163063957345947088083735736593193 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/16.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 47648726345703310818097995578738751371980593382085227649553000414302909877578 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/16.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2942946634 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/16.lc_ctrl_jtag_prog_failure.2942946634 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 16.lc_ctrl_jtag_prog_failure.2942946634 -covoverwrite' seed=47648726345703310818097995578738751371980593382085227649553000414302909877578 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47648726345703310818097995578738751371980593382085227649553000414302909877578 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/16.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 75340677782684575012663287752299362081090280622685440915818796878849134324845 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/16.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4011093101 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/16.lc_ctrl_jtag_errors.4011093101 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 16.lc_ctrl_jtag_errors.4011093101 -covoverwrite' seed=75340677782684575012663287752299362081090280622685440915818796878849134324845 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75340677782684575012663287752299362081090280622685440915818796878849134324845 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/16.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 33526589506224472840325326463550212856139597462262184806863453382875389839438 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/16.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2427930702 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/16.lc_ctrl_jtag_access.2427930702 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 16.lc_ctrl_jtag_access.2427930702 -covoverwrite' seed=33526589506224472840325326463550212856139597462262184806863453382875389839438 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33526589506224472840325326463550212856139597462262184806863453382875389839438 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/16.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 8336953080505840541297912953869889060218062262043092078954238815418378500968 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/16.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2260613992 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/16.lc_ctrl_tl_errors.2260613992 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 16.lc_ctrl_tl_errors.2260613992 -covoverwrite' seed=8336953080505840541297912953869889060218062262043092078954238815418378500968 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8336953080505840541297912953869889060218062262043092078954238815418378500968 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/16.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 5213258459430176448195488989093355947576504986359475875989488782178969048849 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/16.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2201081617 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.2201081617 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 16.lc_ctrl_tl_intg_err.2201081617 -covoverwrite' seed=5213258459430176448195488989093355947576504986359475875989488782178969048849 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5213258459430176448195488989093355947576504986359475875989488782178969048849 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/16.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 29351792284373565477515294020162578026349064186228116069148694365320951880901 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/17.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1990188229 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/17.lc_ctrl_smoke.1990188229 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 17.lc_ctrl_smoke.1990188229 -covoverwrite' seed=29351792284373565477515294020162578026349064186228116069148694365320951880901 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29351792284373565477515294020162578026349064186228116069148694365320951880901 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/17.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 24991723254867340050517263913029135061305610360520574098708120347902685262404 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/17.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=215265860 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/17.lc_ctrl_state_failure.215265860 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 17.lc_ctrl_state_failure.215265860 -covoverwrite' seed=24991723254867340050517263913029135061305610360520574098708120347902685262404 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24991723254867340050517263913029135061305610360520574098708120347902685262404 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/17.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 90575762676619594928946976619898548875582175657550700166028667370215681540567 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/17.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1980744151 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/17.lc_ctrl_state_post_trans.1980744151 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 17.lc_ctrl_state_post_trans.1980744151 -covoverwrite' seed=90575762676619594928946976619898548875582175657550700166028667370215681540567 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90575762676619594928946976619898548875582175657550700166028667370215681540567 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/17.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 73465374166012766056772899393973589379338538607855664092767839841484552147380 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/17.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=544870836 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/17.lc_ctrl_prog_failure.544870836 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 17.lc_ctrl_prog_failure.544870836 -covoverwrite' seed=73465374166012766056772899393973589379338538607855664092767839841484552147380 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73465374166012766056772899393973589379338538607855664092767839841484552147380 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/17.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 17746489097697318639034620274890028545648168418269433250558923125840958159185 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/17.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2525198673 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/17.lc_ctrl_errors.2525198673 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 17.lc_ctrl_errors.2525198673 -covoverwrite' seed=17746489097697318639034620274890028545648168418269433250558923125840958159185 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17746489097697318639034620274890028545648168418269433250558923125840958159185 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/17.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 14715722140717526143166103734515234922409539935823015834432987040634791238397 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/17.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=345742077 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/17.lc_ctrl_security_escalation.345742077 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 17.lc_ctrl_security_escalation.345742077 -covoverwrite' seed=14715722140717526143166103734515234922409539935823015834432987040634791238397 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=14715722140717526143166103734515234922409539935823015834432987040634791238397 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/17.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 40503648781296686333405725917427667666972993695658060810977264890721112301118 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/17.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=521543230 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/17.lc_ctrl_jtag_smoke.521543230 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 17.lc_ctrl_jtag_smoke.521543230 -covoverwrite' seed=40503648781296686333405725917427667666972993695658060810977264890721112301118 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40503648781296686333405725917427667666972993695658060810977264890721112301118 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/17.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 97152610578739706404030845256050991186270145133300427448080328558307958090514 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/17.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3826805522 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/17.lc_ctrl_jtag_state_failure.3826805522 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 17.lc_ctrl_jtag_state_failure.3826805522 -covoverwrite' seed=97152610578739706404030845256050991186270145133300427448080328558307958090514 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97152610578739706404030845256050991186270145133300427448080328558307958090514 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/17.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 9802627755258275233813049792681695439978101101437067644203427865502925269787 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/17.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2739743515 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/17.lc_ctrl_jtag_state_post_trans.2739743515 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 17.lc_ctrl_jtag_state_post_trans.2739743515 -covoverwrite' seed=9802627755258275233813049792681695439978101101437067644203427865502925269787 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9802627755258275233813049792681695439978101101437067644203427865502925269787 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/17.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 35686781505663045742913275255520513283753208470277834721607818268989087538416 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/17.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1510202608 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/17.lc_ctrl_jtag_prog_failure.1510202608 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 17.lc_ctrl_jtag_prog_failure.1510202608 -covoverwrite' seed=35686781505663045742913275255520513283753208470277834721607818268989087538416 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35686781505663045742913275255520513283753208470277834721607818268989087538416 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/17.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 37265035195565425794482777274958970717773012624845500800739426854683556562570 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/17.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3720726154 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/17.lc_ctrl_jtag_errors.3720726154 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 17.lc_ctrl_jtag_errors.3720726154 -covoverwrite' seed=37265035195565425794482777274958970717773012624845500800739426854683556562570 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37265035195565425794482777274958970717773012624845500800739426854683556562570 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/17.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 22182769397566240111248376340074093018466591569037256107586581684409393569135 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/17.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1896963439 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/17.lc_ctrl_jtag_access.1896963439 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 17.lc_ctrl_jtag_access.1896963439 -covoverwrite' seed=22182769397566240111248376340074093018466591569037256107586581684409393569135 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22182769397566240111248376340074093018466591569037256107586581684409393569135 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/17.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 18773137872776608298949225049898501750031026084017126487762196334852343904971 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/17.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1929689803 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1929689803 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 17.lc_ctrl_tl_errors.1929689803 -covoverwrite' seed=18773137872776608298949225049898501750031026084017126487762196334852343904971 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18773137872776608298949225049898501750031026084017126487762196334852343904971 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/17.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 79357440601039066740385492194564427656225443761745982785001400414044272004743 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/17.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4125953671 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.4125953671 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 17.lc_ctrl_tl_intg_err.4125953671 -covoverwrite' seed=79357440601039066740385492194564427656225443761745982785001400414044272004743 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79357440601039066740385492194564427656225443761745982785001400414044272004743 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/17.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 37636433506898434367893783338218188497908616704434450277465833982676855274014 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/18.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3029187102 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/18.lc_ctrl_smoke.3029187102 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 18.lc_ctrl_smoke.3029187102 -covoverwrite' seed=37636433506898434367893783338218188497908616704434450277465833982676855274014 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37636433506898434367893783338218188497908616704434450277465833982676855274014 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/18.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 101355611776004198989282864392792742231905424914307311089544137852829619294864 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/18.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1977455248 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/18.lc_ctrl_state_failure.1977455248 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 18.lc_ctrl_state_failure.1977455248 -covoverwrite' seed=101355611776004198989282864392792742231905424914307311089544137852829619294864 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101355611776004198989282864392792742231905424914307311089544137852829619294864 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/18.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 9898138784178616248878208555483872342212332778720364030027971459766839635305 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/18.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1985703273 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/18.lc_ctrl_state_post_trans.1985703273 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 18.lc_ctrl_state_post_trans.1985703273 -covoverwrite' seed=9898138784178616248878208555483872342212332778720364030027971459766839635305 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9898138784178616248878208555483872342212332778720364030027971459766839635305 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/18.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 61164087200097876424493170594103189733748738948619374778840101457917644621510 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/18.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1161545414 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/18.lc_ctrl_prog_failure.1161545414 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 18.lc_ctrl_prog_failure.1161545414 -covoverwrite' seed=61164087200097876424493170594103189733748738948619374778840101457917644621510 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61164087200097876424493170594103189733748738948619374778840101457917644621510 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/18.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 103504766517192431936805795308588611005107428290367099757840969651850991223799 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/18.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2153890807 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/18.lc_ctrl_errors.2153890807 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 18.lc_ctrl_errors.2153890807 -covoverwrite' seed=103504766517192431936805795308588611005107428290367099757840969651850991223799 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103504766517192431936805795308588611005107428290367099757840969651850991223799 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/18.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 99849472894691490173838389222735997079884053565422411683264929146651986138739 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/18.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3336607347 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/18.lc_ctrl_security_escalation.3336607347 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 18.lc_ctrl_security_escalation.3336607347 -covoverwrite' seed=99849472894691490173838389222735997079884053565422411683264929146651986138739 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99849472894691490173838389222735997079884053565422411683264929146651986138739 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/18.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 84030974068212129278591718980979767415433404532746172867017340991166349859589 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/18.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=257448709 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/18.lc_ctrl_jtag_smoke.257448709 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 18.lc_ctrl_jtag_smoke.257448709 -covoverwrite' seed=84030974068212129278591718980979767415433404532746172867017340991166349859589 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84030974068212129278591718980979767415433404532746172867017340991166349859589 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/18.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 10790625725845345430745264847461089128742052723220489867937582087539311085316 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/18.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3199567620 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/18.lc_ctrl_jtag_state_failure.3199567620 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 18.lc_ctrl_jtag_state_failure.3199567620 -covoverwrite' seed=10790625725845345430745264847461089128742052723220489867937582087539311085316 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10790625725845345430745264847461089128742052723220489867937582087539311085316 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/18.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 39953828963570831909819394439749916232733318047446079900748530826085136284340 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/18.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1941912244 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/18.lc_ctrl_jtag_state_post_trans.1941912244 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 18.lc_ctrl_jtag_state_post_trans.1941912244 -covoverwrite' seed=39953828963570831909819394439749916232733318047446079900748530826085136284340 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39953828963570831909819394439749916232733318047446079900748530826085136284340 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/18.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 18165595215905977723089633765270339967524310165443297281935374456550682007411 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/18.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4094957427 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/18.lc_ctrl_jtag_prog_failure.4094957427 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 18.lc_ctrl_jtag_prog_failure.4094957427 -covoverwrite' seed=18165595215905977723089633765270339967524310165443297281935374456550682007411 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18165595215905977723089633765270339967524310165443297281935374456550682007411 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/18.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 109601450366322388488818472530155397933888243123375010764440486127575499511862 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/18.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1217108022 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/18.lc_ctrl_jtag_errors.1217108022 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 18.lc_ctrl_jtag_errors.1217108022 -covoverwrite' seed=109601450366322388488818472530155397933888243123375010764440486127575499511862 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109601450366322388488818472530155397933888243123375010764440486127575499511862 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/18.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 83277592106230479550174869683542087613540858277224878905640949612148330451541 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/18.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2738999893 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/18.lc_ctrl_jtag_access.2738999893 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 18.lc_ctrl_jtag_access.2738999893 -covoverwrite' seed=83277592106230479550174869683542087613540858277224878905640949612148330451541 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83277592106230479550174869683542087613540858277224878905640949612148330451541 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/18.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 4464760967606647399819811671887992187460799232434238402866911082995275731724 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/18.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=198644492 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/18.lc_ctrl_tl_errors.198644492 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 18.lc_ctrl_tl_errors.198644492 -covoverwrite' seed=4464760967606647399819811671887992187460799232434238402866911082995275731724 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4464760967606647399819811671887992187460799232434238402866911082995275731724 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/18.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 20277038883595367384827374210246053669516777082793859699728034264837114496158 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/18.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1522467998 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1522467998 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 18.lc_ctrl_tl_intg_err.1522467998 -covoverwrite' seed=20277038883595367384827374210246053669516777082793859699728034264837114496158 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20277038883595367384827374210246053669516777082793859699728034264837114496158 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/18.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_smoke 75780625979149676174456607072383493905110387298143365611289081614000477185966 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/19.lc_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=937961390 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/19.lc_ctrl_smoke.937961390 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 19.lc_ctrl_smoke.937961390 -covoverwrite' seed=75780625979149676174456607072383493905110387298143365611289081614000477185966 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75780625979149676174456607072383493905110387298143365611289081614000477185966 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/19.lc_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_failure 64645662486135729797379236965815778925326263008475295870163410687663712136898 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/19.lc_ctrl_state_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1017016002 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/19.lc_ctrl_state_failure.1017016002 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 19.lc_ctrl_state_failure.1017016002 -covoverwrite' seed=64645662486135729797379236965815778925326263008475295870163410687663712136898 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64645662486135729797379236965815778925326263008475295870163410687663712136898 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/19.lc_ctrl_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_state_post_trans 110420213215493153776652058180879131364035197253888407627633245555768039493413 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/19.lc_ctrl_state_post_trans/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2779696933 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/19.lc_ctrl_state_post_trans.2779696933 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 19.lc_ctrl_state_post_trans.2779696933 -covoverwrite' seed=110420213215493153776652058180879131364035197253888407627633245555768039493413 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110420213215493153776652058180879131364035197253888407627633245555768039493413 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/19.lc_ctrl_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_prog_failure 17750701377196291096514025690744704709424996268571308335203717604461058904629 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/19.lc_ctrl_prog_failure/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3394425397 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/19.lc_ctrl_prog_failure.3394425397 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 19.lc_ctrl_prog_failure.3394425397 -covoverwrite' seed=17750701377196291096514025690744704709424996268571308335203717604461058904629 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17750701377196291096514025690744704709424996268571308335203717604461058904629 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/19.lc_ctrl_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_errors 13655104491158059761924206057610326337182987004587434556846771442457341352938 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/19.lc_ctrl_errors/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2088000490 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/19.lc_ctrl_errors.2088000490 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 19.lc_ctrl_errors.2088000490 -covoverwrite' seed=13655104491158059761924206057610326337182987004587434556846771442457341352938 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13655104491158059761924206057610326337182987004587434556846771442457341352938 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/19.lc_ctrl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_security_escalation 1885831378103366192922034004747809852493355622508542997717079851317901470309 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/19.lc_ctrl_security_escalation/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1418799717 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_security_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/19.lc_ctrl_security_escalation.1418799717 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 19.lc_ctrl_security_escalation.1418799717 -covoverwrite' seed=1885831378103366192922034004747809852493355622508542997717079851317901470309 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1885831378103366192922034004747809852493355622508542997717079851317901470309 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/19.lc_ctrl_security_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_security_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_smoke 91688930630753281721872842072661876828056477616720831079034500216230094614378 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/19.lc_ctrl_jtag_smoke/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3746869098 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/19.lc_ctrl_jtag_smoke.3746869098 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 19.lc_ctrl_jtag_smoke.3746869098 -covoverwrite' seed=91688930630753281721872842072661876828056477616720831079034500216230094614378 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91688930630753281721872842072661876828056477616720831079034500216230094614378 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/19.lc_ctrl_jtag_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_failure 62076066750745462292642551854330943938907735592515717079880290486703405818692 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/19.lc_ctrl_jtag_state_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3768214340 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/19.lc_ctrl_jtag_state_failure.3768214340 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 19.lc_ctrl_jtag_state_failure.3768214340 -covoverwrite' seed=62076066750745462292642551854330943938907735592515717079880290486703405818692 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62076066750745462292642551854330943938907735592515717079880290486703405818692 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/19.lc_ctrl_jtag_state_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_state_post_trans 107533190611676771201005872934594330926955630122743889908067904420870370996041 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/19.lc_ctrl_jtag_state_post_trans/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3247812425 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_state_post_trans_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/19.lc_ctrl_jtag_state_post_trans.3247812425 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 19.lc_ctrl_jtag_state_post_trans.3247812425 -covoverwrite' seed=107533190611676771201005872934594330926955630122743889908067904420870370996041 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107533190611676771201005872934594330926955630122743889908067904420870370996041 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/19.lc_ctrl_jtag_state_post_trans/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_state_post_trans_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_prog_failure 61995430719564682831130409749642279751587237531912224219997922618349095586178 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/19.lc_ctrl_jtag_prog_failure/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2355988866 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_prog_failure_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/19.lc_ctrl_jtag_prog_failure.2355988866 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 19.lc_ctrl_jtag_prog_failure.2355988866 -covoverwrite' seed=61995430719564682831130409749642279751587237531912224219997922618349095586178 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61995430719564682831130409749642279751587237531912224219997922618349095586178 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/19.lc_ctrl_jtag_prog_failure/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_prog_failure_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_errors 82440191295634109307458290258254645265659190231278898878230876704859688135919 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/19.lc_ctrl_jtag_errors/latest run_opts='+jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=623504623 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_lc_errors_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/19.lc_ctrl_jtag_errors.623504623 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 19.lc_ctrl_jtag_errors.623504623 -covoverwrite' seed=82440191295634109307458290258254645265659190231278898878230876704859688135919 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82440191295634109307458290258254645265659190231278898878230876704859688135919 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/19.lc_ctrl_jtag_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_lc_errors_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 25109474077878273137721460094257783597930634389944678928482722223609078165935 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/19.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=399061423 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/19.lc_ctrl_jtag_access.399061423 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 19.lc_ctrl_jtag_access.399061423 -covoverwrite' seed=25109474077878273137721460094257783597930634389944678928482722223609078165935 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25109474077878273137721460094257783597930634389944678928482722223609078165935 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/19.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 114898702745422421260064628807114862033969691801331836039476322994145923078125 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/19.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=144087021 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/19.lc_ctrl_tl_errors.144087021 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 19.lc_ctrl_tl_errors.144087021 -covoverwrite' seed=114898702745422421260064628807114862033969691801331836039476322994145923078125 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114898702745422421260064628807114862033969691801331836039476322994145923078125 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/19.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 58574209989785439629422055971982490317793978353542774588292226663244960001089 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/19.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3003804737 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.3003804737 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 19.lc_ctrl_tl_intg_err.3003804737 -covoverwrite' seed=58574209989785439629422055971982490317793978353542774588292226663244960001089 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58574209989785439629422055971982490317793978353542774588292226663244960001089 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/19.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 43439984647817971475750946240088395221088283019431247552578380673118692806840 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/20.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3875639480 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/20.lc_ctrl_jtag_access.3875639480 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 20.lc_ctrl_jtag_access.3875639480 -covoverwrite' seed=43439984647817971475750946240088395221088283019431247552578380673118692806840 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43439984647817971475750946240088395221088283019431247552578380673118692806840 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/20.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 107364096316303057311635842794892681778758850913123857966310956237974979005731 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/20.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2805255459 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/20.lc_ctrl_tl_errors.2805255459 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 20.lc_ctrl_tl_errors.2805255459 -covoverwrite' seed=107364096316303057311635842794892681778758850913123857966310956237974979005731 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107364096316303057311635842794892681778758850913123857966310956237974979005731 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/20.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 19162045431191892552972230870652932942989879615670519666869576847922958041824 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/20.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3943301856 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/20.lc_ctrl_tl_intg_err.3943301856 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 20.lc_ctrl_tl_intg_err.3943301856 -covoverwrite' seed=19162045431191892552972230870652932942989879615670519666869576847922958041824 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19162045431191892552972230870652932942989879615670519666869576847922958041824 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/20.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 83308143689348405476715995823604926107306049244566812260279223229767852076074 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/21.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2895752234 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/21.lc_ctrl_jtag_access.2895752234 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 21.lc_ctrl_jtag_access.2895752234 -covoverwrite' seed=83308143689348405476715995823604926107306049244566812260279223229767852076074 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83308143689348405476715995823604926107306049244566812260279223229767852076074 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/21.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 2426112843012732906044150882549261001029150155830222421515248995759313250431 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/21.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1371400319 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/21.lc_ctrl_tl_errors.1371400319 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 21.lc_ctrl_tl_errors.1371400319 -covoverwrite' seed=2426112843012732906044150882549261001029150155830222421515248995759313250431 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2426112843012732906044150882549261001029150155830222421515248995759313250431 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/21.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 102589650515580118937693554986141398485682623120427352476284928843996104783549 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/21.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1946449597 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/21.lc_ctrl_tl_intg_err.1946449597 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 21.lc_ctrl_tl_intg_err.1946449597 -covoverwrite' seed=102589650515580118937693554986141398485682623120427352476284928843996104783549 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102589650515580118937693554986141398485682623120427352476284928843996104783549 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/21.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 53737956992426447842972218039495571746416303178943738142557676234614165611212 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/22.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1702765260 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/22.lc_ctrl_jtag_access.1702765260 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 22.lc_ctrl_jtag_access.1702765260 -covoverwrite' seed=53737956992426447842972218039495571746416303178943738142557676234614165611212 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53737956992426447842972218039495571746416303178943738142557676234614165611212 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/22.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 10431085537294604885258181437944024282165511538434461933949691927712040526149 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/22.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=775987525 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/22.lc_ctrl_tl_errors.775987525 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 22.lc_ctrl_tl_errors.775987525 -covoverwrite' seed=10431085537294604885258181437944024282165511538434461933949691927712040526149 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10431085537294604885258181437944024282165511538434461933949691927712040526149 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/22.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 103054238204664716605693734513609661392001344296530439618970371320784776805259 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/22.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1753168779 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/22.lc_ctrl_tl_intg_err.1753168779 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 22.lc_ctrl_tl_intg_err.1753168779 -covoverwrite' seed=103054238204664716605693734513609661392001344296530439618970371320784776805259 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103054238204664716605693734513609661392001344296530439618970371320784776805259 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/22.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 105297717614000101419006135263249325316443397476335760798921408419553907836155 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/23.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1535378683 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/23.lc_ctrl_jtag_access.1535378683 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 23.lc_ctrl_jtag_access.1535378683 -covoverwrite' seed=105297717614000101419006135263249325316443397476335760798921408419553907836155 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105297717614000101419006135263249325316443397476335760798921408419553907836155 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/23.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 44770187989437927667575827149695537912982446796476301765557368975388877062088 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/23.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1855258568 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/23.lc_ctrl_tl_errors.1855258568 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 23.lc_ctrl_tl_errors.1855258568 -covoverwrite' seed=44770187989437927667575827149695537912982446796476301765557368975388877062088 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44770187989437927667575827149695537912982446796476301765557368975388877062088 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/23.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 35762769518054984179388762698951283643545602580117730116117631259724489927266 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/23.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2054138466 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/23.lc_ctrl_tl_intg_err.2054138466 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 23.lc_ctrl_tl_intg_err.2054138466 -covoverwrite' seed=35762769518054984179388762698951283643545602580117730116117631259724489927266 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35762769518054984179388762698951283643545602580117730116117631259724489927266 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/23.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 13743670147908303874148929712492346805502718325427985799751952654425289033565 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/24.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2580186973 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/24.lc_ctrl_jtag_access.2580186973 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 24.lc_ctrl_jtag_access.2580186973 -covoverwrite' seed=13743670147908303874148929712492346805502718325427985799751952654425289033565 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13743670147908303874148929712492346805502718325427985799751952654425289033565 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/24.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_errors 104804327963626067055531413661533150510181362412612045274106794536636612034777 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/24.lc_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=99827929 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/24.lc_ctrl_tl_errors.99827929 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 24.lc_ctrl_tl_errors.99827929 -covoverwrite' seed=104804327963626067055531413661533150510181362412612045274106794536636612034777 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104804327963626067055531413661533150510181362412612045274106794536636612034777 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/24.lc_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_tl_intg_err 94121627644218012912533865758396293799085427792979839760537004394906900540065 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/24.lc_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3949243041 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/cover_reg_top/24.lc_ctrl_tl_intg_err.3949243041 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope cover_reg_top -covtest 24.lc_ctrl_tl_intg_err.3949243041 -covoverwrite' seed=94121627644218012912533865758396293799085427792979839760537004394906900540065 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94121627644218012912533865758396293799085427792979839760537004394906900540065 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/24.lc_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 10175172116475326849708807269547277806853851810637172215680790595015476094552 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/25.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=3768952408 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/25.lc_ctrl_jtag_access.3768952408 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 25.lc_ctrl_jtag_access.3768952408 -covoverwrite' seed=10175172116475326849708807269547277806853851810637172215680790595015476094552 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10175172116475326849708807269547277806853851810637172215680790595015476094552 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/25.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 96200284846881895383337242255135198001285866377217026946897517883052751137024 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/26.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4111542528 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/26.lc_ctrl_jtag_access.4111542528 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 26.lc_ctrl_jtag_access.4111542528 -covoverwrite' seed=96200284846881895383337242255135198001285866377217026946897517883052751137024 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96200284846881895383337242255135198001285866377217026946897517883052751137024 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/26.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 81799701121417404232263159163424928199559914914701726810137551437657702995495 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/27.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=535631399 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/27.lc_ctrl_jtag_access.535631399 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 27.lc_ctrl_jtag_access.535631399 -covoverwrite' seed=81799701121417404232263159163424928199559914914701726810137551437657702995495 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81799701121417404232263159163424928199559914914701726810137551437657702995495 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/27.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 60092560575227344069947375986042133501353124486616906279540047641830660091055 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/28.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1514253487 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/28.lc_ctrl_jtag_access.1514253487 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 28.lc_ctrl_jtag_access.1514253487 -covoverwrite' seed=60092560575227344069947375986042133501353124486616906279540047641830660091055 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60092560575227344069947375986042133501353124486616906279540047641830660091055 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/28.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 70671532972908837411935864694233154436621478728886398814861066722101605005820 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/29.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4142496252 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/29.lc_ctrl_jtag_access.4142496252 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 29.lc_ctrl_jtag_access.4142496252 -covoverwrite' seed=70671532972908837411935864694233154436621478728886398814861066722101605005820 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70671532972908837411935864694233154436621478728886398814861066722101605005820 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/29.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 86745576496273497729655269354238732683299329210530571884913164225092691102536 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/30.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2956135240 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/30.lc_ctrl_jtag_access.2956135240 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 30.lc_ctrl_jtag_access.2956135240 -covoverwrite' seed=86745576496273497729655269354238732683299329210530571884913164225092691102536 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86745576496273497729655269354238732683299329210530571884913164225092691102536 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/30.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 74298218614233051172088095642818165197544247721166304525361932151014862641618 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/31.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1074551250 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/31.lc_ctrl_jtag_access.1074551250 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 31.lc_ctrl_jtag_access.1074551250 -covoverwrite' seed=74298218614233051172088095642818165197544247721166304525361932151014862641618 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74298218614233051172088095642818165197544247721166304525361932151014862641618 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/31.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 114830339529070399012510609067525154691229313061451421698102177689310370389485 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/32.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4028292589 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/32.lc_ctrl_jtag_access.4028292589 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 32.lc_ctrl_jtag_access.4028292589 -covoverwrite' seed=114830339529070399012510609067525154691229313061451421698102177689310370389485 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114830339529070399012510609067525154691229313061451421698102177689310370389485 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/32.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 102771467478250664914366028303754666966039095670923623349281392663408757151505 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/33.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=925341457 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/33.lc_ctrl_jtag_access.925341457 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 33.lc_ctrl_jtag_access.925341457 -covoverwrite' seed=102771467478250664914366028303754666966039095670923623349281392663408757151505 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102771467478250664914366028303754666966039095670923623349281392663408757151505 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/33.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 4087904967558055851796215741649468559648653902796659394591849126221601836997 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/34.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=489164741 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/34.lc_ctrl_jtag_access.489164741 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 34.lc_ctrl_jtag_access.489164741 -covoverwrite' seed=4087904967558055851796215741649468559648653902796659394591849126221601836997 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4087904967558055851796215741649468559648653902796659394591849126221601836997 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/34.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 30278203194850698807195660658527751094558640246393496492602261444696634239991 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/35.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=334703607 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/35.lc_ctrl_jtag_access.334703607 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 35.lc_ctrl_jtag_access.334703607 -covoverwrite' seed=30278203194850698807195660658527751094558640246393496492602261444696634239991 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30278203194850698807195660658527751094558640246393496492602261444696634239991 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/35.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 83435099274977322150584107881042154686508450630506638529551452624969577168856 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/36.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2667216856 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/36.lc_ctrl_jtag_access.2667216856 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 36.lc_ctrl_jtag_access.2667216856 -covoverwrite' seed=83435099274977322150584107881042154686508450630506638529551452624969577168856 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83435099274977322150584107881042154686508450630506638529551452624969577168856 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/36.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 99790232718185173187427821370438634529566590607664376678282936258230806842718 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/37.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2033126750 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/37.lc_ctrl_jtag_access.2033126750 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 37.lc_ctrl_jtag_access.2033126750 -covoverwrite' seed=99790232718185173187427821370438634529566590607664376678282936258230806842718 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99790232718185173187427821370438634529566590607664376678282936258230806842718 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/37.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 93637084485625064506908230503352372475136892556120159029154334963255892769918 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/38.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=563346558 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/38.lc_ctrl_jtag_access.563346558 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 38.lc_ctrl_jtag_access.563346558 -covoverwrite' seed=93637084485625064506908230503352372475136892556120159029154334963255892769918 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93637084485625064506908230503352372475136892556120159029154334963255892769918 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/38.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 91893340284217703299768024918547561621766980028129132503770221315050211092971 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/39.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1785702891 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/39.lc_ctrl_jtag_access.1785702891 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 39.lc_ctrl_jtag_access.1785702891 -covoverwrite' seed=91893340284217703299768024918547561621766980028129132503770221315050211092971 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91893340284217703299768024918547561621766980028129132503770221315050211092971 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/39.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 180076896537218414954514694969187026643271031239795751768859720057707671595 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/40.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4233211947 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/40.lc_ctrl_jtag_access.4233211947 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 40.lc_ctrl_jtag_access.4233211947 -covoverwrite' seed=180076896537218414954514694969187026643271031239795751768859720057707671595 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=180076896537218414954514694969187026643271031239795751768859720057707671595 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/40.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 34754795110040164091774954538655661711117984546282572994521282118795516982451 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/41.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2667852979 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/41.lc_ctrl_jtag_access.2667852979 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 41.lc_ctrl_jtag_access.2667852979 -covoverwrite' seed=34754795110040164091774954538655661711117984546282572994521282118795516982451 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34754795110040164091774954538655661711117984546282572994521282118795516982451 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/41.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 16165658216987302878717458660131101586757858639187188683044422906133663869400 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/42.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2087610840 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/42.lc_ctrl_jtag_access.2087610840 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 42.lc_ctrl_jtag_access.2087610840 -covoverwrite' seed=16165658216987302878717458660131101586757858639187188683044422906133663869400 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16165658216987302878717458660131101586757858639187188683044422906133663869400 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/42.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 3896455699932847421096740051074145167182203102089329299934624185179766333387 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/43.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=4139851723 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/43.lc_ctrl_jtag_access.4139851723 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 43.lc_ctrl_jtag_access.4139851723 -covoverwrite' seed=3896455699932847421096740051074145167182203102089329299934624185179766333387 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3896455699932847421096740051074145167182203102089329299934624185179766333387 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/43.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 50148047192704095063079489217854343058014571342807544715810638958572482455022 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/44.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=373941742 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/44.lc_ctrl_jtag_access.373941742 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 44.lc_ctrl_jtag_access.373941742 -covoverwrite' seed=50148047192704095063079489217854343058014571342807544715810638958572482455022 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50148047192704095063079489217854343058014571342807544715810638958572482455022 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/44.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 56209764503413442111114514026178173425785463369704216251886951097038373769031 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/45.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=1378471751 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/45.lc_ctrl_jtag_access.1378471751 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 45.lc_ctrl_jtag_access.1378471751 -covoverwrite' seed=56209764503413442111114514026178173425785463369704216251886951097038373769031 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56209764503413442111114514026178173425785463369704216251886951097038373769031 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/45.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 83094592013676617704313664780752822932195768307568967720793162655342994781011 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/46.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2177495891 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/46.lc_ctrl_jtag_access.2177495891 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 46.lc_ctrl_jtag_access.2177495891 -covoverwrite' seed=83094592013676617704313664780752822932195768307568967720793162655342994781011 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83094592013676617704313664780752822932195768307568967720793162655342994781011 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/46.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 31175542965323665955175252460774140777268904511402957384479706277880847215731 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/47.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=2847485043 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/47.lc_ctrl_jtag_access.2847485043 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 47.lc_ctrl_jtag_access.2847485043 -covoverwrite' seed=31175542965323665955175252460774140777268904511402957384479706277880847215731 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31175542965323665955175252460774140777268904511402957384479706277880847215731 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/47.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 25581652993018971466504845823670811962752914521339296357400864017000770904914 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/48.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=205071186 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/48.lc_ctrl_jtag_access.205071186 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 48.lc_ctrl_jtag_access.205071186 -covoverwrite' seed=25581652993018971466504845823670811962752914521339296357400864017000770904914 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25581652993018971466504845823670811962752914521339296357400864017000770904914 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/48.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
lc_ctrl_jtag_access 11699815342249175172704443995197144275942741071555419018236804810445268349761 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/49.lc_ctrl_jtag_access/latest run_opts='+create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/default/xcelium.d -r tb +SVSEED=808350529 +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_jtag_access_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage/default/49.lc_ctrl_jtag_access.808350529 -covworkdir /nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/coverage -covscope default -covtest 49.lc_ctrl_jtag_access.808350529 -covoverwrite' seed=11699815342249175172704443995197144275942741071555419018236804810445268349761 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11699815342249175172704443995197144275942741071555419018236804810445268349761 --run-dir=/nightly/current_run/scratch/master/lc_ctrl_volatile_unlock_enabled-sim-xcelium/49.lc_ctrl_jtag_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=lc_ctrl_base_test uvm_test_seq=lc_ctrl_jtag_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
Job timed out after * minutes 10 test runs
lc_ctrl_stress_all 7971002351649033924027764817153550972210718583701353991036767809253115522499 None
lc_ctrl_stress_all 96331252409392269429524532090558788509799560208050264151249185334761443113479 None
lc_ctrl_stress_all 79599887962982908776336816635628015935989052891327510740445310418808242374589 None
lc_ctrl_stress_all 48133367850859886596641261970600176973061766227224000111017438100884131057068 None
lc_ctrl_stress_all 47640077534425926526779764131559683749448758695136184108753287632038711648077 None
lc_ctrl_stress_all 54624440303723894135713315267467083300826182239274969410721674314575031429226 None
lc_ctrl_stress_all 102138942216059428436060831075579838208167312354271759265486723093024192811577 None
lc_ctrl_stress_all 112905334500812286277514154060856528642199584026160174056796814354705339983483 None
lc_ctrl_stress_all 39623037976026655306512680094877102517577610887454561834387744428013858650548 None
lc_ctrl_stress_all 71201618120122991144437606091086538758955874867676571881030036897932947463220 None
Job cancelled because all of its dependencies failed or were killed. 1 test run
lc_ctrl None None
Job cancelled because one of its dependencies failed or was killed. 1 test run
lc_ctrl None None