Simulation Results: mbx

 
28/08/2026 21:54:34 DVSim: v1.49.0 sha: a099412 json Branch: master Tool: xcelium [unknown]
Validation stages
V1
0.00%
V2
0.00%
V2S
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_smoke 0 2 0.00
mbx_smoke 0.949s 0.000us 0 2 0.00
csr_hw_reset 0 1 0.00
mbx_csr_hw_reset 0.881s 0.000us 0 1 0.00
csr_rw 0 5 0.00
mbx_csr_rw 1.646s 0.000us 0 5 0.00
csr_bit_bash 0 1 0.00
mbx_csr_bit_bash 0.888s 0.000us 0 1 0.00
csr_aliasing 0 1 0.00
mbx_csr_aliasing 0.832s 0.000us 0 1 0.00
csr_mem_rw_with_rand_reset 0 5 0.00
mbx_csr_mem_rw_with_rand_reset 0.939s 0.000us 0 5 0.00
regwen_csr_and_corresponding_lockable_csr 0 6 0.00
mbx_csr_rw 1.646s 0.000us 0 5 0.00
mbx_csr_aliasing 0.832s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
mbx_stress 0 2 0.00
mbx_stress 1.555s 0.000us 0 2 0.00
mbx_max_activity 0 2 0.00
mbx_stress_zero_delays 0.899s 0.000us 0 2 0.00
mbx_imbx_oob 0 2 0.00
mbx_imbx_oob 0.888s 0.000us 0 2 0.00
mbx_doe_intr_msg 0 5 0.00
mbx_doe_intr_msg 0.920s 0.000us 0 5 0.00
alert_test 0 10 0.00
mbx_alert_test 1.629s 0.000us 0 10 0.00
intr_test 0 10 0.00
mbx_intr_test 1.513s 0.000us 0 10 0.00
tl_d_oob_addr_access 0 25 0.00
mbx_tl_errors 1.686s 0.000us 0 25 0.00
tl_d_illegal_access 0 25 0.00
mbx_tl_errors 1.686s 0.000us 0 25 0.00
tl_d_outstanding_access 0 12 0.00
mbx_csr_hw_reset 0.881s 0.000us 0 1 0.00
mbx_csr_rw 1.646s 0.000us 0 5 0.00
mbx_csr_aliasing 0.832s 0.000us 0 1 0.00
mbx_same_csr_outstanding 1.626s 0.000us 0 5 0.00
tl_d_partial_access 0 12 0.00
mbx_csr_hw_reset 0.881s 0.000us 0 1 0.00
mbx_csr_rw 1.646s 0.000us 0 5 0.00
mbx_csr_aliasing 0.832s 0.000us 0 1 0.00
mbx_same_csr_outstanding 1.626s 0.000us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 30 0.00
mbx_tl_intg_err 1.652s 0.000us 0 25 0.00
mbx_sec_cm 0.984s 0.000us 0 5 0.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 106 test runs
mbx_smoke 112122518911658813296312169724205343427982875630010431493431239239275734681788 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/default/xcelium.d -r tb +SVSEED=3103312060 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/default/0.mbx_smoke.3103312060 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope default -covtest 0.mbx_smoke.3103312060 -covoverwrite' seed=112122518911658813296312169724205343427982875630010431493431239239275734681788 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112122518911658813296312169724205343427982875630010431493431239239275734681788 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_stress 98126680035807372206467617091487051645544018896412600303075125678339541596721 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/default/xcelium.d -r tb +SVSEED=4060248625 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_stress_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/default/0.mbx_stress.4060248625 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope default -covtest 0.mbx_stress.4060248625 -covoverwrite' seed=98126680035807372206467617091487051645544018896412600303075125678339541596721 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98126680035807372206467617091487051645544018896412600303075125678339541596721 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_stress_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_stress_zero_delays 88655463548501241935797545665006733610572141096630015078048443385010031001568 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/default/xcelium.d -r tb +SVSEED=3693182944 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_stress_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/default/0.mbx_stress_zero_delays.3693182944 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope default -covtest 0.mbx_stress_zero_delays.3693182944 -covoverwrite' seed=88655463548501241935797545665006733610572141096630015078048443385010031001568 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88655463548501241935797545665006733610572141096630015078048443385010031001568 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_stress_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_stress_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_imbx_oob 88240588405408824851594172746952945612251623636096576391125138572804801040039 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_imbx_oob/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/default/xcelium.d -r tb +SVSEED=1474694823 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_imbx_oob_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/default/0.mbx_imbx_oob.1474694823 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope default -covtest 0.mbx_imbx_oob.1474694823 -covoverwrite' seed=88240588405408824851594172746952945612251623636096576391125138572804801040039 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88240588405408824851594172746952945612251623636096576391125138572804801040039 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_imbx_oob/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_imbx_oob_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_doe_intr_msg 5079266238419155716993862886467976926458145369137769065845848485838581522008 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_doe_intr_msg/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/default/xcelium.d -r tb +SVSEED=38657624 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_doe_intr_msg_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/default/0.mbx_doe_intr_msg.38657624 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope default -covtest 0.mbx_doe_intr_msg.38657624 -covoverwrite' seed=5079266238419155716993862886467976926458145369137769065845848485838581522008 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5079266238419155716993862886467976926458145369137769065845848485838581522008 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_doe_intr_msg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_doe_intr_msg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_errors 87343673628203307014567198398086886371718047868120852275298692267722593982317 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=49731437 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/0.mbx_tl_errors.49731437 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.mbx_tl_errors.49731437 -covoverwrite' seed=87343673628203307014567198398086886371718047868120852275298692267722593982317 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87343673628203307014567198398086886371718047868120852275298692267722593982317 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_intg_err 103507232805283632620747708983581667166940025308754949278848864662788617163216 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=414160 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/0.mbx_tl_intg_err.414160 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.mbx_tl_intg_err.414160 -covoverwrite' seed=103507232805283632620747708983581667166940025308754949278848864662788617163216 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103507232805283632620747708983581667166940025308754949278848864662788617163216 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_sec_cm 78149618827173082091682415787461775785995631341047582343850453101391382724352 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/default/xcelium.d -r tb +SVSEED=2298625792 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/default/0.mbx_sec_cm.2298625792 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope default -covtest 0.mbx_sec_cm.2298625792 -covoverwrite' seed=78149618827173082091682415787461775785995631341047582343850453101391382724352 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78149618827173082091682415787461775785995631341047582343850453101391382724352 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_intr_test 79519097660403587705439688946407374579538586398357662542496713391351650449620 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2608199892 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/0.mbx_intr_test.2608199892 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.mbx_intr_test.2608199892 -covoverwrite' seed=79519097660403587705439688946407374579538586398357662542496713391351650449620 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79519097660403587705439688946407374579538586398357662542496713391351650449620 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_csr_hw_reset 106892559739254919941997177112959434289920350332310932447484027165653020382881 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_csr_hw_reset/latest run_opts='+csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3234797217 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/0.mbx_csr_hw_reset.3234797217 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.mbx_csr_hw_reset.3234797217 -covoverwrite' seed=106892559739254919941997177112959434289920350332310932447484027165653020382881 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106892559739254919941997177112959434289920350332310932447484027165653020382881 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_csr_rw 67838974091002458498385547794792672935287820509201155570238854888868282349333 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2795484949 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/0.mbx_csr_rw.2795484949 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.mbx_csr_rw.2795484949 -covoverwrite' seed=67838974091002458498385547794792672935287820509201155570238854888868282349333 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67838974091002458498385547794792672935287820509201155570238854888868282349333 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_csr_bit_bash 50857281295701051421744884105325415625603789696163044737658697845845203711292 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_csr_bit_bash/latest run_opts='+csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3707860284 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/0.mbx_csr_bit_bash.3707860284 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.mbx_csr_bit_bash.3707860284 -covoverwrite' seed=50857281295701051421744884105325415625603789696163044737658697845845203711292 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50857281295701051421744884105325415625603789696163044737658697845845203711292 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_csr_aliasing 28538521726719376781359628749014869581750899316332381001652191141419273539035 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_csr_aliasing/latest run_opts='+csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1543097819 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/0.mbx_csr_aliasing.1543097819 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.mbx_csr_aliasing.1543097819 -covoverwrite' seed=28538521726719376781359628749014869581750899316332381001652191141419273539035 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28538521726719376781359628749014869581750899316332381001652191141419273539035 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_same_csr_outstanding 66100572292433405037915652807210107412967403132660713369268262582461163255426 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=473052802 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/0.mbx_same_csr_outstanding.473052802 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.mbx_same_csr_outstanding.473052802 -covoverwrite' seed=66100572292433405037915652807210107412967403132660713369268262582461163255426 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66100572292433405037915652807210107412967403132660713369268262582461163255426 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_csr_mem_rw_with_rand_reset 3665945821405295500076992063287509858844886263916252525849386861409765441432 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=388251544 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/0.mbx_csr_mem_rw_with_rand_reset.388251544 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.mbx_csr_mem_rw_with_rand_reset.388251544 -covoverwrite' seed=3665945821405295500076992063287509858844886263916252525849386861409765441432 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3665945821405295500076992063287509858844886263916252525849386861409765441432 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_alert_test 83736446672410004365444172649923946991948538962766063432489233303890366584843 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/default/xcelium.d -r tb +SVSEED=2970114059 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/default/0.mbx_alert_test.2970114059 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope default -covtest 0.mbx_alert_test.2970114059 -covoverwrite' seed=83736446672410004365444172649923946991948538962766063432489233303890366584843 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83736446672410004365444172649923946991948538962766063432489233303890366584843 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/0.mbx_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_smoke 6983860074211290588039020991775265507657082644902204812054851997809022153181 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/default/xcelium.d -r tb +SVSEED=1925525981 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/default/1.mbx_smoke.1925525981 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope default -covtest 1.mbx_smoke.1925525981 -covoverwrite' seed=6983860074211290588039020991775265507657082644902204812054851997809022153181 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6983860074211290588039020991775265507657082644902204812054851997809022153181 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_stress 2535968049332218423934124167325049545353327177710234578420165224841169644884 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_stress/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/default/xcelium.d -r tb +SVSEED=1028435284 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_stress_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/default/1.mbx_stress.1028435284 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope default -covtest 1.mbx_stress.1028435284 -covoverwrite' seed=2535968049332218423934124167325049545353327177710234578420165224841169644884 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2535968049332218423934124167325049545353327177710234578420165224841169644884 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_stress/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_stress_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_stress_zero_delays 72794632088821178504631755377888182929404508502993570110697579230093302505148 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_stress_zero_delays/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/default/xcelium.d -r tb +SVSEED=3162971836 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_stress_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/default/1.mbx_stress_zero_delays.3162971836 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope default -covtest 1.mbx_stress_zero_delays.3162971836 -covoverwrite' seed=72794632088821178504631755377888182929404508502993570110697579230093302505148 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72794632088821178504631755377888182929404508502993570110697579230093302505148 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_stress_zero_delays/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_stress_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_imbx_oob 105522850907061009401534661154697929260785843528313413656132377440296121417766 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_imbx_oob/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/default/xcelium.d -r tb +SVSEED=1154236454 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_imbx_oob_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/default/1.mbx_imbx_oob.1154236454 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope default -covtest 1.mbx_imbx_oob.1154236454 -covoverwrite' seed=105522850907061009401534661154697929260785843528313413656132377440296121417766 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105522850907061009401534661154697929260785843528313413656132377440296121417766 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_imbx_oob/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_imbx_oob_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_doe_intr_msg 15142319755808892553383486717317778043010876878620221720869055705195467057408 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_doe_intr_msg/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/default/xcelium.d -r tb +SVSEED=963193088 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_doe_intr_msg_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/default/1.mbx_doe_intr_msg.963193088 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope default -covtest 1.mbx_doe_intr_msg.963193088 -covoverwrite' seed=15142319755808892553383486717317778043010876878620221720869055705195467057408 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15142319755808892553383486717317778043010876878620221720869055705195467057408 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_doe_intr_msg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_doe_intr_msg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_errors 91006612330482195540591469315647521545398197355851012388022344145782305978691 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1382283587 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/1.mbx_tl_errors.1382283587 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.mbx_tl_errors.1382283587 -covoverwrite' seed=91006612330482195540591469315647521545398197355851012388022344145782305978691 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91006612330482195540591469315647521545398197355851012388022344145782305978691 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_intg_err 66977637277129058919908615325804914324543357806511382505993331151980993000305 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=742732657 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/1.mbx_tl_intg_err.742732657 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.mbx_tl_intg_err.742732657 -covoverwrite' seed=66977637277129058919908615325804914324543357806511382505993331151980993000305 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66977637277129058919908615325804914324543357806511382505993331151980993000305 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_sec_cm 44782507527582533205569835976571213154350501881140740414008159256778353243484 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/default/xcelium.d -r tb +SVSEED=4222711132 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/default/1.mbx_sec_cm.4222711132 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope default -covtest 1.mbx_sec_cm.4222711132 -covoverwrite' seed=44782507527582533205569835976571213154350501881140740414008159256778353243484 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44782507527582533205569835976571213154350501881140740414008159256778353243484 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_intr_test 39363331428356503134007586834536008836470030872656073292218966039980991988406 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1954693814 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/1.mbx_intr_test.1954693814 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.mbx_intr_test.1954693814 -covoverwrite' seed=39363331428356503134007586834536008836470030872656073292218966039980991988406 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39363331428356503134007586834536008836470030872656073292218966039980991988406 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_csr_rw 95819656850825180386810483483958150441739371229982822788296186158166293863290 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2753289082 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/1.mbx_csr_rw.2753289082 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.mbx_csr_rw.2753289082 -covoverwrite' seed=95819656850825180386810483483958150441739371229982822788296186158166293863290 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95819656850825180386810483483958150441739371229982822788296186158166293863290 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_same_csr_outstanding 9828338068245079104541545685299899898574005828130798162495167130377982076697 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3026741017 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/1.mbx_same_csr_outstanding.3026741017 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.mbx_same_csr_outstanding.3026741017 -covoverwrite' seed=9828338068245079104541545685299899898574005828130798162495167130377982076697 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9828338068245079104541545685299899898574005828130798162495167130377982076697 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_csr_mem_rw_with_rand_reset 108813943695351540169663524908527167342536097100354472223764166675331297195123 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3466212467 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/1.mbx_csr_mem_rw_with_rand_reset.3466212467 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.mbx_csr_mem_rw_with_rand_reset.3466212467 -covoverwrite' seed=108813943695351540169663524908527167342536097100354472223764166675331297195123 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108813943695351540169663524908527167342536097100354472223764166675331297195123 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_alert_test 29803587144280014975129446701608741478534298363008454188418997444777461579822 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/default/xcelium.d -r tb +SVSEED=3765600302 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/default/1.mbx_alert_test.3765600302 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope default -covtest 1.mbx_alert_test.3765600302 -covoverwrite' seed=29803587144280014975129446701608741478534298363008454188418997444777461579822 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29803587144280014975129446701608741478534298363008454188418997444777461579822 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/1.mbx_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_doe_intr_msg 40855262420883571288273908075150887351336487072930311855892175033981943055221 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/2.mbx_doe_intr_msg/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/default/xcelium.d -r tb +SVSEED=3710288757 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_doe_intr_msg_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/default/2.mbx_doe_intr_msg.3710288757 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope default -covtest 2.mbx_doe_intr_msg.3710288757 -covoverwrite' seed=40855262420883571288273908075150887351336487072930311855892175033981943055221 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40855262420883571288273908075150887351336487072930311855892175033981943055221 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/2.mbx_doe_intr_msg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_doe_intr_msg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_errors 19977473797426148808054890191198406026740338064732825914176335846890351076965 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/2.mbx_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3410732645 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/2.mbx_tl_errors.3410732645 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.mbx_tl_errors.3410732645 -covoverwrite' seed=19977473797426148808054890191198406026740338064732825914176335846890351076965 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19977473797426148808054890191198406026740338064732825914176335846890351076965 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/2.mbx_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_intg_err 22589146516446231693666634756040267558609266095599916234081359176467772300552 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/2.mbx_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1310940424 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/2.mbx_tl_intg_err.1310940424 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.mbx_tl_intg_err.1310940424 -covoverwrite' seed=22589146516446231693666634756040267558609266095599916234081359176467772300552 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22589146516446231693666634756040267558609266095599916234081359176467772300552 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/2.mbx_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_sec_cm 8036293911543571246539645271016921537065566695946420282640074311040311694338 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/2.mbx_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/default/xcelium.d -r tb +SVSEED=1122702338 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/default/2.mbx_sec_cm.1122702338 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope default -covtest 2.mbx_sec_cm.1122702338 -covoverwrite' seed=8036293911543571246539645271016921537065566695946420282640074311040311694338 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8036293911543571246539645271016921537065566695946420282640074311040311694338 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/2.mbx_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_intr_test 32278307577340146256125660957848842079262711273905946131010892208873974872313 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/2.mbx_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=914438393 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/2.mbx_intr_test.914438393 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.mbx_intr_test.914438393 -covoverwrite' seed=32278307577340146256125660957848842079262711273905946131010892208873974872313 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32278307577340146256125660957848842079262711273905946131010892208873974872313 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/2.mbx_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_csr_rw 22770678040867716883157697816939797812173543132002797700978903456527491897454 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/2.mbx_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=363960430 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/2.mbx_csr_rw.363960430 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.mbx_csr_rw.363960430 -covoverwrite' seed=22770678040867716883157697816939797812173543132002797700978903456527491897454 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22770678040867716883157697816939797812173543132002797700978903456527491897454 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/2.mbx_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_same_csr_outstanding 82493913833302589383666691544946445687426333182229481978175869025744788969451 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/2.mbx_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4167882731 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/2.mbx_same_csr_outstanding.4167882731 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.mbx_same_csr_outstanding.4167882731 -covoverwrite' seed=82493913833302589383666691544946445687426333182229481978175869025744788969451 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82493913833302589383666691544946445687426333182229481978175869025744788969451 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/2.mbx_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_csr_mem_rw_with_rand_reset 30261229077411860707144399063212351247765159381567670107872002145860049246350 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/2.mbx_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2843285646 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/2.mbx_csr_mem_rw_with_rand_reset.2843285646 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.mbx_csr_mem_rw_with_rand_reset.2843285646 -covoverwrite' seed=30261229077411860707144399063212351247765159381567670107872002145860049246350 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30261229077411860707144399063212351247765159381567670107872002145860049246350 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/2.mbx_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_alert_test 115384251058473980771395867347913736003140125606111783521089673483161155703566 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/2.mbx_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/default/xcelium.d -r tb +SVSEED=3007877902 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/default/2.mbx_alert_test.3007877902 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope default -covtest 2.mbx_alert_test.3007877902 -covoverwrite' seed=115384251058473980771395867347913736003140125606111783521089673483161155703566 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115384251058473980771395867347913736003140125606111783521089673483161155703566 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/2.mbx_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_doe_intr_msg 107408963606790912477329958090456696262831706037679740986993581631811605403580 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/3.mbx_doe_intr_msg/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/default/xcelium.d -r tb +SVSEED=3421673404 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_doe_intr_msg_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/default/3.mbx_doe_intr_msg.3421673404 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope default -covtest 3.mbx_doe_intr_msg.3421673404 -covoverwrite' seed=107408963606790912477329958090456696262831706037679740986993581631811605403580 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107408963606790912477329958090456696262831706037679740986993581631811605403580 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/3.mbx_doe_intr_msg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_doe_intr_msg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_errors 51515958518108265350189952436407756391165533825994620461081684019702200000607 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/3.mbx_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1640226911 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/3.mbx_tl_errors.1640226911 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.mbx_tl_errors.1640226911 -covoverwrite' seed=51515958518108265350189952436407756391165533825994620461081684019702200000607 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51515958518108265350189952436407756391165533825994620461081684019702200000607 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/3.mbx_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_intg_err 10706943029952211302708977528293271691492806008117142568674881500979646961756 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/3.mbx_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2001475676 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/3.mbx_tl_intg_err.2001475676 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.mbx_tl_intg_err.2001475676 -covoverwrite' seed=10706943029952211302708977528293271691492806008117142568674881500979646961756 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10706943029952211302708977528293271691492806008117142568674881500979646961756 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/3.mbx_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_sec_cm 49463691326403024653988510292381980788711926793435253367601400477321769039654 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/3.mbx_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/default/xcelium.d -r tb +SVSEED=1321776934 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/default/3.mbx_sec_cm.1321776934 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope default -covtest 3.mbx_sec_cm.1321776934 -covoverwrite' seed=49463691326403024653988510292381980788711926793435253367601400477321769039654 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49463691326403024653988510292381980788711926793435253367601400477321769039654 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/3.mbx_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_intr_test 86899448310119030087369879727053847262662249306792114969937071571638395032568 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/3.mbx_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3979039736 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/3.mbx_intr_test.3979039736 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.mbx_intr_test.3979039736 -covoverwrite' seed=86899448310119030087369879727053847262662249306792114969937071571638395032568 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86899448310119030087369879727053847262662249306792114969937071571638395032568 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/3.mbx_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_csr_rw 5911905305351144361933469819287362389358928245793098236852228198868544650744 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/3.mbx_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1343225336 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/3.mbx_csr_rw.1343225336 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.mbx_csr_rw.1343225336 -covoverwrite' seed=5911905305351144361933469819287362389358928245793098236852228198868544650744 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5911905305351144361933469819287362389358928245793098236852228198868544650744 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/3.mbx_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_same_csr_outstanding 22634398973821742574777570242073438222793413865905305165398686477281719819847 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/3.mbx_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1323376199 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/3.mbx_same_csr_outstanding.1323376199 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.mbx_same_csr_outstanding.1323376199 -covoverwrite' seed=22634398973821742574777570242073438222793413865905305165398686477281719819847 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22634398973821742574777570242073438222793413865905305165398686477281719819847 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/3.mbx_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_csr_mem_rw_with_rand_reset 99323618512855298974244909735113390580375224195306780703592413455169502302897 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/3.mbx_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1230754481 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/3.mbx_csr_mem_rw_with_rand_reset.1230754481 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.mbx_csr_mem_rw_with_rand_reset.1230754481 -covoverwrite' seed=99323618512855298974244909735113390580375224195306780703592413455169502302897 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99323618512855298974244909735113390580375224195306780703592413455169502302897 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/3.mbx_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_alert_test 79904737958977332281084536289363516899248567276639066879788750050169087450611 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/3.mbx_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/default/xcelium.d -r tb +SVSEED=3848134131 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/default/3.mbx_alert_test.3848134131 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope default -covtest 3.mbx_alert_test.3848134131 -covoverwrite' seed=79904737958977332281084536289363516899248567276639066879788750050169087450611 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79904737958977332281084536289363516899248567276639066879788750050169087450611 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/3.mbx_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_doe_intr_msg 57176742008601087718302214638679291141996747322344358895516760489850303277727 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/4.mbx_doe_intr_msg/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/default/xcelium.d -r tb +SVSEED=1938680479 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_doe_intr_msg_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/default/4.mbx_doe_intr_msg.1938680479 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope default -covtest 4.mbx_doe_intr_msg.1938680479 -covoverwrite' seed=57176742008601087718302214638679291141996747322344358895516760489850303277727 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57176742008601087718302214638679291141996747322344358895516760489850303277727 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/4.mbx_doe_intr_msg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_doe_intr_msg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_errors 53913752166004253378782988295974791578037641605708325841872407858189226763513 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/4.mbx_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2228774137 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/4.mbx_tl_errors.2228774137 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.mbx_tl_errors.2228774137 -covoverwrite' seed=53913752166004253378782988295974791578037641605708325841872407858189226763513 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53913752166004253378782988295974791578037641605708325841872407858189226763513 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/4.mbx_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_intg_err 17167202901314461997827129050013906063035962203980392199011373104900455866366 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/4.mbx_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3343720446 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/4.mbx_tl_intg_err.3343720446 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.mbx_tl_intg_err.3343720446 -covoverwrite' seed=17167202901314461997827129050013906063035962203980392199011373104900455866366 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17167202901314461997827129050013906063035962203980392199011373104900455866366 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/4.mbx_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_sec_cm 18517773120220638448325162157163018098208928767689802430784334875535555956462 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/4.mbx_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/default/xcelium.d -r tb +SVSEED=2580025070 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/default/4.mbx_sec_cm.2580025070 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope default -covtest 4.mbx_sec_cm.2580025070 -covoverwrite' seed=18517773120220638448325162157163018098208928767689802430784334875535555956462 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18517773120220638448325162157163018098208928767689802430784334875535555956462 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/4.mbx_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_intr_test 49918085975967927082147986377863220552754116501672034281708518293635598960708 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/4.mbx_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3077097540 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/4.mbx_intr_test.3077097540 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.mbx_intr_test.3077097540 -covoverwrite' seed=49918085975967927082147986377863220552754116501672034281708518293635598960708 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49918085975967927082147986377863220552754116501672034281708518293635598960708 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/4.mbx_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_csr_rw 8689436232392927040415816843398611560389543294557891345320717013995513188280 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/4.mbx_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4213968824 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/4.mbx_csr_rw.4213968824 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.mbx_csr_rw.4213968824 -covoverwrite' seed=8689436232392927040415816843398611560389543294557891345320717013995513188280 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8689436232392927040415816843398611560389543294557891345320717013995513188280 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/4.mbx_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_same_csr_outstanding 9287528837688240116967335976490623119964557232310441624949199762023388211682 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/4.mbx_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4032752098 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/4.mbx_same_csr_outstanding.4032752098 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.mbx_same_csr_outstanding.4032752098 -covoverwrite' seed=9287528837688240116967335976490623119964557232310441624949199762023388211682 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9287528837688240116967335976490623119964557232310441624949199762023388211682 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/4.mbx_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_csr_mem_rw_with_rand_reset 81343051524958855835040893602393646217771130294545659276689485160675321579100 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/4.mbx_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3006006876 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/4.mbx_csr_mem_rw_with_rand_reset.3006006876 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.mbx_csr_mem_rw_with_rand_reset.3006006876 -covoverwrite' seed=81343051524958855835040893602393646217771130294545659276689485160675321579100 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81343051524958855835040893602393646217771130294545659276689485160675321579100 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/4.mbx_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_alert_test 114483349311910821246681042600911168828294464645906230549487633374018729403390 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/4.mbx_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/default/xcelium.d -r tb +SVSEED=1185932286 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/default/4.mbx_alert_test.1185932286 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope default -covtest 4.mbx_alert_test.1185932286 -covoverwrite' seed=114483349311910821246681042600911168828294464645906230549487633374018729403390 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114483349311910821246681042600911168828294464645906230549487633374018729403390 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/4.mbx_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_errors 61883428215026336166373333102028487266264425041737569350517181963352446218927 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/5.mbx_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3848680111 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/5.mbx_tl_errors.3848680111 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.mbx_tl_errors.3848680111 -covoverwrite' seed=61883428215026336166373333102028487266264425041737569350517181963352446218927 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61883428215026336166373333102028487266264425041737569350517181963352446218927 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/5.mbx_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_intg_err 11909670010332783835933218354010644627538378442714879702033083983344312053291 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/5.mbx_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2322132523 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/5.mbx_tl_intg_err.2322132523 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.mbx_tl_intg_err.2322132523 -covoverwrite' seed=11909670010332783835933218354010644627538378442714879702033083983344312053291 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11909670010332783835933218354010644627538378442714879702033083983344312053291 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/5.mbx_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_intr_test 85238331606649616051856943521622114409813976674942654561553867901742596053432 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/5.mbx_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1292196280 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/5.mbx_intr_test.1292196280 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.mbx_intr_test.1292196280 -covoverwrite' seed=85238331606649616051856943521622114409813976674942654561553867901742596053432 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85238331606649616051856943521622114409813976674942654561553867901742596053432 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/5.mbx_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_alert_test 38444247974009732925107459421836558941204759109031491792530315587919340320977 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/5.mbx_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/default/xcelium.d -r tb +SVSEED=3535222993 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/default/5.mbx_alert_test.3535222993 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope default -covtest 5.mbx_alert_test.3535222993 -covoverwrite' seed=38444247974009732925107459421836558941204759109031491792530315587919340320977 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38444247974009732925107459421836558941204759109031491792530315587919340320977 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/5.mbx_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_errors 101789029361561285901157308280184388557027731341233565795952175048227404956670 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/6.mbx_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=147375102 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/6.mbx_tl_errors.147375102 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.mbx_tl_errors.147375102 -covoverwrite' seed=101789029361561285901157308280184388557027731341233565795952175048227404956670 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101789029361561285901157308280184388557027731341233565795952175048227404956670 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/6.mbx_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_intg_err 43308606725092096348557347291785804650423189458220063288109674314816999731357 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/6.mbx_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=379662493 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/6.mbx_tl_intg_err.379662493 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.mbx_tl_intg_err.379662493 -covoverwrite' seed=43308606725092096348557347291785804650423189458220063288109674314816999731357 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43308606725092096348557347291785804650423189458220063288109674314816999731357 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/6.mbx_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_intr_test 88644818878431798843992877240164370717625584806829560571135103496578530056551 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/6.mbx_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3411843431 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/6.mbx_intr_test.3411843431 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.mbx_intr_test.3411843431 -covoverwrite' seed=88644818878431798843992877240164370717625584806829560571135103496578530056551 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88644818878431798843992877240164370717625584806829560571135103496578530056551 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/6.mbx_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_alert_test 44468133774337634884969279712827125877474587220520361319330590325041916079621 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/6.mbx_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/default/xcelium.d -r tb +SVSEED=4071943685 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/default/6.mbx_alert_test.4071943685 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope default -covtest 6.mbx_alert_test.4071943685 -covoverwrite' seed=44468133774337634884969279712827125877474587220520361319330590325041916079621 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44468133774337634884969279712827125877474587220520361319330590325041916079621 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/6.mbx_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_errors 113641900969160064712985256448348690138662423037383184781450509817402757622654 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/7.mbx_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2207656830 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/7.mbx_tl_errors.2207656830 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.mbx_tl_errors.2207656830 -covoverwrite' seed=113641900969160064712985256448348690138662423037383184781450509817402757622654 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113641900969160064712985256448348690138662423037383184781450509817402757622654 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/7.mbx_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_intg_err 97991130018169799391127392441711024100581687324006010545473902847080321921590 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/7.mbx_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3380228662 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/7.mbx_tl_intg_err.3380228662 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.mbx_tl_intg_err.3380228662 -covoverwrite' seed=97991130018169799391127392441711024100581687324006010545473902847080321921590 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97991130018169799391127392441711024100581687324006010545473902847080321921590 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/7.mbx_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_intr_test 7289636753344952042573028337894521144948583092018027899232203154278481484775 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/7.mbx_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=889019367 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/7.mbx_intr_test.889019367 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.mbx_intr_test.889019367 -covoverwrite' seed=7289636753344952042573028337894521144948583092018027899232203154278481484775 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7289636753344952042573028337894521144948583092018027899232203154278481484775 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/7.mbx_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_alert_test 37480383823185778024426666602892372471890593042375653994283721064220463787299 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/7.mbx_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/default/xcelium.d -r tb +SVSEED=180940067 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/default/7.mbx_alert_test.180940067 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope default -covtest 7.mbx_alert_test.180940067 -covoverwrite' seed=37480383823185778024426666602892372471890593042375653994283721064220463787299 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37480383823185778024426666602892372471890593042375653994283721064220463787299 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/7.mbx_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_errors 61581988512340819027342351849465504804961837146819035259105833010096122524227 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/8.mbx_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2023125571 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/8.mbx_tl_errors.2023125571 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.mbx_tl_errors.2023125571 -covoverwrite' seed=61581988512340819027342351849465504804961837146819035259105833010096122524227 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61581988512340819027342351849465504804961837146819035259105833010096122524227 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/8.mbx_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_intg_err 54466003937663082017871837249194823016846901955398570926459612559154725241567 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/8.mbx_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2522596063 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/8.mbx_tl_intg_err.2522596063 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.mbx_tl_intg_err.2522596063 -covoverwrite' seed=54466003937663082017871837249194823016846901955398570926459612559154725241567 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54466003937663082017871837249194823016846901955398570926459612559154725241567 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/8.mbx_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_intr_test 14967165312748012648043968442612903374980612290403475823141356959325659183233 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/8.mbx_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3869358209 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/8.mbx_intr_test.3869358209 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.mbx_intr_test.3869358209 -covoverwrite' seed=14967165312748012648043968442612903374980612290403475823141356959325659183233 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=14967165312748012648043968442612903374980612290403475823141356959325659183233 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/8.mbx_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_alert_test 25761324906947895533596782388149939847192115410991142394508262133065730273777 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/8.mbx_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/default/xcelium.d -r tb +SVSEED=493662705 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/default/8.mbx_alert_test.493662705 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope default -covtest 8.mbx_alert_test.493662705 -covoverwrite' seed=25761324906947895533596782388149939847192115410991142394508262133065730273777 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25761324906947895533596782388149939847192115410991142394508262133065730273777 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/8.mbx_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_errors 85469053997292316348683016393360768803399373321550068937459400092695838101883 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/9.mbx_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1351913851 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/9.mbx_tl_errors.1351913851 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.mbx_tl_errors.1351913851 -covoverwrite' seed=85469053997292316348683016393360768803399373321550068937459400092695838101883 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85469053997292316348683016393360768803399373321550068937459400092695838101883 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/9.mbx_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_intg_err 46701960802709476231991399307018537989400957128930215260319979568771711408408 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/9.mbx_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1443404056 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/9.mbx_tl_intg_err.1443404056 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.mbx_tl_intg_err.1443404056 -covoverwrite' seed=46701960802709476231991399307018537989400957128930215260319979568771711408408 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46701960802709476231991399307018537989400957128930215260319979568771711408408 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/9.mbx_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_intr_test 113913171614203073118955520719076506943596660405700623094832196447393490082049 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/9.mbx_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1153898753 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/9.mbx_intr_test.1153898753 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.mbx_intr_test.1153898753 -covoverwrite' seed=113913171614203073118955520719076506943596660405700623094832196447393490082049 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113913171614203073118955520719076506943596660405700623094832196447393490082049 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/9.mbx_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_alert_test 71031274453921621405600185713208381064063317772245998006029717019689506612248 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/9.mbx_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/default/xcelium.d -r tb +SVSEED=2920588312 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/default/9.mbx_alert_test.2920588312 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope default -covtest 9.mbx_alert_test.2920588312 -covoverwrite' seed=71031274453921621405600185713208381064063317772245998006029717019689506612248 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71031274453921621405600185713208381064063317772245998006029717019689506612248 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/9.mbx_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_errors 70870612561599715851093001264637124007268289711926898466076515785920427687875 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/10.mbx_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2049802179 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/10.mbx_tl_errors.2049802179 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 10.mbx_tl_errors.2049802179 -covoverwrite' seed=70870612561599715851093001264637124007268289711926898466076515785920427687875 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70870612561599715851093001264637124007268289711926898466076515785920427687875 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/10.mbx_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_intg_err 55834213855358275845234885227563628070127049059231260568496279423082864752315 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/10.mbx_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=485668539 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/10.mbx_tl_intg_err.485668539 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 10.mbx_tl_intg_err.485668539 -covoverwrite' seed=55834213855358275845234885227563628070127049059231260568496279423082864752315 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55834213855358275845234885227563628070127049059231260568496279423082864752315 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/10.mbx_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_errors 97389125055799834703243495749484862146003642344364269463231326453219070985114 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/11.mbx_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3659416474 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/11.mbx_tl_errors.3659416474 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 11.mbx_tl_errors.3659416474 -covoverwrite' seed=97389125055799834703243495749484862146003642344364269463231326453219070985114 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97389125055799834703243495749484862146003642344364269463231326453219070985114 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/11.mbx_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_intg_err 13627194546740429039206168370896313214456685737057689604528200603615161100430 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/11.mbx_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2400594062 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/11.mbx_tl_intg_err.2400594062 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 11.mbx_tl_intg_err.2400594062 -covoverwrite' seed=13627194546740429039206168370896313214456685737057689604528200603615161100430 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13627194546740429039206168370896313214456685737057689604528200603615161100430 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/11.mbx_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_errors 113029788372700208773491384980436807781997016837859516694270548440219720476843 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/12.mbx_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2855397547 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/12.mbx_tl_errors.2855397547 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 12.mbx_tl_errors.2855397547 -covoverwrite' seed=113029788372700208773491384980436807781997016837859516694270548440219720476843 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113029788372700208773491384980436807781997016837859516694270548440219720476843 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/12.mbx_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_intg_err 95447493401809303734122587379140597668431052633406461507888230080865641329660 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/12.mbx_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2968155132 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/12.mbx_tl_intg_err.2968155132 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 12.mbx_tl_intg_err.2968155132 -covoverwrite' seed=95447493401809303734122587379140597668431052633406461507888230080865641329660 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95447493401809303734122587379140597668431052633406461507888230080865641329660 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/12.mbx_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_errors 66422928306187877915378788140525555881111269573417770308952715613986787170786 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/13.mbx_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3844086242 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/13.mbx_tl_errors.3844086242 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 13.mbx_tl_errors.3844086242 -covoverwrite' seed=66422928306187877915378788140525555881111269573417770308952715613986787170786 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66422928306187877915378788140525555881111269573417770308952715613986787170786 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/13.mbx_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_intg_err 89323487619315207036209846468757078321583824135934582744046803098302562351602 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/13.mbx_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4276795890 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/13.mbx_tl_intg_err.4276795890 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 13.mbx_tl_intg_err.4276795890 -covoverwrite' seed=89323487619315207036209846468757078321583824135934582744046803098302562351602 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89323487619315207036209846468757078321583824135934582744046803098302562351602 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/13.mbx_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_errors 58565455900345151088209053436235746785166447135161519894206274876936953891578 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/14.mbx_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1548585722 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/14.mbx_tl_errors.1548585722 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 14.mbx_tl_errors.1548585722 -covoverwrite' seed=58565455900345151088209053436235746785166447135161519894206274876936953891578 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58565455900345151088209053436235746785166447135161519894206274876936953891578 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/14.mbx_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_intg_err 11156240044938522898807447392660774508491646915991097403943502624741540823253 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/14.mbx_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4279828693 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/14.mbx_tl_intg_err.4279828693 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 14.mbx_tl_intg_err.4279828693 -covoverwrite' seed=11156240044938522898807447392660774508491646915991097403943502624741540823253 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11156240044938522898807447392660774508491646915991097403943502624741540823253 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/14.mbx_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_errors 83077743782904960953971077750414744296635913186018796523903161058953638443462 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/15.mbx_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2250242502 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/15.mbx_tl_errors.2250242502 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 15.mbx_tl_errors.2250242502 -covoverwrite' seed=83077743782904960953971077750414744296635913186018796523903161058953638443462 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83077743782904960953971077750414744296635913186018796523903161058953638443462 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/15.mbx_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_intg_err 57243660162898679120887170246357092659626571944804661664219182742776854015794 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/15.mbx_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1379069746 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/15.mbx_tl_intg_err.1379069746 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 15.mbx_tl_intg_err.1379069746 -covoverwrite' seed=57243660162898679120887170246357092659626571944804661664219182742776854015794 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57243660162898679120887170246357092659626571944804661664219182742776854015794 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/15.mbx_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_errors 39557959772028314528200452355709623113494428516833399316647885711391646848080 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/16.mbx_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=450663504 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/16.mbx_tl_errors.450663504 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 16.mbx_tl_errors.450663504 -covoverwrite' seed=39557959772028314528200452355709623113494428516833399316647885711391646848080 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39557959772028314528200452355709623113494428516833399316647885711391646848080 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/16.mbx_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_intg_err 33923740589160204707847912099702491181039670007271261491700975265953192934045 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/16.mbx_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3437820573 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/16.mbx_tl_intg_err.3437820573 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 16.mbx_tl_intg_err.3437820573 -covoverwrite' seed=33923740589160204707847912099702491181039670007271261491700975265953192934045 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33923740589160204707847912099702491181039670007271261491700975265953192934045 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/16.mbx_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_errors 19197160112006596452455034248296622780013545899174641925211103098663513795476 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/17.mbx_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=538618772 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/17.mbx_tl_errors.538618772 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 17.mbx_tl_errors.538618772 -covoverwrite' seed=19197160112006596452455034248296622780013545899174641925211103098663513795476 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19197160112006596452455034248296622780013545899174641925211103098663513795476 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/17.mbx_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_intg_err 1907154872665468388474374517371627396081186581757487766313187955488855356143 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/17.mbx_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3453154031 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/17.mbx_tl_intg_err.3453154031 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 17.mbx_tl_intg_err.3453154031 -covoverwrite' seed=1907154872665468388474374517371627396081186581757487766313187955488855356143 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1907154872665468388474374517371627396081186581757487766313187955488855356143 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/17.mbx_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_errors 97012655675036444823059330242828423372699252703989917764056525150127390855781 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/18.mbx_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3980530277 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/18.mbx_tl_errors.3980530277 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 18.mbx_tl_errors.3980530277 -covoverwrite' seed=97012655675036444823059330242828423372699252703989917764056525150127390855781 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97012655675036444823059330242828423372699252703989917764056525150127390855781 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/18.mbx_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_intg_err 47396092240433133803209299650460994170468888536494983801684999992017501717393 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/18.mbx_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3459941265 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/18.mbx_tl_intg_err.3459941265 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 18.mbx_tl_intg_err.3459941265 -covoverwrite' seed=47396092240433133803209299650460994170468888536494983801684999992017501717393 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47396092240433133803209299650460994170468888536494983801684999992017501717393 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/18.mbx_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_errors 64119893494471345868462095540587161901859212561892996421532866815237995040373 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/19.mbx_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3347517045 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/19.mbx_tl_errors.3347517045 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 19.mbx_tl_errors.3347517045 -covoverwrite' seed=64119893494471345868462095540587161901859212561892996421532866815237995040373 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64119893494471345868462095540587161901859212561892996421532866815237995040373 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/19.mbx_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_intg_err 65018045964954400022747963127006277147178776013967968600223801405968472186621 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/19.mbx_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1858445053 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/19.mbx_tl_intg_err.1858445053 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 19.mbx_tl_intg_err.1858445053 -covoverwrite' seed=65018045964954400022747963127006277147178776013967968600223801405968472186621 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65018045964954400022747963127006277147178776013967968600223801405968472186621 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/19.mbx_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_errors 34598547267782155814122349579889299001605926829018956505205270070565888851647 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/20.mbx_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2966159039 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/20.mbx_tl_errors.2966159039 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 20.mbx_tl_errors.2966159039 -covoverwrite' seed=34598547267782155814122349579889299001605926829018956505205270070565888851647 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34598547267782155814122349579889299001605926829018956505205270070565888851647 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/20.mbx_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_intg_err 86873427767179925747093577126020387678698048005680441938066009247827677687693 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/20.mbx_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1655975821 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/20.mbx_tl_intg_err.1655975821 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 20.mbx_tl_intg_err.1655975821 -covoverwrite' seed=86873427767179925747093577126020387678698048005680441938066009247827677687693 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86873427767179925747093577126020387678698048005680441938066009247827677687693 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/20.mbx_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_errors 39398998924921376494949982424349499729742913998827511578558756644553805158952 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/21.mbx_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1392663080 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/21.mbx_tl_errors.1392663080 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 21.mbx_tl_errors.1392663080 -covoverwrite' seed=39398998924921376494949982424349499729742913998827511578558756644553805158952 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39398998924921376494949982424349499729742913998827511578558756644553805158952 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/21.mbx_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_intg_err 57546731776279975338361548200116964001250523054302121102886674378491288875229 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/21.mbx_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2185752797 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/21.mbx_tl_intg_err.2185752797 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 21.mbx_tl_intg_err.2185752797 -covoverwrite' seed=57546731776279975338361548200116964001250523054302121102886674378491288875229 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57546731776279975338361548200116964001250523054302121102886674378491288875229 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/21.mbx_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_errors 102697658223790851229790408632669594385334877942127994987008356027850538423057 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/22.mbx_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3783070481 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/22.mbx_tl_errors.3783070481 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 22.mbx_tl_errors.3783070481 -covoverwrite' seed=102697658223790851229790408632669594385334877942127994987008356027850538423057 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102697658223790851229790408632669594385334877942127994987008356027850538423057 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/22.mbx_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_intg_err 49927652091152381477823874004968656144214623810157297104875019132375756170444 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/22.mbx_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2171856076 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/22.mbx_tl_intg_err.2171856076 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 22.mbx_tl_intg_err.2171856076 -covoverwrite' seed=49927652091152381477823874004968656144214623810157297104875019132375756170444 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49927652091152381477823874004968656144214623810157297104875019132375756170444 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/22.mbx_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_errors 90486358018898104850869613088359294701295281941758765503315750882715675896336 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/23.mbx_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2974001680 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/23.mbx_tl_errors.2974001680 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 23.mbx_tl_errors.2974001680 -covoverwrite' seed=90486358018898104850869613088359294701295281941758765503315750882715675896336 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90486358018898104850869613088359294701295281941758765503315750882715675896336 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/23.mbx_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_intg_err 51380145649541034615044905161425046802737276091162120844168374803420055337480 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/23.mbx_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1646262792 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/23.mbx_tl_intg_err.1646262792 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 23.mbx_tl_intg_err.1646262792 -covoverwrite' seed=51380145649541034615044905161425046802737276091162120844168374803420055337480 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51380145649541034615044905161425046802737276091162120844168374803420055337480 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/23.mbx_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_errors 61325062640951413938676010514495116688003007729982182110132171343725594080449 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/24.mbx_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2295788737 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/24.mbx_tl_errors.2295788737 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 24.mbx_tl_errors.2295788737 -covoverwrite' seed=61325062640951413938676010514495116688003007729982182110132171343725594080449 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61325062640951413938676010514495116688003007729982182110132171343725594080449 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/24.mbx_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
mbx_tl_intg_err 24563736753382418590806165446966238586767681048794210376594778520223502959205 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/24.mbx_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/mbx-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3210871397 +UVM_TESTNAME=mbx_base_test +UVM_TEST_SEQ=mbx_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage/cover_reg_top/24.mbx_tl_intg_err.3210871397 -covworkdir /nightly/current_run/scratch/master/mbx-sim-xcelium/coverage -covscope cover_reg_top -covtest 24.mbx_tl_intg_err.3210871397 -covoverwrite' seed=24563736753382418590806165446966238586767681048794210376594778520223502959205 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24563736753382418590806165446966238586767681048794210376594778520223502959205 --run-dir=/nightly/current_run/scratch/master/mbx-sim-xcelium/24.mbx_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=mbx_base_test uvm_test_seq=mbx_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
Job cancelled because all of its dependencies failed or were killed. 1 test run
mbx None None
Job cancelled because one of its dependencies failed or was killed. 1 test run
mbx None None