Simulation Results: otp_ctrl

 
28/08/2026 21:54:34 DVSim: v1.49.0 sha: a099412 json Branch: master Tool: vcs [unknown]
Validation stages
V1
0.00%
V2
0.00%
V2S
0.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 0 1 0.00
otp_ctrl_wake_up 0.893s 0.000us 0 1 0.00
smoke 0 10 0.00
otp_ctrl_smoke 1.303s 0.000us 0 10 0.00
csr_hw_reset 0 1 0.00
otp_ctrl_csr_hw_reset 0.829s 0.000us 0 1 0.00
csr_rw 0 5 0.00
otp_ctrl_csr_rw 1.566s 0.000us 0 5 0.00
csr_bit_bash 0 1 0.00
otp_ctrl_csr_bit_bash 0.836s 0.000us 0 1 0.00
csr_aliasing 0 1 0.00
otp_ctrl_csr_aliasing 0.853s 0.000us 0 1 0.00
csr_mem_rw_with_rand_reset 0 5 0.00
otp_ctrl_csr_mem_rw_with_rand_reset 1.545s 0.000us 0 5 0.00
regwen_csr_and_corresponding_lockable_csr 0 6 0.00
otp_ctrl_csr_rw 1.566s 0.000us 0 5 0.00
otp_ctrl_csr_aliasing 0.853s 0.000us 0 1 0.00
mem_walk 0 1 0.00
otp_ctrl_mem_walk 1.630s 0.000us 0 1 0.00
mem_partial_access 0 1 0.00
otp_ctrl_mem_partial_access 0.859s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 0 1 0.00
otp_ctrl_partition_walk 0.865s 0.000us 0 1 0.00
init_fail 0 300 0.00
otp_ctrl_init_fail 1.622s 0.000us 0 300 0.00
partition_check 0 60 0.00
otp_ctrl_background_chks 1.421s 0.000us 0 10 0.00
otp_ctrl_check_fail 1.571s 0.000us 0 50 0.00
regwen_during_otp_init 0 30 0.00
otp_ctrl_regwen 1.566s 0.000us 0 30 0.00
partition_lock 0 30 0.00
otp_ctrl_dai_lock 1.541s 0.000us 0 30 0.00
interface_key_check 0 10 0.00
otp_ctrl_parallel_key_req 1.308s 0.000us 0 10 0.00
lc_interactions 0 210 0.00
otp_ctrl_parallel_lc_req 1.537s 0.000us 0 10 0.00
otp_ctrl_parallel_lc_esc 1.656s 0.000us 0 200 0.00
otp_dai_errors 0 25 0.00
otp_ctrl_dai_errs 1.559s 0.000us 0 25 0.00
otp_macro_errors 0 10 0.00
otp_ctrl_macro_errs 0.908s 0.000us 0 10 0.00
test_access 0 10 0.00
otp_ctrl_test_access 0.868s 0.000us 0 10 0.00
stress_all 0 10 0.00
otp_ctrl_stress_all 117.290s 27026.787us 0 10 0.00
intr_test 0 10 0.00
otp_ctrl_intr_test 1.535s 0.000us 0 10 0.00
alert_test 0 10 0.00
otp_ctrl_alert_test 2.124s 0.000us 0 10 0.00
tl_d_oob_addr_access 0 25 0.00
otp_ctrl_tl_errors 1.682s 0.000us 0 25 0.00
tl_d_illegal_access 0 25 0.00
otp_ctrl_tl_errors 1.682s 0.000us 0 25 0.00
tl_d_outstanding_access 0 12 0.00
otp_ctrl_csr_hw_reset 0.829s 0.000us 0 1 0.00
otp_ctrl_csr_rw 1.566s 0.000us 0 5 0.00
otp_ctrl_csr_aliasing 0.853s 0.000us 0 1 0.00
otp_ctrl_same_csr_outstanding 0.874s 0.000us 0 5 0.00
tl_d_partial_access 0 12 0.00
otp_ctrl_csr_hw_reset 0.829s 0.000us 0 1 0.00
otp_ctrl_csr_rw 1.566s 0.000us 0 5 0.00
otp_ctrl_csr_aliasing 0.853s 0.000us 0 1 0.00
otp_ctrl_same_csr_outstanding 0.874s 0.000us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 0 5 0.00
otp_ctrl_sec_cm 0.858s 0.000us 0 5 0.00
tl_intg_err 0 30 0.00
otp_ctrl_sec_cm 0.858s 0.000us 0 5 0.00
otp_ctrl_tl_intg_err 1.553s 0.000us 0 25 0.00
prim_count_check 0 5 0.00
otp_ctrl_sec_cm 0.858s 0.000us 0 5 0.00
prim_fsm_check 0 5 0.00
otp_ctrl_sec_cm 0.858s 0.000us 0 5 0.00
sec_cm_bus_integrity 0 25 0.00
otp_ctrl_tl_intg_err 1.553s 0.000us 0 25 0.00
sec_cm_secret_mem_scramble 0 10 0.00
otp_ctrl_smoke 1.303s 0.000us 0 10 0.00
sec_cm_part_mem_digest 0 10 0.00
otp_ctrl_smoke 1.303s 0.000us 0 10 0.00
sec_cm_dai_fsm_sparse 0 5 0.00
otp_ctrl_sec_cm 0.858s 0.000us 0 5 0.00
sec_cm_kdi_fsm_sparse 0 5 0.00
otp_ctrl_sec_cm 0.858s 0.000us 0 5 0.00
sec_cm_lci_fsm_sparse 0 5 0.00
otp_ctrl_sec_cm 0.858s 0.000us 0 5 0.00
sec_cm_part_fsm_sparse 0 5 0.00
otp_ctrl_sec_cm 0.858s 0.000us 0 5 0.00
sec_cm_scrmbl_fsm_sparse 0 5 0.00
otp_ctrl_sec_cm 0.858s 0.000us 0 5 0.00
sec_cm_timer_fsm_sparse 0 5 0.00
otp_ctrl_sec_cm 0.858s 0.000us 0 5 0.00
sec_cm_dai_ctr_redun 0 5 0.00
otp_ctrl_sec_cm 0.858s 0.000us 0 5 0.00
sec_cm_kdi_seed_ctr_redun 0 5 0.00
otp_ctrl_sec_cm 0.858s 0.000us 0 5 0.00
sec_cm_kdi_entropy_ctr_redun 0 5 0.00
otp_ctrl_sec_cm 0.858s 0.000us 0 5 0.00
sec_cm_lci_ctr_redun 0 5 0.00
otp_ctrl_sec_cm 0.858s 0.000us 0 5 0.00
sec_cm_part_ctr_redun 0 5 0.00
otp_ctrl_sec_cm 0.858s 0.000us 0 5 0.00
sec_cm_scrmbl_ctr_redun 0 5 0.00
otp_ctrl_sec_cm 0.858s 0.000us 0 5 0.00
sec_cm_timer_integ_ctr_redun 0 5 0.00
otp_ctrl_sec_cm 0.858s 0.000us 0 5 0.00
sec_cm_timer_cnsty_ctr_redun 0 5 0.00
otp_ctrl_sec_cm 0.858s 0.000us 0 5 0.00
sec_cm_timer_lfsr_redun 0 5 0.00
otp_ctrl_sec_cm 0.858s 0.000us 0 5 0.00
sec_cm_dai_fsm_local_esc 0 205 0.00
otp_ctrl_parallel_lc_esc 1.656s 0.000us 0 200 0.00
otp_ctrl_sec_cm 0.858s 0.000us 0 5 0.00
sec_cm_lci_fsm_local_esc 0 200 0.00
otp_ctrl_parallel_lc_esc 1.656s 0.000us 0 200 0.00
sec_cm_kdi_fsm_local_esc 0 200 0.00
otp_ctrl_parallel_lc_esc 1.656s 0.000us 0 200 0.00
sec_cm_part_fsm_local_esc 0 210 0.00
otp_ctrl_parallel_lc_esc 1.656s 0.000us 0 200 0.00
otp_ctrl_macro_errs 0.908s 0.000us 0 10 0.00
sec_cm_scrmbl_fsm_local_esc 0 200 0.00
otp_ctrl_parallel_lc_esc 1.656s 0.000us 0 200 0.00
sec_cm_timer_fsm_local_esc 0 205 0.00
otp_ctrl_parallel_lc_esc 1.656s 0.000us 0 200 0.00
otp_ctrl_sec_cm 0.858s 0.000us 0 5 0.00
sec_cm_dai_fsm_global_esc 0 205 0.00
otp_ctrl_parallel_lc_esc 1.656s 0.000us 0 200 0.00
otp_ctrl_sec_cm 0.858s 0.000us 0 5 0.00
sec_cm_lci_fsm_global_esc 0 200 0.00
otp_ctrl_parallel_lc_esc 1.656s 0.000us 0 200 0.00
sec_cm_kdi_fsm_global_esc 0 200 0.00
otp_ctrl_parallel_lc_esc 1.656s 0.000us 0 200 0.00
sec_cm_part_fsm_global_esc 0 210 0.00
otp_ctrl_parallel_lc_esc 1.656s 0.000us 0 200 0.00
otp_ctrl_macro_errs 0.908s 0.000us 0 10 0.00
sec_cm_scrmbl_fsm_global_esc 0 200 0.00
otp_ctrl_parallel_lc_esc 1.656s 0.000us 0 200 0.00
sec_cm_timer_fsm_global_esc 0 205 0.00
otp_ctrl_parallel_lc_esc 1.656s 0.000us 0 200 0.00
otp_ctrl_sec_cm 0.858s 0.000us 0 5 0.00
sec_cm_part_data_reg_integrity 0 300 0.00
otp_ctrl_init_fail 1.622s 0.000us 0 300 0.00
sec_cm_part_data_reg_bkgn_chk 0 50 0.00
otp_ctrl_check_fail 1.571s 0.000us 0 50 0.00
sec_cm_part_mem_regren 0 30 0.00
otp_ctrl_dai_lock 1.541s 0.000us 0 30 0.00
sec_cm_part_mem_sw_unreadable 0 30 0.00
otp_ctrl_dai_lock 1.541s 0.000us 0 30 0.00
sec_cm_part_mem_sw_unwritable 0 30 0.00
otp_ctrl_dai_lock 1.541s 0.000us 0 30 0.00
sec_cm_lc_part_mem_sw_noaccess 0 30 0.00
otp_ctrl_dai_lock 1.541s 0.000us 0 30 0.00
sec_cm_access_ctrl_mubi 0 30 0.00
otp_ctrl_dai_lock 1.541s 0.000us 0 30 0.00
sec_cm_token_valid_ctrl_mubi 0 10 0.00
otp_ctrl_smoke 1.303s 0.000us 0 10 0.00
sec_cm_lc_ctrl_intersig_mubi 0 30 0.00
otp_ctrl_dai_lock 1.541s 0.000us 0 30 0.00
sec_cm_test_bus_lc_gated 0 10 0.00
otp_ctrl_smoke 1.303s 0.000us 0 10 0.00
sec_cm_test_tl_lc_gate_fsm_sparse 0 5 0.00
otp_ctrl_sec_cm 0.858s 0.000us 0 5 0.00
sec_cm_direct_access_config_regwen 0 30 0.00
otp_ctrl_regwen 1.566s 0.000us 0 30 0.00
sec_cm_check_trigger_config_regwen 0 10 0.00
otp_ctrl_smoke 1.303s 0.000us 0 10 0.00
sec_cm_check_config_regwen 0 10 0.00
otp_ctrl_smoke 1.303s 0.000us 0 10 0.00
sec_cm_macro_mem_integrity 0 10 0.00
otp_ctrl_macro_errs 0.908s 0.000us 0 10 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 0 1 0.00
otp_ctrl_low_freq_read 0.885s 0.000us 0 1 0.00
stress_all_with_rand_reset 0 100 0.00
otp_ctrl_stress_all_with_rand_reset 2.108s 0.000us 0 100 0.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 893 test runs
otp_ctrl_wake_up 17018431719643596126281064690227012913570995169454625767801091074571892127959 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_wake_up/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3019339991 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_wake_up_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_wake_up.3019339991' seed=17018431719643596126281064690227012913570995169454625767801091074571892127959 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17018431719643596126281064690227012913570995169454625767801091074571892127959 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_wake_up/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_wake_up_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_smoke 105355984559879919821299249892487690443130534210386049634768929288323079747031 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=206976471 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_smoke.206976471' seed=105355984559879919821299249892487690443130534210386049634768929288323079747031 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105355984559879919821299249892487690443130534210386049634768929288323079747031 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_partition_walk 105346030727933940182120870075540506486859222718087113582950897030658766427599 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_partition_walk/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1581274575 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_partition_walk_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_partition_walk.1581274575' seed=105346030727933940182120870075540506486859222718087113582950897030658766427599 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105346030727933940182120870075540506486859222718087113582950897030658766427599 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_partition_walk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_partition_walk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_low_freq_read 34164417933251985886793689788334053603858267698790091472720320440763516577599 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_low_freq_read/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=607512383 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_low_freq_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_low_freq_read.607512383' seed=34164417933251985886793689788334053603858267698790091472720320440763516577599 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34164417933251985886793689788334053603858267698790091472720320440763516577599 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_low_freq_read/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_low_freq_read_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 22047480257115273921537265941321441802501829056652984304708188646513920070145 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1222791681 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_init_fail.1222791681' seed=22047480257115273921537265941321441802501829056652984304708188646513920070145 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22047480257115273921537265941321441802501829056652984304708188646513920070145 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_background_chks 114950353246591169470913398146218654316279079557377608203406506267368338531236 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_background_chks/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2225644452 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_background_chks.2225644452' seed=114950353246591169470913398146218654316279079557377608203406506267368338531236 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114950353246591169470913398146218654316279079557377608203406506267368338531236 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_background_chks/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_background_chks_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_req 35765909537082852713218710184188775520816997462417395594504794553838954288984 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_req/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2901088088 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_req.2901088088' seed=35765909537082852713218710184188775520816997462417395594504794553838954288984 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35765909537082852713218710184188775520816997462417395594504794553838954288984 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_req_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 77205178460968853999894181735049902748993775522489572259153011271639183268497 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2888964753 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_lc_esc.2888964753' seed=77205178460968853999894181735049902748993775522489572259153011271639183268497 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77205178460968853999894181735049902748993775522489572259153011271639183268497 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_lock 45087987793585543084821156087416106308321000326524480999416563702394569193988 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_dai_lock/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1614117380 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_lock.1614117380' seed=45087987793585543084821156087416106308321000326524480999416563702394569193988 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45087987793585543084821156087416106308321000326524480999416563702394569193988 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_dai_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_lock_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_errs 84017629583455726960059150602792333406872993588508041645928410192477601518379 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_dai_errs/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1905906475 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_dai_errs.1905906475' seed=84017629583455726960059150602792333406872993588508041645928410192477601518379 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84017629583455726960059150602792333406872993588508041645928410192477601518379 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_dai_errs/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_errs_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 2231078316280755819471236668105056051449708174126852395599286395399826101028 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4157395748 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_check_fail.4157395748' seed=2231078316280755819471236668105056051449708174126852395599286395399826101028 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2231078316280755819471236668105056051449708174126852395599286395399826101028 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_macro_errs 93781469430584623896647750824962130644097249315839378801015383146556478888788 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_macro_errs/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2404555604 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_macro_errs.2404555604' seed=93781469430584623896647750824962130644097249315839378801015383146556478888788 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93781469430584623896647750824962130644097249315839378801015383146556478888788 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_macro_errs/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_macro_errs_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_key_req 22090561408286818430834026659327762848844204334915700762265989362786985489927 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_key_req/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1661384199 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_parallel_key_req.1661384199' seed=22090561408286818430834026659327762848844204334915700762265989362786985489927 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22090561408286818430834026659327762848844204334915700762265989362786985489927 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_parallel_key_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_key_req_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_regwen 106813313427917864261657969133795565162280711335344671092408156570164433228508 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_regwen/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1901564636 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_regwen.1901564636' seed=106813313427917864261657969133795565162280711335344671092408156570164433228508 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106813313427917864261657969133795565162280711335344671092408156570164433228508 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_test_access 6187330920240642649014119321422517032463990109372899760144355840622579667348 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_test_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=130273684 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_test_access.130273684' seed=6187330920240642649014119321422517032463990109372899760144355840622579667348 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6187330920240642649014119321422517032463990109372899760144355840622579667348 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_test_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_test_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 113327368388174687401868632231778320048980921089576467859340007386176060661040 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1728585008 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_stress_all_with_rand_reset.1728585008' seed=113327368388174687401868632231778320048980921089576467859340007386176060661040 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113327368388174687401868632231778320048980921089576467859340007386176060661040 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_sec_cm 55200280348697342790793414837998291501703427355087258305174751995799235138784 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3533116640 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_sec_cm.3533116640' seed=55200280348697342790793414837998291501703427355087258305174751995799235138784 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55200280348697342790793414837998291501703427355087258305174751995799235138784 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_errors 9096383797461274017904995499945595183154059870223921255384652478352265651146 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1657611210 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_errors.1657611210' seed=9096383797461274017904995499945595183154059870223921255384652478352265651146 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9096383797461274017904995499945595183154059870223921255384652478352265651146 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_intg_err 5910725394738026541240504386679041405747076205234297778052319463403536398745 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2316712345 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_tl_intg_err.2316712345' seed=5910725394738026541240504386679041405747076205234297778052319463403536398745 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5910725394738026541240504386679041405747076205234297778052319463403536398745 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_alert_test 2758248813565633495475444728399652749500415842258440541966626256248231017736 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2175122696 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_alert_test.2175122696' seed=2758248813565633495475444728399652749500415842258440541966626256248231017736 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2758248813565633495475444728399652749500415842258440541966626256248231017736 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_intr_test 48943638128744491837887968940258615804276977493613715040268426653788476611050 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2833848810 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_intr_test.2833848810' seed=48943638128744491837887968940258615804276977493613715040268426653788476611050 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48943638128744491837887968940258615804276977493613715040268426653788476611050 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_mem_walk 34041454536045858544975749026196453765207140594130618256856773672630270291861 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_mem_walk/latest run_opts='+csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3423858581 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_walk.3423858581' seed=34041454536045858544975749026196453765207140594130618256856773672630270291861 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34041454536045858544975749026196453765207140594130618256856773672630270291861 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_mem_walk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_mem_partial_access 51174333343604354516311967050902533912907442164460962340690150990413625673369 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_mem_partial_access/latest run_opts='+run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3937257113 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_mem_partial_access.3937257113' seed=51174333343604354516311967050902533912907442164460962340690150990413625673369 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51174333343604354516311967050902533912907442164460962340690150990413625673369 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_mem_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_csr_hw_reset 16284378571096375703720007528744562089102346521334105616871091062983449148661 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_csr_hw_reset/latest run_opts='+csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1005092085 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_hw_reset.1005092085' seed=16284378571096375703720007528744562089102346521334105616871091062983449148661 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16284378571096375703720007528744562089102346521334105616871091062983449148661 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_csr_rw 49208584819866037086171046990370003766997938258197296936238963533017969738475 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2305442539 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_rw.2305442539' seed=49208584819866037086171046990370003766997938258197296936238963533017969738475 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49208584819866037086171046990370003766997938258197296936238963533017969738475 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_csr_bit_bash 97897663216657485608485951172982194460699718935647799209625005701260970837187 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_csr_bit_bash/latest run_opts='+csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1169441987 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_bit_bash.1169441987' seed=97897663216657485608485951172982194460699718935647799209625005701260970837187 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97897663216657485608485951172982194460699718935647799209625005701260970837187 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_csr_aliasing 83147785086407491894319768684027910841648665655343859488487431295212153571503 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_csr_aliasing/latest run_opts='+csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2096728239 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_aliasing.2096728239' seed=83147785086407491894319768684027910841648665655343859488487431295212153571503 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83147785086407491894319768684027910841648665655343859488487431295212153571503 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_same_csr_outstanding 38623366132211020735698804000596194801481819434822063221437021132226925531986 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4228485970 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_same_csr_outstanding.4228485970' seed=38623366132211020735698804000596194801481819434822063221437021132226925531986 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38623366132211020735698804000596194801481819434822063221437021132226925531986 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_csr_mem_rw_with_rand_reset 94468833000967716701474764042549956823471894242268331140689331440578739314117 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=378281413 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.otp_ctrl_csr_mem_rw_with_rand_reset.378281413' seed=94468833000967716701474764042549956823471894242268331140689331440578739314117 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94468833000967716701474764042549956823471894242268331140689331440578739314117 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/0.otp_ctrl_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_smoke 66862149146635044428350110290931910299229700495573374217389945129083700648078 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=863115406 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_smoke.863115406' seed=66862149146635044428350110290931910299229700495573374217389945129083700648078 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66862149146635044428350110290931910299229700495573374217389945129083700648078 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 35455201151058848638020543528772695342342455141478209710395507706781081809211 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=947663163 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_init_fail.947663163' seed=35455201151058848638020543528772695342342455141478209710395507706781081809211 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35455201151058848638020543528772695342342455141478209710395507706781081809211 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_background_chks 62126563816291889431612043044792854760490699916559824020652020343021430524634 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_background_chks/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1295403738 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_background_chks.1295403738' seed=62126563816291889431612043044792854760490699916559824020652020343021430524634 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62126563816291889431612043044792854760490699916559824020652020343021430524634 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_background_chks/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_background_chks_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_req 104343320910188395756910096737323886937265713016117132932942930126312427721770 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_req/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2096600106 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_req.2096600106' seed=104343320910188395756910096737323886937265713016117132932942930126312427721770 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104343320910188395756910096737323886937265713016117132932942930126312427721770 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_req_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 70084783496162404787801185817406488202231997733889207307996020761590855483860 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3789144532 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_lc_esc.3789144532' seed=70084783496162404787801185817406488202231997733889207307996020761590855483860 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70084783496162404787801185817406488202231997733889207307996020761590855483860 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_lock 68958835341575392216800729024596907839238109963661720439012419233915745737885 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_dai_lock/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2799836317 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_lock.2799836317' seed=68958835341575392216800729024596907839238109963661720439012419233915745737885 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68958835341575392216800729024596907839238109963661720439012419233915745737885 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_dai_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_lock_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_errs 94492402431990055923599697303508032729697427942344160840874764878009510015632 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_dai_errs/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=499266192 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_dai_errs.499266192' seed=94492402431990055923599697303508032729697427942344160840874764878009510015632 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94492402431990055923599697303508032729697427942344160840874764878009510015632 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_dai_errs/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_errs_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 6816806720552887890256823303763546045083024753543790684919177797371527292457 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1566434857 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_check_fail.1566434857' seed=6816806720552887890256823303763546045083024753543790684919177797371527292457 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6816806720552887890256823303763546045083024753543790684919177797371527292457 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_macro_errs 52041154287175719244324887711499918215523823572373976075136563998444306652660 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_macro_errs/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3435486708 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_macro_errs.3435486708' seed=52041154287175719244324887711499918215523823572373976075136563998444306652660 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=52041154287175719244324887711499918215523823572373976075136563998444306652660 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_macro_errs/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_macro_errs_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_key_req 15871279723973918081108336807254371247236534932329227162127339402420792635951 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_key_req/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3994858031 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_parallel_key_req.3994858031' seed=15871279723973918081108336807254371247236534932329227162127339402420792635951 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15871279723973918081108336807254371247236534932329227162127339402420792635951 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_parallel_key_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_key_req_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_regwen 91184912680239482605042364924919976588560732037303858322824078482194263399326 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_regwen/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=258169758 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_regwen.258169758' seed=91184912680239482605042364924919976588560732037303858322824078482194263399326 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91184912680239482605042364924919976588560732037303858322824078482194263399326 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_test_access 75304832510881505824441470195386564296450408488379733963076118941102064799649 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_test_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4099149729 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_test_access.4099149729' seed=75304832510881505824441470195386564296450408488379733963076118941102064799649 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75304832510881505824441470195386564296450408488379733963076118941102064799649 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_test_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_test_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 33766946562822345807365890250740772383008777794164816217358304672132608015212 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3632773996 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_stress_all_with_rand_reset.3632773996' seed=33766946562822345807365890250740772383008777794164816217358304672132608015212 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33766946562822345807365890250740772383008777794164816217358304672132608015212 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_sec_cm 26470355161070493784690607323692212903084226273914590780520904883782857480488 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2296076584 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_sec_cm.2296076584' seed=26470355161070493784690607323692212903084226273914590780520904883782857480488 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26470355161070493784690607323692212903084226273914590780520904883782857480488 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_errors 938319540411416807753173845249018330691017868877960127819263845272685109954 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=677110466 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_errors.677110466' seed=938319540411416807753173845249018330691017868877960127819263845272685109954 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=938319540411416807753173845249018330691017868877960127819263845272685109954 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_intg_err 11467173974021090081014418318617745455419596026895976239937943239484860331800 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1302132504 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_tl_intg_err.1302132504' seed=11467173974021090081014418318617745455419596026895976239937943239484860331800 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11467173974021090081014418318617745455419596026895976239937943239484860331800 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_alert_test 33680143344043840822207900662833225290646983650090632470573598453604980016878 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4160145134 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_alert_test.4160145134' seed=33680143344043840822207900662833225290646983650090632470573598453604980016878 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33680143344043840822207900662833225290646983650090632470573598453604980016878 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_intr_test 58973176747150819078679221803438926761449623521926088000936023119986828082539 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=934903147 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_intr_test.934903147' seed=58973176747150819078679221803438926761449623521926088000936023119986828082539 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58973176747150819078679221803438926761449623521926088000936023119986828082539 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_csr_rw 93714144531794348940565678127333252547097942954063635914468224067956736890230 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1676252534 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_rw.1676252534' seed=93714144531794348940565678127333252547097942954063635914468224067956736890230 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93714144531794348940565678127333252547097942954063635914468224067956736890230 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_same_csr_outstanding 35690433244767152524065295168448894800398023418925143449915386695085209013861 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=240242277 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_same_csr_outstanding.240242277' seed=35690433244767152524065295168448894800398023418925143449915386695085209013861 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35690433244767152524065295168448894800398023418925143449915386695085209013861 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_csr_mem_rw_with_rand_reset 84550524915976338520964294674671175672403256259987314530809659654501223914698 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2956221642 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.otp_ctrl_csr_mem_rw_with_rand_reset.2956221642' seed=84550524915976338520964294674671175672403256259987314530809659654501223914698 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84550524915976338520964294674671175672403256259987314530809659654501223914698 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/1.otp_ctrl_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_smoke 66787902096805288396291848729575975864825931815902146557560724075295045149857 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2393728161 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_smoke.2393728161' seed=66787902096805288396291848729575975864825931815902146557560724075295045149857 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66787902096805288396291848729575975864825931815902146557560724075295045149857 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 108097219886174401192142581250939282482966497497230250624399582821778042978513 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=746127569 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_init_fail.746127569' seed=108097219886174401192142581250939282482966497497230250624399582821778042978513 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108097219886174401192142581250939282482966497497230250624399582821778042978513 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_background_chks 61360490229910094998007433710858023366607857697197017964250909697733432405237 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_background_chks/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=291466485 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_background_chks.291466485' seed=61360490229910094998007433710858023366607857697197017964250909697733432405237 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61360490229910094998007433710858023366607857697197017964250909697733432405237 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_background_chks/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_background_chks_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_req 87246954545993318618869035053962937701019428981882777080045209304859799250146 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_lc_req/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1907156194 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_req.1907156194' seed=87246954545993318618869035053962937701019428981882777080045209304859799250146 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87246954545993318618869035053962937701019428981882777080045209304859799250146 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_lc_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_req_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 44715513662420680243639222816820819288971522908238356282669407135322146020610 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1553669378 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_lc_esc.1553669378' seed=44715513662420680243639222816820819288971522908238356282669407135322146020610 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44715513662420680243639222816820819288971522908238356282669407135322146020610 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_lock 84830391439548133986506859873530084956738469968429036857618632764133670205002 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_dai_lock/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1326265930 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_lock.1326265930' seed=84830391439548133986506859873530084956738469968429036857618632764133670205002 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84830391439548133986506859873530084956738469968429036857618632764133670205002 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_dai_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_lock_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_errs 106652623161000044932906495778928052492237819711311375632400455378966750301332 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_dai_errs/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2241203348 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_dai_errs.2241203348' seed=106652623161000044932906495778928052492237819711311375632400455378966750301332 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106652623161000044932906495778928052492237819711311375632400455378966750301332 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_dai_errs/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_errs_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 112247734043405931307429960836381619719476132702154549424890281952523500949174 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2255785654 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_check_fail.2255785654' seed=112247734043405931307429960836381619719476132702154549424890281952523500949174 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112247734043405931307429960836381619719476132702154549424890281952523500949174 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_macro_errs 72147247619584210330471629314035862376885540648160808582279120858032423603938 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_macro_errs/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=815304418 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_macro_errs.815304418' seed=72147247619584210330471629314035862376885540648160808582279120858032423603938 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72147247619584210330471629314035862376885540648160808582279120858032423603938 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_macro_errs/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_macro_errs_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_key_req 30716003002379062670489164528366248992018711549265956239658363721972184092984 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_key_req/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2675020088 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_parallel_key_req.2675020088' seed=30716003002379062670489164528366248992018711549265956239658363721972184092984 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30716003002379062670489164528366248992018711549265956239658363721972184092984 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_parallel_key_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_key_req_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_regwen 41474177681618104336334530768428040331348659419287771336683433646167876029678 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_regwen/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3879849198 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_regwen.3879849198' seed=41474177681618104336334530768428040331348659419287771336683433646167876029678 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41474177681618104336334530768428040331348659419287771336683433646167876029678 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_test_access 62374841302858200586928874535491738217118181800005455313181826671880403021157 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_test_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=999157093 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_test_access.999157093' seed=62374841302858200586928874535491738217118181800005455313181826671880403021157 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62374841302858200586928874535491738217118181800005455313181826671880403021157 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_test_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_test_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 73985373610469637583199680561941642445219599511712893659938834776952681133045 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=981857269 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_stress_all_with_rand_reset.981857269' seed=73985373610469637583199680561941642445219599511712893659938834776952681133045 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73985373610469637583199680561941642445219599511712893659938834776952681133045 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_sec_cm 73380980221688974105250629064990579435933705515477614786314571649884669379226 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2642707098 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_sec_cm.2642707098' seed=73380980221688974105250629064990579435933705515477614786314571649884669379226 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73380980221688974105250629064990579435933705515477614786314571649884669379226 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_errors 63760358312186960732989644461288986793608063753222363245159108025548025374222 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2717132302 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_errors.2717132302' seed=63760358312186960732989644461288986793608063753222363245159108025548025374222 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63760358312186960732989644461288986793608063753222363245159108025548025374222 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_intg_err 40240445034642467570367780996475380421255702907962269786982231174126621439366 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=274740614 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_tl_intg_err.274740614' seed=40240445034642467570367780996475380421255702907962269786982231174126621439366 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40240445034642467570367780996475380421255702907962269786982231174126621439366 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_alert_test 95118776212262211735375674588054179180758216592943535408375075227341704063028 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1965484084 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_alert_test.1965484084' seed=95118776212262211735375674588054179180758216592943535408375075227341704063028 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95118776212262211735375674588054179180758216592943535408375075227341704063028 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_intr_test 109374564764315921853450375037992138090308034018256229408032689255389851978071 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1344702807 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_intr_test.1344702807' seed=109374564764315921853450375037992138090308034018256229408032689255389851978071 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109374564764315921853450375037992138090308034018256229408032689255389851978071 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_csr_rw 87477232077114614832287193485557217952482034733444267920904913832581688213483 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3805560811 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_rw.3805560811' seed=87477232077114614832287193485557217952482034733444267920904913832581688213483 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87477232077114614832287193485557217952482034733444267920904913832581688213483 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_same_csr_outstanding 65822236509402671496815241505936199453210179881189435376260228705874607753710 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=362433006 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_same_csr_outstanding.362433006' seed=65822236509402671496815241505936199453210179881189435376260228705874607753710 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65822236509402671496815241505936199453210179881189435376260228705874607753710 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_csr_mem_rw_with_rand_reset 66853403620491484112910014964060782059995819743627555696461893417323324984277 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=638274517 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.otp_ctrl_csr_mem_rw_with_rand_reset.638274517' seed=66853403620491484112910014964060782059995819743627555696461893417323324984277 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66853403620491484112910014964060782059995819743627555696461893417323324984277 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/2.otp_ctrl_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_smoke 114920317109008095288764918056122524185048244161526671219980020741705187432199 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3194722055 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_smoke.3194722055' seed=114920317109008095288764918056122524185048244161526671219980020741705187432199 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114920317109008095288764918056122524185048244161526671219980020741705187432199 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 80909393732699228579764044048400591062146033872435035597398324166377787153742 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=129555790 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_init_fail.129555790' seed=80909393732699228579764044048400591062146033872435035597398324166377787153742 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80909393732699228579764044048400591062146033872435035597398324166377787153742 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_background_chks 7343296501861221478905579496461948737042485700215184654072885333637368044158 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_background_chks/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=65460862 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_background_chks.65460862' seed=7343296501861221478905579496461948737042485700215184654072885333637368044158 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7343296501861221478905579496461948737042485700215184654072885333637368044158 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_background_chks/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_background_chks_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_req 69938229741359636665850956062886325510166744919310350953232546586380645839156 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_lc_req/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=330707252 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_req.330707252' seed=69938229741359636665850956062886325510166744919310350953232546586380645839156 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69938229741359636665850956062886325510166744919310350953232546586380645839156 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_lc_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_req_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 40652007582132685317964337182608343528781890905872972488971405815086771521029 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4040082949 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_lc_esc.4040082949' seed=40652007582132685317964337182608343528781890905872972488971405815086771521029 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40652007582132685317964337182608343528781890905872972488971405815086771521029 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_lock 4893658224134791861235268346226318560184769165635648346616429530488254411173 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_dai_lock/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4185567653 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_lock.4185567653' seed=4893658224134791861235268346226318560184769165635648346616429530488254411173 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4893658224134791861235268346226318560184769165635648346616429530488254411173 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_dai_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_lock_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_errs 113510226311721687778262675615767711083093415410280461993118397895501309955200 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_dai_errs/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2366000256 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_dai_errs.2366000256' seed=113510226311721687778262675615767711083093415410280461993118397895501309955200 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113510226311721687778262675615767711083093415410280461993118397895501309955200 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_dai_errs/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_errs_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 94725391507962376039304466997092170215776487985449201871957257649678308237192 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=876765064 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_check_fail.876765064' seed=94725391507962376039304466997092170215776487985449201871957257649678308237192 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94725391507962376039304466997092170215776487985449201871957257649678308237192 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_macro_errs 35863252308963773569158526318040651623210109298810041425971171273386758363506 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_macro_errs/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3122780530 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_macro_errs.3122780530' seed=35863252308963773569158526318040651623210109298810041425971171273386758363506 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35863252308963773569158526318040651623210109298810041425971171273386758363506 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_macro_errs/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_macro_errs_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_key_req 42408891107753710254070696414148718756640876797014548278479973274622316273774 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_key_req/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1307336814 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_parallel_key_req.1307336814' seed=42408891107753710254070696414148718756640876797014548278479973274622316273774 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42408891107753710254070696414148718756640876797014548278479973274622316273774 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_parallel_key_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_key_req_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_regwen 29063472303183478797796788309307547559629611807427271433176818879899838069694 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_regwen/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4025367486 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_regwen.4025367486' seed=29063472303183478797796788309307547559629611807427271433176818879899838069694 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29063472303183478797796788309307547559629611807427271433176818879899838069694 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_test_access 50755290141412297116252787054180340649241510548735954802146742120836548324328 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_test_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=86567912 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_test_access.86567912' seed=50755290141412297116252787054180340649241510548735954802146742120836548324328 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50755290141412297116252787054180340649241510548735954802146742120836548324328 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_test_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_test_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 95457478153311095694186453747407010995391996433320759280650117890981139225530 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=518953914 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_stress_all_with_rand_reset.518953914' seed=95457478153311095694186453747407010995391996433320759280650117890981139225530 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95457478153311095694186453747407010995391996433320759280650117890981139225530 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_sec_cm 75177434778347386759293721551253078354096782046334366418222260989179772143104 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3196192256 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_sec_cm.3196192256' seed=75177434778347386759293721551253078354096782046334366418222260989179772143104 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75177434778347386759293721551253078354096782046334366418222260989179772143104 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_errors 31675435359576443599985670474486395389083072450105112298880868054310464720783 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2063536015 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_errors.2063536015' seed=31675435359576443599985670474486395389083072450105112298880868054310464720783 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31675435359576443599985670474486395389083072450105112298880868054310464720783 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_intg_err 2799392981337073873508387842467521583349781045773586268445179409593514068365 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2097678733 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_tl_intg_err.2097678733' seed=2799392981337073873508387842467521583349781045773586268445179409593514068365 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2799392981337073873508387842467521583349781045773586268445179409593514068365 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_alert_test 64468652487634299922240969577632163204893529579475420550120424736549198156546 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1085592322 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_alert_test.1085592322' seed=64468652487634299922240969577632163204893529579475420550120424736549198156546 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64468652487634299922240969577632163204893529579475420550120424736549198156546 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_intr_test 67815970466384729899280958464537277224520641283058814178099985732162585810151 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2810631399 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_intr_test.2810631399' seed=67815970466384729899280958464537277224520641283058814178099985732162585810151 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67815970466384729899280958464537277224520641283058814178099985732162585810151 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_csr_rw 82294292840629727049083178094023831843237532174996660706618741190122943088267 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2780104331 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_rw.2780104331' seed=82294292840629727049083178094023831843237532174996660706618741190122943088267 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82294292840629727049083178094023831843237532174996660706618741190122943088267 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_same_csr_outstanding 56455536471147382192124884684274875281565364325004366011782058445037162965170 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2438178994 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_same_csr_outstanding.2438178994' seed=56455536471147382192124884684274875281565364325004366011782058445037162965170 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56455536471147382192124884684274875281565364325004366011782058445037162965170 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_csr_mem_rw_with_rand_reset 88180377938209179476864293406126633626598379415824256857801279081152057962365 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3379556221 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.otp_ctrl_csr_mem_rw_with_rand_reset.3379556221' seed=88180377938209179476864293406126633626598379415824256857801279081152057962365 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88180377938209179476864293406126633626598379415824256857801279081152057962365 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/3.otp_ctrl_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_smoke 56102687152181733313385010174454987118249115651979687911793682086690007403574 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3608005686 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_smoke.3608005686' seed=56102687152181733313385010174454987118249115651979687911793682086690007403574 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56102687152181733313385010174454987118249115651979687911793682086690007403574 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 101125566464974075490346883043914854398129565451621497011762881551546728810575 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4085221455 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_init_fail.4085221455' seed=101125566464974075490346883043914854398129565451621497011762881551546728810575 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101125566464974075490346883043914854398129565451621497011762881551546728810575 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_background_chks 88084643468480525261901469528339884046426004526278556895628872577343436685971 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_background_chks/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2437481107 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_background_chks.2437481107' seed=88084643468480525261901469528339884046426004526278556895628872577343436685971 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88084643468480525261901469528339884046426004526278556895628872577343436685971 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_background_chks/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_background_chks_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_req 113651637981373447955068571505288016721548173439863889318059768626189448875450 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_lc_req/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2062912954 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_req.2062912954' seed=113651637981373447955068571505288016721548173439863889318059768626189448875450 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113651637981373447955068571505288016721548173439863889318059768626189448875450 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_lc_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_req_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 78443111020167661655596220430929520170772261709541746976940164855362408830432 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=987911648 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_lc_esc.987911648' seed=78443111020167661655596220430929520170772261709541746976940164855362408830432 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78443111020167661655596220430929520170772261709541746976940164855362408830432 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_lock 86939906104304435008858602662810446006231867488879889670849258400043703205277 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_dai_lock/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4181982621 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_lock.4181982621' seed=86939906104304435008858602662810446006231867488879889670849258400043703205277 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86939906104304435008858602662810446006231867488879889670849258400043703205277 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_dai_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_lock_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_errs 19731870287324603327184359373818075136433224055165735159952296732471169633201 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_dai_errs/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2309213105 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_dai_errs.2309213105' seed=19731870287324603327184359373818075136433224055165735159952296732471169633201 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19731870287324603327184359373818075136433224055165735159952296732471169633201 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_dai_errs/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_errs_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 94043470675434242738529686192965791646462682318329526334443214612221448107249 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1017853169 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_check_fail.1017853169' seed=94043470675434242738529686192965791646462682318329526334443214612221448107249 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94043470675434242738529686192965791646462682318329526334443214612221448107249 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_macro_errs 42813614011461014394787546324300077569932778369448586156452665902317592468278 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_macro_errs/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=927292214 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_macro_errs.927292214' seed=42813614011461014394787546324300077569932778369448586156452665902317592468278 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42813614011461014394787546324300077569932778369448586156452665902317592468278 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_macro_errs/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_macro_errs_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_key_req 96151132003790397843993658381517875516813360575800777505576863424463982782436 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_key_req/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3853740004 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_parallel_key_req.3853740004' seed=96151132003790397843993658381517875516813360575800777505576863424463982782436 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96151132003790397843993658381517875516813360575800777505576863424463982782436 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_parallel_key_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_key_req_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_regwen 110688397805625326784114463372933234118034253578946934032507978716066549784681 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_regwen/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1203167337 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_regwen.1203167337' seed=110688397805625326784114463372933234118034253578946934032507978716066549784681 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110688397805625326784114463372933234118034253578946934032507978716066549784681 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_test_access 104956677976960883896587478842162441396818315415833903275957501718938263138022 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_test_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3388387046 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_test_access.3388387046' seed=104956677976960883896587478842162441396818315415833903275957501718938263138022 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104956677976960883896587478842162441396818315415833903275957501718938263138022 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_test_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_test_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 72163399937256539498718875641227419755480953706348051748286120497196411119625 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1018947593 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_stress_all_with_rand_reset.1018947593' seed=72163399937256539498718875641227419755480953706348051748286120497196411119625 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72163399937256539498718875641227419755480953706348051748286120497196411119625 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_sec_cm 77182820615899743485568460162679211889439712567700525537754725151865044979377 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3412053681 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_sec_cm.3412053681' seed=77182820615899743485568460162679211889439712567700525537754725151865044979377 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77182820615899743485568460162679211889439712567700525537754725151865044979377 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_errors 36691220314204301832453277800350181822931038533628826944516191991974625150939 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=886179803 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_errors.886179803' seed=36691220314204301832453277800350181822931038533628826944516191991974625150939 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36691220314204301832453277800350181822931038533628826944516191991974625150939 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_intg_err 23655499885080465740354951960322826183252240658314493052558768050879444592308 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3492849332 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_tl_intg_err.3492849332' seed=23655499885080465740354951960322826183252240658314493052558768050879444592308 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23655499885080465740354951960322826183252240658314493052558768050879444592308 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_alert_test 53739577532754696436769029946442532894624857492199371194230627868883443656103 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=122037671 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_alert_test.122037671' seed=53739577532754696436769029946442532894624857492199371194230627868883443656103 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53739577532754696436769029946442532894624857492199371194230627868883443656103 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_intr_test 15373463295429835917213107419347016552063912239892504087767804568615605664603 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3885398875 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_intr_test.3885398875' seed=15373463295429835917213107419347016552063912239892504087767804568615605664603 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15373463295429835917213107419347016552063912239892504087767804568615605664603 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_csr_rw 69235956943588400551498717804562672454150492507393263540912878542960785554465 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1179319329 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_rw.1179319329' seed=69235956943588400551498717804562672454150492507393263540912878542960785554465 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69235956943588400551498717804562672454150492507393263540912878542960785554465 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_same_csr_outstanding 41206456681059653481083413548725744739492707859719992773731927906212253951329 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=301098337 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_same_csr_outstanding.301098337' seed=41206456681059653481083413548725744739492707859719992773731927906212253951329 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41206456681059653481083413548725744739492707859719992773731927906212253951329 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_csr_mem_rw_with_rand_reset 75736510001087634422902333360070780035954495889435663196939368193215863459523 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1301024451 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.otp_ctrl_csr_mem_rw_with_rand_reset.1301024451' seed=75736510001087634422902333360070780035954495889435663196939368193215863459523 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75736510001087634422902333360070780035954495889435663196939368193215863459523 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/4.otp_ctrl_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_smoke 21024138691379894409973910287944827067720302019551118543030260602693062483553 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/5.otp_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3835158113 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_smoke.3835158113' seed=21024138691379894409973910287944827067720302019551118543030260602693062483553 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21024138691379894409973910287944827067720302019551118543030260602693062483553 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/5.otp_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 71195702600818883722487019057066373458571138041009794447110117102909512360837 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/5.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=872293253 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_init_fail.872293253' seed=71195702600818883722487019057066373458571138041009794447110117102909512360837 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71195702600818883722487019057066373458571138041009794447110117102909512360837 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/5.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_background_chks 112872353360143508111445696166980584130164896110700364834683767700398078865379 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/5.otp_ctrl_background_chks/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2054598627 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_background_chks.2054598627' seed=112872353360143508111445696166980584130164896110700364834683767700398078865379 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112872353360143508111445696166980584130164896110700364834683767700398078865379 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/5.otp_ctrl_background_chks/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_background_chks_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_req 107188582463685906124995715868869132362152251725877225530843301836623975364857 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_lc_req/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=382548217 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_req.382548217' seed=107188582463685906124995715868869132362152251725877225530843301836623975364857 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107188582463685906124995715868869132362152251725877225530843301836623975364857 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_lc_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_req_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 7287454566015100875650895523689969666388303184866156407239902979209881367158 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3343299190 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_lc_esc.3343299190' seed=7287454566015100875650895523689969666388303184866156407239902979209881367158 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7287454566015100875650895523689969666388303184866156407239902979209881367158 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_lock 61498772168264065265846915121868459721583260773974758590050801928259134538534 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/5.otp_ctrl_dai_lock/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=693617446 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_lock.693617446' seed=61498772168264065265846915121868459721583260773974758590050801928259134538534 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61498772168264065265846915121868459721583260773974758590050801928259134538534 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/5.otp_ctrl_dai_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_lock_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_errs 3544491176497346664240361306030206640067217024845768514957237827070906243481 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/5.otp_ctrl_dai_errs/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2238355865 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_dai_errs.2238355865' seed=3544491176497346664240361306030206640067217024845768514957237827070906243481 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3544491176497346664240361306030206640067217024845768514957237827070906243481 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/5.otp_ctrl_dai_errs/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_errs_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 90075527478073179353993892167183907324988184697555077158756526981822993367151 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/5.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1772847215 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_check_fail.1772847215' seed=90075527478073179353993892167183907324988184697555077158756526981822993367151 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90075527478073179353993892167183907324988184697555077158756526981822993367151 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/5.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_macro_errs 26599224791062502924187625524534818549267659618175789251180083348308007733299 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/5.otp_ctrl_macro_errs/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2040416307 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_macro_errs.2040416307' seed=26599224791062502924187625524534818549267659618175789251180083348308007733299 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26599224791062502924187625524534818549267659618175789251180083348308007733299 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/5.otp_ctrl_macro_errs/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_macro_errs_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_key_req 43554356724802728508269170503355425049688976456652427139337303554533289508229 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_key_req/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=87178629 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_parallel_key_req.87178629' seed=43554356724802728508269170503355425049688976456652427139337303554533289508229 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43554356724802728508269170503355425049688976456652427139337303554533289508229 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/5.otp_ctrl_parallel_key_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_key_req_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_regwen 13456523188872862869272915005238069056645211612202073856965714842797186279592 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/5.otp_ctrl_regwen/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4034717864 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_regwen.4034717864' seed=13456523188872862869272915005238069056645211612202073856965714842797186279592 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13456523188872862869272915005238069056645211612202073856965714842797186279592 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/5.otp_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_test_access 98703485812085475391561573021141450707710680976492873002231588480988167148705 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/5.otp_ctrl_test_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4064416929 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_test_access.4064416929' seed=98703485812085475391561573021141450707710680976492873002231588480988167148705 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98703485812085475391561573021141450707710680976492873002231588480988167148705 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/5.otp_ctrl_test_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_test_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 11755630017960460170799445525222246160658246722076002362764975064308591284914 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2439959218 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_stress_all_with_rand_reset.2439959218' seed=11755630017960460170799445525222246160658246722076002362764975064308591284914 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11755630017960460170799445525222246160658246722076002362764975064308591284914 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/5.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_errors 28380299041491754429607278234863023854414113355090351188041931355653001404998 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/5.otp_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2218222150 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_errors.2218222150' seed=28380299041491754429607278234863023854414113355090351188041931355653001404998 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28380299041491754429607278234863023854414113355090351188041931355653001404998 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/5.otp_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_intg_err 57687382225278764601368941150531857364937742103451060727396548730750144404149 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/5.otp_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=448846517 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_tl_intg_err.448846517' seed=57687382225278764601368941150531857364937742103451060727396548730750144404149 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57687382225278764601368941150531857364937742103451060727396548730750144404149 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/5.otp_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_alert_test 1118027335366172054156225085103476817269722681123245831614643496217805437543 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/5.otp_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2228337255 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_alert_test.2228337255' seed=1118027335366172054156225085103476817269722681123245831614643496217805437543 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1118027335366172054156225085103476817269722681123245831614643496217805437543 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/5.otp_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_intr_test 75295203165692057063439329307194934871775044275526480205023900292641825223657 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/5.otp_ctrl_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3858756585 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.otp_ctrl_intr_test.3858756585' seed=75295203165692057063439329307194934871775044275526480205023900292641825223657 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75295203165692057063439329307194934871775044275526480205023900292641825223657 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/5.otp_ctrl_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_smoke 4397258126494647786288633828240768963636249480988872192165255789885527688252 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/6.otp_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1400374332 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_smoke.1400374332' seed=4397258126494647786288633828240768963636249480988872192165255789885527688252 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4397258126494647786288633828240768963636249480988872192165255789885527688252 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/6.otp_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 43788037364387394159096585158697806011929711587077887662015200306616110418116 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/6.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=990382276 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_init_fail.990382276' seed=43788037364387394159096585158697806011929711587077887662015200306616110418116 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43788037364387394159096585158697806011929711587077887662015200306616110418116 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/6.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_background_chks 25871428413726863496810136500329319808687365667561245315481133042617868922743 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/6.otp_ctrl_background_chks/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=148156279 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_background_chks.148156279' seed=25871428413726863496810136500329319808687365667561245315481133042617868922743 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25871428413726863496810136500329319808687365667561245315481133042617868922743 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/6.otp_ctrl_background_chks/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_background_chks_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_req 31844018226196313858568531255003821778520538365789199882643366679067843278241 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_lc_req/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1137358241 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_req.1137358241' seed=31844018226196313858568531255003821778520538365789199882643366679067843278241 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31844018226196313858568531255003821778520538365789199882643366679067843278241 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_lc_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_req_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 69308587155053134000368259561553952295672937850041131582915010446962520178658 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1999323106 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_lc_esc.1999323106' seed=69308587155053134000368259561553952295672937850041131582915010446962520178658 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69308587155053134000368259561553952295672937850041131582915010446962520178658 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_lock 11864129213128110889257063929135795302398401671550648753029615886716805761359 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/6.otp_ctrl_dai_lock/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=873122127 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_lock.873122127' seed=11864129213128110889257063929135795302398401671550648753029615886716805761359 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11864129213128110889257063929135795302398401671550648753029615886716805761359 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/6.otp_ctrl_dai_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_lock_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_errs 106759629125275168299115207100844685974447451794391465249189293020427744093519 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/6.otp_ctrl_dai_errs/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=856859983 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_dai_errs.856859983' seed=106759629125275168299115207100844685974447451794391465249189293020427744093519 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106759629125275168299115207100844685974447451794391465249189293020427744093519 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/6.otp_ctrl_dai_errs/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_errs_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 101183900748914084572237558649246508836235081812065510143175540522613299035463 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/6.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1702706503 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_check_fail.1702706503' seed=101183900748914084572237558649246508836235081812065510143175540522613299035463 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101183900748914084572237558649246508836235081812065510143175540522613299035463 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/6.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_macro_errs 101253897140364159476305624841740889511195142204739215915834847272345988170272 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/6.otp_ctrl_macro_errs/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2739601952 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_macro_errs.2739601952' seed=101253897140364159476305624841740889511195142204739215915834847272345988170272 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101253897140364159476305624841740889511195142204739215915834847272345988170272 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/6.otp_ctrl_macro_errs/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_macro_errs_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_key_req 69362916813883071523259560530805133872953953141958587148303011069195449224689 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_key_req/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1435454961 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_parallel_key_req.1435454961' seed=69362916813883071523259560530805133872953953141958587148303011069195449224689 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69362916813883071523259560530805133872953953141958587148303011069195449224689 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/6.otp_ctrl_parallel_key_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_key_req_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_regwen 110055419739285120881568417346871081812441358493741938657688739523052216855027 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/6.otp_ctrl_regwen/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=637086195 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_regwen.637086195' seed=110055419739285120881568417346871081812441358493741938657688739523052216855027 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110055419739285120881568417346871081812441358493741938657688739523052216855027 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/6.otp_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_test_access 19603544037138171282241100027792067386213832745839106267314470515437379502253 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/6.otp_ctrl_test_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3856646317 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_test_access.3856646317' seed=19603544037138171282241100027792067386213832745839106267314470515437379502253 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19603544037138171282241100027792067386213832745839106267314470515437379502253 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/6.otp_ctrl_test_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_test_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 99764642082129759618768649614675621440992424677948409599127973229962692929061 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=789587493 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_stress_all_with_rand_reset.789587493' seed=99764642082129759618768649614675621440992424677948409599127973229962692929061 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99764642082129759618768649614675621440992424677948409599127973229962692929061 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/6.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_errors 30128103850146064183895873276268204871873371267078470661160728206868514721019 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/6.otp_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1618070779 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_errors.1618070779' seed=30128103850146064183895873276268204871873371267078470661160728206868514721019 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30128103850146064183895873276268204871873371267078470661160728206868514721019 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/6.otp_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_intg_err 66575990187895889352530217277847769588922486475792625896221838005045104824299 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/6.otp_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1271484395 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_tl_intg_err.1271484395' seed=66575990187895889352530217277847769588922486475792625896221838005045104824299 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66575990187895889352530217277847769588922486475792625896221838005045104824299 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/6.otp_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_alert_test 28155947580043540075235175494549881787108463410806364025655063248331926532706 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/6.otp_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3080319586 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_alert_test.3080319586' seed=28155947580043540075235175494549881787108463410806364025655063248331926532706 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28155947580043540075235175494549881787108463410806364025655063248331926532706 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/6.otp_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_intr_test 98452420754447864787552097475092600629178158460932577041479384651983507264536 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/6.otp_ctrl_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1138070552 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.otp_ctrl_intr_test.1138070552' seed=98452420754447864787552097475092600629178158460932577041479384651983507264536 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98452420754447864787552097475092600629178158460932577041479384651983507264536 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/6.otp_ctrl_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_smoke 90633262208539880015649215252772925245785463284033383807034417114399295147500 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/7.otp_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3713535468 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_smoke.3713535468' seed=90633262208539880015649215252772925245785463284033383807034417114399295147500 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90633262208539880015649215252772925245785463284033383807034417114399295147500 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/7.otp_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 8510952113304265340491657922570653284121220570864198928294573236416019127231 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/7.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4227554239 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_init_fail.4227554239' seed=8510952113304265340491657922570653284121220570864198928294573236416019127231 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8510952113304265340491657922570653284121220570864198928294573236416019127231 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/7.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_background_chks 27825621428579626573863047998392971313789134039781135582177526276251508052533 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/7.otp_ctrl_background_chks/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2881524277 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_background_chks.2881524277' seed=27825621428579626573863047998392971313789134039781135582177526276251508052533 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27825621428579626573863047998392971313789134039781135582177526276251508052533 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/7.otp_ctrl_background_chks/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_background_chks_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_req 30527478984646582322812468870794354060670403263877760307880542777023528876006 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_lc_req/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2706290662 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_req.2706290662' seed=30527478984646582322812468870794354060670403263877760307880542777023528876006 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30527478984646582322812468870794354060670403263877760307880542777023528876006 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_lc_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_req_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 20039427077269885135060396235695552120683643954662964526777772581024639785696 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1830853344 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_lc_esc.1830853344' seed=20039427077269885135060396235695552120683643954662964526777772581024639785696 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20039427077269885135060396235695552120683643954662964526777772581024639785696 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_lock 47998581644233456149900020939197228586154454208494163109259017768537647022425 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/7.otp_ctrl_dai_lock/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1710031193 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_lock.1710031193' seed=47998581644233456149900020939197228586154454208494163109259017768537647022425 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47998581644233456149900020939197228586154454208494163109259017768537647022425 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/7.otp_ctrl_dai_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_lock_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_errs 51669313136203924340012505580060380272607699384007312249887922054584143520334 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/7.otp_ctrl_dai_errs/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1686184526 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_dai_errs.1686184526' seed=51669313136203924340012505580060380272607699384007312249887922054584143520334 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51669313136203924340012505580060380272607699384007312249887922054584143520334 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/7.otp_ctrl_dai_errs/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_errs_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 62592447306220939652875025199798933737389047890375702020546518125238805645364 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/7.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=368363572 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_check_fail.368363572' seed=62592447306220939652875025199798933737389047890375702020546518125238805645364 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62592447306220939652875025199798933737389047890375702020546518125238805645364 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/7.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_macro_errs 9191001680996566733906626050587286548674644184234715030717922037241344580533 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/7.otp_ctrl_macro_errs/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=81419189 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_macro_errs.81419189' seed=9191001680996566733906626050587286548674644184234715030717922037241344580533 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9191001680996566733906626050587286548674644184234715030717922037241344580533 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/7.otp_ctrl_macro_errs/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_macro_errs_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_key_req 16942038986808682063623483016292894119436368335020185195183837668234597302678 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_key_req/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2955477398 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_parallel_key_req.2955477398' seed=16942038986808682063623483016292894119436368335020185195183837668234597302678 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16942038986808682063623483016292894119436368335020185195183837668234597302678 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/7.otp_ctrl_parallel_key_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_key_req_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_regwen 90269685668538267852148987663136052183361228724573648455002932149579397772378 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/7.otp_ctrl_regwen/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1521529946 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_regwen.1521529946' seed=90269685668538267852148987663136052183361228724573648455002932149579397772378 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90269685668538267852148987663136052183361228724573648455002932149579397772378 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/7.otp_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_test_access 96691293917371638280909058819053801957484403858596940074261511893216343580836 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/7.otp_ctrl_test_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3662373028 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_test_access.3662373028' seed=96691293917371638280909058819053801957484403858596940074261511893216343580836 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96691293917371638280909058819053801957484403858596940074261511893216343580836 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/7.otp_ctrl_test_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_test_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 20780503860999543384953711773830375131574280558954282029778965809813447537462 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3676861238 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_stress_all_with_rand_reset.3676861238' seed=20780503860999543384953711773830375131574280558954282029778965809813447537462 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20780503860999543384953711773830375131574280558954282029778965809813447537462 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/7.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_errors 70438063085768211346591404940388099462931205672186875513690147275319120073105 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/7.otp_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2105381265 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_errors.2105381265' seed=70438063085768211346591404940388099462931205672186875513690147275319120073105 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70438063085768211346591404940388099462931205672186875513690147275319120073105 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/7.otp_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_intg_err 68853309568076981454922960313349506856820499470622973715893130353493445861247 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/7.otp_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2512805759 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_tl_intg_err.2512805759' seed=68853309568076981454922960313349506856820499470622973715893130353493445861247 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68853309568076981454922960313349506856820499470622973715893130353493445861247 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/7.otp_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_alert_test 12470742278042191163932308120841281571399939605134943661207170703254302395203 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/7.otp_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2125368131 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_alert_test.2125368131' seed=12470742278042191163932308120841281571399939605134943661207170703254302395203 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12470742278042191163932308120841281571399939605134943661207170703254302395203 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/7.otp_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_intr_test 14407373967155190505900914944772782435021653200450724611481095374910556043167 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/7.otp_ctrl_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3471931295 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.otp_ctrl_intr_test.3471931295' seed=14407373967155190505900914944772782435021653200450724611481095374910556043167 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=14407373967155190505900914944772782435021653200450724611481095374910556043167 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/7.otp_ctrl_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_smoke 104456071290928983139226966162217204178439070017794664260880067880319013697456 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/8.otp_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1213020080 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_smoke.1213020080' seed=104456071290928983139226966162217204178439070017794664260880067880319013697456 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104456071290928983139226966162217204178439070017794664260880067880319013697456 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/8.otp_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 16245335343410547140109946405401111798573431368620207361109684221460303081749 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/8.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1162113301 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_init_fail.1162113301' seed=16245335343410547140109946405401111798573431368620207361109684221460303081749 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16245335343410547140109946405401111798573431368620207361109684221460303081749 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/8.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_background_chks 80278695753897067374552890221372580923000151840584169699849464699793502688709 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/8.otp_ctrl_background_chks/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2440091077 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_background_chks.2440091077' seed=80278695753897067374552890221372580923000151840584169699849464699793502688709 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80278695753897067374552890221372580923000151840584169699849464699793502688709 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/8.otp_ctrl_background_chks/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_background_chks_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_req 97510226852947658880686770827921481201759043987402344036016057066851325176425 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_lc_req/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3866094185 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_req.3866094185' seed=97510226852947658880686770827921481201759043987402344036016057066851325176425 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97510226852947658880686770827921481201759043987402344036016057066851325176425 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_lc_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_req_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 4304084465589989073153562781851121558098461149945744584404613395976582378140 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2712187548 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_lc_esc.2712187548' seed=4304084465589989073153562781851121558098461149945744584404613395976582378140 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4304084465589989073153562781851121558098461149945744584404613395976582378140 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_lock 35877506835901404875568997940460295677613007593009297151948785677630334459019 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/8.otp_ctrl_dai_lock/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3216923787 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_lock.3216923787' seed=35877506835901404875568997940460295677613007593009297151948785677630334459019 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35877506835901404875568997940460295677613007593009297151948785677630334459019 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/8.otp_ctrl_dai_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_lock_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_errs 55059240544201075263510812257160518980211824746728516520221553271444849898523 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/8.otp_ctrl_dai_errs/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=418984987 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_dai_errs.418984987' seed=55059240544201075263510812257160518980211824746728516520221553271444849898523 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55059240544201075263510812257160518980211824746728516520221553271444849898523 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/8.otp_ctrl_dai_errs/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_errs_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 30979706443639734877626292324307713740982306655952716344418741027981733819564 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/8.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=942044332 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_check_fail.942044332' seed=30979706443639734877626292324307713740982306655952716344418741027981733819564 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30979706443639734877626292324307713740982306655952716344418741027981733819564 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/8.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_macro_errs 97384293636768310407202599881167266198805398401479876138603603470907835988682 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/8.otp_ctrl_macro_errs/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1956952778 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_macro_errs.1956952778' seed=97384293636768310407202599881167266198805398401479876138603603470907835988682 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97384293636768310407202599881167266198805398401479876138603603470907835988682 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/8.otp_ctrl_macro_errs/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_macro_errs_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_key_req 83336412805882326806634717797580238321932684949665388182891454898578393379595 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_key_req/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2562962187 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_parallel_key_req.2562962187' seed=83336412805882326806634717797580238321932684949665388182891454898578393379595 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83336412805882326806634717797580238321932684949665388182891454898578393379595 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/8.otp_ctrl_parallel_key_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_key_req_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_regwen 7863705321780974922530446379516834742029943702290429641708284901931086169922 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/8.otp_ctrl_regwen/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2053556034 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_regwen.2053556034' seed=7863705321780974922530446379516834742029943702290429641708284901931086169922 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7863705321780974922530446379516834742029943702290429641708284901931086169922 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/8.otp_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_test_access 15088851818608389902514946838854016713531297136063843179923060877199410893672 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/8.otp_ctrl_test_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4164588392 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_test_access.4164588392' seed=15088851818608389902514946838854016713531297136063843179923060877199410893672 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15088851818608389902514946838854016713531297136063843179923060877199410893672 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/8.otp_ctrl_test_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_test_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 70221217329251187386730988388727064511952879613189933587273507105546465387954 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=272049586 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_stress_all_with_rand_reset.272049586' seed=70221217329251187386730988388727064511952879613189933587273507105546465387954 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70221217329251187386730988388727064511952879613189933587273507105546465387954 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/8.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_errors 67142440607596039876763952918237699203611202057767780481086847065607242251854 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/8.otp_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4149739086 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_errors.4149739086' seed=67142440607596039876763952918237699203611202057767780481086847065607242251854 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67142440607596039876763952918237699203611202057767780481086847065607242251854 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/8.otp_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_intg_err 93688838402681422145485850141083913527241627542516211006107975807288327343557 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/8.otp_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=126422469 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_tl_intg_err.126422469' seed=93688838402681422145485850141083913527241627542516211006107975807288327343557 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93688838402681422145485850141083913527241627542516211006107975807288327343557 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/8.otp_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_alert_test 53929724862269624673677429769919343734901474337664493443817202149849344131329 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/8.otp_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=194134273 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_alert_test.194134273' seed=53929724862269624673677429769919343734901474337664493443817202149849344131329 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53929724862269624673677429769919343734901474337664493443817202149849344131329 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/8.otp_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_intr_test 33503646800726674235243328119735359607595235958006719089703092734351217295630 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/8.otp_ctrl_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3741614350 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.otp_ctrl_intr_test.3741614350' seed=33503646800726674235243328119735359607595235958006719089703092734351217295630 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33503646800726674235243328119735359607595235958006719089703092734351217295630 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/8.otp_ctrl_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_smoke 102749068031695781850334869413201317761346748953704657159655391389522887018042 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/9.otp_ctrl_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2277082682 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_smoke.2277082682' seed=102749068031695781850334869413201317761346748953704657159655391389522887018042 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102749068031695781850334869413201317761346748953704657159655391389522887018042 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/9.otp_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 36429341096048041355256503345180820872828126237932282071225346528462313188931 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/9.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=67202627 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_init_fail.67202627' seed=36429341096048041355256503345180820872828126237932282071225346528462313188931 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36429341096048041355256503345180820872828126237932282071225346528462313188931 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/9.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_background_chks 109740719892584871445444613438709868270637351160790524247580379933313365164695 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/9.otp_ctrl_background_chks/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1818739351 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_background_chks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_background_chks.1818739351' seed=109740719892584871445444613438709868270637351160790524247580379933313365164695 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109740719892584871445444613438709868270637351160790524247580379933313365164695 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/9.otp_ctrl_background_chks/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_background_chks_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_req 98888309430017604138293663077809434385042361630802657584804242570199758053960 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_lc_req/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3518800456 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_req.3518800456' seed=98888309430017604138293663077809434385042361630802657584804242570199758053960 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98888309430017604138293663077809434385042361630802657584804242570199758053960 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_lc_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_req_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 5397036864826870198815511897211488370985707300059008395525697925366222402767 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2254419151 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_lc_esc.2254419151' seed=5397036864826870198815511897211488370985707300059008395525697925366222402767 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5397036864826870198815511897211488370985707300059008395525697925366222402767 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_lock 75116680430396981537513879204675756307967418597653660657989006855431274695226 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/9.otp_ctrl_dai_lock/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2614954554 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_lock.2614954554' seed=75116680430396981537513879204675756307967418597653660657989006855431274695226 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75116680430396981537513879204675756307967418597653660657989006855431274695226 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/9.otp_ctrl_dai_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_lock_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_errs 67973687419349076162516285046330524217354407775390859555184626353585265292670 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/9.otp_ctrl_dai_errs/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3376919934 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_dai_errs.3376919934' seed=67973687419349076162516285046330524217354407775390859555184626353585265292670 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67973687419349076162516285046330524217354407775390859555184626353585265292670 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/9.otp_ctrl_dai_errs/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_errs_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 103614315837587734497203632799185271107898788185550276632114350393601963598560 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/9.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1243882208 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_check_fail.1243882208' seed=103614315837587734497203632799185271107898788185550276632114350393601963598560 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103614315837587734497203632799185271107898788185550276632114350393601963598560 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/9.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_macro_errs 49344024626235374363305102100837869086996774922495922696677038205260059017950 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/9.otp_ctrl_macro_errs/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=718439134 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_macro_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_macro_errs.718439134' seed=49344024626235374363305102100837869086996774922495922696677038205260059017950 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49344024626235374363305102100837869086996774922495922696677038205260059017950 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/9.otp_ctrl_macro_errs/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_macro_errs_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_key_req 13633950954016146026583556741221173124664011112402655393665560665193103752113 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_key_req/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2655255473 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_key_req_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_parallel_key_req.2655255473' seed=13633950954016146026583556741221173124664011112402655393665560665193103752113 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13633950954016146026583556741221173124664011112402655393665560665193103752113 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/9.otp_ctrl_parallel_key_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_key_req_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_regwen 83587382633289873029597494720130608750021069232659694682245427030391551762838 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/9.otp_ctrl_regwen/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3820036502 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_regwen.3820036502' seed=83587382633289873029597494720130608750021069232659694682245427030391551762838 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83587382633289873029597494720130608750021069232659694682245427030391551762838 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/9.otp_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_test_access 15721860824525979292279041182682359715620217152779487972388623699117329473237 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/9.otp_ctrl_test_access/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=691396309 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_test_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_test_access.691396309' seed=15721860824525979292279041182682359715620217152779487972388623699117329473237 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15721860824525979292279041182682359715620217152779487972388623699117329473237 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/9.otp_ctrl_test_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_test_access_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 102262296572361681691588192498478133918499218219295075799677456246866407576122 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1441780282 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_stress_all_with_rand_reset.1441780282' seed=102262296572361681691588192498478133918499218219295075799677456246866407576122 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102262296572361681691588192498478133918499218219295075799677456246866407576122 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/9.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_errors 76988482380112864064400464337765768310155014934126687013603492744967233726674 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/9.otp_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=914352338 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_errors.914352338' seed=76988482380112864064400464337765768310155014934126687013603492744967233726674 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76988482380112864064400464337765768310155014934126687013603492744967233726674 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/9.otp_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_intg_err 27093565897876544811537857638741234818402972003595165448895681733923811776004 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/9.otp_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3552466436 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_tl_intg_err.3552466436' seed=27093565897876544811537857638741234818402972003595165448895681733923811776004 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27093565897876544811537857638741234818402972003595165448895681733923811776004 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/9.otp_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_alert_test 28949035844563171524418684732470668451700626704068840668696856656821830840924 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/9.otp_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=553939548 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_alert_test.553939548' seed=28949035844563171524418684732470668451700626704068840668696856656821830840924 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28949035844563171524418684732470668451700626704068840668696856656821830840924 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/9.otp_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_intr_test 77016468995100022470797582650737799825853352987951547673886316299974239627872 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/9.otp_ctrl_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3367807584 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.otp_ctrl_intr_test.3367807584' seed=77016468995100022470797582650737799825853352987951547673886316299974239627872 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77016468995100022470797582650737799825853352987951547673886316299974239627872 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/9.otp_ctrl_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 38598479580439316007962955181426399536217074845438819651829719954028779781361 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/10.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1589361905 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_init_fail.1589361905' seed=38598479580439316007962955181426399536217074845438819651829719954028779781361 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38598479580439316007962955181426399536217074845438819651829719954028779781361 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/10.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 48399518501204613558394835825330679134648238442308586075990775532909273893897 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=679300105 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_parallel_lc_esc.679300105' seed=48399518501204613558394835825330679134648238442308586075990775532909273893897 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48399518501204613558394835825330679134648238442308586075990775532909273893897 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/10.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_lock 95457409804281987614691720946166820056606058065610712527025453263918004929555 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/10.otp_ctrl_dai_lock/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1112769555 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_lock.1112769555' seed=95457409804281987614691720946166820056606058065610712527025453263918004929555 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95457409804281987614691720946166820056606058065610712527025453263918004929555 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/10.otp_ctrl_dai_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_lock_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_errs 89737736194833848568302106624505119344245054531925830183278722578526290736241 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/10.otp_ctrl_dai_errs/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1322939505 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_dai_errs.1322939505' seed=89737736194833848568302106624505119344245054531925830183278722578526290736241 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89737736194833848568302106624505119344245054531925830183278722578526290736241 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/10.otp_ctrl_dai_errs/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_errs_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 38001917374620187145443964233260208352721410195791025924574897710318197402596 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/10.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1611918308 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_check_fail.1611918308' seed=38001917374620187145443964233260208352721410195791025924574897710318197402596 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38001917374620187145443964233260208352721410195791025924574897710318197402596 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/10.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_regwen 92507875068072804660552110244572966993819675189635893132309411327942401058290 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/10.otp_ctrl_regwen/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3224757746 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_regwen.3224757746' seed=92507875068072804660552110244572966993819675189635893132309411327942401058290 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92507875068072804660552110244572966993819675189635893132309411327942401058290 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/10.otp_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 48501137709531550316906726177236573196156756177506214957665178190133735690187 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4239364043 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_stress_all_with_rand_reset.4239364043' seed=48501137709531550316906726177236573196156756177506214957665178190133735690187 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48501137709531550316906726177236573196156756177506214957665178190133735690187 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/10.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_errors 16875118999035492832283413676331573808588447220974858546117836821836487464188 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/10.otp_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1813255420 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_errors.1813255420' seed=16875118999035492832283413676331573808588447220974858546117836821836487464188 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16875118999035492832283413676331573808588447220974858546117836821836487464188 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/10.otp_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_intg_err 20653224585535761464442958367702715732054582742224148456048405876052210197561 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/10.otp_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4271088697 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.otp_ctrl_tl_intg_err.4271088697' seed=20653224585535761464442958367702715732054582742224148456048405876052210197561 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20653224585535761464442958367702715732054582742224148456048405876052210197561 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/10.otp_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 92991957510514615805096578122899550079663738610005865986241144789217462802890 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/11.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3297860042 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_init_fail.3297860042' seed=92991957510514615805096578122899550079663738610005865986241144789217462802890 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92991957510514615805096578122899550079663738610005865986241144789217462802890 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/11.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 108989447280069778540249026690507531965528820883508621627410128979887797397103 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1348298351 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_parallel_lc_esc.1348298351' seed=108989447280069778540249026690507531965528820883508621627410128979887797397103 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108989447280069778540249026690507531965528820883508621627410128979887797397103 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/11.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_lock 17823642009016220254571160389638152835431670663950076874807777757360337251427 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/11.otp_ctrl_dai_lock/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=114617443 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_lock.114617443' seed=17823642009016220254571160389638152835431670663950076874807777757360337251427 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17823642009016220254571160389638152835431670663950076874807777757360337251427 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/11.otp_ctrl_dai_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_lock_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_errs 77811315973304325658458287436850198252119685311184867749720377231731779650324 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/11.otp_ctrl_dai_errs/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3508224788 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_dai_errs.3508224788' seed=77811315973304325658458287436850198252119685311184867749720377231731779650324 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77811315973304325658458287436850198252119685311184867749720377231731779650324 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/11.otp_ctrl_dai_errs/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_errs_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 24155641247296494468990174255861606351175912831645282230708151090638804276678 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/11.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1159779782 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_check_fail.1159779782' seed=24155641247296494468990174255861606351175912831645282230708151090638804276678 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24155641247296494468990174255861606351175912831645282230708151090638804276678 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/11.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_regwen 27071416711580997857843885551915647918352135058993438223196835331989584014138 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/11.otp_ctrl_regwen/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3231509306 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_regwen.3231509306' seed=27071416711580997857843885551915647918352135058993438223196835331989584014138 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27071416711580997857843885551915647918352135058993438223196835331989584014138 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/11.otp_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 55895600728725352662097891082865126389836108929550372322995385038146879454135 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3567614903 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_stress_all_with_rand_reset.3567614903' seed=55895600728725352662097891082865126389836108929550372322995385038146879454135 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55895600728725352662097891082865126389836108929550372322995385038146879454135 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/11.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_errors 100389646415527152426915285848522977383363972666881863017951058959398323738415 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/11.otp_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3982350127 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_errors.3982350127' seed=100389646415527152426915285848522977383363972666881863017951058959398323738415 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100389646415527152426915285848522977383363972666881863017951058959398323738415 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/11.otp_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_intg_err 46497651902183122037714395341694461300866762684288220515456610397532888323340 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/11.otp_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3650442508 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.otp_ctrl_tl_intg_err.3650442508' seed=46497651902183122037714395341694461300866762684288220515456610397532888323340 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46497651902183122037714395341694461300866762684288220515456610397532888323340 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/11.otp_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 64634561370895534330977103970340956271703643327950872252292873136164970887606 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/12.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1966274998 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_init_fail.1966274998' seed=64634561370895534330977103970340956271703643327950872252292873136164970887606 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64634561370895534330977103970340956271703643327950872252292873136164970887606 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/12.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 38008572579240806813984686904471806988238448731182341401724058733962415334318 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2322883502 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_parallel_lc_esc.2322883502' seed=38008572579240806813984686904471806988238448731182341401724058733962415334318 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38008572579240806813984686904471806988238448731182341401724058733962415334318 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/12.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_lock 72853991034094671270110422026489434067824002634214016304627647746533386039628 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/12.otp_ctrl_dai_lock/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=585314636 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_lock.585314636' seed=72853991034094671270110422026489434067824002634214016304627647746533386039628 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72853991034094671270110422026489434067824002634214016304627647746533386039628 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/12.otp_ctrl_dai_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_lock_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_errs 29907773008567570927509184183047798769546967457395712319961246097475734067130 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/12.otp_ctrl_dai_errs/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1963186106 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_dai_errs.1963186106' seed=29907773008567570927509184183047798769546967457395712319961246097475734067130 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29907773008567570927509184183047798769546967457395712319961246097475734067130 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/12.otp_ctrl_dai_errs/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_errs_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 93260779735257414708508772661836828029710688977812537255648633440229117711874 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/12.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2457916930 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_check_fail.2457916930' seed=93260779735257414708508772661836828029710688977812537255648633440229117711874 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93260779735257414708508772661836828029710688977812537255648633440229117711874 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/12.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_regwen 91594068503739797045233075118505220460159933597663312984917048568688604687456 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/12.otp_ctrl_regwen/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2813406304 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_regwen.2813406304' seed=91594068503739797045233075118505220460159933597663312984917048568688604687456 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91594068503739797045233075118505220460159933597663312984917048568688604687456 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/12.otp_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 70263774239849546452407276342284444251480935666519211613336565535559850577866 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3156135882 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_stress_all_with_rand_reset.3156135882' seed=70263774239849546452407276342284444251480935666519211613336565535559850577866 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70263774239849546452407276342284444251480935666519211613336565535559850577866 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/12.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_errors 25325531210637025650180594978962274364679863255261286381315839499351315320690 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/12.otp_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3263041394 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_errors.3263041394' seed=25325531210637025650180594978962274364679863255261286381315839499351315320690 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25325531210637025650180594978962274364679863255261286381315839499351315320690 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/12.otp_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_intg_err 62712996758827475470567368221743964366478334914688253402976905449661330728262 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/12.otp_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1394451782 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.otp_ctrl_tl_intg_err.1394451782' seed=62712996758827475470567368221743964366478334914688253402976905449661330728262 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62712996758827475470567368221743964366478334914688253402976905449661330728262 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/12.otp_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 112380187889995887902181418509298688203047552382112314084117831734220173194438 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/13.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3693720774 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_init_fail.3693720774' seed=112380187889995887902181418509298688203047552382112314084117831734220173194438 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112380187889995887902181418509298688203047552382112314084117831734220173194438 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/13.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 59232649296631256869239510118394164217438421925837139575503264685016232693568 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3553038144 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_parallel_lc_esc.3553038144' seed=59232649296631256869239510118394164217438421925837139575503264685016232693568 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=59232649296631256869239510118394164217438421925837139575503264685016232693568 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/13.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_lock 113341260515335725395256533462848557861556668520824738981887474658090254310413 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/13.otp_ctrl_dai_lock/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2751175693 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_lock.2751175693' seed=113341260515335725395256533462848557861556668520824738981887474658090254310413 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113341260515335725395256533462848557861556668520824738981887474658090254310413 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/13.otp_ctrl_dai_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_lock_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_errs 13903062692602898909587967084295005900532917660598584418658877870587712719250 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/13.otp_ctrl_dai_errs/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4087957906 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_dai_errs.4087957906' seed=13903062692602898909587967084295005900532917660598584418658877870587712719250 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13903062692602898909587967084295005900532917660598584418658877870587712719250 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/13.otp_ctrl_dai_errs/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_errs_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 115525051725313017535930813119279687850260880429667520436821154782954283867960 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/13.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2610175800 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_check_fail.2610175800' seed=115525051725313017535930813119279687850260880429667520436821154782954283867960 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115525051725313017535930813119279687850260880429667520436821154782954283867960 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/13.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_regwen 47533477579609128461184559771889403075569374051231072626764380178130675158279 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/13.otp_ctrl_regwen/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=804506887 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_regwen.804506887' seed=47533477579609128461184559771889403075569374051231072626764380178130675158279 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47533477579609128461184559771889403075569374051231072626764380178130675158279 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/13.otp_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 52148507308857943886870841873813990753956608542077108611232765573293525859744 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4037180832 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_stress_all_with_rand_reset.4037180832' seed=52148507308857943886870841873813990753956608542077108611232765573293525859744 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=52148507308857943886870841873813990753956608542077108611232765573293525859744 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/13.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_errors 99405330739587148704345360817061518356237681728547186859372001226118087144886 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/13.otp_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3476649398 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_errors.3476649398' seed=99405330739587148704345360817061518356237681728547186859372001226118087144886 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99405330739587148704345360817061518356237681728547186859372001226118087144886 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/13.otp_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_intg_err 63355804444198660107867914643953835927547287643367338054697203196159981516452 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/13.otp_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1450178212 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.otp_ctrl_tl_intg_err.1450178212' seed=63355804444198660107867914643953835927547287643367338054697203196159981516452 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63355804444198660107867914643953835927547287643367338054697203196159981516452 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/13.otp_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 80031720105403774962443185803374043820382901985967786294331758293371943710862 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/14.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3796430990 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_init_fail.3796430990' seed=80031720105403774962443185803374043820382901985967786294331758293371943710862 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80031720105403774962443185803374043820382901985967786294331758293371943710862 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/14.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 18338931356216199540178414908296194472935618964034942680164866822587627178470 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3588065766 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_parallel_lc_esc.3588065766' seed=18338931356216199540178414908296194472935618964034942680164866822587627178470 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18338931356216199540178414908296194472935618964034942680164866822587627178470 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/14.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_lock 9505859135196861939703748020150602575379883988537700977606895738486855066949 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/14.otp_ctrl_dai_lock/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=872179013 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_lock.872179013' seed=9505859135196861939703748020150602575379883988537700977606895738486855066949 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9505859135196861939703748020150602575379883988537700977606895738486855066949 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/14.otp_ctrl_dai_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_lock_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_errs 47548972461562653242129601365229147415564352648794605548259331531855921905746 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/14.otp_ctrl_dai_errs/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1570734162 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_dai_errs.1570734162' seed=47548972461562653242129601365229147415564352648794605548259331531855921905746 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47548972461562653242129601365229147415564352648794605548259331531855921905746 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/14.otp_ctrl_dai_errs/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_errs_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 115393340760575544133533902343448023211433613922669244987067501338308781414761 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/14.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2101483881 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_check_fail.2101483881' seed=115393340760575544133533902343448023211433613922669244987067501338308781414761 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115393340760575544133533902343448023211433613922669244987067501338308781414761 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/14.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_regwen 3197877145221052845391625121347217414252407522949262403483208519447746809127 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/14.otp_ctrl_regwen/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3510734119 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_regwen.3510734119' seed=3197877145221052845391625121347217414252407522949262403483208519447746809127 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3197877145221052845391625121347217414252407522949262403483208519447746809127 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/14.otp_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 37738963070607252473242141608132814099772930483256863030411806126029466817343 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2715603775 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_stress_all_with_rand_reset.2715603775' seed=37738963070607252473242141608132814099772930483256863030411806126029466817343 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37738963070607252473242141608132814099772930483256863030411806126029466817343 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/14.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_errors 73781472153150278981731889086352309694182698114107721458212995356828061775082 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/14.otp_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3279009002 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_errors.3279009002' seed=73781472153150278981731889086352309694182698114107721458212995356828061775082 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73781472153150278981731889086352309694182698114107721458212995356828061775082 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/14.otp_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_intg_err 53345683636806693363389111948273204796119847004328518822823131276991667009048 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/14.otp_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1975154200 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.otp_ctrl_tl_intg_err.1975154200' seed=53345683636806693363389111948273204796119847004328518822823131276991667009048 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53345683636806693363389111948273204796119847004328518822823131276991667009048 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/14.otp_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 7824313902874646203279689762632941774164201679260303984364647219536454952423 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/15.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3930531303 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_init_fail.3930531303' seed=7824313902874646203279689762632941774164201679260303984364647219536454952423 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7824313902874646203279689762632941774164201679260303984364647219536454952423 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/15.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 22367156267412750172179759520058225847125640353902697882782449867150827728027 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2834050203 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_parallel_lc_esc.2834050203' seed=22367156267412750172179759520058225847125640353902697882782449867150827728027 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22367156267412750172179759520058225847125640353902697882782449867150827728027 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/15.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_lock 50656125164099021022880401593942558627379985296340999694575289749536298999775 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/15.otp_ctrl_dai_lock/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4014710751 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_lock.4014710751' seed=50656125164099021022880401593942558627379985296340999694575289749536298999775 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50656125164099021022880401593942558627379985296340999694575289749536298999775 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/15.otp_ctrl_dai_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_lock_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_errs 25864803476582517279597118891813773038725608024737820676124565680494845778194 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/15.otp_ctrl_dai_errs/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1184258322 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_dai_errs.1184258322' seed=25864803476582517279597118891813773038725608024737820676124565680494845778194 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25864803476582517279597118891813773038725608024737820676124565680494845778194 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/15.otp_ctrl_dai_errs/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_errs_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 103766819776886609372316360127211219280417499236733978109031946463848802989194 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/15.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2246227082 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_check_fail.2246227082' seed=103766819776886609372316360127211219280417499236733978109031946463848802989194 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103766819776886609372316360127211219280417499236733978109031946463848802989194 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/15.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_regwen 49344908392461298120058516365000612615594486783948284242658970603054354690642 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/15.otp_ctrl_regwen/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=251687506 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_regwen.251687506' seed=49344908392461298120058516365000612615594486783948284242658970603054354690642 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49344908392461298120058516365000612615594486783948284242658970603054354690642 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/15.otp_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 810437937606696621769266296654965350719140044544949935543183002553072587681 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=895325089 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_stress_all_with_rand_reset.895325089' seed=810437937606696621769266296654965350719140044544949935543183002553072587681 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=810437937606696621769266296654965350719140044544949935543183002553072587681 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/15.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_errors 74807564489549956600618696981381872987876963544454759757925955696458497406372 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/15.otp_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2085238180 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_errors.2085238180' seed=74807564489549956600618696981381872987876963544454759757925955696458497406372 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74807564489549956600618696981381872987876963544454759757925955696458497406372 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/15.otp_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_intg_err 95361345748265020415447163068903736631142395224404343218858739637978424750343 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/15.otp_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=114110727 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.otp_ctrl_tl_intg_err.114110727' seed=95361345748265020415447163068903736631142395224404343218858739637978424750343 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95361345748265020415447163068903736631142395224404343218858739637978424750343 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/15.otp_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 9139665459779388878186777802526360652561932755886685519174412939248756408131 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/16.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2907258691 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_init_fail.2907258691' seed=9139665459779388878186777802526360652561932755886685519174412939248756408131 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9139665459779388878186777802526360652561932755886685519174412939248756408131 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/16.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 104321954367569894767124956289644720269037663965060423342497811406841374555276 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=777501836 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_parallel_lc_esc.777501836' seed=104321954367569894767124956289644720269037663965060423342497811406841374555276 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104321954367569894767124956289644720269037663965060423342497811406841374555276 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/16.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_lock 59176425956754913671761690327333968169586584015131382018403497986378880945124 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/16.otp_ctrl_dai_lock/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4292512740 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_lock.4292512740' seed=59176425956754913671761690327333968169586584015131382018403497986378880945124 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=59176425956754913671761690327333968169586584015131382018403497986378880945124 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/16.otp_ctrl_dai_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_lock_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_errs 83211839538182368850379447909250775085461745370444650566541802704930994957439 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/16.otp_ctrl_dai_errs/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1568451711 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_dai_errs.1568451711' seed=83211839538182368850379447909250775085461745370444650566541802704930994957439 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83211839538182368850379447909250775085461745370444650566541802704930994957439 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/16.otp_ctrl_dai_errs/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_errs_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 39243125048252079803197819232038723438884191340547426436181579366961782852317 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/16.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3286108893 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_check_fail.3286108893' seed=39243125048252079803197819232038723438884191340547426436181579366961782852317 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39243125048252079803197819232038723438884191340547426436181579366961782852317 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/16.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_regwen 71679576683571575136206360944661413111639542157068495446928741885767478762362 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/16.otp_ctrl_regwen/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2528992122 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_regwen.2528992122' seed=71679576683571575136206360944661413111639542157068495446928741885767478762362 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71679576683571575136206360944661413111639542157068495446928741885767478762362 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/16.otp_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 69347940150475442116431749778709488776514512973209609298080847993246670983644 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2386629084 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_stress_all_with_rand_reset.2386629084' seed=69347940150475442116431749778709488776514512973209609298080847993246670983644 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69347940150475442116431749778709488776514512973209609298080847993246670983644 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/16.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_errors 32732363991069861028496672188728732551536104217787655239233398561941327720059 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/16.otp_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3996659323 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_errors.3996659323' seed=32732363991069861028496672188728732551536104217787655239233398561941327720059 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32732363991069861028496672188728732551536104217787655239233398561941327720059 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/16.otp_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_intg_err 94275144292026919220855434493482671144921325726841124522602453541053312109418 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/16.otp_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2502003562 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.otp_ctrl_tl_intg_err.2502003562' seed=94275144292026919220855434493482671144921325726841124522602453541053312109418 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94275144292026919220855434493482671144921325726841124522602453541053312109418 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/16.otp_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 77593300812657859740013583534438724159062492688138076437146162410869493156359 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/17.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2717207047 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_init_fail.2717207047' seed=77593300812657859740013583534438724159062492688138076437146162410869493156359 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77593300812657859740013583534438724159062492688138076437146162410869493156359 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/17.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 89697755057978215351874752777415312300365728776377234093721293175915265262309 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=819593957 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_parallel_lc_esc.819593957' seed=89697755057978215351874752777415312300365728776377234093721293175915265262309 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89697755057978215351874752777415312300365728776377234093721293175915265262309 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/17.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_lock 81160039539990744889321961173990809837905072486153704456953614894374969011506 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/17.otp_ctrl_dai_lock/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2997742898 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_lock.2997742898' seed=81160039539990744889321961173990809837905072486153704456953614894374969011506 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81160039539990744889321961173990809837905072486153704456953614894374969011506 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/17.otp_ctrl_dai_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_lock_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_errs 87572238235574616896872812913748405738735683877244315640351483952186175998336 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/17.otp_ctrl_dai_errs/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2389133696 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_dai_errs.2389133696' seed=87572238235574616896872812913748405738735683877244315640351483952186175998336 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87572238235574616896872812913748405738735683877244315640351483952186175998336 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/17.otp_ctrl_dai_errs/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_errs_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 101009088165784049392544173718989867448287047083628701352656592799538891409101 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/17.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4225976013 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_check_fail.4225976013' seed=101009088165784049392544173718989867448287047083628701352656592799538891409101 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101009088165784049392544173718989867448287047083628701352656592799538891409101 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/17.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_regwen 8373432331082103153679049733243278906050849916915332776686582882428673199460 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/17.otp_ctrl_regwen/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1910115684 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_regwen.1910115684' seed=8373432331082103153679049733243278906050849916915332776686582882428673199460 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8373432331082103153679049733243278906050849916915332776686582882428673199460 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/17.otp_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 81496866431953395985102962736128728748221547994842573897337440473556060469693 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3895720381 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_stress_all_with_rand_reset.3895720381' seed=81496866431953395985102962736128728748221547994842573897337440473556060469693 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81496866431953395985102962736128728748221547994842573897337440473556060469693 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/17.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_errors 18863021536822988471472915545131888598620347239078593746372602794459680512435 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/17.otp_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1717868979 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_errors.1717868979' seed=18863021536822988471472915545131888598620347239078593746372602794459680512435 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18863021536822988471472915545131888598620347239078593746372602794459680512435 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/17.otp_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_intg_err 66519319795035442189057464109659568139687173323999456899515793770441386963438 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/17.otp_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=840905198 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.otp_ctrl_tl_intg_err.840905198' seed=66519319795035442189057464109659568139687173323999456899515793770441386963438 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66519319795035442189057464109659568139687173323999456899515793770441386963438 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/17.otp_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 1388062123165909099147540409822426338604604312507557516946762380743436055971 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/18.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1126348195 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_init_fail.1126348195' seed=1388062123165909099147540409822426338604604312507557516946762380743436055971 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1388062123165909099147540409822426338604604312507557516946762380743436055971 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/18.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 2870885881093650160532762371007836067528325723726060762326826850357012884128 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=297822880 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_parallel_lc_esc.297822880' seed=2870885881093650160532762371007836067528325723726060762326826850357012884128 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2870885881093650160532762371007836067528325723726060762326826850357012884128 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/18.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_lock 20673043801094525204697300222672998948217892613833946889301360971477842209430 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/18.otp_ctrl_dai_lock/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2332633750 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_lock.2332633750' seed=20673043801094525204697300222672998948217892613833946889301360971477842209430 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20673043801094525204697300222672998948217892613833946889301360971477842209430 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/18.otp_ctrl_dai_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_lock_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_errs 8346206357227349123107235719141080965569714685779933859781284882461633408697 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/18.otp_ctrl_dai_errs/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2488921785 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_dai_errs.2488921785' seed=8346206357227349123107235719141080965569714685779933859781284882461633408697 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8346206357227349123107235719141080965569714685779933859781284882461633408697 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/18.otp_ctrl_dai_errs/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_errs_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 53523222990439665921779039405786444346866918482250837153342913157240783221880 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/18.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1127068792 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_check_fail.1127068792' seed=53523222990439665921779039405786444346866918482250837153342913157240783221880 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53523222990439665921779039405786444346866918482250837153342913157240783221880 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/18.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_regwen 80954855617347555791765919875651986088689875893672549119952153071928530887456 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/18.otp_ctrl_regwen/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=577430304 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_regwen.577430304' seed=80954855617347555791765919875651986088689875893672549119952153071928530887456 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80954855617347555791765919875651986088689875893672549119952153071928530887456 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/18.otp_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 40501426294833616513250049984863628446247873300707324738597440417570584161669 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=284585349 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_stress_all_with_rand_reset.284585349' seed=40501426294833616513250049984863628446247873300707324738597440417570584161669 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40501426294833616513250049984863628446247873300707324738597440417570584161669 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/18.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_errors 82960189561211501506267770807155352742855977820668769797057106052812019864664 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/18.otp_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3661894744 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_errors.3661894744' seed=82960189561211501506267770807155352742855977820668769797057106052812019864664 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82960189561211501506267770807155352742855977820668769797057106052812019864664 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/18.otp_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_intg_err 88862857396851652350879757143982274071568446685816726514790161907162542706250 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/18.otp_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3217755722 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.otp_ctrl_tl_intg_err.3217755722' seed=88862857396851652350879757143982274071568446685816726514790161907162542706250 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88862857396851652350879757143982274071568446685816726514790161907162542706250 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/18.otp_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 3990446151142944736757475111449500643366970555817090368766666086060900394186 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/19.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4010190026 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_init_fail.4010190026' seed=3990446151142944736757475111449500643366970555817090368766666086060900394186 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3990446151142944736757475111449500643366970555817090368766666086060900394186 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/19.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 38141708378904556281236777463847623403618134347670701153486559178288899338135 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2389487511 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_parallel_lc_esc.2389487511' seed=38141708378904556281236777463847623403618134347670701153486559178288899338135 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38141708378904556281236777463847623403618134347670701153486559178288899338135 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/19.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_lock 13077828692014058314861446660437613360713429499015537439187754386528906320999 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/19.otp_ctrl_dai_lock/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=842603623 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_lock.842603623' seed=13077828692014058314861446660437613360713429499015537439187754386528906320999 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13077828692014058314861446660437613360713429499015537439187754386528906320999 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/19.otp_ctrl_dai_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_lock_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_errs 40226610140359194543729179334323143406968262770477607683679568562675726408545 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/19.otp_ctrl_dai_errs/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=894688097 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_dai_errs.894688097' seed=40226610140359194543729179334323143406968262770477607683679568562675726408545 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40226610140359194543729179334323143406968262770477607683679568562675726408545 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/19.otp_ctrl_dai_errs/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_errs_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 42733432370748122345434039010360550982328002048914478135089022733163151793997 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/19.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2288820045 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_check_fail.2288820045' seed=42733432370748122345434039010360550982328002048914478135089022733163151793997 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42733432370748122345434039010360550982328002048914478135089022733163151793997 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/19.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_regwen 105898837899527721157916000641886331838217484165739529388019059845077149532419 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/19.otp_ctrl_regwen/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1425654019 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_regwen.1425654019' seed=105898837899527721157916000641886331838217484165739529388019059845077149532419 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105898837899527721157916000641886331838217484165739529388019059845077149532419 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/19.otp_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 54456306540953724422804452554943823547029369468814293104813734496489121240859 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1366021915 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_stress_all_with_rand_reset.1366021915' seed=54456306540953724422804452554943823547029369468814293104813734496489121240859 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54456306540953724422804452554943823547029369468814293104813734496489121240859 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/19.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_errors 87971013491979646678666626806415778910125852759115039803267314234914778038514 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/19.otp_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3683303666 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_errors.3683303666' seed=87971013491979646678666626806415778910125852759115039803267314234914778038514 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87971013491979646678666626806415778910125852759115039803267314234914778038514 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/19.otp_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_intg_err 40824636938859994297683802591928631016133043248930400104475624205348872238607 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/19.otp_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2381952527 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.otp_ctrl_tl_intg_err.2381952527' seed=40824636938859994297683802591928631016133043248930400104475624205348872238607 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40824636938859994297683802591928631016133043248930400104475624205348872238607 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/19.otp_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 8529455366529623344794542762973153001409124355855481312494114876990041449151 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/20.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4148257471 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_init_fail.4148257471' seed=8529455366529623344794542762973153001409124355855481312494114876990041449151 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8529455366529623344794542762973153001409124355855481312494114876990041449151 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/20.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 17595003529285575450666378289876158523001398480217103851719373866170037244628 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2706838228 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_parallel_lc_esc.2706838228' seed=17595003529285575450666378289876158523001398480217103851719373866170037244628 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17595003529285575450666378289876158523001398480217103851719373866170037244628 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/20.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_lock 7371254220252526959723463748811607371724567292961207698388641025334338173743 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/20.otp_ctrl_dai_lock/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4228954927 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_lock.4228954927' seed=7371254220252526959723463748811607371724567292961207698388641025334338173743 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7371254220252526959723463748811607371724567292961207698388641025334338173743 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/20.otp_ctrl_dai_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_lock_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_errs 33638638778400575490386339084563273616266193408199629206897204934204455642446 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/20.otp_ctrl_dai_errs/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1376511310 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_dai_errs.1376511310' seed=33638638778400575490386339084563273616266193408199629206897204934204455642446 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33638638778400575490386339084563273616266193408199629206897204934204455642446 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/20.otp_ctrl_dai_errs/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_errs_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 10142015386920103882170694081687420804611887793141893929930413944749790908543 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/20.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=685035647 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_check_fail.685035647' seed=10142015386920103882170694081687420804611887793141893929930413944749790908543 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10142015386920103882170694081687420804611887793141893929930413944749790908543 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/20.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_regwen 36378102664064151341662080436202366670376287940914247566082319727079845260672 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/20.otp_ctrl_regwen/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1174924672 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_regwen.1174924672' seed=36378102664064151341662080436202366670376287940914247566082319727079845260672 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36378102664064151341662080436202366670376287940914247566082319727079845260672 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/20.otp_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 115435856851273098858877962657337418133785552957490248065951998282254954520151 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/20.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2604654167 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_stress_all_with_rand_reset.2604654167' seed=115435856851273098858877962657337418133785552957490248065951998282254954520151 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115435856851273098858877962657337418133785552957490248065951998282254954520151 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/20.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_errors 50704864496579378595513210048398789322071845726457087238599635650503944767586 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/20.otp_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4222158946 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_tl_errors.4222158946' seed=50704864496579378595513210048398789322071845726457087238599635650503944767586 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50704864496579378595513210048398789322071845726457087238599635650503944767586 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/20.otp_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_intg_err 24143974628015256205509408463945790980967435737475848818718471862991055554913 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/20.otp_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3392997729 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.otp_ctrl_tl_intg_err.3392997729' seed=24143974628015256205509408463945790980967435737475848818718471862991055554913 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24143974628015256205509408463945790980967435737475848818718471862991055554913 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/20.otp_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 113308795793318684464090523351157095992891156768503446447212703091308681951518 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/21.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2698443038 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_init_fail.2698443038' seed=113308795793318684464090523351157095992891156768503446447212703091308681951518 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113308795793318684464090523351157095992891156768503446447212703091308681951518 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/21.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 92352795206561002230490418016707860468250512840753093912662109767334620032788 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=126873364 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_parallel_lc_esc.126873364' seed=92352795206561002230490418016707860468250512840753093912662109767334620032788 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92352795206561002230490418016707860468250512840753093912662109767334620032788 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/21.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_lock 84203712160433201219487284302631162865776005982518139823917276475139936842327 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/21.otp_ctrl_dai_lock/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1908240983 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_lock.1908240983' seed=84203712160433201219487284302631162865776005982518139823917276475139936842327 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84203712160433201219487284302631162865776005982518139823917276475139936842327 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/21.otp_ctrl_dai_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_lock_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_errs 18931612823740081626648491026271421447549689824886632551878155316588116719251 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/21.otp_ctrl_dai_errs/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3653514899 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_dai_errs.3653514899' seed=18931612823740081626648491026271421447549689824886632551878155316588116719251 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18931612823740081626648491026271421447549689824886632551878155316588116719251 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/21.otp_ctrl_dai_errs/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_errs_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 16687394428025435180754331621296267967392387538839294023028661557358536724860 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/21.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2809172348 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_check_fail.2809172348' seed=16687394428025435180754331621296267967392387538839294023028661557358536724860 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16687394428025435180754331621296267967392387538839294023028661557358536724860 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/21.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_regwen 99068473344983523294999143108892065449589586021010501843807151876402247691076 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/21.otp_ctrl_regwen/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2816011076 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_regwen.2816011076' seed=99068473344983523294999143108892065449589586021010501843807151876402247691076 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99068473344983523294999143108892065449589586021010501843807151876402247691076 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/21.otp_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 100434009488826939669712585831287223814992420578327813712711499775729263371452 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4074169532 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_stress_all_with_rand_reset.4074169532' seed=100434009488826939669712585831287223814992420578327813712711499775729263371452 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100434009488826939669712585831287223814992420578327813712711499775729263371452 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/21.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_errors 11092865306073051473547421576097404858641481106806261779208135395633352555819 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/21.otp_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4248714539 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_tl_errors.4248714539' seed=11092865306073051473547421576097404858641481106806261779208135395633352555819 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11092865306073051473547421576097404858641481106806261779208135395633352555819 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/21.otp_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_intg_err 9247551135751998446748783309055333882383294437119458703877084698512827304153 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/21.otp_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=789006553 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.otp_ctrl_tl_intg_err.789006553' seed=9247551135751998446748783309055333882383294437119458703877084698512827304153 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9247551135751998446748783309055333882383294437119458703877084698512827304153 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/21.otp_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 48426677248865547125943269214129915652153929199432212526800947651583541692419 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/22.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1092012035 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_init_fail.1092012035' seed=48426677248865547125943269214129915652153929199432212526800947651583541692419 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48426677248865547125943269214129915652153929199432212526800947651583541692419 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/22.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 83207789025569619184454551463427083912006040516847407895055828652733349131863 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=474642007 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_parallel_lc_esc.474642007' seed=83207789025569619184454551463427083912006040516847407895055828652733349131863 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83207789025569619184454551463427083912006040516847407895055828652733349131863 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/22.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_lock 8128173957615402716953715062569344263949697108087763936314910693460771170119 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/22.otp_ctrl_dai_lock/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2704369479 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_lock.2704369479' seed=8128173957615402716953715062569344263949697108087763936314910693460771170119 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8128173957615402716953715062569344263949697108087763936314910693460771170119 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/22.otp_ctrl_dai_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_lock_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_errs 60110825325520838229223773884782937166306622841123247508973135781173172556965 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/22.otp_ctrl_dai_errs/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4256617637 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_dai_errs.4256617637' seed=60110825325520838229223773884782937166306622841123247508973135781173172556965 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60110825325520838229223773884782937166306622841123247508973135781173172556965 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/22.otp_ctrl_dai_errs/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_errs_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 88312505021373912828834169380842878808480258978696384725403569595180173494382 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/22.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=697305198 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_check_fail.697305198' seed=88312505021373912828834169380842878808480258978696384725403569595180173494382 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88312505021373912828834169380842878808480258978696384725403569595180173494382 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/22.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_regwen 16762990470077524853347417024656623131810611308699220067586361252634024034932 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/22.otp_ctrl_regwen/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2415215220 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_regwen.2415215220' seed=16762990470077524853347417024656623131810611308699220067586361252634024034932 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16762990470077524853347417024656623131810611308699220067586361252634024034932 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/22.otp_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 112435953702165413778469373717560717368183763336944186510646727716405070675262 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1619934526 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_stress_all_with_rand_reset.1619934526' seed=112435953702165413778469373717560717368183763336944186510646727716405070675262 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112435953702165413778469373717560717368183763336944186510646727716405070675262 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/22.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_errors 63387650866737201908991896929460871229471676418683087247955033378402011941739 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/22.otp_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1082362731 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_tl_errors.1082362731' seed=63387650866737201908991896929460871229471676418683087247955033378402011941739 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63387650866737201908991896929460871229471676418683087247955033378402011941739 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/22.otp_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_intg_err 46712719805157668425626810198296303227591359310961589031742734056035835872106 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/22.otp_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1131578218 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.otp_ctrl_tl_intg_err.1131578218' seed=46712719805157668425626810198296303227591359310961589031742734056035835872106 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46712719805157668425626810198296303227591359310961589031742734056035835872106 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/22.otp_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 37875907290320454717752905754265952029386930515165224474425010275566919119848 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/23.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=492336104 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_init_fail.492336104' seed=37875907290320454717752905754265952029386930515165224474425010275566919119848 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37875907290320454717752905754265952029386930515165224474425010275566919119848 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/23.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 92877302361071690182165915275795579866113472037167618179284515403116701955919 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=100022095 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_parallel_lc_esc.100022095' seed=92877302361071690182165915275795579866113472037167618179284515403116701955919 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92877302361071690182165915275795579866113472037167618179284515403116701955919 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/23.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_lock 66847772674589828016347625377068148273019050775481832901563665442957217291420 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/23.otp_ctrl_dai_lock/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2638535836 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_lock.2638535836' seed=66847772674589828016347625377068148273019050775481832901563665442957217291420 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66847772674589828016347625377068148273019050775481832901563665442957217291420 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/23.otp_ctrl_dai_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_lock_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_errs 16156960424398101950677596184902682100553961385513738672714823355004745145291 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/23.otp_ctrl_dai_errs/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1086839755 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_dai_errs.1086839755' seed=16156960424398101950677596184902682100553961385513738672714823355004745145291 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16156960424398101950677596184902682100553961385513738672714823355004745145291 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/23.otp_ctrl_dai_errs/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_errs_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 63422947206184187214163609718276088717012016619322974548745794969314568742995 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/23.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=12101715 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_check_fail.12101715' seed=63422947206184187214163609718276088717012016619322974548745794969314568742995 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63422947206184187214163609718276088717012016619322974548745794969314568742995 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/23.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_regwen 83041949532880776435708340784777885373968250365737873646950460268840975291928 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/23.otp_ctrl_regwen/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2774226456 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_regwen.2774226456' seed=83041949532880776435708340784777885373968250365737873646950460268840975291928 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83041949532880776435708340784777885373968250365737873646950460268840975291928 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/23.otp_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 27787422989032011275395241412897221121475946137600428063981368494027871099365 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=414194149 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_stress_all_with_rand_reset.414194149' seed=27787422989032011275395241412897221121475946137600428063981368494027871099365 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27787422989032011275395241412897221121475946137600428063981368494027871099365 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/23.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_errors 19854447749141336718101408957939200575643169792328818790019416673541034952434 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/23.otp_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3772598002 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_tl_errors.3772598002' seed=19854447749141336718101408957939200575643169792328818790019416673541034952434 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19854447749141336718101408957939200575643169792328818790019416673541034952434 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/23.otp_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_intg_err 112426315927987160150916830646008274452991424128461724145204353556159605021755 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/23.otp_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3451427899 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.otp_ctrl_tl_intg_err.3451427899' seed=112426315927987160150916830646008274452991424128461724145204353556159605021755 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112426315927987160150916830646008274452991424128461724145204353556159605021755 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/23.otp_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 81107655403910022586860191084964787623148091522428482647809450402169111841407 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/24.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=324930175 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_init_fail.324930175' seed=81107655403910022586860191084964787623148091522428482647809450402169111841407 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81107655403910022586860191084964787623148091522428482647809450402169111841407 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/24.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 99134202706954918665559649912402342840061238421796118459917742524855332953565 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2534989277 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_parallel_lc_esc.2534989277' seed=99134202706954918665559649912402342840061238421796118459917742524855332953565 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99134202706954918665559649912402342840061238421796118459917742524855332953565 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/24.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_lock 59609458689065806817168395018456880335606555501278000557798747487802676183590 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/24.otp_ctrl_dai_lock/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2487976486 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_lock.2487976486' seed=59609458689065806817168395018456880335606555501278000557798747487802676183590 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=59609458689065806817168395018456880335606555501278000557798747487802676183590 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/24.otp_ctrl_dai_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_lock_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_errs 78367848589659398485940807206349978071580653730774865712447568848367921303111 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/24.otp_ctrl_dai_errs/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=178163271 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_errs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_dai_errs.178163271' seed=78367848589659398485940807206349978071580653730774865712447568848367921303111 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78367848589659398485940807206349978071580653730774865712447568848367921303111 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/24.otp_ctrl_dai_errs/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_errs_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 65435239496724076623489174822354911289894127980175011780803084678868638549079 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/24.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1583006807 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_check_fail.1583006807' seed=65435239496724076623489174822354911289894127980175011780803084678868638549079 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65435239496724076623489174822354911289894127980175011780803084678868638549079 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/24.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_regwen 53612199022550978903944560833824450434554005053080134109670101567592790061442 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/24.otp_ctrl_regwen/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3905515906 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_regwen.3905515906' seed=53612199022550978903944560833824450434554005053080134109670101567592790061442 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53612199022550978903944560833824450434554005053080134109670101567592790061442 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/24.otp_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 32256687209821308411788427110513867285078013159805736024688382951972298873636 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=380164900 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_stress_all_with_rand_reset.380164900' seed=32256687209821308411788427110513867285078013159805736024688382951972298873636 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32256687209821308411788427110513867285078013159805736024688382951972298873636 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/24.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_errors 55290562658638501222129758940517371035557804618185816596455316516386525684144 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/24.otp_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=665854384 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_tl_errors.665854384' seed=55290562658638501222129758940517371035557804618185816596455316516386525684144 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55290562658638501222129758940517371035557804618185816596455316516386525684144 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/24.otp_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_tl_intg_err 80019573951659578437500518687779480931593687261719477510853019771645505948072 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/24.otp_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=183880104 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.otp_ctrl_tl_intg_err.183880104' seed=80019573951659578437500518687779480931593687261719477510853019771645505948072 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80019573951659578437500518687779480931593687261719477510853019771645505948072 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/24.otp_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 3528729065989401201438539228171887380116953242965783173084150509507855015955 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/25.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1827954707 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_init_fail.1827954707' seed=3528729065989401201438539228171887380116953242965783173084150509507855015955 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3528729065989401201438539228171887380116953242965783173084150509507855015955 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/25.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 31137834324673970936747083053734931783453174071625100251963597871014206953660 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=257611964 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_parallel_lc_esc.257611964' seed=31137834324673970936747083053734931783453174071625100251963597871014206953660 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31137834324673970936747083053734931783453174071625100251963597871014206953660 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/25.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_lock 68374348746533379504496031025500749560187394112134021055697243106662397344265 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/25.otp_ctrl_dai_lock/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3881662985 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_dai_lock.3881662985' seed=68374348746533379504496031025500749560187394112134021055697243106662397344265 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68374348746533379504496031025500749560187394112134021055697243106662397344265 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/25.otp_ctrl_dai_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_lock_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 46248643716446851354189614074360476768543586504242720605641593024366019736777 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/25.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=960885961 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_check_fail.960885961' seed=46248643716446851354189614074360476768543586504242720605641593024366019736777 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46248643716446851354189614074360476768543586504242720605641593024366019736777 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/25.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_regwen 7791576179162032354240213010559357369325351051980588340908448303316273604663 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/25.otp_ctrl_regwen/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3176015927 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_regwen.3176015927' seed=7791576179162032354240213010559357369325351051980588340908448303316273604663 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7791576179162032354240213010559357369325351051980588340908448303316273604663 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/25.otp_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 54852098793071697879844248826591561112121091016730434753653402696094206679890 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=542399314 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.otp_ctrl_stress_all_with_rand_reset.542399314' seed=54852098793071697879844248826591561112121091016730434753653402696094206679890 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54852098793071697879844248826591561112121091016730434753653402696094206679890 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/25.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 56965695957941758424069799106776850710395942575282080602098097737280119782459 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/26.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=258096187 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_init_fail.258096187' seed=56965695957941758424069799106776850710395942575282080602098097737280119782459 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56965695957941758424069799106776850710395942575282080602098097737280119782459 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/26.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 54181335068159412351283471465825605355629655690987058525344468260002308521080 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2862578808 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_parallel_lc_esc.2862578808' seed=54181335068159412351283471465825605355629655690987058525344468260002308521080 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54181335068159412351283471465825605355629655690987058525344468260002308521080 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/26.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_lock 75883537663596499777882067413940030380241923704839824458336420427643550578049 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/26.otp_ctrl_dai_lock/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1763063169 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_dai_lock.1763063169' seed=75883537663596499777882067413940030380241923704839824458336420427643550578049 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75883537663596499777882067413940030380241923704839824458336420427643550578049 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/26.otp_ctrl_dai_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_lock_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 40300724456583737202144456330478266982413311810664609233136448585081420844012 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/26.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=190909420 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_check_fail.190909420' seed=40300724456583737202144456330478266982413311810664609233136448585081420844012 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40300724456583737202144456330478266982413311810664609233136448585081420844012 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/26.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_regwen 102930940630749320773609735533459534653192436122458189803826503717309025650759 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/26.otp_ctrl_regwen/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=490244167 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_regwen.490244167' seed=102930940630749320773609735533459534653192436122458189803826503717309025650759 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102930940630749320773609735533459534653192436122458189803826503717309025650759 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/26.otp_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 10101408873447758131919228162201915515555017232944597537606436069653223490632 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=990823496 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.otp_ctrl_stress_all_with_rand_reset.990823496' seed=10101408873447758131919228162201915515555017232944597537606436069653223490632 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10101408873447758131919228162201915515555017232944597537606436069653223490632 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/26.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 71390967284986522006194669612156289015162975920404094659891530433832605021921 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/27.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2519824097 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_init_fail.2519824097' seed=71390967284986522006194669612156289015162975920404094659891530433832605021921 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71390967284986522006194669612156289015162975920404094659891530433832605021921 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/27.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 56308815254103454151880907204141340461962071509233369150857621617444121470993 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3884967953 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_parallel_lc_esc.3884967953' seed=56308815254103454151880907204141340461962071509233369150857621617444121470993 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56308815254103454151880907204141340461962071509233369150857621617444121470993 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/27.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_lock 74649277924062751871861023868218934291365116128553701502860466345549345205600 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/27.otp_ctrl_dai_lock/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1375612256 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_dai_lock.1375612256' seed=74649277924062751871861023868218934291365116128553701502860466345549345205600 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74649277924062751871861023868218934291365116128553701502860466345549345205600 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/27.otp_ctrl_dai_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_lock_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 55858116716734036144329201482555586873211445078646144153991674454921885296378 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/27.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=498640634 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_check_fail.498640634' seed=55858116716734036144329201482555586873211445078646144153991674454921885296378 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55858116716734036144329201482555586873211445078646144153991674454921885296378 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/27.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_regwen 101166245802733664670470148672647552341109581998244074909414647234265944034277 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/27.otp_ctrl_regwen/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=400952293 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_regwen.400952293' seed=101166245802733664670470148672647552341109581998244074909414647234265944034277 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101166245802733664670470148672647552341109581998244074909414647234265944034277 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/27.otp_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 61244698220421130138437882957832541541589519639492705922383037266098258826272 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3770536992 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.otp_ctrl_stress_all_with_rand_reset.3770536992' seed=61244698220421130138437882957832541541589519639492705922383037266098258826272 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61244698220421130138437882957832541541589519639492705922383037266098258826272 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/27.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 65095044198111601884887883017461751897964600545539838641613398558704276963834 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/28.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2779087354 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_init_fail.2779087354' seed=65095044198111601884887883017461751897964600545539838641613398558704276963834 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65095044198111601884887883017461751897964600545539838641613398558704276963834 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/28.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 24901485394387142774081507039878720971352479533853618722946214665582699971307 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=723354347 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_parallel_lc_esc.723354347' seed=24901485394387142774081507039878720971352479533853618722946214665582699971307 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24901485394387142774081507039878720971352479533853618722946214665582699971307 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/28.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_lock 92881853913361317669625412771733634030674805158918162564039878834052061817997 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/28.otp_ctrl_dai_lock/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1281715341 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_dai_lock.1281715341' seed=92881853913361317669625412771733634030674805158918162564039878834052061817997 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92881853913361317669625412771733634030674805158918162564039878834052061817997 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/28.otp_ctrl_dai_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_lock_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 90843621593647344375594754791601459309898866812137681751985186416840651350352 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/28.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2538643792 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_check_fail.2538643792' seed=90843621593647344375594754791601459309898866812137681751985186416840651350352 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90843621593647344375594754791601459309898866812137681751985186416840651350352 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/28.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_regwen 94982403328365968630723951036764039150888417151611757014721432252165609709692 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/28.otp_ctrl_regwen/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=452157564 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_regwen.452157564' seed=94982403328365968630723951036764039150888417151611757014721432252165609709692 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94982403328365968630723951036764039150888417151611757014721432252165609709692 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/28.otp_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 25147094819692791143917532961826025677067112613357734185762259982008457181430 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3848091894 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.otp_ctrl_stress_all_with_rand_reset.3848091894' seed=25147094819692791143917532961826025677067112613357734185762259982008457181430 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25147094819692791143917532961826025677067112613357734185762259982008457181430 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/28.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 69144137469074426443765483645600994286296593525973595026153021504460592879461 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/29.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1220384613 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_init_fail.1220384613' seed=69144137469074426443765483645600994286296593525973595026153021504460592879461 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69144137469074426443765483645600994286296593525973595026153021504460592879461 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/29.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 97450470662256830844635408751489633059585406844718995274804340274405231671528 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=978172136 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_parallel_lc_esc.978172136' seed=97450470662256830844635408751489633059585406844718995274804340274405231671528 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97450470662256830844635408751489633059585406844718995274804340274405231671528 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/29.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_dai_lock 114609773972796738788378658099223876112979227604013397900292824296662748275575 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/29.otp_ctrl_dai_lock/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2587272055 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_dai_lock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_dai_lock.2587272055' seed=114609773972796738788378658099223876112979227604013397900292824296662748275575 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114609773972796738788378658099223876112979227604013397900292824296662748275575 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/29.otp_ctrl_dai_lock/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_dai_lock_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 91737295711321943003109965249119687061364750986279196602593609603491422757201 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/29.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=654008657 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_check_fail.654008657' seed=91737295711321943003109965249119687061364750986279196602593609603491422757201 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91737295711321943003109965249119687061364750986279196602593609603491422757201 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/29.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_regwen 64280603171353323956943705316044722313633079527607692831168703490761811394298 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/29.otp_ctrl_regwen/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1871281914 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_regwen.1871281914' seed=64280603171353323956943705316044722313633079527607692831168703490761811394298 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64280603171353323956943705316044722313633079527607692831168703490761811394298 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/29.otp_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 53086855742859175290267995238679338675025540888142294267513186927524786838049 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=535665185 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.otp_ctrl_stress_all_with_rand_reset.535665185' seed=53086855742859175290267995238679338675025540888142294267513186927524786838049 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53086855742859175290267995238679338675025540888142294267513186927524786838049 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/29.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 100201255616178711618765038312354728967626057062101409131640907632449365355842 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/30.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=166341954 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_init_fail.166341954' seed=100201255616178711618765038312354728967626057062101409131640907632449365355842 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100201255616178711618765038312354728967626057062101409131640907632449365355842 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/30.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 44027478788645778709563544069684574712585515018056858791373873177470594447379 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=532412435 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_parallel_lc_esc.532412435' seed=44027478788645778709563544069684574712585515018056858791373873177470594447379 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44027478788645778709563544069684574712585515018056858791373873177470594447379 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/30.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 103885020021531261681157511487030554792181957762619358282878528694687260407211 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/30.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1208153515 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_check_fail.1208153515' seed=103885020021531261681157511487030554792181957762619358282878528694687260407211 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103885020021531261681157511487030554792181957762619358282878528694687260407211 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/30.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 53822374786316408191366547844394007954496368479270690615992815646142716394888 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1055341960 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.otp_ctrl_stress_all_with_rand_reset.1055341960' seed=53822374786316408191366547844394007954496368479270690615992815646142716394888 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53822374786316408191366547844394007954496368479270690615992815646142716394888 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/30.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 90890519459519430236485848514433592318393519327250120607771024815969940775608 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/31.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=144679608 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_init_fail.144679608' seed=90890519459519430236485848514433592318393519327250120607771024815969940775608 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90890519459519430236485848514433592318393519327250120607771024815969940775608 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/31.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 64496670978455587403724456105672569483261165737888277944238796339473231803032 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3767693976 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_parallel_lc_esc.3767693976' seed=64496670978455587403724456105672569483261165737888277944238796339473231803032 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64496670978455587403724456105672569483261165737888277944238796339473231803032 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/31.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 76393627951891223026790313587019271606046326152032973324485890925867883280170 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/31.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=341292842 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_check_fail.341292842' seed=76393627951891223026790313587019271606046326152032973324485890925867883280170 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76393627951891223026790313587019271606046326152032973324485890925867883280170 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/31.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 23493975976551475213960864666276135733165666454595851119240642883392536952095 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1766440223 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.otp_ctrl_stress_all_with_rand_reset.1766440223' seed=23493975976551475213960864666276135733165666454595851119240642883392536952095 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23493975976551475213960864666276135733165666454595851119240642883392536952095 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/31.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 72600115985163222530660669307611717508159201204103477728855351477648310520737 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/32.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2433076129 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_init_fail.2433076129' seed=72600115985163222530660669307611717508159201204103477728855351477648310520737 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72600115985163222530660669307611717508159201204103477728855351477648310520737 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/32.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 77047635806310937305301905523293605936621059749388114439048583027369559681579 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1913612843 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_parallel_lc_esc.1913612843' seed=77047635806310937305301905523293605936621059749388114439048583027369559681579 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77047635806310937305301905523293605936621059749388114439048583027369559681579 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/32.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 2529833937134711711531179585642665762056816325667789895635613622233219734772 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/32.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4173602036 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_check_fail.4173602036' seed=2529833937134711711531179585642665762056816325667789895635613622233219734772 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2529833937134711711531179585642665762056816325667789895635613622233219734772 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/32.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 12709683206032005835261620591042799578104221370689461996426594933635451440982 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/32.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3454783318 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.otp_ctrl_stress_all_with_rand_reset.3454783318' seed=12709683206032005835261620591042799578104221370689461996426594933635451440982 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12709683206032005835261620591042799578104221370689461996426594933635451440982 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/32.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 89351382002575068139776739687292364142321190059731889137207214010722838163057 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/33.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=660647537 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_init_fail.660647537' seed=89351382002575068139776739687292364142321190059731889137207214010722838163057 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89351382002575068139776739687292364142321190059731889137207214010722838163057 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/33.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 42735657620706582065407081969626630603896278763014068159138660092431696597649 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1937445521 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_parallel_lc_esc.1937445521' seed=42735657620706582065407081969626630603896278763014068159138660092431696597649 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42735657620706582065407081969626630603896278763014068159138660092431696597649 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/33.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 75818590114845117689608489064356457198374416835181391313094289828813450672601 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/33.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2260629977 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_check_fail.2260629977' seed=75818590114845117689608489064356457198374416835181391313094289828813450672601 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75818590114845117689608489064356457198374416835181391313094289828813450672601 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/33.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 82102060962165903255404440280142446140392864743495618284469443251674885969778 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1767954290 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.otp_ctrl_stress_all_with_rand_reset.1767954290' seed=82102060962165903255404440280142446140392864743495618284469443251674885969778 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82102060962165903255404440280142446140392864743495618284469443251674885969778 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/33.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 40163681219148806296228419587745318642062882069467474569275783511531193645462 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/34.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1380202902 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_init_fail.1380202902' seed=40163681219148806296228419587745318642062882069467474569275783511531193645462 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40163681219148806296228419587745318642062882069467474569275783511531193645462 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/34.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 103834154496553553080170918767516384079403406969414864965404585010732186490715 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2092193627 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_parallel_lc_esc.2092193627' seed=103834154496553553080170918767516384079403406969414864965404585010732186490715 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103834154496553553080170918767516384079403406969414864965404585010732186490715 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/34.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 62338336273333233208360657778572944733194187843689741089688677227212643707651 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/34.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1094396675 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_check_fail.1094396675' seed=62338336273333233208360657778572944733194187843689741089688677227212643707651 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62338336273333233208360657778572944733194187843689741089688677227212643707651 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/34.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 89353321895720839367021762508939329521984784311011121860885133127600259916603 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=981394235 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.otp_ctrl_stress_all_with_rand_reset.981394235' seed=89353321895720839367021762508939329521984784311011121860885133127600259916603 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89353321895720839367021762508939329521984784311011121860885133127600259916603 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/34.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 58369532658520725067086676273609886364042584025668472842403479534674523965249 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/35.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=556255041 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_init_fail.556255041' seed=58369532658520725067086676273609886364042584025668472842403479534674523965249 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58369532658520725067086676273609886364042584025668472842403479534674523965249 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/35.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 100138192479964973121519756800746228940699158035832828973641172966790095057815 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3574739863 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_parallel_lc_esc.3574739863' seed=100138192479964973121519756800746228940699158035832828973641172966790095057815 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100138192479964973121519756800746228940699158035832828973641172966790095057815 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/35.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 79255687693206501255725194319190735181821391766931921348788726389907051741919 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/35.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3968828127 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_check_fail.3968828127' seed=79255687693206501255725194319190735181821391766931921348788726389907051741919 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79255687693206501255725194319190735181821391766931921348788726389907051741919 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/35.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 102559069722875224758670973975363567324613208345208742895777461625735831034174 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4182186302 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.otp_ctrl_stress_all_with_rand_reset.4182186302' seed=102559069722875224758670973975363567324613208345208742895777461625735831034174 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102559069722875224758670973975363567324613208345208742895777461625735831034174 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/35.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 82764922896718481245325137988584311600608523004228466416093119670918904588736 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/36.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1486137792 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_init_fail.1486137792' seed=82764922896718481245325137988584311600608523004228466416093119670918904588736 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82764922896718481245325137988584311600608523004228466416093119670918904588736 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/36.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 8685498846290686248905350198089759763844670193805833554964165996575637912844 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1352940812 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_parallel_lc_esc.1352940812' seed=8685498846290686248905350198089759763844670193805833554964165996575637912844 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8685498846290686248905350198089759763844670193805833554964165996575637912844 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/36.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 9863640128835221926576746504571791051638274702356522385639020877365728568634 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/36.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2337596730 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_check_fail.2337596730' seed=9863640128835221926576746504571791051638274702356522385639020877365728568634 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9863640128835221926576746504571791051638274702356522385639020877365728568634 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/36.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 97894516309359988877715492355460498810440891683136171805339132504844562677164 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/36.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2159623596 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.otp_ctrl_stress_all_with_rand_reset.2159623596' seed=97894516309359988877715492355460498810440891683136171805339132504844562677164 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97894516309359988877715492355460498810440891683136171805339132504844562677164 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/36.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 13551281547895378139833254061177467220771544949383962425587395406410071539529 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/37.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3123052361 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_init_fail.3123052361' seed=13551281547895378139833254061177467220771544949383962425587395406410071539529 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13551281547895378139833254061177467220771544949383962425587395406410071539529 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/37.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 46888619382276522992231318100377960135868829686241350475024748629948927426216 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2823405224 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_parallel_lc_esc.2823405224' seed=46888619382276522992231318100377960135868829686241350475024748629948927426216 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46888619382276522992231318100377960135868829686241350475024748629948927426216 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/37.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 27716721963695220331693559444778305719238863323322465786250421055212241748660 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/37.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=342295220 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_check_fail.342295220' seed=27716721963695220331693559444778305719238863323322465786250421055212241748660 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27716721963695220331693559444778305719238863323322465786250421055212241748660 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/37.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 109277750677541070371788031485417030311020570128467912047618393953229438253620 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3113286196 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.otp_ctrl_stress_all_with_rand_reset.3113286196' seed=109277750677541070371788031485417030311020570128467912047618393953229438253620 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109277750677541070371788031485417030311020570128467912047618393953229438253620 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/37.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 41482125399458719541863025253151707585783366368078407865461888546923950011857 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/38.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2298639825 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_init_fail.2298639825' seed=41482125399458719541863025253151707585783366368078407865461888546923950011857 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41482125399458719541863025253151707585783366368078407865461888546923950011857 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/38.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 48260675719794443347013942473886829201172915457895738162509777568736162120645 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2155381701 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_parallel_lc_esc.2155381701' seed=48260675719794443347013942473886829201172915457895738162509777568736162120645 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48260675719794443347013942473886829201172915457895738162509777568736162120645 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/38.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 80754737820714575585226254720518911333179253677191455030961627743959571908039 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/38.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=475153863 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_check_fail.475153863' seed=80754737820714575585226254720518911333179253677191455030961627743959571908039 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80754737820714575585226254720518911333179253677191455030961627743959571908039 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/38.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 91296826187331690129587453150480337691138238661543573139337669140437033739150 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/38.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2529354638 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.otp_ctrl_stress_all_with_rand_reset.2529354638' seed=91296826187331690129587453150480337691138238661543573139337669140437033739150 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91296826187331690129587453150480337691138238661543573139337669140437033739150 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/38.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 83524470285176171837548006740590192029297711486230478899107945666474751011770 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/39.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1345563578 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_init_fail.1345563578' seed=83524470285176171837548006740590192029297711486230478899107945666474751011770 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83524470285176171837548006740590192029297711486230478899107945666474751011770 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/39.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 74369764199955347513574786171839897139846058983122816588704044587569263559024 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2648326512 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_parallel_lc_esc.2648326512' seed=74369764199955347513574786171839897139846058983122816588704044587569263559024 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74369764199955347513574786171839897139846058983122816588704044587569263559024 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/39.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 33223827073884962943860455583092437140855282255959861838014921615337235709062 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/39.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1739881606 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_check_fail.1739881606' seed=33223827073884962943860455583092437140855282255959861838014921615337235709062 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33223827073884962943860455583092437140855282255959861838014921615337235709062 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/39.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 96829058271923831084964004362033419345713704594112161135422648382462252511503 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2606723343 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.otp_ctrl_stress_all_with_rand_reset.2606723343' seed=96829058271923831084964004362033419345713704594112161135422648382462252511503 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96829058271923831084964004362033419345713704594112161135422648382462252511503 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/39.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 76231615824497244401554432116528240106164547213046554975412192176420596552562 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/40.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1445794674 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_init_fail.1445794674' seed=76231615824497244401554432116528240106164547213046554975412192176420596552562 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76231615824497244401554432116528240106164547213046554975412192176420596552562 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/40.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 57924586257324555660486425686053052404154103372045035048222018816824750068039 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=482300231 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_parallel_lc_esc.482300231' seed=57924586257324555660486425686053052404154103372045035048222018816824750068039 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57924586257324555660486425686053052404154103372045035048222018816824750068039 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/40.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 113260760394388546863498713841728848058147926022607198556077550063876779170670 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/40.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1975933806 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_check_fail.1975933806' seed=113260760394388546863498713841728848058147926022607198556077550063876779170670 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113260760394388546863498713841728848058147926022607198556077550063876779170670 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/40.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 42797722576735524119054181361041860508797159454425457043280801195476990220870 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/40.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=619108934 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.otp_ctrl_stress_all_with_rand_reset.619108934' seed=42797722576735524119054181361041860508797159454425457043280801195476990220870 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42797722576735524119054181361041860508797159454425457043280801195476990220870 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/40.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 15096778508728203011815391939450241625706594506142332596065978249811289313084 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/41.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=6426428 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_init_fail.6426428' seed=15096778508728203011815391939450241625706594506142332596065978249811289313084 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15096778508728203011815391939450241625706594506142332596065978249811289313084 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/41.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 7207189877596387740186136580640248767750352058898449336763525752655396688563 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4071576243 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_parallel_lc_esc.4071576243' seed=7207189877596387740186136580640248767750352058898449336763525752655396688563 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7207189877596387740186136580640248767750352058898449336763525752655396688563 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/41.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 39314217104383664206512941850936898762897010134651865681148830752186028155834 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/41.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2802213818 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_check_fail.2802213818' seed=39314217104383664206512941850936898762897010134651865681148830752186028155834 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39314217104383664206512941850936898762897010134651865681148830752186028155834 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/41.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 61321573454495228346654867300952610920122303853913289755974523756872591683471 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2631348111 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.otp_ctrl_stress_all_with_rand_reset.2631348111' seed=61321573454495228346654867300952610920122303853913289755974523756872591683471 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61321573454495228346654867300952610920122303853913289755974523756872591683471 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/41.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 60918060979081896305250988448285775249401435325641831056987270242075631454531 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/42.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1106020675 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_init_fail.1106020675' seed=60918060979081896305250988448285775249401435325641831056987270242075631454531 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60918060979081896305250988448285775249401435325641831056987270242075631454531 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/42.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 59674052182578751532519788492678682557124137165003085361297818778707848546392 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=513493080 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_parallel_lc_esc.513493080' seed=59674052182578751532519788492678682557124137165003085361297818778707848546392 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=59674052182578751532519788492678682557124137165003085361297818778707848546392 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/42.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 109720729429613146712704681589611551468028780992572561603840572996906323047747 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/42.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1455977795 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_check_fail.1455977795' seed=109720729429613146712704681589611551468028780992572561603840572996906323047747 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109720729429613146712704681589611551468028780992572561603840572996906323047747 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/42.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 69808766526537053173422891018797234478371803574899995461273475083003817945947 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/42.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4096322395 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.otp_ctrl_stress_all_with_rand_reset.4096322395' seed=69808766526537053173422891018797234478371803574899995461273475083003817945947 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69808766526537053173422891018797234478371803574899995461273475083003817945947 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/42.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 95012610989302076947586639545837506229209703858358333381257660655195810132785 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/43.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=902525745 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_init_fail.902525745' seed=95012610989302076947586639545837506229209703858358333381257660655195810132785 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95012610989302076947586639545837506229209703858358333381257660655195810132785 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/43.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 35743737030986663216031803790323672032842880633167310571800971572889452130598 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1787932966 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_parallel_lc_esc.1787932966' seed=35743737030986663216031803790323672032842880633167310571800971572889452130598 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35743737030986663216031803790323672032842880633167310571800971572889452130598 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/43.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 111916711120183402986906402796673411415692311815622889450470092160845217966321 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/43.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=423799025 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_check_fail.423799025' seed=111916711120183402986906402796673411415692311815622889450470092160845217966321 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111916711120183402986906402796673411415692311815622889450470092160845217966321 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/43.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 81714702652082556054679842836512225369823070104003012987698791213049827308921 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2787390841 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.otp_ctrl_stress_all_with_rand_reset.2787390841' seed=81714702652082556054679842836512225369823070104003012987698791213049827308921 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81714702652082556054679842836512225369823070104003012987698791213049827308921 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/43.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 53538117422036167989108204022109523087816191787306079176785448707053276188164 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/44.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=492916228 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_init_fail.492916228' seed=53538117422036167989108204022109523087816191787306079176785448707053276188164 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53538117422036167989108204022109523087816191787306079176785448707053276188164 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/44.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 62583422749530665482289318261173017803013918362834823171510893046568444060652 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1830118380 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_parallel_lc_esc.1830118380' seed=62583422749530665482289318261173017803013918362834823171510893046568444060652 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62583422749530665482289318261173017803013918362834823171510893046568444060652 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/44.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 103167761815490413938610578197977963511842620191043359472360429356769243039967 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/44.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1262749919 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_check_fail.1262749919' seed=103167761815490413938610578197977963511842620191043359472360429356769243039967 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103167761815490413938610578197977963511842620191043359472360429356769243039967 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/44.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 29426301656031990982165625927232568734105699627228405336086812938221081011521 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/44.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3329697089 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.otp_ctrl_stress_all_with_rand_reset.3329697089' seed=29426301656031990982165625927232568734105699627228405336086812938221081011521 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29426301656031990982165625927232568734105699627228405336086812938221081011521 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/44.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 362586372707726894810018233876392688351500920757717201824190340443135690879 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/45.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1845381247 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_init_fail.1845381247' seed=362586372707726894810018233876392688351500920757717201824190340443135690879 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=362586372707726894810018233876392688351500920757717201824190340443135690879 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/45.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 35275540135109978242123115928856441668286887438691313737566066508986056257751 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2600022231 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_parallel_lc_esc.2600022231' seed=35275540135109978242123115928856441668286887438691313737566066508986056257751 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35275540135109978242123115928856441668286887438691313737566066508986056257751 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/45.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 83944580984714974079381696937858425895480490637514654943721700419603187367208 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/45.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3887594792 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_check_fail.3887594792' seed=83944580984714974079381696937858425895480490637514654943721700419603187367208 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83944580984714974079381696937858425895480490637514654943721700419603187367208 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/45.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 51150605722975629591108695758407502100763130329608958085165038539977793491274 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/45.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1654411594 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.otp_ctrl_stress_all_with_rand_reset.1654411594' seed=51150605722975629591108695758407502100763130329608958085165038539977793491274 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51150605722975629591108695758407502100763130329608958085165038539977793491274 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/45.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 8303134463055907456227578600759615599834327708851154089824491518917282068877 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/46.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=578517389 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_init_fail.578517389' seed=8303134463055907456227578600759615599834327708851154089824491518917282068877 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8303134463055907456227578600759615599834327708851154089824491518917282068877 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/46.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 36621735525759115524517935326361410624550718389131592923440166639188483961854 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=704574462 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_parallel_lc_esc.704574462' seed=36621735525759115524517935326361410624550718389131592923440166639188483961854 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36621735525759115524517935326361410624550718389131592923440166639188483961854 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/46.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 2474332305918248565281185016455008010061162095798192149102609695087077607980 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/46.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2206714412 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_check_fail.2206714412' seed=2474332305918248565281185016455008010061162095798192149102609695087077607980 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2474332305918248565281185016455008010061162095798192149102609695087077607980 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/46.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 99070857966993899512702140572885023195927973831776378437113107950108755264956 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/46.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4061562300 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.otp_ctrl_stress_all_with_rand_reset.4061562300' seed=99070857966993899512702140572885023195927973831776378437113107950108755264956 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99070857966993899512702140572885023195927973831776378437113107950108755264956 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/46.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 93392444286496960876722882640467781924776156234357913896384047695413703954730 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/47.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1581076778 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_init_fail.1581076778' seed=93392444286496960876722882640467781924776156234357913896384047695413703954730 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93392444286496960876722882640467781924776156234357913896384047695413703954730 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/47.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 23279015556900344725804607952236709314184477168475092090248816536147333141822 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2167330110 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_parallel_lc_esc.2167330110' seed=23279015556900344725804607952236709314184477168475092090248816536147333141822 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23279015556900344725804607952236709314184477168475092090248816536147333141822 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/47.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 54781956010924805472736929997290791651951163505710754557911322058706492374811 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/47.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3729309467 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_check_fail.3729309467' seed=54781956010924805472736929997290791651951163505710754557911322058706492374811 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54781956010924805472736929997290791651951163505710754557911322058706492374811 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/47.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 61045389666710000256425636485537772735538659274258889952072610389902750281921 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/47.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1342861505 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.otp_ctrl_stress_all_with_rand_reset.1342861505' seed=61045389666710000256425636485537772735538659274258889952072610389902750281921 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61045389666710000256425636485537772735538659274258889952072610389902750281921 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/47.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 57167651744954028193096641146893933913962663877289765192829991167665333157161 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/48.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3369942313 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_init_fail.3369942313' seed=57167651744954028193096641146893933913962663877289765192829991167665333157161 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57167651744954028193096641146893933913962663877289765192829991167665333157161 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/48.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 105216116076634768735024470788397371774781761781330195432157428720917702439640 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2160259800 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_parallel_lc_esc.2160259800' seed=105216116076634768735024470788397371774781761781330195432157428720917702439640 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105216116076634768735024470788397371774781761781330195432157428720917702439640 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/48.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 100959883430383549233023648415178876437327224853858313944151284672114866406720 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/48.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=252593472 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_check_fail.252593472' seed=100959883430383549233023648415178876437327224853858313944151284672114866406720 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100959883430383549233023648415178876437327224853858313944151284672114866406720 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/48.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 108388914439104009349973904898454633272422001592603303594059814184022840048471 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/48.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1098513239 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.otp_ctrl_stress_all_with_rand_reset.1098513239' seed=108388914439104009349973904898454633272422001592603303594059814184022840048471 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108388914439104009349973904898454633272422001592603303594059814184022840048471 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/48.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 36508732569987820705009274743916849575074296109512379030294293856303040078996 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/49.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=474915988 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_init_fail.474915988' seed=36508732569987820705009274743916849575074296109512379030294293856303040078996 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36508732569987820705009274743916849575074296109512379030294293856303040078996 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/49.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 38728768596642205084100576939361605440248542315371900842618365923386417233818 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3826270106 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_parallel_lc_esc.3826270106' seed=38728768596642205084100576939361605440248542315371900842618365923386417233818 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38728768596642205084100576939361605440248542315371900842618365923386417233818 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/49.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_check_fail 62586476871274828439064718531038627060432950229080462994178723005848006375916 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/49.otp_ctrl_check_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=263928300 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_check_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_check_fail.263928300' seed=62586476871274828439064718531038627060432950229080462994178723005848006375916 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62586476871274828439064718531038627060432950229080462994178723005848006375916 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/49.otp_ctrl_check_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_check_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 72873820907615917922626583197771497040114871193668094615294853923844490430003 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/49.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=625903155 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.otp_ctrl_stress_all_with_rand_reset.625903155' seed=72873820907615917922626583197771497040114871193668094615294853923844490430003 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72873820907615917922626583197771497040114871193668094615294853923844490430003 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/49.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 42402705967399299648732971965921988824411990369756594394266958969179897476570 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/50.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3900585434 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_init_fail.3900585434' seed=42402705967399299648732971965921988824411990369756594394266958969179897476570 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42402705967399299648732971965921988824411990369756594394266958969179897476570 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/50.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 32195455420677865843357371984601353265118892836159739539462478169444657457819 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/50.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1066986139 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_parallel_lc_esc.1066986139' seed=32195455420677865843357371984601353265118892836159739539462478169444657457819 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32195455420677865843357371984601353265118892836159739539462478169444657457819 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/50.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 4338289654991691612497192551877510604795882278057591696727783914959113770456 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/50.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4145239512 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.otp_ctrl_stress_all_with_rand_reset.4145239512' seed=4338289654991691612497192551877510604795882278057591696727783914959113770456 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4338289654991691612497192551877510604795882278057591696727783914959113770456 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/50.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 39726122797069637592412614360907016144191703490380803907153654782113770191836 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/51.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2939239388 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_init_fail.2939239388' seed=39726122797069637592412614360907016144191703490380803907153654782113770191836 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39726122797069637592412614360907016144191703490380803907153654782113770191836 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/51.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 61482535757728452258918791640129436583729074759155689431982243176510419508296 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/51.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3812498504 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_parallel_lc_esc.3812498504' seed=61482535757728452258918791640129436583729074759155689431982243176510419508296 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61482535757728452258918791640129436583729074759155689431982243176510419508296 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/51.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 91824225002776812930673300928033565720436974394276326717205410757075589837283 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/51.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2193011171 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.otp_ctrl_stress_all_with_rand_reset.2193011171' seed=91824225002776812930673300928033565720436974394276326717205410757075589837283 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91824225002776812930673300928033565720436974394276326717205410757075589837283 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/51.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 33629459288489812214155178614069948306545285105719799227712304399097884648647 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/52.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=811410631 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_init_fail.811410631' seed=33629459288489812214155178614069948306545285105719799227712304399097884648647 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33629459288489812214155178614069948306545285105719799227712304399097884648647 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/52.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 5925824241062071228349264668896521743430597852312937762454717129504397138636 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/52.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2753764044 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_parallel_lc_esc.2753764044' seed=5925824241062071228349264668896521743430597852312937762454717129504397138636 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5925824241062071228349264668896521743430597852312937762454717129504397138636 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/52.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 40493972409511815014820944806948545322273889693886000184743095846248296792089 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/52.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3036987417 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.otp_ctrl_stress_all_with_rand_reset.3036987417' seed=40493972409511815014820944806948545322273889693886000184743095846248296792089 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40493972409511815014820944806948545322273889693886000184743095846248296792089 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/52.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 23024567066771994151987564435327532708578974675740542965665572883903989331385 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/53.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1555477945 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_init_fail.1555477945' seed=23024567066771994151987564435327532708578974675740542965665572883903989331385 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23024567066771994151987564435327532708578974675740542965665572883903989331385 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/53.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 39439311980708363169148472771521789044186678305734067865691731361065010634783 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/53.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=588161055 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_parallel_lc_esc.588161055' seed=39439311980708363169148472771521789044186678305734067865691731361065010634783 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39439311980708363169148472771521789044186678305734067865691731361065010634783 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/53.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 3252525024945881011820246325154045900978953891011781943523646011825291048572 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/53.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=81311356 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.otp_ctrl_stress_all_with_rand_reset.81311356' seed=3252525024945881011820246325154045900978953891011781943523646011825291048572 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3252525024945881011820246325154045900978953891011781943523646011825291048572 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/53.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 100124720679731986647219443845080619556034712818375936879480845678690330498774 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/54.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=237262550 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_init_fail.237262550' seed=100124720679731986647219443845080619556034712818375936879480845678690330498774 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100124720679731986647219443845080619556034712818375936879480845678690330498774 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/54.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 90955232827719353041655862002586541642473641104946573823094952334324372094726 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/54.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2410954502 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_parallel_lc_esc.2410954502' seed=90955232827719353041655862002586541642473641104946573823094952334324372094726 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90955232827719353041655862002586541642473641104946573823094952334324372094726 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/54.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 17699773809978596782691877848107991665384409516039155427862503558969607336980 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/54.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3447731220 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.otp_ctrl_stress_all_with_rand_reset.3447731220' seed=17699773809978596782691877848107991665384409516039155427862503558969607336980 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17699773809978596782691877848107991665384409516039155427862503558969607336980 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/54.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 29040976090109900346171381610116092801141799917874844239165497782538964426924 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/55.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3375489196 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_init_fail.3375489196' seed=29040976090109900346171381610116092801141799917874844239165497782538964426924 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29040976090109900346171381610116092801141799917874844239165497782538964426924 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/55.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 93349214066310530747572598863468771319572838986442906649970014148309854389533 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/55.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2509440285 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_parallel_lc_esc.2509440285' seed=93349214066310530747572598863468771319572838986442906649970014148309854389533 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93349214066310530747572598863468771319572838986442906649970014148309854389533 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/55.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 96541822414348479475676129659731259277743271335520085724338471855411188552005 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/55.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=751128901 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.otp_ctrl_stress_all_with_rand_reset.751128901' seed=96541822414348479475676129659731259277743271335520085724338471855411188552005 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96541822414348479475676129659731259277743271335520085724338471855411188552005 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/55.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 58934299382180833179336074086140269126464398571405640723601049936672988726883 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/56.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3060139619 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_init_fail.3060139619' seed=58934299382180833179336074086140269126464398571405640723601049936672988726883 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58934299382180833179336074086140269126464398571405640723601049936672988726883 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/56.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 1417550535964363579191857520544925070138973844126187071350301191901415768648 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/56.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2838790728 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_parallel_lc_esc.2838790728' seed=1417550535964363579191857520544925070138973844126187071350301191901415768648 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1417550535964363579191857520544925070138973844126187071350301191901415768648 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/56.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 16427806548915356248294202825216595903059060047910644076659689238878260941946 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/56.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=437113978 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.otp_ctrl_stress_all_with_rand_reset.437113978' seed=16427806548915356248294202825216595903059060047910644076659689238878260941946 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16427806548915356248294202825216595903059060047910644076659689238878260941946 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/56.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 11194709645732274587088657763014161766121390742004475385535727729327693673231 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/57.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1097642767 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_init_fail.1097642767' seed=11194709645732274587088657763014161766121390742004475385535727729327693673231 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11194709645732274587088657763014161766121390742004475385535727729327693673231 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/57.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 96552345843167035962617926601015981394912490965327021780676262363502856107682 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/57.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1582560930 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_parallel_lc_esc.1582560930' seed=96552345843167035962617926601015981394912490965327021780676262363502856107682 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96552345843167035962617926601015981394912490965327021780676262363502856107682 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/57.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 43878232495718636175936616951388389554229470714563157657099911406497039691360 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/57.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3746868832 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.otp_ctrl_stress_all_with_rand_reset.3746868832' seed=43878232495718636175936616951388389554229470714563157657099911406497039691360 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43878232495718636175936616951388389554229470714563157657099911406497039691360 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/57.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 45859127860789856506890562280272667781840733253400442496464891544520990713134 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/58.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=542696750 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_init_fail.542696750' seed=45859127860789856506890562280272667781840733253400442496464891544520990713134 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45859127860789856506890562280272667781840733253400442496464891544520990713134 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/58.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 8162158884724006188064311829468554331722970858125173414304932403009429332081 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/58.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=923426929 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_parallel_lc_esc.923426929' seed=8162158884724006188064311829468554331722970858125173414304932403009429332081 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8162158884724006188064311829468554331722970858125173414304932403009429332081 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/58.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 76893511080108175233796564378830082109399154137055842556777355661628845297272 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/58.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=731090552 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.otp_ctrl_stress_all_with_rand_reset.731090552' seed=76893511080108175233796564378830082109399154137055842556777355661628845297272 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76893511080108175233796564378830082109399154137055842556777355661628845297272 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/58.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 88358809393508062365545595887197982120563928174089812431265158464125635143132 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/59.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1208231388 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_init_fail.1208231388' seed=88358809393508062365545595887197982120563928174089812431265158464125635143132 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88358809393508062365545595887197982120563928174089812431265158464125635143132 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/59.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 88327768415810239403932263895418561717303769046500431484412165477399830998016 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/59.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2109221888 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_parallel_lc_esc.2109221888' seed=88327768415810239403932263895418561717303769046500431484412165477399830998016 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88327768415810239403932263895418561717303769046500431484412165477399830998016 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/59.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 96504346102746229258478223630797511901477668815329297959759188112550942477801 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/59.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1150553577 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.otp_ctrl_stress_all_with_rand_reset.1150553577' seed=96504346102746229258478223630797511901477668815329297959759188112550942477801 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96504346102746229258478223630797511901477668815329297959759188112550942477801 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/59.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 74094704392982688431606593368909119141871359892538867497487109296064206328308 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/60.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1899614708 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_init_fail.1899614708' seed=74094704392982688431606593368909119141871359892538867497487109296064206328308 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74094704392982688431606593368909119141871359892538867497487109296064206328308 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/60.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 79275565837089260841094068070661321176561585625500871978217689408014068748768 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/60.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=837030368 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_parallel_lc_esc.837030368' seed=79275565837089260841094068070661321176561585625500871978217689408014068748768 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79275565837089260841094068070661321176561585625500871978217689408014068748768 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/60.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 29943965688320121786352932706807780613859572140950965094665747570917639622849 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/60.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1423347905 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.otp_ctrl_stress_all_with_rand_reset.1423347905' seed=29943965688320121786352932706807780613859572140950965094665747570917639622849 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29943965688320121786352932706807780613859572140950965094665747570917639622849 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/60.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 104894183879828145339722606216647647462229459870152348099066939014139790117684 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/61.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3974777652 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_init_fail.3974777652' seed=104894183879828145339722606216647647462229459870152348099066939014139790117684 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104894183879828145339722606216647647462229459870152348099066939014139790117684 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/61.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 6053932299085758659912533418493034829379686173465187351839305692617966177765 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/61.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=426855909 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_parallel_lc_esc.426855909' seed=6053932299085758659912533418493034829379686173465187351839305692617966177765 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6053932299085758659912533418493034829379686173465187351839305692617966177765 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/61.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 25498253071116782989892198268734334255420943509943923371187924230663446309544 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/61.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2083105448 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.otp_ctrl_stress_all_with_rand_reset.2083105448' seed=25498253071116782989892198268734334255420943509943923371187924230663446309544 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25498253071116782989892198268734334255420943509943923371187924230663446309544 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/61.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 15812057907837000473471291713534011928456852904884386737049940587551581489504 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/62.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3807332704 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_init_fail.3807332704' seed=15812057907837000473471291713534011928456852904884386737049940587551581489504 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15812057907837000473471291713534011928456852904884386737049940587551581489504 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/62.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 68542377880896427501017668324087704015047729033971957509011652524702333140117 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/62.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1546124437 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_parallel_lc_esc.1546124437' seed=68542377880896427501017668324087704015047729033971957509011652524702333140117 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68542377880896427501017668324087704015047729033971957509011652524702333140117 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/62.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 61718017034512853779348564957830742732404970421989475066889427275250941016230 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/62.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2754328742 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.otp_ctrl_stress_all_with_rand_reset.2754328742' seed=61718017034512853779348564957830742732404970421989475066889427275250941016230 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61718017034512853779348564957830742732404970421989475066889427275250941016230 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/62.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 46786399155007644156556483896247520412168172789631623105917131637398344348827 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/63.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4283217051 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_init_fail.4283217051' seed=46786399155007644156556483896247520412168172789631623105917131637398344348827 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46786399155007644156556483896247520412168172789631623105917131637398344348827 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/63.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 8127756707544968013943853439776340762067716889363354046954062226826350608478 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/63.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2911420510 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_parallel_lc_esc.2911420510' seed=8127756707544968013943853439776340762067716889363354046954062226826350608478 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8127756707544968013943853439776340762067716889363354046954062226826350608478 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/63.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 110001194522918225895930903967725412132557066943366933160161804926900244115463 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/63.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3860393991 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.otp_ctrl_stress_all_with_rand_reset.3860393991' seed=110001194522918225895930903967725412132557066943366933160161804926900244115463 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110001194522918225895930903967725412132557066943366933160161804926900244115463 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/63.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 13011329887722863695113725461389330699740260724776747631604139448713381898197 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/64.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1758685141 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_init_fail.1758685141' seed=13011329887722863695113725461389330699740260724776747631604139448713381898197 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13011329887722863695113725461389330699740260724776747631604139448713381898197 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/64.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 7378243280386630711671714114502061506159005267282094001340108167536664570899 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/64.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3431918611 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_parallel_lc_esc.3431918611' seed=7378243280386630711671714114502061506159005267282094001340108167536664570899 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7378243280386630711671714114502061506159005267282094001340108167536664570899 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/64.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 45007898036710718849091272588020265911894683491555108381566112437370037629219 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/64.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1271558435 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.otp_ctrl_stress_all_with_rand_reset.1271558435' seed=45007898036710718849091272588020265911894683491555108381566112437370037629219 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45007898036710718849091272588020265911894683491555108381566112437370037629219 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/64.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 44832119990279397603163033535310914591650483243512459309984159578694315034055 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/65.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2799584711 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_init_fail.2799584711' seed=44832119990279397603163033535310914591650483243512459309984159578694315034055 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44832119990279397603163033535310914591650483243512459309984159578694315034055 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/65.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 53181208319205483130371948632837344769067483318448267505323033402618279518794 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/65.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3840565834 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_parallel_lc_esc.3840565834' seed=53181208319205483130371948632837344769067483318448267505323033402618279518794 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53181208319205483130371948632837344769067483318448267505323033402618279518794 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/65.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 20816813161706710057610842350692282797614549310218420228020199474747391160630 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/65.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1647915318 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.otp_ctrl_stress_all_with_rand_reset.1647915318' seed=20816813161706710057610842350692282797614549310218420228020199474747391160630 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20816813161706710057610842350692282797614549310218420228020199474747391160630 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/65.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 29126195880898322859851709684499846479842109257487560814473273266763852469735 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/66.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1960629735 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_init_fail.1960629735' seed=29126195880898322859851709684499846479842109257487560814473273266763852469735 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29126195880898322859851709684499846479842109257487560814473273266763852469735 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/66.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 28989754478416253395098926351238937360596156689085199743952443451929490810539 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/66.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=964880043 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_parallel_lc_esc.964880043' seed=28989754478416253395098926351238937360596156689085199743952443451929490810539 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28989754478416253395098926351238937360596156689085199743952443451929490810539 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/66.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 97411257222521770684419682036265907029540218071411042851611731103132444300845 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/66.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=454071853 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.otp_ctrl_stress_all_with_rand_reset.454071853' seed=97411257222521770684419682036265907029540218071411042851611731103132444300845 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97411257222521770684419682036265907029540218071411042851611731103132444300845 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/66.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 23080485528381707038520360292902136763362109984945905890225775735467083967749 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/67.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3277466885 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_init_fail.3277466885' seed=23080485528381707038520360292902136763362109984945905890225775735467083967749 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23080485528381707038520360292902136763362109984945905890225775735467083967749 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/67.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 69505547264267920728694122254327501071697005138445562580555128463525638753711 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/67.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3734425007 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_parallel_lc_esc.3734425007' seed=69505547264267920728694122254327501071697005138445562580555128463525638753711 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69505547264267920728694122254327501071697005138445562580555128463525638753711 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/67.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 43910588095002538056308414592575098525660024021544139388697381036575550506508 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/67.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4175595020 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.otp_ctrl_stress_all_with_rand_reset.4175595020' seed=43910588095002538056308414592575098525660024021544139388697381036575550506508 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43910588095002538056308414592575098525660024021544139388697381036575550506508 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/67.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 53400320947286082082103913872723875414903409756040577757560832872870257920883 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/68.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=296258419 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_init_fail.296258419' seed=53400320947286082082103913872723875414903409756040577757560832872870257920883 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53400320947286082082103913872723875414903409756040577757560832872870257920883 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/68.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 24765038229796968279812333057460461674320829592905653402744933681460626236631 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/68.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1490986199 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_parallel_lc_esc.1490986199' seed=24765038229796968279812333057460461674320829592905653402744933681460626236631 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24765038229796968279812333057460461674320829592905653402744933681460626236631 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/68.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 105658617101224162493757328506106164669552732817695555247034551663812011978656 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/68.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2568056736 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.otp_ctrl_stress_all_with_rand_reset.2568056736' seed=105658617101224162493757328506106164669552732817695555247034551663812011978656 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105658617101224162493757328506106164669552732817695555247034551663812011978656 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/68.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 35076248673166093194058489642443388651480832486808799095232317226820831694024 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/69.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1877363912 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_init_fail.1877363912' seed=35076248673166093194058489642443388651480832486808799095232317226820831694024 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35076248673166093194058489642443388651480832486808799095232317226820831694024 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/69.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 94611128962916413289022968970579488636533105764641807699325550544465644333858 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/69.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=463317794 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_parallel_lc_esc.463317794' seed=94611128962916413289022968970579488636533105764641807699325550544465644333858 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94611128962916413289022968970579488636533105764641807699325550544465644333858 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/69.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 54982185358569035653082539241067710080224759935598546554144131956495470247246 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/69.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3335470414 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.otp_ctrl_stress_all_with_rand_reset.3335470414' seed=54982185358569035653082539241067710080224759935598546554144131956495470247246 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54982185358569035653082539241067710080224759935598546554144131956495470247246 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/69.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 95821001543154884675384638950231986836608112613479209408206325276618006749382 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/70.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2692767942 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_init_fail.2692767942' seed=95821001543154884675384638950231986836608112613479209408206325276618006749382 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95821001543154884675384638950231986836608112613479209408206325276618006749382 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/70.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 82051583177272343343514271505289432315108214780772427657109048785599367365982 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/70.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1235633502 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_parallel_lc_esc.1235633502' seed=82051583177272343343514271505289432315108214780772427657109048785599367365982 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82051583177272343343514271505289432315108214780772427657109048785599367365982 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/70.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 57921253237061046197309291704939946625743023526338167608767204867331082354147 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/70.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2799369699 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.otp_ctrl_stress_all_with_rand_reset.2799369699' seed=57921253237061046197309291704939946625743023526338167608767204867331082354147 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57921253237061046197309291704939946625743023526338167608767204867331082354147 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/70.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 93073469109586785695841955801277403072840832363996717259820003128165213543862 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/71.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1837768118 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_init_fail.1837768118' seed=93073469109586785695841955801277403072840832363996717259820003128165213543862 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93073469109586785695841955801277403072840832363996717259820003128165213543862 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/71.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 81843674624144573491615757704499323071945491176785835727229823605084002747989 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/71.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1392805461 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_parallel_lc_esc.1392805461' seed=81843674624144573491615757704499323071945491176785835727229823605084002747989 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81843674624144573491615757704499323071945491176785835727229823605084002747989 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/71.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 28528187263764499423239675164758820487772180911662400544952295234606466108276 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/71.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1135643508 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.otp_ctrl_stress_all_with_rand_reset.1135643508' seed=28528187263764499423239675164758820487772180911662400544952295234606466108276 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28528187263764499423239675164758820487772180911662400544952295234606466108276 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/71.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 21075306857700949252056885395251811790653887460345998243100592456597926721821 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/72.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=187840797 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_init_fail.187840797' seed=21075306857700949252056885395251811790653887460345998243100592456597926721821 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21075306857700949252056885395251811790653887460345998243100592456597926721821 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/72.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 20903890165500194436441998438831295493436130829660186090974320173053136410935 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/72.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2274433335 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_parallel_lc_esc.2274433335' seed=20903890165500194436441998438831295493436130829660186090974320173053136410935 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20903890165500194436441998438831295493436130829660186090974320173053136410935 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/72.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 56416223243982797191985316809898646628632564552074531800113222414096859828000 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/72.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4001533728 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.otp_ctrl_stress_all_with_rand_reset.4001533728' seed=56416223243982797191985316809898646628632564552074531800113222414096859828000 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56416223243982797191985316809898646628632564552074531800113222414096859828000 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/72.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 72232126071240672572988723296644300306712013182052882914138810587326939368327 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/73.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1993313159 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_init_fail.1993313159' seed=72232126071240672572988723296644300306712013182052882914138810587326939368327 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72232126071240672572988723296644300306712013182052882914138810587326939368327 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/73.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 72297518570084873749519233693970724736565620922185731964245094083284113540379 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/73.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=18335003 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_parallel_lc_esc.18335003' seed=72297518570084873749519233693970724736565620922185731964245094083284113540379 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72297518570084873749519233693970724736565620922185731964245094083284113540379 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/73.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 2586305194726005115104036809810783706456811192557624420314650416647313234700 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/73.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1782782732 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.otp_ctrl_stress_all_with_rand_reset.1782782732' seed=2586305194726005115104036809810783706456811192557624420314650416647313234700 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2586305194726005115104036809810783706456811192557624420314650416647313234700 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/73.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 93151417856241814700267845408299699306377033841800137449847149804046096487650 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/74.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=754668770 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_init_fail.754668770' seed=93151417856241814700267845408299699306377033841800137449847149804046096487650 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93151417856241814700267845408299699306377033841800137449847149804046096487650 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/74.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 95268077589988753636994027495821101618164681624701981499813740559094714958318 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/74.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1998553582 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_parallel_lc_esc.1998553582' seed=95268077589988753636994027495821101618164681624701981499813740559094714958318 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95268077589988753636994027495821101618164681624701981499813740559094714958318 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/74.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 66761085822222369517187774072299774802613663576881665654488892879355543206473 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/74.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2194586185 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.otp_ctrl_stress_all_with_rand_reset.2194586185' seed=66761085822222369517187774072299774802613663576881665654488892879355543206473 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66761085822222369517187774072299774802613663576881665654488892879355543206473 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/74.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 24268235713859295775523080095981198634089931547762204046053026345462961471648 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/75.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1572274336 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_init_fail.1572274336' seed=24268235713859295775523080095981198634089931547762204046053026345462961471648 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24268235713859295775523080095981198634089931547762204046053026345462961471648 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/75.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 64203282024404918157540898987942245560538179534479058111526940582624118873852 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/75.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1364893436 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_parallel_lc_esc.1364893436' seed=64203282024404918157540898987942245560538179534479058111526940582624118873852 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64203282024404918157540898987942245560538179534479058111526940582624118873852 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/75.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 11604548930970486191606212629016782139249159518462444260478126738984569937503 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/75.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1840520799 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.otp_ctrl_stress_all_with_rand_reset.1840520799' seed=11604548930970486191606212629016782139249159518462444260478126738984569937503 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11604548930970486191606212629016782139249159518462444260478126738984569937503 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/75.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 15477124078322444796914482447060955954610061959849116579079179653274314028365 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/76.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3321181517 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_init_fail.3321181517' seed=15477124078322444796914482447060955954610061959849116579079179653274314028365 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15477124078322444796914482447060955954610061959849116579079179653274314028365 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/76.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 3399557582932925899453137290703252071645923515854073144478978014903905316587 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/76.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4094193387 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_parallel_lc_esc.4094193387' seed=3399557582932925899453137290703252071645923515854073144478978014903905316587 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3399557582932925899453137290703252071645923515854073144478978014903905316587 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/76.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 69985400420933826035555534722325333036152720500473678953016061991474872853260 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/76.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1153835788 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.otp_ctrl_stress_all_with_rand_reset.1153835788' seed=69985400420933826035555534722325333036152720500473678953016061991474872853260 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69985400420933826035555534722325333036152720500473678953016061991474872853260 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/76.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 108957245027126574113058630338530353910632532323965511573947581590054564614213 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/77.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3913633861 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_init_fail.3913633861' seed=108957245027126574113058630338530353910632532323965511573947581590054564614213 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108957245027126574113058630338530353910632532323965511573947581590054564614213 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/77.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 8843734941191072317935418656469845781250660264803407946887131188678853837113 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/77.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3747529017 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_parallel_lc_esc.3747529017' seed=8843734941191072317935418656469845781250660264803407946887131188678853837113 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8843734941191072317935418656469845781250660264803407946887131188678853837113 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/77.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 72950254880615812857807554451157161291798764519954511203515673927101291855059 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/77.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3138288851 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.otp_ctrl_stress_all_with_rand_reset.3138288851' seed=72950254880615812857807554451157161291798764519954511203515673927101291855059 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72950254880615812857807554451157161291798764519954511203515673927101291855059 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/77.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 58812679842282682004486411478685261996221404430920847527816318971872648630159 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/78.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=867176335 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_init_fail.867176335' seed=58812679842282682004486411478685261996221404430920847527816318971872648630159 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58812679842282682004486411478685261996221404430920847527816318971872648630159 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/78.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 49473640485183573448481495331152790570859855976844787470170058026321925851721 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/78.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2536196681 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_parallel_lc_esc.2536196681' seed=49473640485183573448481495331152790570859855976844787470170058026321925851721 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49473640485183573448481495331152790570859855976844787470170058026321925851721 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/78.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 11650116820320338144217505961034805282174834574084002498016974167452415139783 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/78.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1685299143 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.otp_ctrl_stress_all_with_rand_reset.1685299143' seed=11650116820320338144217505961034805282174834574084002498016974167452415139783 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11650116820320338144217505961034805282174834574084002498016974167452415139783 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/78.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 17380783483600406573791265018381839700757847109005618163965946863313595446605 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/79.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4018713933 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_init_fail.4018713933' seed=17380783483600406573791265018381839700757847109005618163965946863313595446605 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17380783483600406573791265018381839700757847109005618163965946863313595446605 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/79.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 114585303621484629699040551796506350693145193914406910523128199494393130646319 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/79.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=907803439 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_parallel_lc_esc.907803439' seed=114585303621484629699040551796506350693145193914406910523128199494393130646319 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114585303621484629699040551796506350693145193914406910523128199494393130646319 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/79.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 63462968957443389721599196083635975548240809938091570941898976630598909176738 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/79.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3853134754 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.otp_ctrl_stress_all_with_rand_reset.3853134754' seed=63462968957443389721599196083635975548240809938091570941898976630598909176738 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63462968957443389721599196083635975548240809938091570941898976630598909176738 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/79.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 67022225794133268825933363181214128322970766082935838742203427194530342955105 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/80.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1428220001 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_init_fail.1428220001' seed=67022225794133268825933363181214128322970766082935838742203427194530342955105 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67022225794133268825933363181214128322970766082935838742203427194530342955105 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/80.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 111025019245318833675260749132975273312708371191806579662934368798114205770098 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/80.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=178889074 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_parallel_lc_esc.178889074' seed=111025019245318833675260749132975273312708371191806579662934368798114205770098 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111025019245318833675260749132975273312708371191806579662934368798114205770098 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/80.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 95393265285960028385377856869554944818869376871984732441226534345416069218834 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/80.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1276248594 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.otp_ctrl_stress_all_with_rand_reset.1276248594' seed=95393265285960028385377856869554944818869376871984732441226534345416069218834 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95393265285960028385377856869554944818869376871984732441226534345416069218834 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/80.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 26368275214735166390173023537095665590125417542305240683132875587970194578244 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/81.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3380452164 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_init_fail.3380452164' seed=26368275214735166390173023537095665590125417542305240683132875587970194578244 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26368275214735166390173023537095665590125417542305240683132875587970194578244 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/81.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 35377917059293491851843495040077039407429369295066228307269632182128148949763 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/81.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2678008579 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_parallel_lc_esc.2678008579' seed=35377917059293491851843495040077039407429369295066228307269632182128148949763 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35377917059293491851843495040077039407429369295066228307269632182128148949763 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/81.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 65838779614703705320575630735786159611979574524618925340431666398677931156914 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/81.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1740400050 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.otp_ctrl_stress_all_with_rand_reset.1740400050' seed=65838779614703705320575630735786159611979574524618925340431666398677931156914 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65838779614703705320575630735786159611979574524618925340431666398677931156914 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/81.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 106701094204875778701079457309429570624877125293470471908182704591743614679521 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/82.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=896236001 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_init_fail.896236001' seed=106701094204875778701079457309429570624877125293470471908182704591743614679521 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106701094204875778701079457309429570624877125293470471908182704591743614679521 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/82.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 103725578145043253414442715759327462404242730407466345624360864831966165606050 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/82.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1767120546 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_parallel_lc_esc.1767120546' seed=103725578145043253414442715759327462404242730407466345624360864831966165606050 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103725578145043253414442715759327462404242730407466345624360864831966165606050 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/82.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 14801514745522544873936383688893691920919593003001370672906988253770857907529 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/82.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3050636617 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.otp_ctrl_stress_all_with_rand_reset.3050636617' seed=14801514745522544873936383688893691920919593003001370672906988253770857907529 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=14801514745522544873936383688893691920919593003001370672906988253770857907529 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/82.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 69027296248739011677562503310721757405835544380728282561904304589784886579582 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/83.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3122696574 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_init_fail.3122696574' seed=69027296248739011677562503310721757405835544380728282561904304589784886579582 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69027296248739011677562503310721757405835544380728282561904304589784886579582 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/83.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 37554516253785643512246089436504893106529042977756013107063618141204952877337 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/83.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1773898009 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_parallel_lc_esc.1773898009' seed=37554516253785643512246089436504893106529042977756013107063618141204952877337 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37554516253785643512246089436504893106529042977756013107063618141204952877337 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/83.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 17659063969080707066152925946488594382476656907987708816828974733424920615269 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/83.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=948427109 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.otp_ctrl_stress_all_with_rand_reset.948427109' seed=17659063969080707066152925946488594382476656907987708816828974733424920615269 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17659063969080707066152925946488594382476656907987708816828974733424920615269 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/83.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 34034142600957081179819600337148018098437459826735664521442808773795757581145 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/84.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3054396249 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_init_fail.3054396249' seed=34034142600957081179819600337148018098437459826735664521442808773795757581145 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34034142600957081179819600337148018098437459826735664521442808773795757581145 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/84.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 36071017663558568668714447556238703992424626674459772290472482545827224149913 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/84.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1495981977 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_parallel_lc_esc.1495981977' seed=36071017663558568668714447556238703992424626674459772290472482545827224149913 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36071017663558568668714447556238703992424626674459772290472482545827224149913 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/84.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 104919630526596857984408423061618039290740006159803793681770036972487382668504 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/84.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3964671192 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.otp_ctrl_stress_all_with_rand_reset.3964671192' seed=104919630526596857984408423061618039290740006159803793681770036972487382668504 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104919630526596857984408423061618039290740006159803793681770036972487382668504 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/84.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 61713031976619259870020797094830757064042274307073746786141583839844667566568 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/85.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2658478568 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_init_fail.2658478568' seed=61713031976619259870020797094830757064042274307073746786141583839844667566568 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61713031976619259870020797094830757064042274307073746786141583839844667566568 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/85.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 109881567505987937609649253441744064839669973165878511977584526443852698604409 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/85.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3725185913 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_parallel_lc_esc.3725185913' seed=109881567505987937609649253441744064839669973165878511977584526443852698604409 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109881567505987937609649253441744064839669973165878511977584526443852698604409 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/85.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 8556675498142245209380527784023943815491215543272061098561892486259918683088 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/85.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=29539280 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.otp_ctrl_stress_all_with_rand_reset.29539280' seed=8556675498142245209380527784023943815491215543272061098561892486259918683088 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8556675498142245209380527784023943815491215543272061098561892486259918683088 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/85.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 8319275806550740024083415209173367920424968139858993615651684724717778003233 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/86.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=314729761 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_init_fail.314729761' seed=8319275806550740024083415209173367920424968139858993615651684724717778003233 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8319275806550740024083415209173367920424968139858993615651684724717778003233 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/86.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 97971534137889124089669436427186156461333839865121195767803403803599661046106 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/86.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2682132826 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_parallel_lc_esc.2682132826' seed=97971534137889124089669436427186156461333839865121195767803403803599661046106 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97971534137889124089669436427186156461333839865121195767803403803599661046106 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/86.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 11777419408002877866263968531490667043991486607375408302753460063527608536060 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/86.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1864125436 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.otp_ctrl_stress_all_with_rand_reset.1864125436' seed=11777419408002877866263968531490667043991486607375408302753460063527608536060 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11777419408002877866263968531490667043991486607375408302753460063527608536060 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/86.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 67750362819121843069988209412055421516684223847951513168198547466931513277549 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/87.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3564584045 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_init_fail.3564584045' seed=67750362819121843069988209412055421516684223847951513168198547466931513277549 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67750362819121843069988209412055421516684223847951513168198547466931513277549 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/87.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 100115816516516285010532556396381882013679126931777368496139049488640360142246 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/87.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2388743590 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_parallel_lc_esc.2388743590' seed=100115816516516285010532556396381882013679126931777368496139049488640360142246 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100115816516516285010532556396381882013679126931777368496139049488640360142246 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/87.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 48232838514699774320318648802461085391032348517778370471267213571681727093885 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/87.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1327045757 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.otp_ctrl_stress_all_with_rand_reset.1327045757' seed=48232838514699774320318648802461085391032348517778370471267213571681727093885 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48232838514699774320318648802461085391032348517778370471267213571681727093885 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/87.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 94586083413479787694820521204007712606006265832588050193616735672341399466276 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/88.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3044143396 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_init_fail.3044143396' seed=94586083413479787694820521204007712606006265832588050193616735672341399466276 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94586083413479787694820521204007712606006265832588050193616735672341399466276 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/88.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 43930193346845319230561876158961122421429820614375963525234079369408721422269 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/88.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=258443197 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_parallel_lc_esc.258443197' seed=43930193346845319230561876158961122421429820614375963525234079369408721422269 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43930193346845319230561876158961122421429820614375963525234079369408721422269 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/88.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 99918888003419162286700167937578033682009880271639515835004321510793273234137 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/88.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1827754713 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.otp_ctrl_stress_all_with_rand_reset.1827754713' seed=99918888003419162286700167937578033682009880271639515835004321510793273234137 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99918888003419162286700167937578033682009880271639515835004321510793273234137 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/88.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 90003058815948524774158930462669638075439211492290595557282874493031518164173 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/89.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=796513485 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_init_fail.796513485' seed=90003058815948524774158930462669638075439211492290595557282874493031518164173 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90003058815948524774158930462669638075439211492290595557282874493031518164173 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/89.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 19734525272080150425919232296878345345704262016938691114598496317891951325000 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/89.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=122023752 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_parallel_lc_esc.122023752' seed=19734525272080150425919232296878345345704262016938691114598496317891951325000 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19734525272080150425919232296878345345704262016938691114598496317891951325000 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/89.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 24649762693759714499943495735310312782565139892637487620462546955038713393194 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/89.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2274832426 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.otp_ctrl_stress_all_with_rand_reset.2274832426' seed=24649762693759714499943495735310312782565139892637487620462546955038713393194 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24649762693759714499943495735310312782565139892637487620462546955038713393194 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/89.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 17777688005931441126227362039781449319255988686903050646862669508973998998225 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/90.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=228426449 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_init_fail.228426449' seed=17777688005931441126227362039781449319255988686903050646862669508973998998225 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17777688005931441126227362039781449319255988686903050646862669508973998998225 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/90.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 50198535946945726643652707725617705241086786280352690271872792197727715814168 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/90.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2724162328 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_parallel_lc_esc.2724162328' seed=50198535946945726643652707725617705241086786280352690271872792197727715814168 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50198535946945726643652707725617705241086786280352690271872792197727715814168 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/90.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 64346091886084884270107148575373943062904576786137087199869826849573055756050 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/90.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4034918162 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.otp_ctrl_stress_all_with_rand_reset.4034918162' seed=64346091886084884270107148575373943062904576786137087199869826849573055756050 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64346091886084884270107148575373943062904576786137087199869826849573055756050 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/90.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 50549325553875757563119739466693561735691699836277236685068962925190034867486 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/91.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1711129886 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_init_fail.1711129886' seed=50549325553875757563119739466693561735691699836277236685068962925190034867486 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50549325553875757563119739466693561735691699836277236685068962925190034867486 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/91.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 104369431785875191325930793769256250800476083057985041086144214029382225564671 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/91.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1980568575 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_parallel_lc_esc.1980568575' seed=104369431785875191325930793769256250800476083057985041086144214029382225564671 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104369431785875191325930793769256250800476083057985041086144214029382225564671 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/91.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 11599740041466147837334851486154905754344750661294791490179438418529134187918 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/91.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2754221454 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.otp_ctrl_stress_all_with_rand_reset.2754221454' seed=11599740041466147837334851486154905754344750661294791490179438418529134187918 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11599740041466147837334851486154905754344750661294791490179438418529134187918 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/91.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 69854932377520379197640062056091255641314185428068154578313191410149708461824 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/92.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=608892672 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_init_fail.608892672' seed=69854932377520379197640062056091255641314185428068154578313191410149708461824 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69854932377520379197640062056091255641314185428068154578313191410149708461824 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/92.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 58182157306166836106905305226244011415958401290475688635817679108404359169217 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/92.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4208166081 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_parallel_lc_esc.4208166081' seed=58182157306166836106905305226244011415958401290475688635817679108404359169217 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58182157306166836106905305226244011415958401290475688635817679108404359169217 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/92.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 23348860186557584279966682292360410227486850871224672697640786789704133341336 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/92.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=929919128 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.otp_ctrl_stress_all_with_rand_reset.929919128' seed=23348860186557584279966682292360410227486850871224672697640786789704133341336 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23348860186557584279966682292360410227486850871224672697640786789704133341336 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/92.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 100070650883882474266823857508921245384956410463648971154668336830367470716356 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/93.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2732066244 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_init_fail.2732066244' seed=100070650883882474266823857508921245384956410463648971154668336830367470716356 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100070650883882474266823857508921245384956410463648971154668336830367470716356 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/93.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 7993711983400865451569844854024656157299620901616686282242426732305039747104 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/93.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2799429664 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_parallel_lc_esc.2799429664' seed=7993711983400865451569844854024656157299620901616686282242426732305039747104 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7993711983400865451569844854024656157299620901616686282242426732305039747104 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/93.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 23236835070877694327495989526740598310681161114723623511229510036176677641336 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/93.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4065074296 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.otp_ctrl_stress_all_with_rand_reset.4065074296' seed=23236835070877694327495989526740598310681161114723623511229510036176677641336 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23236835070877694327495989526740598310681161114723623511229510036176677641336 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/93.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 9314852488289911106671166779049097987725263207327286311201184478420466258870 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/94.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=948032438 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_init_fail.948032438' seed=9314852488289911106671166779049097987725263207327286311201184478420466258870 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9314852488289911106671166779049097987725263207327286311201184478420466258870 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/94.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 101437012241966132735045965224654736049280838675976251309862691791806144315969 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/94.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4103733825 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_parallel_lc_esc.4103733825' seed=101437012241966132735045965224654736049280838675976251309862691791806144315969 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101437012241966132735045965224654736049280838675976251309862691791806144315969 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/94.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 49297211673487354732949119741316096954973462822499257574014627457394002534456 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/94.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2490277944 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.otp_ctrl_stress_all_with_rand_reset.2490277944' seed=49297211673487354732949119741316096954973462822499257574014627457394002534456 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49297211673487354732949119741316096954973462822499257574014627457394002534456 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/94.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 106637287239284960453711575227861841513336445482454905430069019677041276661565 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/95.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1463463741 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_init_fail.1463463741' seed=106637287239284960453711575227861841513336445482454905430069019677041276661565 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106637287239284960453711575227861841513336445482454905430069019677041276661565 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/95.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 50037534167715811757318438516023218950684531903238525902970125809489172820823 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/95.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2636968791 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_parallel_lc_esc.2636968791' seed=50037534167715811757318438516023218950684531903238525902970125809489172820823 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50037534167715811757318438516023218950684531903238525902970125809489172820823 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/95.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 57798935033482339395975947125345834960400013813451919459856255925221355177254 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/95.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3526378790 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.otp_ctrl_stress_all_with_rand_reset.3526378790' seed=57798935033482339395975947125345834960400013813451919459856255925221355177254 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57798935033482339395975947125345834960400013813451919459856255925221355177254 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/95.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 102141875384810696028706133631978878036281017152474859564940751742982374736516 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/96.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1502003844 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_init_fail.1502003844' seed=102141875384810696028706133631978878036281017152474859564940751742982374736516 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102141875384810696028706133631978878036281017152474859564940751742982374736516 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/96.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 12686064680554781686481917186791841816461172704482317326977625121403885317048 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/96.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1433922488 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_parallel_lc_esc.1433922488' seed=12686064680554781686481917186791841816461172704482317326977625121403885317048 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12686064680554781686481917186791841816461172704482317326977625121403885317048 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/96.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 106185480227599718204325695081720453757185342009830125701824667349822152398809 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/96.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=357586905 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.otp_ctrl_stress_all_with_rand_reset.357586905' seed=106185480227599718204325695081720453757185342009830125701824667349822152398809 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106185480227599718204325695081720453757185342009830125701824667349822152398809 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/96.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 35840852785465259989357339905285076885317732642950360737248897721505267208847 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/97.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3492696719 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_init_fail.3492696719' seed=35840852785465259989357339905285076885317732642950360737248897721505267208847 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35840852785465259989357339905285076885317732642950360737248897721505267208847 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/97.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 37171628196698689084025104863309248188390922255722964389127875420414968664174 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/97.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1460736110 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_parallel_lc_esc.1460736110' seed=37171628196698689084025104863309248188390922255722964389127875420414968664174 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37171628196698689084025104863309248188390922255722964389127875420414968664174 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/97.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 72331396843749316722027549219468338053065414481509931384344329466168548874984 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/97.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4282211048 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.otp_ctrl_stress_all_with_rand_reset.4282211048' seed=72331396843749316722027549219468338053065414481509931384344329466168548874984 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72331396843749316722027549219468338053065414481509931384344329466168548874984 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/97.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 88980166178328052659492429319120722068515756148939128127318564362301532968712 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/98.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3273037576 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_init_fail.3273037576' seed=88980166178328052659492429319120722068515756148939128127318564362301532968712 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88980166178328052659492429319120722068515756148939128127318564362301532968712 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/98.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 45411706929457202410574525447771433242041502808743407685332148727498428406858 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/98.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1190681674 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_parallel_lc_esc.1190681674' seed=45411706929457202410574525447771433242041502808743407685332148727498428406858 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45411706929457202410574525447771433242041502808743407685332148727498428406858 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/98.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 106067165027182455537182610877798541215157944742543265826743258916559655869774 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/98.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2705136974 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.otp_ctrl_stress_all_with_rand_reset.2705136974' seed=106067165027182455537182610877798541215157944742543265826743258916559655869774 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106067165027182455537182610877798541215157944742543265826743258916559655869774 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/98.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 6759509806345970233808250038334337407964615620564562030475894310879437177912 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/99.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4008363064 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_init_fail.4008363064' seed=6759509806345970233808250038334337407964615620564562030475894310879437177912 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6759509806345970233808250038334337407964615620564562030475894310879437177912 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/99.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 47084764193682893451439952246042533103227095638218535000618867376815653006226 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/99.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3855625106 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_parallel_lc_esc.3855625106' seed=47084764193682893451439952246042533103227095638218535000618867376815653006226 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47084764193682893451439952246042533103227095638218535000618867376815653006226 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/99.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_stress_all_with_rand_reset 73326938539862638981435881201103819857023930953013033005076299713363150323570 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/99.otp_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=otp_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=349388658 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.otp_ctrl_stress_all_with_rand_reset.349388658' seed=73326938539862638981435881201103819857023930953013033005076299713363150323570 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73326938539862638981435881201103819857023930953013033005076299713363150323570 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/99.otp_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 21223984817811844420399748084146052949974611299537875586001496930691720457620 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/100.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3265310100 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_init_fail.3265310100' seed=21223984817811844420399748084146052949974611299537875586001496930691720457620 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21223984817811844420399748084146052949974611299537875586001496930691720457620 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/100.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 84287074263910493773704389337829627088599934323138077686601174372190151183899 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/100.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=204410395 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 100.otp_ctrl_parallel_lc_esc.204410395' seed=84287074263910493773704389337829627088599934323138077686601174372190151183899 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84287074263910493773704389337829627088599934323138077686601174372190151183899 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/100.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 48413228993099885510558308834073709383909661250879466389964957898204898032418 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/101.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1637776162 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_init_fail.1637776162' seed=48413228993099885510558308834073709383909661250879466389964957898204898032418 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48413228993099885510558308834073709383909661250879466389964957898204898032418 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/101.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 65084015486512245995262982915625163260525762953658222481680034386237961107465 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/101.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=85293065 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 101.otp_ctrl_parallel_lc_esc.85293065' seed=65084015486512245995262982915625163260525762953658222481680034386237961107465 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65084015486512245995262982915625163260525762953658222481680034386237961107465 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/101.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 91582844707988201444196771193875480140084247523106613611600721977442573006164 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/102.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2812851540 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_init_fail.2812851540' seed=91582844707988201444196771193875480140084247523106613611600721977442573006164 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91582844707988201444196771193875480140084247523106613611600721977442573006164 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/102.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 97766140878588087700467244582308856573463717563565002034745459592537857051696 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/102.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=631753776 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 102.otp_ctrl_parallel_lc_esc.631753776' seed=97766140878588087700467244582308856573463717563565002034745459592537857051696 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97766140878588087700467244582308856573463717563565002034745459592537857051696 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/102.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 66401739124712376931625601228318530309059588732145895506007818865752209389874 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/103.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=170424626 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_init_fail.170424626' seed=66401739124712376931625601228318530309059588732145895506007818865752209389874 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66401739124712376931625601228318530309059588732145895506007818865752209389874 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/103.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 107469050785630911621176128420475772224256397593019495696686707265778876610126 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/103.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=531822158 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 103.otp_ctrl_parallel_lc_esc.531822158' seed=107469050785630911621176128420475772224256397593019495696686707265778876610126 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107469050785630911621176128420475772224256397593019495696686707265778876610126 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/103.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 112593166110719230125277891051869844267492393529382492109629451028516576840757 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/104.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3237366837 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_init_fail.3237366837' seed=112593166110719230125277891051869844267492393529382492109629451028516576840757 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112593166110719230125277891051869844267492393529382492109629451028516576840757 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/104.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 24828788086163434325103980407823467049113782701014052318240267550804222743731 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/104.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=294720691 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 104.otp_ctrl_parallel_lc_esc.294720691' seed=24828788086163434325103980407823467049113782701014052318240267550804222743731 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24828788086163434325103980407823467049113782701014052318240267550804222743731 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/104.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 5909026355280650746830631912786878634876102575286850114319037870458614673742 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/105.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2081517902 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_init_fail.2081517902' seed=5909026355280650746830631912786878634876102575286850114319037870458614673742 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5909026355280650746830631912786878634876102575286850114319037870458614673742 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/105.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 81614114446816557825940319112528254458061791342509838215455731869688735541605 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/105.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4228983141 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 105.otp_ctrl_parallel_lc_esc.4228983141' seed=81614114446816557825940319112528254458061791342509838215455731869688735541605 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81614114446816557825940319112528254458061791342509838215455731869688735541605 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/105.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 103260931687978459854590982777029574895136644526297801738693547492413107672760 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/106.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1148524216 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_init_fail.1148524216' seed=103260931687978459854590982777029574895136644526297801738693547492413107672760 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103260931687978459854590982777029574895136644526297801738693547492413107672760 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/106.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 12903130580286168354384824188479056951040054813577450765988829366777385357256 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/106.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=245403592 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 106.otp_ctrl_parallel_lc_esc.245403592' seed=12903130580286168354384824188479056951040054813577450765988829366777385357256 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12903130580286168354384824188479056951040054813577450765988829366777385357256 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/106.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 39273784523546693337601946963171329401528587014536941872441035798377523626167 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/107.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=18399415 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_init_fail.18399415' seed=39273784523546693337601946963171329401528587014536941872441035798377523626167 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39273784523546693337601946963171329401528587014536941872441035798377523626167 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/107.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 13020325713269679079063807328470836065525661199900120714630862616007782131668 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/107.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=63137748 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 107.otp_ctrl_parallel_lc_esc.63137748' seed=13020325713269679079063807328470836065525661199900120714630862616007782131668 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13020325713269679079063807328470836065525661199900120714630862616007782131668 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/107.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 3886456612955397624078345499527052183188978867921506210001729251773613769529 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/108.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3199632185 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_init_fail.3199632185' seed=3886456612955397624078345499527052183188978867921506210001729251773613769529 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3886456612955397624078345499527052183188978867921506210001729251773613769529 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/108.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 84092544391596781005010471373741233723333445308489349364201506459532665074132 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/108.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2543890900 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 108.otp_ctrl_parallel_lc_esc.2543890900' seed=84092544391596781005010471373741233723333445308489349364201506459532665074132 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84092544391596781005010471373741233723333445308489349364201506459532665074132 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/108.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 115091525895775750892044096144452138027834915276078496390676945039854819773948 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/109.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2028899836 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_init_fail.2028899836' seed=115091525895775750892044096144452138027834915276078496390676945039854819773948 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115091525895775750892044096144452138027834915276078496390676945039854819773948 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/109.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 75276143476201606853489467707616260218847059185813817631616609871811507084080 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/109.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3378993968 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 109.otp_ctrl_parallel_lc_esc.3378993968' seed=75276143476201606853489467707616260218847059185813817631616609871811507084080 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75276143476201606853489467707616260218847059185813817631616609871811507084080 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/109.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 5399415550306781433681497656439584980610926498671031027004148623839867762932 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/110.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2078865652 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_init_fail.2078865652' seed=5399415550306781433681497656439584980610926498671031027004148623839867762932 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5399415550306781433681497656439584980610926498671031027004148623839867762932 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/110.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 90726509124184487312432665339144588536851267305178935508464614936660574792528 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/110.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1051519824 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 110.otp_ctrl_parallel_lc_esc.1051519824' seed=90726509124184487312432665339144588536851267305178935508464614936660574792528 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90726509124184487312432665339144588536851267305178935508464614936660574792528 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/110.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 55355165255136411196724724337197309741010848737052289792145528458944532156587 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/111.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3806040235 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_init_fail.3806040235' seed=55355165255136411196724724337197309741010848737052289792145528458944532156587 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55355165255136411196724724337197309741010848737052289792145528458944532156587 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/111.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 12542316230906944065580008151739138232708535541871861869313137149527969258418 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/111.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1394367410 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 111.otp_ctrl_parallel_lc_esc.1394367410' seed=12542316230906944065580008151739138232708535541871861869313137149527969258418 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12542316230906944065580008151739138232708535541871861869313137149527969258418 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/111.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 11407713319096424637331767009500746135799083327690605726510947996260046382887 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/112.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3362694951 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_init_fail.3362694951' seed=11407713319096424637331767009500746135799083327690605726510947996260046382887 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11407713319096424637331767009500746135799083327690605726510947996260046382887 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/112.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 20738276649913193470579286510256999547932542159653640281251618673176211119329 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/112.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1489788129 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 112.otp_ctrl_parallel_lc_esc.1489788129' seed=20738276649913193470579286510256999547932542159653640281251618673176211119329 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20738276649913193470579286510256999547932542159653640281251618673176211119329 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/112.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 41186061078644877590603582824430379763069985659371299086020350326466684803646 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/113.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2595904062 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_init_fail.2595904062' seed=41186061078644877590603582824430379763069985659371299086020350326466684803646 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41186061078644877590603582824430379763069985659371299086020350326466684803646 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/113.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 5572599072623416624428990126158306546845189435513880503946354485214570325378 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/113.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3229590914 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 113.otp_ctrl_parallel_lc_esc.3229590914' seed=5572599072623416624428990126158306546845189435513880503946354485214570325378 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5572599072623416624428990126158306546845189435513880503946354485214570325378 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/113.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 18674543668030992917223817565748445342634098823669655242361639128740676168290 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/114.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2281892450 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_init_fail.2281892450' seed=18674543668030992917223817565748445342634098823669655242361639128740676168290 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18674543668030992917223817565748445342634098823669655242361639128740676168290 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/114.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 49250476238991846341519356236176213651077087678232216392702789017113563610337 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/114.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3907108065 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 114.otp_ctrl_parallel_lc_esc.3907108065' seed=49250476238991846341519356236176213651077087678232216392702789017113563610337 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49250476238991846341519356236176213651077087678232216392702789017113563610337 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/114.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 79645073867331092171056917307293190496467746775948893763670644601719305317709 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/115.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1348775245 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_init_fail.1348775245' seed=79645073867331092171056917307293190496467746775948893763670644601719305317709 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79645073867331092171056917307293190496467746775948893763670644601719305317709 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/115.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 42265787848450605324942481289071273444341609897284206906936501515478337120234 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/115.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3045386218 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 115.otp_ctrl_parallel_lc_esc.3045386218' seed=42265787848450605324942481289071273444341609897284206906936501515478337120234 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42265787848450605324942481289071273444341609897284206906936501515478337120234 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/115.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 107774793997589204939158151143382909886399466181598650234360924681243326495898 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/116.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3956358298 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_init_fail.3956358298' seed=107774793997589204939158151143382909886399466181598650234360924681243326495898 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107774793997589204939158151143382909886399466181598650234360924681243326495898 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/116.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 53729015118485309498258427456167655749567832879215094971375267942354559768249 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/116.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=841815737 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 116.otp_ctrl_parallel_lc_esc.841815737' seed=53729015118485309498258427456167655749567832879215094971375267942354559768249 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53729015118485309498258427456167655749567832879215094971375267942354559768249 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/116.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 64566471464545372498371598141983342809803269001203794040492141990573808508946 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/117.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3229573138 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_init_fail.3229573138' seed=64566471464545372498371598141983342809803269001203794040492141990573808508946 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64566471464545372498371598141983342809803269001203794040492141990573808508946 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/117.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 91264551491126849248672934267940660356692284292347302418054927965408797977361 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/117.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2711153425 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 117.otp_ctrl_parallel_lc_esc.2711153425' seed=91264551491126849248672934267940660356692284292347302418054927965408797977361 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91264551491126849248672934267940660356692284292347302418054927965408797977361 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/117.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 26025793502077823388736319633104687860106335434299359316219672961232721718939 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/118.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=923315867 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_init_fail.923315867' seed=26025793502077823388736319633104687860106335434299359316219672961232721718939 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26025793502077823388736319633104687860106335434299359316219672961232721718939 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/118.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 5412542818580298831842477107573030359382644999677321281843910706770769884690 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/118.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1530148370 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 118.otp_ctrl_parallel_lc_esc.1530148370' seed=5412542818580298831842477107573030359382644999677321281843910706770769884690 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5412542818580298831842477107573030359382644999677321281843910706770769884690 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/118.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 72962197626583724019121954653939105450277389795841895743418008170483253475144 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/119.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=446658376 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_init_fail.446658376' seed=72962197626583724019121954653939105450277389795841895743418008170483253475144 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72962197626583724019121954653939105450277389795841895743418008170483253475144 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/119.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 36677576382239280539434380983486049824356887957449408339440797137647092206197 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/119.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3049622133 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 119.otp_ctrl_parallel_lc_esc.3049622133' seed=36677576382239280539434380983486049824356887957449408339440797137647092206197 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36677576382239280539434380983486049824356887957449408339440797137647092206197 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/119.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 87660293410618462449246964300743047393318699828423827438968047536086860748594 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/120.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4265137970 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_init_fail.4265137970' seed=87660293410618462449246964300743047393318699828423827438968047536086860748594 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87660293410618462449246964300743047393318699828423827438968047536086860748594 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/120.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 51081986148761145987477942739099170776619427052547535455480752081799806814946 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/120.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1080396514 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 120.otp_ctrl_parallel_lc_esc.1080396514' seed=51081986148761145987477942739099170776619427052547535455480752081799806814946 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51081986148761145987477942739099170776619427052547535455480752081799806814946 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/120.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 64043456033736750003013734567863613850933432946122185983426974116022869112679 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/121.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1726560103 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_init_fail.1726560103' seed=64043456033736750003013734567863613850933432946122185983426974116022869112679 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64043456033736750003013734567863613850933432946122185983426974116022869112679 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/121.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 47579963630807782077852777250755976505618266008796675978992815774511289684588 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/121.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2415743596 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 121.otp_ctrl_parallel_lc_esc.2415743596' seed=47579963630807782077852777250755976505618266008796675978992815774511289684588 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47579963630807782077852777250755976505618266008796675978992815774511289684588 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/121.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 23198688419964487975274432662637745297687814394117081949043385342980079523623 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/122.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4064319271 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_init_fail.4064319271' seed=23198688419964487975274432662637745297687814394117081949043385342980079523623 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23198688419964487975274432662637745297687814394117081949043385342980079523623 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/122.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 21211618225204288294132105204639245143562273922294837610834244332718861827714 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/122.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1422638722 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 122.otp_ctrl_parallel_lc_esc.1422638722' seed=21211618225204288294132105204639245143562273922294837610834244332718861827714 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21211618225204288294132105204639245143562273922294837610834244332718861827714 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/122.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 95003087297324563498751867844700382047420067689804238912623423498151644951848 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/123.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1076950312 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_init_fail.1076950312' seed=95003087297324563498751867844700382047420067689804238912623423498151644951848 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95003087297324563498751867844700382047420067689804238912623423498151644951848 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/123.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 46813049198134544759363183866089172316274461433381864388522211627315095340951 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/123.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2708408215 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 123.otp_ctrl_parallel_lc_esc.2708408215' seed=46813049198134544759363183866089172316274461433381864388522211627315095340951 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46813049198134544759363183866089172316274461433381864388522211627315095340951 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/123.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 68543725283840710176030576821198330478939101101847616598923252257345405164397 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/124.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3894909805 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_init_fail.3894909805' seed=68543725283840710176030576821198330478939101101847616598923252257345405164397 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68543725283840710176030576821198330478939101101847616598923252257345405164397 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/124.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 36210547299003995570444419351366785742877304503552268088317898943414576418718 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/124.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=752160670 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 124.otp_ctrl_parallel_lc_esc.752160670' seed=36210547299003995570444419351366785742877304503552268088317898943414576418718 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36210547299003995570444419351366785742877304503552268088317898943414576418718 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/124.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 30712717095506126196110201784081540567509764290616749890158720637676601083555 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/125.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=713688739 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_init_fail.713688739' seed=30712717095506126196110201784081540567509764290616749890158720637676601083555 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30712717095506126196110201784081540567509764290616749890158720637676601083555 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/125.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 34564151523837543503300722788532201019490197744134060199290021424822528754912 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/125.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=299615456 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 125.otp_ctrl_parallel_lc_esc.299615456' seed=34564151523837543503300722788532201019490197744134060199290021424822528754912 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34564151523837543503300722788532201019490197744134060199290021424822528754912 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/125.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 43825294469845928156301412509296686025315806044259223697580487908153835182775 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/126.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3616332471 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_init_fail.3616332471' seed=43825294469845928156301412509296686025315806044259223697580487908153835182775 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43825294469845928156301412509296686025315806044259223697580487908153835182775 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/126.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 22009097322020524974956381406296853855688994322472054755209039979332047545541 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/126.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=227615941 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 126.otp_ctrl_parallel_lc_esc.227615941' seed=22009097322020524974956381406296853855688994322472054755209039979332047545541 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22009097322020524974956381406296853855688994322472054755209039979332047545541 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/126.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 13688260463342248662628148244201462458976603676365889255350252682591284593618 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/127.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3683222482 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_init_fail.3683222482' seed=13688260463342248662628148244201462458976603676365889255350252682591284593618 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13688260463342248662628148244201462458976603676365889255350252682591284593618 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/127.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 59134100050440937902007608492615145615656322410530612956738809117989422305851 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/127.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3836547643 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 127.otp_ctrl_parallel_lc_esc.3836547643' seed=59134100050440937902007608492615145615656322410530612956738809117989422305851 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=59134100050440937902007608492615145615656322410530612956738809117989422305851 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/127.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 11271472583057824971430350593095059007723195414404151264579219757172003843090 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/128.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2437819410 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_init_fail.2437819410' seed=11271472583057824971430350593095059007723195414404151264579219757172003843090 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11271472583057824971430350593095059007723195414404151264579219757172003843090 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/128.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 106377060370703825668913538930693063910110280867814196140523271587236607012815 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/128.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2286530511 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 128.otp_ctrl_parallel_lc_esc.2286530511' seed=106377060370703825668913538930693063910110280867814196140523271587236607012815 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106377060370703825668913538930693063910110280867814196140523271587236607012815 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/128.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 14229142889905573592294686299403633382986125955791627946626875041478098837583 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/129.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2056806479 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_init_fail.2056806479' seed=14229142889905573592294686299403633382986125955791627946626875041478098837583 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=14229142889905573592294686299403633382986125955791627946626875041478098837583 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/129.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 77742745582445557559068217722037309404067361152401656310337757280302003156649 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/129.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=212891305 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 129.otp_ctrl_parallel_lc_esc.212891305' seed=77742745582445557559068217722037309404067361152401656310337757280302003156649 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77742745582445557559068217722037309404067361152401656310337757280302003156649 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/129.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 19179742064859013178944168073819206421972687077205066543469950534028590388042 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/130.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=446763850 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_init_fail.446763850' seed=19179742064859013178944168073819206421972687077205066543469950534028590388042 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19179742064859013178944168073819206421972687077205066543469950534028590388042 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/130.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 47899678692285726781265185576758823435883448361204207172351683639934233328864 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/130.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1323023584 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 130.otp_ctrl_parallel_lc_esc.1323023584' seed=47899678692285726781265185576758823435883448361204207172351683639934233328864 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47899678692285726781265185576758823435883448361204207172351683639934233328864 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/130.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 14219907667947938575913031902013293201476800863144060245935961996802084825577 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/131.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=145746409 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_init_fail.145746409' seed=14219907667947938575913031902013293201476800863144060245935961996802084825577 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=14219907667947938575913031902013293201476800863144060245935961996802084825577 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/131.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 93727530985872837860614004784621738170875128147213989759714020831828806288494 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/131.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3394061422 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 131.otp_ctrl_parallel_lc_esc.3394061422' seed=93727530985872837860614004784621738170875128147213989759714020831828806288494 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93727530985872837860614004784621738170875128147213989759714020831828806288494 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/131.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 61991646169655461057201747565657082986852435213189272094182920733516352644961 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/132.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2530666337 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_init_fail.2530666337' seed=61991646169655461057201747565657082986852435213189272094182920733516352644961 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61991646169655461057201747565657082986852435213189272094182920733516352644961 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/132.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 67064106913570504978711018612502919299320082686742984404313034029282381115682 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/132.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2114826530 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 132.otp_ctrl_parallel_lc_esc.2114826530' seed=67064106913570504978711018612502919299320082686742984404313034029282381115682 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67064106913570504978711018612502919299320082686742984404313034029282381115682 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/132.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 75060172541152834644399073052805935172969709992781189003084287943740756026594 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/133.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2898224354 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_init_fail.2898224354' seed=75060172541152834644399073052805935172969709992781189003084287943740756026594 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75060172541152834644399073052805935172969709992781189003084287943740756026594 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/133.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 64106574499370140355143899955144493125490697639100942630124997563720485441807 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/133.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3767144719 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 133.otp_ctrl_parallel_lc_esc.3767144719' seed=64106574499370140355143899955144493125490697639100942630124997563720485441807 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64106574499370140355143899955144493125490697639100942630124997563720485441807 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/133.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 49744321173727665732577178607083875568478361927993975114771484659266460412078 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/134.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=317024430 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_init_fail.317024430' seed=49744321173727665732577178607083875568478361927993975114771484659266460412078 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49744321173727665732577178607083875568478361927993975114771484659266460412078 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/134.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 110620239488290287986162808888539019309663221620331679772428878271084129037662 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/134.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=112340318 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 134.otp_ctrl_parallel_lc_esc.112340318' seed=110620239488290287986162808888539019309663221620331679772428878271084129037662 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110620239488290287986162808888539019309663221620331679772428878271084129037662 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/134.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 110096628163162946627810249921880753321471445600670739292283025321401771687983 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/135.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=853344303 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_init_fail.853344303' seed=110096628163162946627810249921880753321471445600670739292283025321401771687983 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110096628163162946627810249921880753321471445600670739292283025321401771687983 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/135.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 35204353160856196361656872177422554910019946091122664702815297777230150185053 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/135.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1936273501 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 135.otp_ctrl_parallel_lc_esc.1936273501' seed=35204353160856196361656872177422554910019946091122664702815297777230150185053 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35204353160856196361656872177422554910019946091122664702815297777230150185053 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/135.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 60112478378361016104784605407873410914963057623570087142408335493267602187784 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/136.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3138823688 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_init_fail.3138823688' seed=60112478378361016104784605407873410914963057623570087142408335493267602187784 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60112478378361016104784605407873410914963057623570087142408335493267602187784 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/136.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 21118293327620105720235341990010147381304067689544628681646754445520757962417 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/136.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=86095537 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 136.otp_ctrl_parallel_lc_esc.86095537' seed=21118293327620105720235341990010147381304067689544628681646754445520757962417 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21118293327620105720235341990010147381304067689544628681646754445520757962417 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/136.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 80996384638465483032298506305471893213290764428306208241235665424157532320291 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/137.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1142518307 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_init_fail.1142518307' seed=80996384638465483032298506305471893213290764428306208241235665424157532320291 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80996384638465483032298506305471893213290764428306208241235665424157532320291 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/137.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 88705223671005725298614818019755865138153007669819483872729948162207494403670 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/137.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1189836374 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 137.otp_ctrl_parallel_lc_esc.1189836374' seed=88705223671005725298614818019755865138153007669819483872729948162207494403670 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88705223671005725298614818019755865138153007669819483872729948162207494403670 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/137.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 32831209662737963218479564873838895849296560849310344865810244870450521824805 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/138.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=6282789 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_init_fail.6282789' seed=32831209662737963218479564873838895849296560849310344865810244870450521824805 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32831209662737963218479564873838895849296560849310344865810244870450521824805 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/138.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 46682420530052664738276717753866702655104619641843576720435062825065884138514 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/138.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2414853138 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 138.otp_ctrl_parallel_lc_esc.2414853138' seed=46682420530052664738276717753866702655104619641843576720435062825065884138514 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46682420530052664738276717753866702655104619641843576720435062825065884138514 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/138.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 14264915797170819828604983348252867059913347600283869334367579718157312961497 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/139.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=513256409 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_init_fail.513256409' seed=14264915797170819828604983348252867059913347600283869334367579718157312961497 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=14264915797170819828604983348252867059913347600283869334367579718157312961497 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/139.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 6643557214873603237420138709975807598015282749489676713862336481990787409142 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/139.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3096126710 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 139.otp_ctrl_parallel_lc_esc.3096126710' seed=6643557214873603237420138709975807598015282749489676713862336481990787409142 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6643557214873603237420138709975807598015282749489676713862336481990787409142 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/139.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 44825569754704068424161908070837529847480980075259407730396354480660264583129 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/140.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2093023193 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_init_fail.2093023193' seed=44825569754704068424161908070837529847480980075259407730396354480660264583129 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44825569754704068424161908070837529847480980075259407730396354480660264583129 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/140.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 78937616409731925855879770245193856687076155737138091736362700277888312249044 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/140.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3276901076 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 140.otp_ctrl_parallel_lc_esc.3276901076' seed=78937616409731925855879770245193856687076155737138091736362700277888312249044 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78937616409731925855879770245193856687076155737138091736362700277888312249044 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/140.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 49068566326111352898379335942588762334819413685915215613821453825436792686913 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/141.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=635734337 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_init_fail.635734337' seed=49068566326111352898379335942588762334819413685915215613821453825436792686913 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49068566326111352898379335942588762334819413685915215613821453825436792686913 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/141.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 100308994066612849668778466232430747324351931334965447817341458727534340305033 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/141.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2967433353 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 141.otp_ctrl_parallel_lc_esc.2967433353' seed=100308994066612849668778466232430747324351931334965447817341458727534340305033 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100308994066612849668778466232430747324351931334965447817341458727534340305033 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/141.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 60216919942145473451108006106805918891321358451365474818861419216431063525992 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/142.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1914727016 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_init_fail.1914727016' seed=60216919942145473451108006106805918891321358451365474818861419216431063525992 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60216919942145473451108006106805918891321358451365474818861419216431063525992 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/142.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 78358477043534377634905914501385763206933735060466379447452066787567487697190 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/142.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1148469542 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 142.otp_ctrl_parallel_lc_esc.1148469542' seed=78358477043534377634905914501385763206933735060466379447452066787567487697190 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78358477043534377634905914501385763206933735060466379447452066787567487697190 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/142.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 90932134351923559024121053862848459674676210452035631818308551940142027138361 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/143.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3579733305 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_init_fail.3579733305' seed=90932134351923559024121053862848459674676210452035631818308551940142027138361 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90932134351923559024121053862848459674676210452035631818308551940142027138361 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/143.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 76662339006748571518093083661415387270050591403433360971373740225561079512293 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/143.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3009608933 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 143.otp_ctrl_parallel_lc_esc.3009608933' seed=76662339006748571518093083661415387270050591403433360971373740225561079512293 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76662339006748571518093083661415387270050591403433360971373740225561079512293 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/143.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 102252829964713837223444237216768562979414128023218019523575016726825585386535 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/144.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2662900775 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_init_fail.2662900775' seed=102252829964713837223444237216768562979414128023218019523575016726825585386535 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102252829964713837223444237216768562979414128023218019523575016726825585386535 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/144.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 47243919420129737346979066208065788090869807163460967685481259803532657663798 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/144.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3078070070 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 144.otp_ctrl_parallel_lc_esc.3078070070' seed=47243919420129737346979066208065788090869807163460967685481259803532657663798 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47243919420129737346979066208065788090869807163460967685481259803532657663798 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/144.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 69075171465305467635586469498203907520935096743915439730279346502494800935361 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/145.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=899774913 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_init_fail.899774913' seed=69075171465305467635586469498203907520935096743915439730279346502494800935361 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69075171465305467635586469498203907520935096743915439730279346502494800935361 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/145.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 112878338898134644536075980402447401778282770128539933823061036218102397051262 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/145.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3959726462 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 145.otp_ctrl_parallel_lc_esc.3959726462' seed=112878338898134644536075980402447401778282770128539933823061036218102397051262 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112878338898134644536075980402447401778282770128539933823061036218102397051262 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/145.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 84513640148322092348193123633888499040043608137743354409823823648999012229851 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/146.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2681660123 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_init_fail.2681660123' seed=84513640148322092348193123633888499040043608137743354409823823648999012229851 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84513640148322092348193123633888499040043608137743354409823823648999012229851 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/146.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 41178782065154947490202945822108705735058244782855725693334715558927616439410 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/146.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=151516274 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 146.otp_ctrl_parallel_lc_esc.151516274' seed=41178782065154947490202945822108705735058244782855725693334715558927616439410 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41178782065154947490202945822108705735058244782855725693334715558927616439410 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/146.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 8049327698877451736057962046970948946853151629625653602383268210847098391065 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/147.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1913702937 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_init_fail.1913702937' seed=8049327698877451736057962046970948946853151629625653602383268210847098391065 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8049327698877451736057962046970948946853151629625653602383268210847098391065 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/147.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 94678490266678098383950375665487553449803412993277456626960694016968632036643 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/147.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2913463587 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 147.otp_ctrl_parallel_lc_esc.2913463587' seed=94678490266678098383950375665487553449803412993277456626960694016968632036643 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94678490266678098383950375665487553449803412993277456626960694016968632036643 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/147.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 113919898103454414114995696610878353353660449603786699463906955058595984331050 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/148.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1469862186 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_init_fail.1469862186' seed=113919898103454414114995696610878353353660449603786699463906955058595984331050 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113919898103454414114995696610878353353660449603786699463906955058595984331050 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/148.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 109154348617664490322142796642373988272733951678371238183244028751921215377106 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/148.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1750535890 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 148.otp_ctrl_parallel_lc_esc.1750535890' seed=109154348617664490322142796642373988272733951678371238183244028751921215377106 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109154348617664490322142796642373988272733951678371238183244028751921215377106 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/148.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 56488209169172000004764952016484048876139838404820578127006600207678944647080 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/149.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=917313448 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_init_fail.917313448' seed=56488209169172000004764952016484048876139838404820578127006600207678944647080 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56488209169172000004764952016484048876139838404820578127006600207678944647080 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/149.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 91670754677606668803850348910753585236898209642586287738493849276173829815275 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/149.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1697135595 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 149.otp_ctrl_parallel_lc_esc.1697135595' seed=91670754677606668803850348910753585236898209642586287738493849276173829815275 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91670754677606668803850348910753585236898209642586287738493849276173829815275 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/149.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 105392638350092358388583145955036971667260890032784155467419937582388495916452 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/150.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=260185508 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_init_fail.260185508' seed=105392638350092358388583145955036971667260890032784155467419937582388495916452 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105392638350092358388583145955036971667260890032784155467419937582388495916452 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/150.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 71514518483519875681573264627469983915941622066428649907580369930104853236906 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/150.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4092595370 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 150.otp_ctrl_parallel_lc_esc.4092595370' seed=71514518483519875681573264627469983915941622066428649907580369930104853236906 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71514518483519875681573264627469983915941622066428649907580369930104853236906 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/150.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 75672185403098165861006965987822079112429120352092566090641424686176991126692 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/151.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2889295012 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_init_fail.2889295012' seed=75672185403098165861006965987822079112429120352092566090641424686176991126692 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75672185403098165861006965987822079112429120352092566090641424686176991126692 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/151.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 92178895214034107441914907204928476354314766251307599093203708240113786259315 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/151.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3646261107 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 151.otp_ctrl_parallel_lc_esc.3646261107' seed=92178895214034107441914907204928476354314766251307599093203708240113786259315 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92178895214034107441914907204928476354314766251307599093203708240113786259315 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/151.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 38136584693001984280493614084500654400576200277278061704245547691262914004738 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/152.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1011287810 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_init_fail.1011287810' seed=38136584693001984280493614084500654400576200277278061704245547691262914004738 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38136584693001984280493614084500654400576200277278061704245547691262914004738 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/152.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 35782243419649315994741835341101696692954517359509334340579377282414737251159 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/152.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3491126103 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 152.otp_ctrl_parallel_lc_esc.3491126103' seed=35782243419649315994741835341101696692954517359509334340579377282414737251159 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35782243419649315994741835341101696692954517359509334340579377282414737251159 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/152.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 108807728135927590746268107466440783114495634012085951174362787932483043107123 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/153.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1374593331 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_init_fail.1374593331' seed=108807728135927590746268107466440783114495634012085951174362787932483043107123 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108807728135927590746268107466440783114495634012085951174362787932483043107123 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/153.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 74305875535553726677926736572108100020804578339567559309130143403158037985522 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/153.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1970141426 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 153.otp_ctrl_parallel_lc_esc.1970141426' seed=74305875535553726677926736572108100020804578339567559309130143403158037985522 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74305875535553726677926736572108100020804578339567559309130143403158037985522 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/153.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 23372228858817917041650820430161034432638193185899146575727966448800364400069 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/154.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1873710533 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_init_fail.1873710533' seed=23372228858817917041650820430161034432638193185899146575727966448800364400069 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23372228858817917041650820430161034432638193185899146575727966448800364400069 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/154.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 112463647740972542918071247636336444066031562954718089911721296226563218019454 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/154.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=917050494 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 154.otp_ctrl_parallel_lc_esc.917050494' seed=112463647740972542918071247636336444066031562954718089911721296226563218019454 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112463647740972542918071247636336444066031562954718089911721296226563218019454 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/154.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 48039846701822953517011234358857423808801451555246441552769200497844178146327 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/155.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=31216663 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_init_fail.31216663' seed=48039846701822953517011234358857423808801451555246441552769200497844178146327 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48039846701822953517011234358857423808801451555246441552769200497844178146327 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/155.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 57926460249312739869461044284581500385547234251201388544975149188591533715986 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/155.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1355051538 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 155.otp_ctrl_parallel_lc_esc.1355051538' seed=57926460249312739869461044284581500385547234251201388544975149188591533715986 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57926460249312739869461044284581500385547234251201388544975149188591533715986 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/155.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 87445667014810752139658033903835842154167474020468119861599793044746070788196 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/156.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=245762148 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_init_fail.245762148' seed=87445667014810752139658033903835842154167474020468119861599793044746070788196 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87445667014810752139658033903835842154167474020468119861599793044746070788196 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/156.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 27634144713133305088539605446251817778585307253037144305013438002976008607306 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/156.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3896677962 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 156.otp_ctrl_parallel_lc_esc.3896677962' seed=27634144713133305088539605446251817778585307253037144305013438002976008607306 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27634144713133305088539605446251817778585307253037144305013438002976008607306 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/156.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 30645897172636829260660715224464442667766182970355117415647224874021426166556 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/157.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3865967388 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_init_fail.3865967388' seed=30645897172636829260660715224464442667766182970355117415647224874021426166556 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30645897172636829260660715224464442667766182970355117415647224874021426166556 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/157.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 12748258893469345016184958463569897569090584981770290060563067125307148478758 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/157.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=947005734 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 157.otp_ctrl_parallel_lc_esc.947005734' seed=12748258893469345016184958463569897569090584981770290060563067125307148478758 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12748258893469345016184958463569897569090584981770290060563067125307148478758 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/157.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 67619364263655676316777865578515532288064832115519630102012663375540075538942 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/158.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3578964478 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_init_fail.3578964478' seed=67619364263655676316777865578515532288064832115519630102012663375540075538942 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67619364263655676316777865578515532288064832115519630102012663375540075538942 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/158.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 31648527117382815458124110468016664192172267322179015663537351882689610325349 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/158.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4109966693 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 158.otp_ctrl_parallel_lc_esc.4109966693' seed=31648527117382815458124110468016664192172267322179015663537351882689610325349 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31648527117382815458124110468016664192172267322179015663537351882689610325349 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/158.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 45574956512139696100671818524023867167464944122719807263952819537463607892359 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/159.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4156103047 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_init_fail.4156103047' seed=45574956512139696100671818524023867167464944122719807263952819537463607892359 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45574956512139696100671818524023867167464944122719807263952819537463607892359 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/159.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 27087055985391766659775383399365779310242627222223776584017240492152945180917 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/159.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1580531957 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 159.otp_ctrl_parallel_lc_esc.1580531957' seed=27087055985391766659775383399365779310242627222223776584017240492152945180917 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27087055985391766659775383399365779310242627222223776584017240492152945180917 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/159.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 24897785267182579736454270797752865304958825832710171456816339763270147120922 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/160.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4153941786 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_init_fail.4153941786' seed=24897785267182579736454270797752865304958825832710171456816339763270147120922 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24897785267182579736454270797752865304958825832710171456816339763270147120922 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/160.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 8483353191972737140966843842260615269553038048668637796023973373540932131199 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/160.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1300371839 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 160.otp_ctrl_parallel_lc_esc.1300371839' seed=8483353191972737140966843842260615269553038048668637796023973373540932131199 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8483353191972737140966843842260615269553038048668637796023973373540932131199 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/160.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 105278289090865763832665195649576145260232974356692165230057353226280779000810 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/161.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2100177898 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_init_fail.2100177898' seed=105278289090865763832665195649576145260232974356692165230057353226280779000810 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105278289090865763832665195649576145260232974356692165230057353226280779000810 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/161.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 76088297700184117087867422800731806923833144708389016273153017180474055466724 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/161.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3767148260 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 161.otp_ctrl_parallel_lc_esc.3767148260' seed=76088297700184117087867422800731806923833144708389016273153017180474055466724 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76088297700184117087867422800731806923833144708389016273153017180474055466724 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/161.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 9905765061681882397080595124952906691095287016478842410196160587486973410445 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/162.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1664892045 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_init_fail.1664892045' seed=9905765061681882397080595124952906691095287016478842410196160587486973410445 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9905765061681882397080595124952906691095287016478842410196160587486973410445 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/162.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 61244741990898408353813079687122631562771027340998501233476992095174990448399 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/162.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2336179983 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 162.otp_ctrl_parallel_lc_esc.2336179983' seed=61244741990898408353813079687122631562771027340998501233476992095174990448399 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61244741990898408353813079687122631562771027340998501233476992095174990448399 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/162.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 39165948858351753906955263471239549528882190378877347893550374444136806306480 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/163.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=445207216 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_init_fail.445207216' seed=39165948858351753906955263471239549528882190378877347893550374444136806306480 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39165948858351753906955263471239549528882190378877347893550374444136806306480 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/163.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 50388568873160645677130798214418340544410676350835079828614611025546149719944 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/163.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2705944456 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 163.otp_ctrl_parallel_lc_esc.2705944456' seed=50388568873160645677130798214418340544410676350835079828614611025546149719944 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50388568873160645677130798214418340544410676350835079828614611025546149719944 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/163.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 81896592606688541118846577730492746456512683114209715324351700810377454507983 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/164.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=447829967 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_init_fail.447829967' seed=81896592606688541118846577730492746456512683114209715324351700810377454507983 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81896592606688541118846577730492746456512683114209715324351700810377454507983 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/164.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 35643789757562674540392474002419660190378833818626473389011201721506668608649 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/164.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4294311049 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 164.otp_ctrl_parallel_lc_esc.4294311049' seed=35643789757562674540392474002419660190378833818626473389011201721506668608649 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35643789757562674540392474002419660190378833818626473389011201721506668608649 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/164.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 15437920598671775053410065783599116935786985063387508471717409554250415880149 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/165.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=465450965 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_init_fail.465450965' seed=15437920598671775053410065783599116935786985063387508471717409554250415880149 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15437920598671775053410065783599116935786985063387508471717409554250415880149 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/165.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 63842995184849778205032293638435623641928726488727388168055663666211377829816 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/165.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=370595768 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 165.otp_ctrl_parallel_lc_esc.370595768' seed=63842995184849778205032293638435623641928726488727388168055663666211377829816 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63842995184849778205032293638435623641928726488727388168055663666211377829816 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/165.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 4509804160135775923624729842539009607153551277154608733615745366783877230018 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/166.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3451694530 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_init_fail.3451694530' seed=4509804160135775923624729842539009607153551277154608733615745366783877230018 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4509804160135775923624729842539009607153551277154608733615745366783877230018 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/166.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 113395985386892311627235411024017661920768956185858924895802848583918338431834 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/166.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2337528666 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 166.otp_ctrl_parallel_lc_esc.2337528666' seed=113395985386892311627235411024017661920768956185858924895802848583918338431834 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113395985386892311627235411024017661920768956185858924895802848583918338431834 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/166.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 75998042997003437720260284554458472047402458947985785456657644139168600219698 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/167.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2012799026 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_init_fail.2012799026' seed=75998042997003437720260284554458472047402458947985785456657644139168600219698 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75998042997003437720260284554458472047402458947985785456657644139168600219698 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/167.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 36923355329944057035275109935024785354821326942233617537067457297733141134136 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/167.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=172227384 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 167.otp_ctrl_parallel_lc_esc.172227384' seed=36923355329944057035275109935024785354821326942233617537067457297733141134136 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36923355329944057035275109935024785354821326942233617537067457297733141134136 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/167.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 54794059170466874586395810395768251810311471361047569090620028500651456162086 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/168.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1633249574 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_init_fail.1633249574' seed=54794059170466874586395810395768251810311471361047569090620028500651456162086 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54794059170466874586395810395768251810311471361047569090620028500651456162086 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/168.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 103842512253543838504488402205627015712549040086873223811756401122881090013687 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/168.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=366397943 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 168.otp_ctrl_parallel_lc_esc.366397943' seed=103842512253543838504488402205627015712549040086873223811756401122881090013687 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103842512253543838504488402205627015712549040086873223811756401122881090013687 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/168.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 64183307162446072776986439324589440460709295459351398285102068964995551616547 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/169.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4257373731 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_init_fail.4257373731' seed=64183307162446072776986439324589440460709295459351398285102068964995551616547 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64183307162446072776986439324589440460709295459351398285102068964995551616547 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/169.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 74919249151782746086236545284091066927661800482418402141277582205147127910109 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/169.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=71995101 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 169.otp_ctrl_parallel_lc_esc.71995101' seed=74919249151782746086236545284091066927661800482418402141277582205147127910109 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74919249151782746086236545284091066927661800482418402141277582205147127910109 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/169.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 63361758334068902641213031108591799572580435072862235796003800810676199349768 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/170.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1507843592 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_init_fail.1507843592' seed=63361758334068902641213031108591799572580435072862235796003800810676199349768 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63361758334068902641213031108591799572580435072862235796003800810676199349768 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/170.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 21375395836168361482841303023995696327415373329801867629048345760900978743611 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/170.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3975059771 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 170.otp_ctrl_parallel_lc_esc.3975059771' seed=21375395836168361482841303023995696327415373329801867629048345760900978743611 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21375395836168361482841303023995696327415373329801867629048345760900978743611 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/170.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 76829419574865137126580133338303993315885060548109389725420604969752452176039 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/171.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1660197031 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_init_fail.1660197031' seed=76829419574865137126580133338303993315885060548109389725420604969752452176039 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76829419574865137126580133338303993315885060548109389725420604969752452176039 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/171.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 58335430521799795476330354684438273328890517061075099977421129659940543911555 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/171.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3435910787 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 171.otp_ctrl_parallel_lc_esc.3435910787' seed=58335430521799795476330354684438273328890517061075099977421129659940543911555 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58335430521799795476330354684438273328890517061075099977421129659940543911555 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/171.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 67133865598564379457318829170147107448440432918367020334568099445066198441049 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/172.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1275878489 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_init_fail.1275878489' seed=67133865598564379457318829170147107448440432918367020334568099445066198441049 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67133865598564379457318829170147107448440432918367020334568099445066198441049 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/172.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 16176752394597731178673126803395799296487491703695655909106753919286636735975 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/172.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=433352167 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 172.otp_ctrl_parallel_lc_esc.433352167' seed=16176752394597731178673126803395799296487491703695655909106753919286636735975 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16176752394597731178673126803395799296487491703695655909106753919286636735975 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/172.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 29170657146376226128639989457826753271847223170587466238844611756715149634980 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/173.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=535047588 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_init_fail.535047588' seed=29170657146376226128639989457826753271847223170587466238844611756715149634980 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29170657146376226128639989457826753271847223170587466238844611756715149634980 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/173.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 77710630960283380703967670100503772638227665118490363568145164012575781498764 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/173.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=868953996 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 173.otp_ctrl_parallel_lc_esc.868953996' seed=77710630960283380703967670100503772638227665118490363568145164012575781498764 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77710630960283380703967670100503772638227665118490363568145164012575781498764 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/173.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 32001991004954088348745803002855942969576439456010660668163294047928673370959 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/174.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=565183311 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_init_fail.565183311' seed=32001991004954088348745803002855942969576439456010660668163294047928673370959 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32001991004954088348745803002855942969576439456010660668163294047928673370959 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/174.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 14299555766220922920948710967188052236836717638740526404282550370616704745855 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/174.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2519187839 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 174.otp_ctrl_parallel_lc_esc.2519187839' seed=14299555766220922920948710967188052236836717638740526404282550370616704745855 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=14299555766220922920948710967188052236836717638740526404282550370616704745855 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/174.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 50839031679861428804642376421458680131433579745260799673383703314361386112845 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/175.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2216007501 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_init_fail.2216007501' seed=50839031679861428804642376421458680131433579745260799673383703314361386112845 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50839031679861428804642376421458680131433579745260799673383703314361386112845 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/175.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 80751056734637271056015545899518058608918598677928725140805286763285548345437 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/175.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2880415837 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 175.otp_ctrl_parallel_lc_esc.2880415837' seed=80751056734637271056015545899518058608918598677928725140805286763285548345437 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80751056734637271056015545899518058608918598677928725140805286763285548345437 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/175.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 16187060271681768748089440025672527083132833569863408683791905676025933431984 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/176.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=708150448 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_init_fail.708150448' seed=16187060271681768748089440025672527083132833569863408683791905676025933431984 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16187060271681768748089440025672527083132833569863408683791905676025933431984 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/176.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 113688264587167511485477608374021327003592150591410341975946665822285784022589 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/176.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2476342845 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 176.otp_ctrl_parallel_lc_esc.2476342845' seed=113688264587167511485477608374021327003592150591410341975946665822285784022589 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113688264587167511485477608374021327003592150591410341975946665822285784022589 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/176.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 89469274385540450631137631703620072443412613558708836599936723342708802118906 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/177.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1258611962 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_init_fail.1258611962' seed=89469274385540450631137631703620072443412613558708836599936723342708802118906 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89469274385540450631137631703620072443412613558708836599936723342708802118906 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/177.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 21687085096805087723302553862947839239776770607838517203237272747373655031916 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/177.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1704263788 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 177.otp_ctrl_parallel_lc_esc.1704263788' seed=21687085096805087723302553862947839239776770607838517203237272747373655031916 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21687085096805087723302553862947839239776770607838517203237272747373655031916 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/177.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 35777237493572342456507368496481578437272629712359572408377889616310875600400 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/178.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2842048016 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_init_fail.2842048016' seed=35777237493572342456507368496481578437272629712359572408377889616310875600400 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35777237493572342456507368496481578437272629712359572408377889616310875600400 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/178.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 110864924498234631146154594042049773882409159974343985551971349655815708894312 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/178.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2225497192 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 178.otp_ctrl_parallel_lc_esc.2225497192' seed=110864924498234631146154594042049773882409159974343985551971349655815708894312 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110864924498234631146154594042049773882409159974343985551971349655815708894312 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/178.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 65747242952864562458053647231219502723149261029708376636051369047779179650480 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/179.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3180486064 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_init_fail.3180486064' seed=65747242952864562458053647231219502723149261029708376636051369047779179650480 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65747242952864562458053647231219502723149261029708376636051369047779179650480 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/179.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 1928572628986667829749289465708199192080652590475752960143342644749095979101 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/179.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3135293533 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 179.otp_ctrl_parallel_lc_esc.3135293533' seed=1928572628986667829749289465708199192080652590475752960143342644749095979101 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1928572628986667829749289465708199192080652590475752960143342644749095979101 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/179.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 68019035159202937042262917631342517272562750185363159504944213883373086578599 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/180.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=787486631 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_init_fail.787486631' seed=68019035159202937042262917631342517272562750185363159504944213883373086578599 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68019035159202937042262917631342517272562750185363159504944213883373086578599 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/180.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 104363915987269895874905775118156630563201370555986628154886732028390253906074 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/180.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3404581018 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 180.otp_ctrl_parallel_lc_esc.3404581018' seed=104363915987269895874905775118156630563201370555986628154886732028390253906074 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104363915987269895874905775118156630563201370555986628154886732028390253906074 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/180.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 10656664891088107983060223835537698237142721825442774389517119720948522047573 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/181.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1827166293 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_init_fail.1827166293' seed=10656664891088107983060223835537698237142721825442774389517119720948522047573 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10656664891088107983060223835537698237142721825442774389517119720948522047573 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/181.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 46316988462618501495233294893900143418152401680751129453578891386400071939191 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/181.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3754882167 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 181.otp_ctrl_parallel_lc_esc.3754882167' seed=46316988462618501495233294893900143418152401680751129453578891386400071939191 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46316988462618501495233294893900143418152401680751129453578891386400071939191 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/181.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 91287378392751620612773013991407745430424469601094409427857961582384926591643 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/182.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4151741083 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_init_fail.4151741083' seed=91287378392751620612773013991407745430424469601094409427857961582384926591643 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91287378392751620612773013991407745430424469601094409427857961582384926591643 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/182.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 23971994334139778833752488482279513710375766232477469885388389690560137408353 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/182.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2164272993 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 182.otp_ctrl_parallel_lc_esc.2164272993' seed=23971994334139778833752488482279513710375766232477469885388389690560137408353 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23971994334139778833752488482279513710375766232477469885388389690560137408353 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/182.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 93131492765299430947899973883800315887796653587804439493037468325049735915554 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/183.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=662775842 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_init_fail.662775842' seed=93131492765299430947899973883800315887796653587804439493037468325049735915554 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93131492765299430947899973883800315887796653587804439493037468325049735915554 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/183.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 9002082026696907669287530198529599175308895053515231694152107254486352940211 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/183.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1069698227 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 183.otp_ctrl_parallel_lc_esc.1069698227' seed=9002082026696907669287530198529599175308895053515231694152107254486352940211 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9002082026696907669287530198529599175308895053515231694152107254486352940211 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/183.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 13368537843158687103687012985996003835847688790394673086026146316615183134633 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/184.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1268936617 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_init_fail.1268936617' seed=13368537843158687103687012985996003835847688790394673086026146316615183134633 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13368537843158687103687012985996003835847688790394673086026146316615183134633 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/184.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 70624636714049412246501186294945506280051418020727491353232852508280626420251 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/184.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=51452443 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 184.otp_ctrl_parallel_lc_esc.51452443' seed=70624636714049412246501186294945506280051418020727491353232852508280626420251 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70624636714049412246501186294945506280051418020727491353232852508280626420251 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/184.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 87555931063399398349839428034545766948147728802562963119264336357531838955526 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/185.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=826916870 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_init_fail.826916870' seed=87555931063399398349839428034545766948147728802562963119264336357531838955526 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87555931063399398349839428034545766948147728802562963119264336357531838955526 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/185.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 3995568425979260280543236454913190390114140287991109553094023194898563299079 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/185.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3973019399 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 185.otp_ctrl_parallel_lc_esc.3973019399' seed=3995568425979260280543236454913190390114140287991109553094023194898563299079 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3995568425979260280543236454913190390114140287991109553094023194898563299079 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/185.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 51402086433974696976513068170539293418818665409097419289179203842353740906407 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/186.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1970536359 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_init_fail.1970536359' seed=51402086433974696976513068170539293418818665409097419289179203842353740906407 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51402086433974696976513068170539293418818665409097419289179203842353740906407 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/186.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 3476013408902705824013482639825884181344904611098198105672585009542452518186 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/186.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=473472298 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 186.otp_ctrl_parallel_lc_esc.473472298' seed=3476013408902705824013482639825884181344904611098198105672585009542452518186 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3476013408902705824013482639825884181344904611098198105672585009542452518186 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/186.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 57794955101026656849668526144339993431025826167544876866404426060736132688260 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/187.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1560160644 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_init_fail.1560160644' seed=57794955101026656849668526144339993431025826167544876866404426060736132688260 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57794955101026656849668526144339993431025826167544876866404426060736132688260 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/187.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 80428692119681766506764134328592443872427036977725519833834411452727220025928 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/187.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3107502664 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 187.otp_ctrl_parallel_lc_esc.3107502664' seed=80428692119681766506764134328592443872427036977725519833834411452727220025928 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80428692119681766506764134328592443872427036977725519833834411452727220025928 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/187.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 14336421077040149611846486003285676866259170123229497720903260087274947286738 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/188.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=244389586 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_init_fail.244389586' seed=14336421077040149611846486003285676866259170123229497720903260087274947286738 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=14336421077040149611846486003285676866259170123229497720903260087274947286738 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/188.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 95811912233665617602496046328594484227803187540468530299266755938078708596836 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/188.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3529900132 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 188.otp_ctrl_parallel_lc_esc.3529900132' seed=95811912233665617602496046328594484227803187540468530299266755938078708596836 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95811912233665617602496046328594484227803187540468530299266755938078708596836 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/188.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 40595069680942984850003005769566994386710766613969440065028055366546322178741 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/189.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2475246261 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_init_fail.2475246261' seed=40595069680942984850003005769566994386710766613969440065028055366546322178741 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40595069680942984850003005769566994386710766613969440065028055366546322178741 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/189.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 67211007864803500440806028704239406024418946765712136291703812749731214726901 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/189.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3486848757 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 189.otp_ctrl_parallel_lc_esc.3486848757' seed=67211007864803500440806028704239406024418946765712136291703812749731214726901 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67211007864803500440806028704239406024418946765712136291703812749731214726901 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/189.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 102360874577676022309085491091901145166641445690882642447453143885167526765354 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/190.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2855625514 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_init_fail.2855625514' seed=102360874577676022309085491091901145166641445690882642447453143885167526765354 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102360874577676022309085491091901145166641445690882642447453143885167526765354 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/190.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 95865496141262339587519887401815369846940329978826092383057182668129237393462 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/190.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1570693174 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 190.otp_ctrl_parallel_lc_esc.1570693174' seed=95865496141262339587519887401815369846940329978826092383057182668129237393462 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95865496141262339587519887401815369846940329978826092383057182668129237393462 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/190.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 28488419030107235576500759564015421730424778391083280261279996344474147152389 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/191.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2928861701 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_init_fail.2928861701' seed=28488419030107235576500759564015421730424778391083280261279996344474147152389 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28488419030107235576500759564015421730424778391083280261279996344474147152389 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/191.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 4709500463695014744663879406393049870530057563411499591240702373200333626629 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/191.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1036246277 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 191.otp_ctrl_parallel_lc_esc.1036246277' seed=4709500463695014744663879406393049870530057563411499591240702373200333626629 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4709500463695014744663879406393049870530057563411499591240702373200333626629 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/191.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 33606302939123626343820798826274862541510307047887655811110134194151171989671 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/192.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1348640935 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_init_fail.1348640935' seed=33606302939123626343820798826274862541510307047887655811110134194151171989671 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33606302939123626343820798826274862541510307047887655811110134194151171989671 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/192.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 68244405970295460961757158460632377138607857979020886708123837311322693266383 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/192.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1763142607 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 192.otp_ctrl_parallel_lc_esc.1763142607' seed=68244405970295460961757158460632377138607857979020886708123837311322693266383 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68244405970295460961757158460632377138607857979020886708123837311322693266383 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/192.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 56071064763966705782045550293128409947167589266602169677588793394363299270399 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/193.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3608153855 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_init_fail.3608153855' seed=56071064763966705782045550293128409947167589266602169677588793394363299270399 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56071064763966705782045550293128409947167589266602169677588793394363299270399 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/193.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 97293353199948116838291914345279752043397121309415081682323159085416261131401 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/193.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1872534665 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 193.otp_ctrl_parallel_lc_esc.1872534665' seed=97293353199948116838291914345279752043397121309415081682323159085416261131401 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97293353199948116838291914345279752043397121309415081682323159085416261131401 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/193.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 63958556200968712529609561251473400211957055614865210048694335330805105082444 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/194.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=832618572 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_init_fail.832618572' seed=63958556200968712529609561251473400211957055614865210048694335330805105082444 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63958556200968712529609561251473400211957055614865210048694335330805105082444 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/194.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 94995766924703415047628604828575259612383669926007382399669964562451774359316 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/194.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4284794644 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 194.otp_ctrl_parallel_lc_esc.4284794644' seed=94995766924703415047628604828575259612383669926007382399669964562451774359316 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94995766924703415047628604828575259612383669926007382399669964562451774359316 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/194.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 113212933627511566764904479614518921028149391445621490278140479212044120697228 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/195.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=743909772 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_init_fail.743909772' seed=113212933627511566764904479614518921028149391445621490278140479212044120697228 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113212933627511566764904479614518921028149391445621490278140479212044120697228 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/195.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 20393902585792806727307043056194970374292607229978224136909730771317038368130 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/195.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=791790978 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 195.otp_ctrl_parallel_lc_esc.791790978' seed=20393902585792806727307043056194970374292607229978224136909730771317038368130 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20393902585792806727307043056194970374292607229978224136909730771317038368130 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/195.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 72568582374307127748885383780357685198658558050442075821107220571342707984482 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/196.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3668543586 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_init_fail.3668543586' seed=72568582374307127748885383780357685198658558050442075821107220571342707984482 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72568582374307127748885383780357685198658558050442075821107220571342707984482 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/196.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 360654739947219849746663865273127659313130250075060528475114464294651335791 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/196.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1521783919 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 196.otp_ctrl_parallel_lc_esc.1521783919' seed=360654739947219849746663865273127659313130250075060528475114464294651335791 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=360654739947219849746663865273127659313130250075060528475114464294651335791 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/196.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 100539603898308093230627812369785386371144660152443483469880125386670787976505 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/197.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3250773305 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_init_fail.3250773305' seed=100539603898308093230627812369785386371144660152443483469880125386670787976505 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100539603898308093230627812369785386371144660152443483469880125386670787976505 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/197.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 19783343879018190981911282799031571188119670367177862414964175421874761298977 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/197.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2756375585 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 197.otp_ctrl_parallel_lc_esc.2756375585' seed=19783343879018190981911282799031571188119670367177862414964175421874761298977 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19783343879018190981911282799031571188119670367177862414964175421874761298977 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/197.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 61475585270561853010522109566775619076564429129932836391063962901020511134949 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/198.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1030317285 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_init_fail.1030317285' seed=61475585270561853010522109566775619076564429129932836391063962901020511134949 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61475585270561853010522109566775619076564429129932836391063962901020511134949 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/198.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 95512080451146558262249862363694792698820472104602890264860433546202751042326 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/198.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2745303830 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 198.otp_ctrl_parallel_lc_esc.2745303830' seed=95512080451146558262249862363694792698820472104602890264860433546202751042326 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95512080451146558262249862363694792698820472104602890264860433546202751042326 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/198.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 36164411485844629482209389100054193405105100589877322580409472558697841631249 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/199.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=597893137 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_init_fail.597893137' seed=36164411485844629482209389100054193405105100589877322580409472558697841631249 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36164411485844629482209389100054193405105100589877322580409472558697841631249 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/199.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_parallel_lc_esc 41388686415868733657563386741362713430087661667098674376968689564928265273311 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/199.otp_ctrl_parallel_lc_esc/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1978777567 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_parallel_lc_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 199.otp_ctrl_parallel_lc_esc.1978777567' seed=41388686415868733657563386741362713430087661667098674376968689564928265273311 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41388686415868733657563386741362713430087661667098674376968689564928265273311 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/199.otp_ctrl_parallel_lc_esc/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_parallel_lc_esc_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 49198492643567557880358145106256492442307139886712349234799062615610715856446 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/200.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=511237694 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 200.otp_ctrl_init_fail.511237694' seed=49198492643567557880358145106256492442307139886712349234799062615610715856446 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49198492643567557880358145106256492442307139886712349234799062615610715856446 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/200.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 70557168415346644016221365252407771132207901004690764529233691608864366494848 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/201.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=985105536 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 201.otp_ctrl_init_fail.985105536' seed=70557168415346644016221365252407771132207901004690764529233691608864366494848 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70557168415346644016221365252407771132207901004690764529233691608864366494848 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/201.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 43745626730555071710600633466583553764079631453101584460059278435911714924875 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/202.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=906422603 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 202.otp_ctrl_init_fail.906422603' seed=43745626730555071710600633466583553764079631453101584460059278435911714924875 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43745626730555071710600633466583553764079631453101584460059278435911714924875 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/202.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 17729083565400300668738318628930128831089054776085494946041100595883525784601 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/203.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2142225433 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 203.otp_ctrl_init_fail.2142225433' seed=17729083565400300668738318628930128831089054776085494946041100595883525784601 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17729083565400300668738318628930128831089054776085494946041100595883525784601 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/203.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 16232500570237774121726919803034554791804545369166053640683272405735453413318 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/204.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3846623174 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 204.otp_ctrl_init_fail.3846623174' seed=16232500570237774121726919803034554791804545369166053640683272405735453413318 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16232500570237774121726919803034554791804545369166053640683272405735453413318 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/204.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 97793937179873442278340062485757682284887711752536225690932036479867701554083 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/205.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3357404067 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 205.otp_ctrl_init_fail.3357404067' seed=97793937179873442278340062485757682284887711752536225690932036479867701554083 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97793937179873442278340062485757682284887711752536225690932036479867701554083 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/205.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 64110575097079964071697599101621206635138462410270807295550086754882254636742 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/206.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4119430854 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 206.otp_ctrl_init_fail.4119430854' seed=64110575097079964071697599101621206635138462410270807295550086754882254636742 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64110575097079964071697599101621206635138462410270807295550086754882254636742 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/206.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 64502063747996602320598803524552560305954463088968101787156970318252702958296 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/207.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2134901464 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 207.otp_ctrl_init_fail.2134901464' seed=64502063747996602320598803524552560305954463088968101787156970318252702958296 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64502063747996602320598803524552560305954463088968101787156970318252702958296 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/207.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 106825953334969355612005390466999219666106314761089964111500550770345027644766 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/208.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2464230750 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 208.otp_ctrl_init_fail.2464230750' seed=106825953334969355612005390466999219666106314761089964111500550770345027644766 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106825953334969355612005390466999219666106314761089964111500550770345027644766 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/208.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 20243873167062752021843468014375375419547090782625680208246358019030836207922 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/209.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2951373106 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 209.otp_ctrl_init_fail.2951373106' seed=20243873167062752021843468014375375419547090782625680208246358019030836207922 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20243873167062752021843468014375375419547090782625680208246358019030836207922 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/209.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 3380301337221335927976940664185686590863694923929014469521499932432648273883 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/210.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=257327067 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 210.otp_ctrl_init_fail.257327067' seed=3380301337221335927976940664185686590863694923929014469521499932432648273883 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3380301337221335927976940664185686590863694923929014469521499932432648273883 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/210.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 6940199183538052767290458299565374740009130736041735859213824214297507866714 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/211.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=366291034 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 211.otp_ctrl_init_fail.366291034' seed=6940199183538052767290458299565374740009130736041735859213824214297507866714 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6940199183538052767290458299565374740009130736041735859213824214297507866714 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/211.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 55938596033887495754263169607526156357845220701763000437672713945242020637456 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/212.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1633184528 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 212.otp_ctrl_init_fail.1633184528' seed=55938596033887495754263169607526156357845220701763000437672713945242020637456 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55938596033887495754263169607526156357845220701763000437672713945242020637456 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/212.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 25061643718159042019427043839080755519919841035464453655797167790056821876258 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/213.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3496601122 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 213.otp_ctrl_init_fail.3496601122' seed=25061643718159042019427043839080755519919841035464453655797167790056821876258 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25061643718159042019427043839080755519919841035464453655797167790056821876258 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/213.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 78495871544649667672727139832434934239194760743646372685147011680329310304677 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/214.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2347923877 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 214.otp_ctrl_init_fail.2347923877' seed=78495871544649667672727139832434934239194760743646372685147011680329310304677 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78495871544649667672727139832434934239194760743646372685147011680329310304677 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/214.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 106834000450784362742863449040176947717514120166308108695778508512302529627928 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/215.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1517930264 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 215.otp_ctrl_init_fail.1517930264' seed=106834000450784362742863449040176947717514120166308108695778508512302529627928 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106834000450784362742863449040176947717514120166308108695778508512302529627928 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/215.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 40580842427864691900329784556495305324788179858130871895702547877023797308456 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/216.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2225171496 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 216.otp_ctrl_init_fail.2225171496' seed=40580842427864691900329784556495305324788179858130871895702547877023797308456 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40580842427864691900329784556495305324788179858130871895702547877023797308456 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/216.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 32987663148745995478775554442991965790440033816306182332966542977789560708894 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/217.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1552506654 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 217.otp_ctrl_init_fail.1552506654' seed=32987663148745995478775554442991965790440033816306182332966542977789560708894 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32987663148745995478775554442991965790440033816306182332966542977789560708894 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/217.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 42325039125997824205105291064983984938976091588743237216920854689039101734484 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/218.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3832819284 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 218.otp_ctrl_init_fail.3832819284' seed=42325039125997824205105291064983984938976091588743237216920854689039101734484 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42325039125997824205105291064983984938976091588743237216920854689039101734484 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/218.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 38512729230142751588155579002498716758118813593872168903911987703811587891635 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/219.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1278927283 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 219.otp_ctrl_init_fail.1278927283' seed=38512729230142751588155579002498716758118813593872168903911987703811587891635 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38512729230142751588155579002498716758118813593872168903911987703811587891635 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/219.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 58860478262386359800056928883033458895225038468249029916229994447110864945803 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/220.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=486064779 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 220.otp_ctrl_init_fail.486064779' seed=58860478262386359800056928883033458895225038468249029916229994447110864945803 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58860478262386359800056928883033458895225038468249029916229994447110864945803 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/220.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 15501721636204501729476280118091710993722437974439201586651297384316042838034 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/221.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3188555794 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 221.otp_ctrl_init_fail.3188555794' seed=15501721636204501729476280118091710993722437974439201586651297384316042838034 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15501721636204501729476280118091710993722437974439201586651297384316042838034 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/221.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 4420622679175190974664079250248753508483003880938611175606977656860101034429 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/222.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3282289085 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 222.otp_ctrl_init_fail.3282289085' seed=4420622679175190974664079250248753508483003880938611175606977656860101034429 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4420622679175190974664079250248753508483003880938611175606977656860101034429 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/222.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 97073024607066209906543638609849168818690115759783746822324772134180966660588 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/223.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2311354860 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 223.otp_ctrl_init_fail.2311354860' seed=97073024607066209906543638609849168818690115759783746822324772134180966660588 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97073024607066209906543638609849168818690115759783746822324772134180966660588 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/223.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 27910372658879443781810398320898511032316899558751511953006143079513394786159 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/224.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1468018543 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 224.otp_ctrl_init_fail.1468018543' seed=27910372658879443781810398320898511032316899558751511953006143079513394786159 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27910372658879443781810398320898511032316899558751511953006143079513394786159 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/224.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 2860320848037552964009051633138582991639363339770477554685594205481303204404 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/225.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3867075124 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 225.otp_ctrl_init_fail.3867075124' seed=2860320848037552964009051633138582991639363339770477554685594205481303204404 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2860320848037552964009051633138582991639363339770477554685594205481303204404 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/225.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 89249790019212307154010119998899027229950688998754722951580458597138802964638 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/226.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=642545822 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 226.otp_ctrl_init_fail.642545822' seed=89249790019212307154010119998899027229950688998754722951580458597138802964638 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89249790019212307154010119998899027229950688998754722951580458597138802964638 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/226.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 94849493653752735178689745675363053468488848469637978357286357738648766757451 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/227.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3942890059 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 227.otp_ctrl_init_fail.3942890059' seed=94849493653752735178689745675363053468488848469637978357286357738648766757451 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94849493653752735178689745675363053468488848469637978357286357738648766757451 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/227.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 84096965506257695757244907794421718205614170637007367691792224698647857155128 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/228.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4249439288 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 228.otp_ctrl_init_fail.4249439288' seed=84096965506257695757244907794421718205614170637007367691792224698647857155128 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84096965506257695757244907794421718205614170637007367691792224698647857155128 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/228.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 47249897076980631040519764245228030188199584731136256761094797599449587727471 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/229.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2047949935 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 229.otp_ctrl_init_fail.2047949935' seed=47249897076980631040519764245228030188199584731136256761094797599449587727471 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47249897076980631040519764245228030188199584731136256761094797599449587727471 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/229.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 60713830298803261178678378905603763599432997916380251349965256005472033689613 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/230.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2352205837 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 230.otp_ctrl_init_fail.2352205837' seed=60713830298803261178678378905603763599432997916380251349965256005472033689613 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60713830298803261178678378905603763599432997916380251349965256005472033689613 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/230.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 62299771280278117682199660519082640416709051375885428555002186428539967079871 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/231.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3697509823 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 231.otp_ctrl_init_fail.3697509823' seed=62299771280278117682199660519082640416709051375885428555002186428539967079871 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62299771280278117682199660519082640416709051375885428555002186428539967079871 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/231.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 78304085796353293394922582958476270666468203919092730277371368886916131408992 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/232.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3512290400 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 232.otp_ctrl_init_fail.3512290400' seed=78304085796353293394922582958476270666468203919092730277371368886916131408992 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78304085796353293394922582958476270666468203919092730277371368886916131408992 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/232.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 37242789153777788245563868844602936976942703365586133052972519668261751948744 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/233.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2616526280 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 233.otp_ctrl_init_fail.2616526280' seed=37242789153777788245563868844602936976942703365586133052972519668261751948744 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37242789153777788245563868844602936976942703365586133052972519668261751948744 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/233.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 82869864456826025127016830446304384223884288373195589184820732261458460023652 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/234.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1183325028 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 234.otp_ctrl_init_fail.1183325028' seed=82869864456826025127016830446304384223884288373195589184820732261458460023652 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82869864456826025127016830446304384223884288373195589184820732261458460023652 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/234.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 7152806009441315632523677398057751503447275272272251159636707248523305538838 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/235.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1683739926 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 235.otp_ctrl_init_fail.1683739926' seed=7152806009441315632523677398057751503447275272272251159636707248523305538838 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7152806009441315632523677398057751503447275272272251159636707248523305538838 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/235.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 57652432165604245521390319412092323319287349553211088896860418995629322195817 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/236.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1679872873 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 236.otp_ctrl_init_fail.1679872873' seed=57652432165604245521390319412092323319287349553211088896860418995629322195817 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57652432165604245521390319412092323319287349553211088896860418995629322195817 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/236.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 21870395832452268501501780110035544502943808837247981430152998334169223484993 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/237.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2496878145 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 237.otp_ctrl_init_fail.2496878145' seed=21870395832452268501501780110035544502943808837247981430152998334169223484993 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21870395832452268501501780110035544502943808837247981430152998334169223484993 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/237.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 14160660865861790551855214009652115544256710672972820015708279335088049556045 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/238.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3899591245 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 238.otp_ctrl_init_fail.3899591245' seed=14160660865861790551855214009652115544256710672972820015708279335088049556045 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=14160660865861790551855214009652115544256710672972820015708279335088049556045 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/238.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 110986092023393257297377493367075947466021957989782758642510468882763196943381 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/239.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4196420629 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 239.otp_ctrl_init_fail.4196420629' seed=110986092023393257297377493367075947466021957989782758642510468882763196943381 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110986092023393257297377493367075947466021957989782758642510468882763196943381 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/239.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 91152839230834355799410513045010639416274932067471809486103980620393233321457 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/240.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3022589425 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 240.otp_ctrl_init_fail.3022589425' seed=91152839230834355799410513045010639416274932067471809486103980620393233321457 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91152839230834355799410513045010639416274932067471809486103980620393233321457 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/240.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 50058378575227674942528928701649132892164813817325327743172632022170504288245 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/241.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3416545269 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 241.otp_ctrl_init_fail.3416545269' seed=50058378575227674942528928701649132892164813817325327743172632022170504288245 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50058378575227674942528928701649132892164813817325327743172632022170504288245 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/241.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 1800845660310634496860817546493876305670965693062709010449170874409674897731 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/242.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1736735043 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 242.otp_ctrl_init_fail.1736735043' seed=1800845660310634496860817546493876305670965693062709010449170874409674897731 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1800845660310634496860817546493876305670965693062709010449170874409674897731 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/242.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 7482645336480897977324291414184785777095875277170915980559295404478226611858 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/243.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1352515218 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 243.otp_ctrl_init_fail.1352515218' seed=7482645336480897977324291414184785777095875277170915980559295404478226611858 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7482645336480897977324291414184785777095875277170915980559295404478226611858 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/243.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 1688730654659728183181623302178975518785604299653935336255587027703185021567 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/244.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2000951935 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 244.otp_ctrl_init_fail.2000951935' seed=1688730654659728183181623302178975518785604299653935336255587027703185021567 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1688730654659728183181623302178975518785604299653935336255587027703185021567 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/244.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 108788086615471226627335352332274053080377307335415150998810019637619504727321 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/245.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1257784601 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 245.otp_ctrl_init_fail.1257784601' seed=108788086615471226627335352332274053080377307335415150998810019637619504727321 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108788086615471226627335352332274053080377307335415150998810019637619504727321 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/245.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 10096090899180524150901633707829038075052408402973324504745468589285535552681 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/246.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1860867241 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 246.otp_ctrl_init_fail.1860867241' seed=10096090899180524150901633707829038075052408402973324504745468589285535552681 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10096090899180524150901633707829038075052408402973324504745468589285535552681 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/246.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 6979397800026081361418183972321373883525618063884360415234890603156993143257 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/247.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1999827417 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 247.otp_ctrl_init_fail.1999827417' seed=6979397800026081361418183972321373883525618063884360415234890603156993143257 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6979397800026081361418183972321373883525618063884360415234890603156993143257 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/247.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 22605487169085944282304266562799770140564336640392159815459312859971813755551 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/248.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3138505375 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 248.otp_ctrl_init_fail.3138505375' seed=22605487169085944282304266562799770140564336640392159815459312859971813755551 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22605487169085944282304266562799770140564336640392159815459312859971813755551 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/248.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 23277599308068155508621215615154057017292145329697504308548965597944797431908 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/249.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=168790116 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 249.otp_ctrl_init_fail.168790116' seed=23277599308068155508621215615154057017292145329697504308548965597944797431908 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23277599308068155508621215615154057017292145329697504308548965597944797431908 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/249.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 69823862055105152421990757773658398316725238158131271243816092159378548687015 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/250.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4106059943 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 250.otp_ctrl_init_fail.4106059943' seed=69823862055105152421990757773658398316725238158131271243816092159378548687015 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69823862055105152421990757773658398316725238158131271243816092159378548687015 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/250.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 14364737507521245708894327782049413047455825360393882736962538806437697085561 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/251.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2640896121 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 251.otp_ctrl_init_fail.2640896121' seed=14364737507521245708894327782049413047455825360393882736962538806437697085561 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=14364737507521245708894327782049413047455825360393882736962538806437697085561 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/251.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 63820947891022261931522378396779445019172090015073089724543169102700175518072 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/252.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=287402360 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 252.otp_ctrl_init_fail.287402360' seed=63820947891022261931522378396779445019172090015073089724543169102700175518072 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63820947891022261931522378396779445019172090015073089724543169102700175518072 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/252.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 36360121751259637586895595352306133208783739803432532682768051839353132120621 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/253.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=185825837 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 253.otp_ctrl_init_fail.185825837' seed=36360121751259637586895595352306133208783739803432532682768051839353132120621 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36360121751259637586895595352306133208783739803432532682768051839353132120621 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/253.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 18669214311804450369137539686429303231778526718580265814113590503681739887285 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/254.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3649999541 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 254.otp_ctrl_init_fail.3649999541' seed=18669214311804450369137539686429303231778526718580265814113590503681739887285 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18669214311804450369137539686429303231778526718580265814113590503681739887285 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/254.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 711602615716987611834043657268122766995036333577255198222965499064942255836 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/255.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2622676700 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 255.otp_ctrl_init_fail.2622676700' seed=711602615716987611834043657268122766995036333577255198222965499064942255836 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=711602615716987611834043657268122766995036333577255198222965499064942255836 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/255.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 101416846258333358056026706479139700496659687683679167879430900622742014195037 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/256.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1723659613 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 256.otp_ctrl_init_fail.1723659613' seed=101416846258333358056026706479139700496659687683679167879430900622742014195037 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101416846258333358056026706479139700496659687683679167879430900622742014195037 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/256.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 56672367518710501962638865317639666007887203781339356525490686105553158855225 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/257.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3724335673 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 257.otp_ctrl_init_fail.3724335673' seed=56672367518710501962638865317639666007887203781339356525490686105553158855225 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56672367518710501962638865317639666007887203781339356525490686105553158855225 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/257.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 32933740865711501200154011516889376464566016404154469584230147652057719110597 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/258.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1754004421 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 258.otp_ctrl_init_fail.1754004421' seed=32933740865711501200154011516889376464566016404154469584230147652057719110597 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32933740865711501200154011516889376464566016404154469584230147652057719110597 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/258.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 74967351688394001237317442559186307965946856110350460086798662987279868896075 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/259.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2863145803 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 259.otp_ctrl_init_fail.2863145803' seed=74967351688394001237317442559186307965946856110350460086798662987279868896075 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74967351688394001237317442559186307965946856110350460086798662987279868896075 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/259.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 64710453816875877427655968621993124624997728138986236710147523908529723090866 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/260.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=991766450 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 260.otp_ctrl_init_fail.991766450' seed=64710453816875877427655968621993124624997728138986236710147523908529723090866 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64710453816875877427655968621993124624997728138986236710147523908529723090866 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/260.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 8364825584612172837809396599893745529835153780582528458083087678891899531713 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/261.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3852775873 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 261.otp_ctrl_init_fail.3852775873' seed=8364825584612172837809396599893745529835153780582528458083087678891899531713 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8364825584612172837809396599893745529835153780582528458083087678891899531713 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/261.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 51260233567140293840731393952538729203849040209291862825570969955812892196539 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/262.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2005647035 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 262.otp_ctrl_init_fail.2005647035' seed=51260233567140293840731393952538729203849040209291862825570969955812892196539 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51260233567140293840731393952538729203849040209291862825570969955812892196539 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/262.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 16376650419334067103037641883573980603542297065256042013462872090559962954691 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/263.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1965571011 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 263.otp_ctrl_init_fail.1965571011' seed=16376650419334067103037641883573980603542297065256042013462872090559962954691 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16376650419334067103037641883573980603542297065256042013462872090559962954691 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/263.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 50218936899325296953581430391203566865076990884695336451911319322860273644916 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/264.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=536982900 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 264.otp_ctrl_init_fail.536982900' seed=50218936899325296953581430391203566865076990884695336451911319322860273644916 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50218936899325296953581430391203566865076990884695336451911319322860273644916 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/264.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 86512093869211730820988399753403585568162221107319257489572585938722904601313 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/265.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3136287457 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 265.otp_ctrl_init_fail.3136287457' seed=86512093869211730820988399753403585568162221107319257489572585938722904601313 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86512093869211730820988399753403585568162221107319257489572585938722904601313 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/265.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 6366192768690163130551298643185213823303637060553766994121347635762308181224 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/266.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3105746152 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 266.otp_ctrl_init_fail.3105746152' seed=6366192768690163130551298643185213823303637060553766994121347635762308181224 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6366192768690163130551298643185213823303637060553766994121347635762308181224 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/266.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 84053272654910979619582904312471917882861905216487976879238820629409771028003 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/267.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3690724899 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 267.otp_ctrl_init_fail.3690724899' seed=84053272654910979619582904312471917882861905216487976879238820629409771028003 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84053272654910979619582904312471917882861905216487976879238820629409771028003 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/267.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 115614504081749131371837300426931930236365924327598071548319765063397078855121 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/268.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2829446609 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 268.otp_ctrl_init_fail.2829446609' seed=115614504081749131371837300426931930236365924327598071548319765063397078855121 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115614504081749131371837300426931930236365924327598071548319765063397078855121 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/268.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 19920392678551269051883279897474325537468064326293975726749057439337657055029 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/269.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1166194485 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 269.otp_ctrl_init_fail.1166194485' seed=19920392678551269051883279897474325537468064326293975726749057439337657055029 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19920392678551269051883279897474325537468064326293975726749057439337657055029 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/269.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 58525833635456132356307493805403896559392067838438704670194998925941456908840 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/270.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2583573032 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 270.otp_ctrl_init_fail.2583573032' seed=58525833635456132356307493805403896559392067838438704670194998925941456908840 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58525833635456132356307493805403896559392067838438704670194998925941456908840 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/270.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 95497740239961077939137625300613320162954144301757191987526424298978001613591 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/271.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3484480279 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 271.otp_ctrl_init_fail.3484480279' seed=95497740239961077939137625300613320162954144301757191987526424298978001613591 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95497740239961077939137625300613320162954144301757191987526424298978001613591 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/271.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 86941719959526114419327461546021772779653018547883883080943452822788509754964 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/272.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3316606548 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 272.otp_ctrl_init_fail.3316606548' seed=86941719959526114419327461546021772779653018547883883080943452822788509754964 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86941719959526114419327461546021772779653018547883883080943452822788509754964 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/272.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 45372350095171272279406888298486917943137450560219510370772790194212829721961 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/273.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4061721961 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 273.otp_ctrl_init_fail.4061721961' seed=45372350095171272279406888298486917943137450560219510370772790194212829721961 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45372350095171272279406888298486917943137450560219510370772790194212829721961 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/273.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 76106209988925874470760355164252078400750213903743793092882489755954026777377 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/274.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2339244833 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 274.otp_ctrl_init_fail.2339244833' seed=76106209988925874470760355164252078400750213903743793092882489755954026777377 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76106209988925874470760355164252078400750213903743793092882489755954026777377 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/274.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 25748048157746565960013620871751394147771155519020479341987493991058338718921 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/275.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=455845065 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 275.otp_ctrl_init_fail.455845065' seed=25748048157746565960013620871751394147771155519020479341987493991058338718921 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25748048157746565960013620871751394147771155519020479341987493991058338718921 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/275.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 34362302107516400568237600715700488793586950628989849131548844450604648955128 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/276.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1197931768 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 276.otp_ctrl_init_fail.1197931768' seed=34362302107516400568237600715700488793586950628989849131548844450604648955128 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34362302107516400568237600715700488793586950628989849131548844450604648955128 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/276.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 26409927466784305447114119855335143310082123323087804648502596279465172160797 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/277.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2877968669 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 277.otp_ctrl_init_fail.2877968669' seed=26409927466784305447114119855335143310082123323087804648502596279465172160797 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26409927466784305447114119855335143310082123323087804648502596279465172160797 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/277.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 60815870341996295548404775004205046968717379845180427647627123232302031852641 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/278.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3200406625 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 278.otp_ctrl_init_fail.3200406625' seed=60815870341996295548404775004205046968717379845180427647627123232302031852641 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60815870341996295548404775004205046968717379845180427647627123232302031852641 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/278.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 110676206041188829158475969913049234891615878964956203296637447195612716547056 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/279.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1357462512 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 279.otp_ctrl_init_fail.1357462512' seed=110676206041188829158475969913049234891615878964956203296637447195612716547056 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110676206041188829158475969913049234891615878964956203296637447195612716547056 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/279.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 82796958606613701341369982042439475240436375470426915329599557874612896787326 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/280.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4236766078 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 280.otp_ctrl_init_fail.4236766078' seed=82796958606613701341369982042439475240436375470426915329599557874612896787326 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82796958606613701341369982042439475240436375470426915329599557874612896787326 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/280.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 97026403690808278901359835539894917226857813693086899730403575610678616883191 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/281.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3045949431 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 281.otp_ctrl_init_fail.3045949431' seed=97026403690808278901359835539894917226857813693086899730403575610678616883191 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97026403690808278901359835539894917226857813693086899730403575610678616883191 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/281.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 29708034633696258223708832848480532423854742397217228946794176724613638058093 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/282.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2925457517 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 282.otp_ctrl_init_fail.2925457517' seed=29708034633696258223708832848480532423854742397217228946794176724613638058093 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29708034633696258223708832848480532423854742397217228946794176724613638058093 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/282.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 24862707470421547586656355292065460767094283368217987477081066978212121368661 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/283.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1727223893 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 283.otp_ctrl_init_fail.1727223893' seed=24862707470421547586656355292065460767094283368217987477081066978212121368661 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24862707470421547586656355292065460767094283368217987477081066978212121368661 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/283.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 71098527585155111065649106046265684446141618484145153411078488292580206526518 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/284.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3389210678 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 284.otp_ctrl_init_fail.3389210678' seed=71098527585155111065649106046265684446141618484145153411078488292580206526518 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71098527585155111065649106046265684446141618484145153411078488292580206526518 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/284.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 43930840222541507783054251889318707613056032890589276643494518558191658176856 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/285.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2482999640 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 285.otp_ctrl_init_fail.2482999640' seed=43930840222541507783054251889318707613056032890589276643494518558191658176856 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43930840222541507783054251889318707613056032890589276643494518558191658176856 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/285.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 28646896862623785560538063978357649383696315882554100141956319096962256903062 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/286.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1204460438 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 286.otp_ctrl_init_fail.1204460438' seed=28646896862623785560538063978357649383696315882554100141956319096962256903062 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28646896862623785560538063978357649383696315882554100141956319096962256903062 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/286.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 110879655033845522343992799582934316296994137422810959908534772578319944407079 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/287.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4203501607 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 287.otp_ctrl_init_fail.4203501607' seed=110879655033845522343992799582934316296994137422810959908534772578319944407079 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110879655033845522343992799582934316296994137422810959908534772578319944407079 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/287.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 50931343147918872294559562012499629477034658800359915761518842937030219850322 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/288.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2537480786 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 288.otp_ctrl_init_fail.2537480786' seed=50931343147918872294559562012499629477034658800359915761518842937030219850322 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50931343147918872294559562012499629477034658800359915761518842937030219850322 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/288.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 61087209962812992597325765572785583177022029321762106987439449554447756597841 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/289.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1192663633 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 289.otp_ctrl_init_fail.1192663633' seed=61087209962812992597325765572785583177022029321762106987439449554447756597841 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61087209962812992597325765572785583177022029321762106987439449554447756597841 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/289.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 87289966142631121609347083544335865284219111890929831320962603012029582883339 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/290.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1331378699 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 290.otp_ctrl_init_fail.1331378699' seed=87289966142631121609347083544335865284219111890929831320962603012029582883339 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87289966142631121609347083544335865284219111890929831320962603012029582883339 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/290.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 47349653647856123074813916873740657550092197266922176405981083251651176766423 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/291.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3970898903 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 291.otp_ctrl_init_fail.3970898903' seed=47349653647856123074813916873740657550092197266922176405981083251651176766423 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47349653647856123074813916873740657550092197266922176405981083251651176766423 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/291.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 25597812237888646856996393206815635089158092444680667817839659692050744203970 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/292.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2585647810 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 292.otp_ctrl_init_fail.2585647810' seed=25597812237888646856996393206815635089158092444680667817839659692050744203970 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25597812237888646856996393206815635089158092444680667817839659692050744203970 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/292.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 94266654727296066683912347230738622081369853949736811414615023974905937963639 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/293.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=988850807 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 293.otp_ctrl_init_fail.988850807' seed=94266654727296066683912347230738622081369853949736811414615023974905937963639 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94266654727296066683912347230738622081369853949736811414615023974905937963639 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/293.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 30304554375655996907734725882822123399201221080236992562516800234457464851096 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/294.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2936556184 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 294.otp_ctrl_init_fail.2936556184' seed=30304554375655996907734725882822123399201221080236992562516800234457464851096 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30304554375655996907734725882822123399201221080236992562516800234457464851096 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/294.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 87208823157386518660567795505490046607117615967671196122258587356462350318110 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/295.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=368294430 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 295.otp_ctrl_init_fail.368294430' seed=87208823157386518660567795505490046607117615967671196122258587356462350318110 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87208823157386518660567795505490046607117615967671196122258587356462350318110 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/295.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 89993780503458807293071907650198085466826141053292171541925937749514349771775 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/296.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3130063871 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 296.otp_ctrl_init_fail.3130063871' seed=89993780503458807293071907650198085466826141053292171541925937749514349771775 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89993780503458807293071907650198085466826141053292171541925937749514349771775 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/296.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 82044629881996069607996716444163829656074533632105267830537529216333885655907 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/297.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2769996643 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 297.otp_ctrl_init_fail.2769996643' seed=82044629881996069607996716444163829656074533632105267830537529216333885655907 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82044629881996069607996716444163829656074533632105267830537529216333885655907 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/297.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 70132446359418639659690713352101626208883822234549290564624299998407522662840 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/298.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=936524216 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 298.otp_ctrl_init_fail.936524216' seed=70132446359418639659690713352101626208883822234549290564624299998407522662840 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70132446359418639659690713352101626208883822234549290564624299998407522662840 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/298.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
otp_ctrl_init_fail 104381687650868228154315225216098874985565043331029354866516338983708308641613 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/299.otp_ctrl_init_fail/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=657561421 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=otp_ctrl_base_test +UVM_TEST_SEQ=otp_ctrl_init_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/otp_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 299.otp_ctrl_init_fail.657561421' seed=104381687650868228154315225216098874985565043331029354866516338983708308641613 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104381687650868228154315225216098874985565043331029354866516338983708308641613 --run-dir=/nightly/current_run/scratch/master/otp_ctrl-sim-vcs/299.otp_ctrl_init_fail/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=otp_ctrl_base_test uvm_test_seq=otp_ctrl_init_fail_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.err_code_* 7 test runs
otp_ctrl_stress_all 70288758810986551248476216768631822164249383849466125840740030622113366932088 3515
UVM_INFO @ 1621995283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 16385033815148815576434398536844131199442648154812517463758897031695777775278 10926
UVM_INFO @ 4629641907 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 79700100662419223817378133784626700408535872626742494640929342483448699561757 29301
UVM_INFO @ 915042719 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 20481021375466667033526747550715453099760334907734287104635771169167953502817 41429
UVM_INFO @ 3026485008 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 81107571560585059242281492812303163340068482251216866775125309769699747163720 8368
UVM_INFO @ 402718925 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 41395217894425523335230347037166757082914405659305290561686530526042592273597 20756
UVM_INFO @ 3459844667 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 47990563347895474925135115735302891947927254036835218116728277049826448674989 4898
UVM_INFO @ 3318078066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:674) [scoreboard] Check failed cfg.intr_vif.pins[i] === (intr_en[i] & intr_exp[i]) (* [*] vs * [*]) Interrupt_pin: OtpErr 1 test run
otp_ctrl_stress_all 98463255260080495898778178508711746359820479033679182910844034025187634725445 3837
UVM_INFO @ 8069818092 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_base_vseq.sv:215) [otp_ctrl_low_freq_read_vseq] Check failed rdata* == exp_data* (* [*] vs * [*]) dai addr *ed* rdata* readout mismatch 1 test run
otp_ctrl_stress_all 100544510137782804099322770630570757885463408912744950002013655944637232862819 14148
UVM_INFO @ 27026787233 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1323) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 1 test run
otp_ctrl_stress_all 69102745180065576161298766145948205509235133339518306611171340881573463433716 9317
UVM_INFO @ 12052611940 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job cancelled because all of its dependencies failed or were killed. 1 test run
otp_ctrl None None
Job cancelled because one of its dependencies failed or was killed. 1 test run
otp_ctrl None None