Simulation Results: prim_alert

 
28/08/2026 21:54:34 DVSim: v1.49.0 sha: a099412 json Branch: master Tool: vcs [unknown]
Validation stages
V1
0.00%
V2
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
prim_alert_request_test 0 50 0.00
prim_async_alert 1.592s 0.000us 0 20 0.00
prim_async_fatal_alert 2.108s 0.000us 0 10 0.00
prim_sync_alert 1.558s 0.000us 0 10 0.00
prim_sync_fatal_alert 1.574s 0.000us 0 10 0.00
prim_alert_test 0 50 0.00
prim_async_alert 1.592s 0.000us 0 20 0.00
prim_async_fatal_alert 2.108s 0.000us 0 10 0.00
prim_sync_alert 1.558s 0.000us 0 10 0.00
prim_sync_fatal_alert 1.574s 0.000us 0 10 0.00
prim_alert_ping_request_test 0 50 0.00
prim_async_alert 1.592s 0.000us 0 20 0.00
prim_async_fatal_alert 2.108s 0.000us 0 10 0.00
prim_sync_alert 1.558s 0.000us 0 10 0.00
prim_sync_fatal_alert 1.574s 0.000us 0 10 0.00
prim_alert_integrity_errors_test 0 50 0.00
prim_async_alert 1.592s 0.000us 0 20 0.00
prim_async_fatal_alert 2.108s 0.000us 0 10 0.00
prim_sync_alert 1.558s 0.000us 0 10 0.00
prim_sync_fatal_alert 1.574s 0.000us 0 10 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
prim_alert_init_trigger_test 0 50 0.00
prim_async_alert 1.592s 0.000us 0 20 0.00
prim_async_fatal_alert 2.108s 0.000us 0 10 0.00
prim_sync_alert 1.558s 0.000us 0 10 0.00
prim_sync_fatal_alert 1.574s 0.000us 0 10 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 10 0.00
prim_async_fatal_alert_with_3_cycles_skew 1.509s 0.000us 0 10 0.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 60 test runs
prim_async_alert 86369785614257472426872123484144020079140714886577115867592549392613159389317 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/0.prim_async_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2276903045 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_async_alert.2276903045' seed=86369785614257472426872123484144020079140714886577115867592549392613159389317 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86369785614257472426872123484144020079140714886577115867592549392613159389317 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/0.prim_async_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_fatal_alert 87458850932606875366688022057519711198924047809544536103830510823971768473017 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/fatal_alert/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/0.prim_async_fatal_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3298530745 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert.3298530745' seed=87458850932606875366688022057519711198924047809544536103830510823971768473017 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87458850932606875366688022057519711198924047809544536103830510823971768473017 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/0.prim_async_fatal_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_fatal_alert_with_3_cycles_skew 52478022974958749165552827948680777350765057316365507762014791878441678756697 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/fatal_alert_with_3_cycles_skew/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/0.prim_async_fatal_alert_with_3_cycles_skew/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3091553113 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/fatal_alert_with_3_cycles_skew.vdb -cm_log /dev/null -cm_name 0.prim_async_fatal_alert_with_3_cycles_skew.3091553113' seed=52478022974958749165552827948680777350765057316365507762014791878441678756697 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=52478022974958749165552827948680777350765057316365507762014791878441678756697 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/0.prim_async_fatal_alert_with_3_cycles_skew/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_sync_alert 2591515726550182356353676659969816497902032773873342881759691793128714986179 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/sync_alert/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/0.prim_sync_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1530454723 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_alert.1530454723' seed=2591515726550182356353676659969816497902032773873342881759691793128714986179 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2591515726550182356353676659969816497902032773873342881759691793128714986179 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/0.prim_sync_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_sync_fatal_alert 103369909767272260361011324705419268251625864127210482817400209114307771071701 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/sync_fatal_alert/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/0.prim_sync_fatal_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=453344469 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 0.prim_sync_fatal_alert.453344469' seed=103369909767272260361011324705419268251625864127210482817400209114307771071701 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103369909767272260361011324705419268251625864127210482817400209114307771071701 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/0.prim_sync_fatal_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_alert 27578038815753826453143734237584390726275227000245373377681827479010687025503 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/1.prim_async_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1790673247 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_async_alert.1790673247' seed=27578038815753826453143734237584390726275227000245373377681827479010687025503 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27578038815753826453143734237584390726275227000245373377681827479010687025503 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/1.prim_async_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_fatal_alert 62779803592537441837775347462404420391498407972658362730258042080229952338630 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/fatal_alert/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/1.prim_async_fatal_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2271754950 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert.2271754950' seed=62779803592537441837775347462404420391498407972658362730258042080229952338630 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62779803592537441837775347462404420391498407972658362730258042080229952338630 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/1.prim_async_fatal_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_fatal_alert_with_3_cycles_skew 4865431923453719700831500779925020678457592330433161437013543443170073210742 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/fatal_alert_with_3_cycles_skew/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/1.prim_async_fatal_alert_with_3_cycles_skew/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3288821622 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/fatal_alert_with_3_cycles_skew.vdb -cm_log /dev/null -cm_name 1.prim_async_fatal_alert_with_3_cycles_skew.3288821622' seed=4865431923453719700831500779925020678457592330433161437013543443170073210742 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4865431923453719700831500779925020678457592330433161437013543443170073210742 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/1.prim_async_fatal_alert_with_3_cycles_skew/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_sync_alert 36855826116281332602889562536215392846186451368783227373809182621115555543178 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/sync_alert/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/1.prim_sync_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2521856138 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_alert.2521856138' seed=36855826116281332602889562536215392846186451368783227373809182621115555543178 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36855826116281332602889562536215392846186451368783227373809182621115555543178 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/1.prim_sync_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_sync_fatal_alert 16857981399902103387640621731231407982478013235443943996401202061336011392673 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/sync_fatal_alert/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/1.prim_sync_fatal_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2364589729 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 1.prim_sync_fatal_alert.2364589729' seed=16857981399902103387640621731231407982478013235443943996401202061336011392673 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16857981399902103387640621731231407982478013235443943996401202061336011392673 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/1.prim_sync_fatal_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_alert 22343865606546577097203966526152852647429203865201280550011967288507781036131 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/2.prim_async_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3668392035 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_async_alert.3668392035' seed=22343865606546577097203966526152852647429203865201280550011967288507781036131 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22343865606546577097203966526152852647429203865201280550011967288507781036131 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/2.prim_async_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_fatal_alert 84302533688589084481116625505284046428707522156515976443320636535726625948494 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/fatal_alert/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/2.prim_async_fatal_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4097999694 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert.4097999694' seed=84302533688589084481116625505284046428707522156515976443320636535726625948494 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84302533688589084481116625505284046428707522156515976443320636535726625948494 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/2.prim_async_fatal_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_fatal_alert_with_3_cycles_skew 24832925442040409783951048421065995560165422821662941681390138249298125937351 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/fatal_alert_with_3_cycles_skew/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/2.prim_async_fatal_alert_with_3_cycles_skew/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1211521735 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/fatal_alert_with_3_cycles_skew.vdb -cm_log /dev/null -cm_name 2.prim_async_fatal_alert_with_3_cycles_skew.1211521735' seed=24832925442040409783951048421065995560165422821662941681390138249298125937351 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24832925442040409783951048421065995560165422821662941681390138249298125937351 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/2.prim_async_fatal_alert_with_3_cycles_skew/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_sync_alert 48791769889461829231998863961408594930876081446556673136548871331963454096949 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/sync_alert/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/2.prim_sync_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=456132149 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_alert.456132149' seed=48791769889461829231998863961408594930876081446556673136548871331963454096949 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48791769889461829231998863961408594930876081446556673136548871331963454096949 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/2.prim_sync_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_sync_fatal_alert 56969625656227039302637013024119258304701156614236432050861701302860180917212 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/sync_fatal_alert/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/2.prim_sync_fatal_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3684731868 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 2.prim_sync_fatal_alert.3684731868' seed=56969625656227039302637013024119258304701156614236432050861701302860180917212 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56969625656227039302637013024119258304701156614236432050861701302860180917212 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/2.prim_sync_fatal_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_alert 34667618130273704422992262639312295433559515508507832561174538415766922153797 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/3.prim_async_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3950333765 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_async_alert.3950333765' seed=34667618130273704422992262639312295433559515508507832561174538415766922153797 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34667618130273704422992262639312295433559515508507832561174538415766922153797 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/3.prim_async_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_fatal_alert 73807352521265590652085035120156003351395862291080640947753917588765097924887 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/fatal_alert/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/3.prim_async_fatal_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1888557335 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert.1888557335' seed=73807352521265590652085035120156003351395862291080640947753917588765097924887 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73807352521265590652085035120156003351395862291080640947753917588765097924887 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/3.prim_async_fatal_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_fatal_alert_with_3_cycles_skew 66791443671132311518575868992836906053134330727493371526436681997109376164190 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/fatal_alert_with_3_cycles_skew/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/3.prim_async_fatal_alert_with_3_cycles_skew/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1346740574 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/fatal_alert_with_3_cycles_skew.vdb -cm_log /dev/null -cm_name 3.prim_async_fatal_alert_with_3_cycles_skew.1346740574' seed=66791443671132311518575868992836906053134330727493371526436681997109376164190 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66791443671132311518575868992836906053134330727493371526436681997109376164190 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/3.prim_async_fatal_alert_with_3_cycles_skew/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_sync_alert 13814901916062206729137537185083949244970784760626408069556033547810790484156 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/sync_alert/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/3.prim_sync_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3615008956 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_alert.3615008956' seed=13814901916062206729137537185083949244970784760626408069556033547810790484156 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13814901916062206729137537185083949244970784760626408069556033547810790484156 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/3.prim_sync_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_sync_fatal_alert 11741532880982411269979509294901292211948753969486404951168824983668057786412 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/sync_fatal_alert/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/3.prim_sync_fatal_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=303384620 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 3.prim_sync_fatal_alert.303384620' seed=11741532880982411269979509294901292211948753969486404951168824983668057786412 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11741532880982411269979509294901292211948753969486404951168824983668057786412 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/3.prim_sync_fatal_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_alert 86850866563652600278098898015413613123705493933038768024149474038804863932814 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/4.prim_async_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=165566862 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_async_alert.165566862' seed=86850866563652600278098898015413613123705493933038768024149474038804863932814 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86850866563652600278098898015413613123705493933038768024149474038804863932814 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/4.prim_async_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_fatal_alert 94508585707490512918990281030054287862103900740643925126405800988138757042832 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/fatal_alert/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/4.prim_async_fatal_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3235787408 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert.3235787408' seed=94508585707490512918990281030054287862103900740643925126405800988138757042832 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94508585707490512918990281030054287862103900740643925126405800988138757042832 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/4.prim_async_fatal_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_fatal_alert_with_3_cycles_skew 90868169247859658629071215026291549349530151857255560625958368411585351697124 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/fatal_alert_with_3_cycles_skew/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/4.prim_async_fatal_alert_with_3_cycles_skew/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=14598884 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/fatal_alert_with_3_cycles_skew.vdb -cm_log /dev/null -cm_name 4.prim_async_fatal_alert_with_3_cycles_skew.14598884' seed=90868169247859658629071215026291549349530151857255560625958368411585351697124 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90868169247859658629071215026291549349530151857255560625958368411585351697124 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/4.prim_async_fatal_alert_with_3_cycles_skew/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_sync_alert 40560104807577153306324839332114976234393773571891235451491844184544241886892 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/sync_alert/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/4.prim_sync_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=269854380 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_alert.269854380' seed=40560104807577153306324839332114976234393773571891235451491844184544241886892 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40560104807577153306324839332114976234393773571891235451491844184544241886892 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/4.prim_sync_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_sync_fatal_alert 46425852297612013929995489247612045889838228153278464232742014212651389675496 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/sync_fatal_alert/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/4.prim_sync_fatal_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2990401512 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 4.prim_sync_fatal_alert.2990401512' seed=46425852297612013929995489247612045889838228153278464232742014212651389675496 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46425852297612013929995489247612045889838228153278464232742014212651389675496 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/4.prim_sync_fatal_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_alert 64981588040059251735454047568348479648195484874188107344246687272836327874035 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/5.prim_async_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=87105011 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_async_alert.87105011' seed=64981588040059251735454047568348479648195484874188107344246687272836327874035 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64981588040059251735454047568348479648195484874188107344246687272836327874035 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/5.prim_async_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_fatal_alert 88332199639092327481824095096047213838141607654582699757950723369598538592542 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/fatal_alert/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/5.prim_async_fatal_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1097707806 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert.1097707806' seed=88332199639092327481824095096047213838141607654582699757950723369598538592542 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88332199639092327481824095096047213838141607654582699757950723369598538592542 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/5.prim_async_fatal_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_fatal_alert_with_3_cycles_skew 61260988390058245294140154300096991109938825500424932040116301839711130456679 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/fatal_alert_with_3_cycles_skew/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/5.prim_async_fatal_alert_with_3_cycles_skew/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1062834791 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/fatal_alert_with_3_cycles_skew.vdb -cm_log /dev/null -cm_name 5.prim_async_fatal_alert_with_3_cycles_skew.1062834791' seed=61260988390058245294140154300096991109938825500424932040116301839711130456679 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61260988390058245294140154300096991109938825500424932040116301839711130456679 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/5.prim_async_fatal_alert_with_3_cycles_skew/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_sync_alert 115332527356463394085203770367451644909357512652892029560628222962094132028855 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/sync_alert/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/5.prim_sync_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=527295927 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_alert.527295927' seed=115332527356463394085203770367451644909357512652892029560628222962094132028855 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115332527356463394085203770367451644909357512652892029560628222962094132028855 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/5.prim_sync_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_sync_fatal_alert 64192802365448116358154990442429813378190251663859543657440183101738184677802 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/sync_fatal_alert/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/5.prim_sync_fatal_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1371609514 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 5.prim_sync_fatal_alert.1371609514' seed=64192802365448116358154990442429813378190251663859543657440183101738184677802 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64192802365448116358154990442429813378190251663859543657440183101738184677802 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/5.prim_sync_fatal_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_alert 31601575565489471371615156382619728216324146516386468693326838760789887046468 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/6.prim_async_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2302038852 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_async_alert.2302038852' seed=31601575565489471371615156382619728216324146516386468693326838760789887046468 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31601575565489471371615156382619728216324146516386468693326838760789887046468 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/6.prim_async_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_fatal_alert 111171874340624493427848842775060080280702454395347308323289469751360372863351 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/fatal_alert/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/6.prim_async_fatal_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1603006839 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert.1603006839' seed=111171874340624493427848842775060080280702454395347308323289469751360372863351 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111171874340624493427848842775060080280702454395347308323289469751360372863351 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/6.prim_async_fatal_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_fatal_alert_with_3_cycles_skew 62610540670402336028051307015924369315464283610006281099123142476852181212634 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/fatal_alert_with_3_cycles_skew/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/6.prim_async_fatal_alert_with_3_cycles_skew/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1625693658 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/fatal_alert_with_3_cycles_skew.vdb -cm_log /dev/null -cm_name 6.prim_async_fatal_alert_with_3_cycles_skew.1625693658' seed=62610540670402336028051307015924369315464283610006281099123142476852181212634 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62610540670402336028051307015924369315464283610006281099123142476852181212634 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/6.prim_async_fatal_alert_with_3_cycles_skew/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_sync_alert 64342545865637880009257956813844088181864515994531946178483217395987082490924 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/sync_alert/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/6.prim_sync_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3767645228 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_alert.3767645228' seed=64342545865637880009257956813844088181864515994531946178483217395987082490924 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64342545865637880009257956813844088181864515994531946178483217395987082490924 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/6.prim_sync_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_sync_fatal_alert 67245659901829984063135873604312808791176850090093895914886791884018464626346 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/sync_fatal_alert/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/6.prim_sync_fatal_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2319226538 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 6.prim_sync_fatal_alert.2319226538' seed=67245659901829984063135873604312808791176850090093895914886791884018464626346 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67245659901829984063135873604312808791176850090093895914886791884018464626346 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/6.prim_sync_fatal_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_alert 72466862090962494984106914677842946345006874842616756502067905389166884117578 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/7.prim_async_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=210328650 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_async_alert.210328650' seed=72466862090962494984106914677842946345006874842616756502067905389166884117578 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72466862090962494984106914677842946345006874842616756502067905389166884117578 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/7.prim_async_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_fatal_alert 15412464735203766114976755896242826215226787126216401809788186455932730199842 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/fatal_alert/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/7.prim_async_fatal_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=219533090 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert.219533090' seed=15412464735203766114976755896242826215226787126216401809788186455932730199842 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15412464735203766114976755896242826215226787126216401809788186455932730199842 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/7.prim_async_fatal_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_fatal_alert_with_3_cycles_skew 111791357496949042153897243275598340940848350136723803214909034250950429473061 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/fatal_alert_with_3_cycles_skew/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/7.prim_async_fatal_alert_with_3_cycles_skew/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2288351525 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/fatal_alert_with_3_cycles_skew.vdb -cm_log /dev/null -cm_name 7.prim_async_fatal_alert_with_3_cycles_skew.2288351525' seed=111791357496949042153897243275598340940848350136723803214909034250950429473061 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111791357496949042153897243275598340940848350136723803214909034250950429473061 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/7.prim_async_fatal_alert_with_3_cycles_skew/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_sync_alert 12673228028682671279548874554397519147572099272012781912270847050234525384983 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/sync_alert/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/7.prim_sync_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=38011159 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_alert.38011159' seed=12673228028682671279548874554397519147572099272012781912270847050234525384983 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12673228028682671279548874554397519147572099272012781912270847050234525384983 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/7.prim_sync_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_sync_fatal_alert 15806195538732668469613254605299320983335661383031795821946409155966839503522 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/sync_fatal_alert/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/7.prim_sync_fatal_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1994078882 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 7.prim_sync_fatal_alert.1994078882' seed=15806195538732668469613254605299320983335661383031795821946409155966839503522 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15806195538732668469613254605299320983335661383031795821946409155966839503522 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/7.prim_sync_fatal_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_alert 1780673802376553325771342514560639007189790069295345624852628676436271277695 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/8.prim_async_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2657855103 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_async_alert.2657855103' seed=1780673802376553325771342514560639007189790069295345624852628676436271277695 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1780673802376553325771342514560639007189790069295345624852628676436271277695 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/8.prim_async_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_fatal_alert 114034924112360979697549549376156098531945015914594634359232073238222110049038 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/fatal_alert/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/8.prim_async_fatal_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3554263822 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert.3554263822' seed=114034924112360979697549549376156098531945015914594634359232073238222110049038 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114034924112360979697549549376156098531945015914594634359232073238222110049038 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/8.prim_async_fatal_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_fatal_alert_with_3_cycles_skew 5098615437165268888208028054842730081788681394431969722438247564467981094933 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/fatal_alert_with_3_cycles_skew/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/8.prim_async_fatal_alert_with_3_cycles_skew/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=844992533 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/fatal_alert_with_3_cycles_skew.vdb -cm_log /dev/null -cm_name 8.prim_async_fatal_alert_with_3_cycles_skew.844992533' seed=5098615437165268888208028054842730081788681394431969722438247564467981094933 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5098615437165268888208028054842730081788681394431969722438247564467981094933 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/8.prim_async_fatal_alert_with_3_cycles_skew/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_sync_alert 68565497214235393735607235973735376545760682007434927738014293140387619358966 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/sync_alert/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/8.prim_sync_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=555174134 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_alert.555174134' seed=68565497214235393735607235973735376545760682007434927738014293140387619358966 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68565497214235393735607235973735376545760682007434927738014293140387619358966 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/8.prim_sync_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_sync_fatal_alert 50175034164976964048915690998963821338641616130628776454729945236195383114813 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/sync_fatal_alert/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/8.prim_sync_fatal_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3928685629 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 8.prim_sync_fatal_alert.3928685629' seed=50175034164976964048915690998963821338641616130628776454729945236195383114813 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50175034164976964048915690998963821338641616130628776454729945236195383114813 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/8.prim_sync_fatal_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_alert 66378870705531319002978362183934589031489394393732559838621962011879262979007 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/9.prim_async_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=159450047 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_async_alert.159450047' seed=66378870705531319002978362183934589031489394393732559838621962011879262979007 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66378870705531319002978362183934589031489394393732559838621962011879262979007 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/9.prim_async_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_fatal_alert 60789176046358843690972743151345365342293044754555125747870910249461248733387 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/fatal_alert/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/9.prim_async_fatal_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2188423371 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert.2188423371' seed=60789176046358843690972743151345365342293044754555125747870910249461248733387 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60789176046358843690972743151345365342293044754555125747870910249461248733387 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/9.prim_async_fatal_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_fatal_alert_with_3_cycles_skew 23470326966995727313901868901484031629359429816632681572933565864034066755287 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/fatal_alert_with_3_cycles_skew/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/9.prim_async_fatal_alert_with_3_cycles_skew/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3417042647 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/fatal_alert_with_3_cycles_skew.vdb -cm_log /dev/null -cm_name 9.prim_async_fatal_alert_with_3_cycles_skew.3417042647' seed=23470326966995727313901868901484031629359429816632681572933565864034066755287 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23470326966995727313901868901484031629359429816632681572933565864034066755287 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/9.prim_async_fatal_alert_with_3_cycles_skew/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_sync_alert 45225295328516357882021881237521831825378250560848264687655679325636225202316 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/sync_alert/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/9.prim_sync_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1648425100 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/sync_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_alert.1648425100' seed=45225295328516357882021881237521831825378250560848264687655679325636225202316 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45225295328516357882021881237521831825378250560848264687655679325636225202316 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/9.prim_sync_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_sync_fatal_alert 87748192147483337578143998641437465909439723671202000139450725729265324243853 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/sync_fatal_alert/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/9.prim_sync_fatal_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3848911757 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/sync_fatal_alert.vdb -cm_log /dev/null -cm_name 9.prim_sync_fatal_alert.3848911757' seed=87748192147483337578143998641437465909439723671202000139450725729265324243853 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87748192147483337578143998641437465909439723671202000139450725729265324243853 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/9.prim_sync_fatal_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_alert 10045352333173299964410931727108122816726848156871040196096706113877062371676 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/10.prim_async_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=893831516 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_async_alert.893831516' seed=10045352333173299964410931727108122816726848156871040196096706113877062371676 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10045352333173299964410931727108122816726848156871040196096706113877062371676 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/10.prim_async_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_alert 99894661122520871154588176603441462889935380776794131985373425213512046439951 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/11.prim_async_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=546139663 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_async_alert.546139663' seed=99894661122520871154588176603441462889935380776794131985373425213512046439951 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99894661122520871154588176603441462889935380776794131985373425213512046439951 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/11.prim_async_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_alert 38100016563680434231208008759255390180599550123423907061533416027334555478761 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/12.prim_async_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=660351721 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_async_alert.660351721' seed=38100016563680434231208008759255390180599550123423907061533416027334555478761 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38100016563680434231208008759255390180599550123423907061533416027334555478761 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/12.prim_async_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_alert 46819351969493562556292925348439783774228640904869647591682103718521471135698 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/13.prim_async_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1873965010 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_async_alert.1873965010' seed=46819351969493562556292925348439783774228640904869647591682103718521471135698 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46819351969493562556292925348439783774228640904869647591682103718521471135698 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/13.prim_async_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_alert 1729182940585801045857261010337866403068325066124540265813265188792730163275 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/14.prim_async_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3578566731 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_async_alert.3578566731' seed=1729182940585801045857261010337866403068325066124540265813265188792730163275 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1729182940585801045857261010337866403068325066124540265813265188792730163275 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/14.prim_async_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_alert 11871505150619254119654459732288495209775035544453564479190991391168051482330 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/15.prim_async_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3401780954 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_async_alert.3401780954' seed=11871505150619254119654459732288495209775035544453564479190991391168051482330 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11871505150619254119654459732288495209775035544453564479190991391168051482330 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/15.prim_async_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_alert 44388759696609473973425079921709841375641471231885961447853852920732467505121 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/16.prim_async_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3269371873 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_async_alert.3269371873' seed=44388759696609473973425079921709841375641471231885961447853852920732467505121 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44388759696609473973425079921709841375641471231885961447853852920732467505121 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/16.prim_async_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_alert 95701121963494986336275451747406971696286648460656470856647831950993241824942 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/17.prim_async_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3379715758 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_async_alert.3379715758' seed=95701121963494986336275451747406971696286648460656470856647831950993241824942 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95701121963494986336275451747406971696286648460656470856647831950993241824942 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/17.prim_async_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_alert 45072565887186282779061544106961349208032229856068197954616425803355129968976 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/18.prim_async_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=747698512 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_async_alert.747698512' seed=45072565887186282779061544106961349208032229856068197954616425803355129968976 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45072565887186282779061544106961349208032229856068197954616425803355129968976 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/18.prim_async_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_async_alert 103901039163036086583567248806109464230585689917868379522002028309089226728687 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_alert-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/19.prim_async_alert/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4081984751 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_alert-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_async_alert.4081984751' seed=103901039163036086583567248806109464230585689917868379522002028309089226728687 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103901039163036086583567248806109464230585689917868379522002028309089226728687 --run-dir=/nightly/current_run/scratch/master/prim_alert-sim-vcs/19.prim_async_alert/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
Job cancelled because all of its dependencies failed or were killed. 1 test run
prim_alert None None
Job cancelled because one of its dependencies failed or was killed. 1 test run
prim_alert None None