Simulation Results: prim_esc

 
28/08/2026 21:54:34 DVSim: v1.49.0 sha: a099412 json Branch: master Tool: vcs [unknown]
Validation stages
V1
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
prim_esc_request_test 0 20 0.00
prim_esc_test 1.575s 0.000us 0 20 0.00
prim_ping_req_interrupted_by_esc_req_test 0 20 0.00
prim_esc_test 1.575s 0.000us 0 20 0.00
prim_esc_tx_integrity_errors_test 0 20 0.00
prim_esc_test 1.575s 0.000us 0 20 0.00
prim_esc_reverse_ping_timeout_test 0 20 0.00
prim_esc_test 1.575s 0.000us 0 20 0.00
prim_esc_receiver_counter_fail_test 0 20 0.00
prim_esc_test 1.575s 0.000us 0 20 0.00
prim_esc_handshake_with_rand_reset_test 0 20 0.00
prim_esc_test 1.575s 0.000us 0 20 0.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 20 test runs
prim_esc_test 15537247442918994999697334179749775102894255102356808754983526998401034592827 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_esc-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/0.prim_esc_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2803475003 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.prim_esc_test.2803475003' seed=15537247442918994999697334179749775102894255102356808754983526998401034592827 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15537247442918994999697334179749775102894255102356808754983526998401034592827 --run-dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/0.prim_esc_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_esc_test 3256783901501867391711248766244777504015928707608886321293418153651536835257 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_esc-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/1.prim_esc_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2272703161 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.prim_esc_test.2272703161' seed=3256783901501867391711248766244777504015928707608886321293418153651536835257 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3256783901501867391711248766244777504015928707608886321293418153651536835257 --run-dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/1.prim_esc_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_esc_test 65050592690489591465149168226029805690867949148689558407120589220669670835500 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_esc-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/2.prim_esc_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2202813740 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.prim_esc_test.2202813740' seed=65050592690489591465149168226029805690867949148689558407120589220669670835500 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65050592690489591465149168226029805690867949148689558407120589220669670835500 --run-dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/2.prim_esc_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_esc_test 100046916057913053713163322885793116010708322014601433581756674109955468711634 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_esc-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/3.prim_esc_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3769915090 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.prim_esc_test.3769915090' seed=100046916057913053713163322885793116010708322014601433581756674109955468711634 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100046916057913053713163322885793116010708322014601433581756674109955468711634 --run-dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/3.prim_esc_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_esc_test 15178705677718070654010492391107869742330306765117429108145757778134713628707 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_esc-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/4.prim_esc_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2857236515 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.prim_esc_test.2857236515' seed=15178705677718070654010492391107869742330306765117429108145757778134713628707 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15178705677718070654010492391107869742330306765117429108145757778134713628707 --run-dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/4.prim_esc_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_esc_test 57436166146853042540933546036536823029943756675559620513518840863197824504362 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_esc-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/5.prim_esc_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2852082218 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.prim_esc_test.2852082218' seed=57436166146853042540933546036536823029943756675559620513518840863197824504362 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57436166146853042540933546036536823029943756675559620513518840863197824504362 --run-dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/5.prim_esc_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_esc_test 106034659765397758154873766039840752386142835597085710474540261484857989876910 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_esc-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/6.prim_esc_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3822144686 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.prim_esc_test.3822144686' seed=106034659765397758154873766039840752386142835597085710474540261484857989876910 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106034659765397758154873766039840752386142835597085710474540261484857989876910 --run-dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/6.prim_esc_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_esc_test 37911432671490593387178646093507130555664501714025191835744496970685259661899 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_esc-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/7.prim_esc_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1815036491 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.prim_esc_test.1815036491' seed=37911432671490593387178646093507130555664501714025191835744496970685259661899 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37911432671490593387178646093507130555664501714025191835744496970685259661899 --run-dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/7.prim_esc_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_esc_test 100272601267818932074969438033366509228404532526105999508184317664731974563815 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_esc-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/8.prim_esc_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=123959271 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.prim_esc_test.123959271' seed=100272601267818932074969438033366509228404532526105999508184317664731974563815 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100272601267818932074969438033366509228404532526105999508184317664731974563815 --run-dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/8.prim_esc_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_esc_test 78152268042843414105939358809068217670459165768854115480555657704694953363681 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_esc-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/9.prim_esc_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=177817825 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.prim_esc_test.177817825' seed=78152268042843414105939358809068217670459165768854115480555657704694953363681 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78152268042843414105939358809068217670459165768854115480555657704694953363681 --run-dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/9.prim_esc_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_esc_test 93037235995474368590360624347741290666308704355791133705060339427176317437202 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_esc-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/10.prim_esc_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2123613458 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.prim_esc_test.2123613458' seed=93037235995474368590360624347741290666308704355791133705060339427176317437202 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93037235995474368590360624347741290666308704355791133705060339427176317437202 --run-dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/10.prim_esc_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_esc_test 7077410471821895700082577870973498413289932545910473117326035511770988467893 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_esc-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/11.prim_esc_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3499415221 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.prim_esc_test.3499415221' seed=7077410471821895700082577870973498413289932545910473117326035511770988467893 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7077410471821895700082577870973498413289932545910473117326035511770988467893 --run-dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/11.prim_esc_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_esc_test 79694087421734906673505928620208086365210159863457307529607909103883245657124 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_esc-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/12.prim_esc_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=847584292 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.prim_esc_test.847584292' seed=79694087421734906673505928620208086365210159863457307529607909103883245657124 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79694087421734906673505928620208086365210159863457307529607909103883245657124 --run-dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/12.prim_esc_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_esc_test 97355936231206424930061168868956248899611678959913002805672376826870463287671 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_esc-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/13.prim_esc_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2842251639 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.prim_esc_test.2842251639' seed=97355936231206424930061168868956248899611678959913002805672376826870463287671 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97355936231206424930061168868956248899611678959913002805672376826870463287671 --run-dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/13.prim_esc_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_esc_test 41490711077603189953998532640524221833957851671643668739634101162291756585866 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_esc-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/14.prim_esc_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1247335306 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.prim_esc_test.1247335306' seed=41490711077603189953998532640524221833957851671643668739634101162291756585866 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41490711077603189953998532640524221833957851671643668739634101162291756585866 --run-dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/14.prim_esc_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_esc_test 92875817071007910426795896843596953704241385760704943969973068644921339651422 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_esc-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/15.prim_esc_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=701080926 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.prim_esc_test.701080926' seed=92875817071007910426795896843596953704241385760704943969973068644921339651422 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92875817071007910426795896843596953704241385760704943969973068644921339651422 --run-dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/15.prim_esc_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_esc_test 84775261943308969599147906989151608580537066351516599416077065854505911964332 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_esc-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/16.prim_esc_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=869388972 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.prim_esc_test.869388972' seed=84775261943308969599147906989151608580537066351516599416077065854505911964332 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84775261943308969599147906989151608580537066351516599416077065854505911964332 --run-dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/16.prim_esc_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_esc_test 27740474302674300288180591493174703316686835375001275447742191668597063182274 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_esc-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/17.prim_esc_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1388603330 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.prim_esc_test.1388603330' seed=27740474302674300288180591493174703316686835375001275447742191668597063182274 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27740474302674300288180591493174703316686835375001275447742191668597063182274 --run-dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/17.prim_esc_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_esc_test 48094428649748187796451694907455133099521649139288476079947670782530335678232 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_esc-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/18.prim_esc_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1350442776 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.prim_esc_test.1350442776' seed=48094428649748187796451694907455133099521649139288476079947670782530335678232 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48094428649748187796451694907455133099521649139288476079947670782530335678232 --run-dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/18.prim_esc_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
prim_esc_test 94738065992746794256333307441181187998177598447149874664213812175214205301251 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/prim_esc-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/19.prim_esc_test/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=155808259 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME= +UVM_TEST_SEQ= +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/prim_esc-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.prim_esc_test.155808259' seed=94738065992746794256333307441181187998177598447149874664213812175214205301251 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94738065992746794256333307441181187998177598447149874664213812175214205301251 --run-dir=/nightly/current_run/scratch/master/prim_esc-sim-vcs/19.prim_esc_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test='' uvm_test_seq=''
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
Job cancelled because all of its dependencies failed or were killed. 1 test run
prim_esc None None
Job cancelled because one of its dependencies failed or was killed. 1 test run
prim_esc None None