Simulation Results: rom_ctrl/32kb

 
28/08/2026 21:54:34 DVSim: v1.49.0 sha: a099412 json Branch: master Tool: xcelium [unknown]
Validation stages
V1
0.00%
V2
18.31%
V2S
0.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 0 2 0.00
rom_ctrl_smoke 0.892s 0.000us 0 2 0.00
csr_hw_reset 0 1 0.00
rom_ctrl_csr_hw_reset 0.867s 0.000us 0 1 0.00
csr_rw 0 5 0.00
rom_ctrl_csr_rw 0.873s 0.000us 0 5 0.00
csr_bit_bash 0 1 0.00
rom_ctrl_csr_bit_bash 0.820s 0.000us 0 1 0.00
csr_aliasing 0 1 0.00
rom_ctrl_csr_aliasing 0.871s 0.000us 0 1 0.00
csr_mem_rw_with_rand_reset 0 5 0.00
rom_ctrl_csr_mem_rw_with_rand_reset 1.577s 0.000us 0 5 0.00
regwen_csr_and_corresponding_lockable_csr 0 6 0.00
rom_ctrl_csr_rw 0.873s 0.000us 0 5 0.00
rom_ctrl_csr_aliasing 0.871s 0.000us 0 1 0.00
mem_walk 0 1 0.00
rom_ctrl_mem_walk 0.850s 0.000us 0 1 0.00
mem_partial_access 0 1 0.00
rom_ctrl_mem_partial_access 0.845s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 0.912s 0.000us 0 2 0.00
stress_all 13 20 65.00
rom_ctrl_stress_all 10803.000s 0.000us 13 20 65.00
kmac_err_chk 0 2 0.00
rom_ctrl_kmac_err_chk 0.889s 0.000us 0 2 0.00
alert_test 0 10 0.00
rom_ctrl_alert_test 1.553s 0.000us 0 10 0.00
tl_d_oob_addr_access 0 25 0.00
rom_ctrl_tl_errors 0.881s 0.000us 0 25 0.00
tl_d_illegal_access 0 25 0.00
rom_ctrl_tl_errors 0.881s 0.000us 0 25 0.00
tl_d_outstanding_access 0 12 0.00
rom_ctrl_csr_hw_reset 0.867s 0.000us 0 1 0.00
rom_ctrl_csr_rw 0.873s 0.000us 0 5 0.00
rom_ctrl_csr_aliasing 0.871s 0.000us 0 1 0.00
rom_ctrl_same_csr_outstanding 0.980s 0.000us 0 5 0.00
tl_d_partial_access 0 12 0.00
rom_ctrl_csr_hw_reset 0.867s 0.000us 0 1 0.00
rom_ctrl_csr_rw 0.873s 0.000us 0 5 0.00
rom_ctrl_csr_aliasing 0.871s 0.000us 0 1 0.00
rom_ctrl_same_csr_outstanding 0.980s 0.000us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 0.872s 0.000us 0 20 0.00
passthru_mem_tl_intg_err 0 5 0.00
rom_ctrl_passthru_mem_tl_intg_err 0.873s 0.000us 0 5 0.00
tl_intg_err 0 30 0.00
rom_ctrl_sec_cm 0.905s 0.000us 0 5 0.00
rom_ctrl_tl_intg_err 0.888s 0.000us 0 25 0.00
prim_fsm_check 0 5 0.00
rom_ctrl_sec_cm 0.905s 0.000us 0 5 0.00
prim_count_check 0 5 0.00
rom_ctrl_sec_cm 0.905s 0.000us 0 5 0.00
sec_cm_checker_ctr_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 0.872s 0.000us 0 20 0.00
sec_cm_checker_ctrl_flow_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 0.872s 0.000us 0 20 0.00
sec_cm_checker_fsm_local_esc 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 0.872s 0.000us 0 20 0.00
sec_cm_compare_ctrl_flow_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 0.872s 0.000us 0 20 0.00
sec_cm_compare_ctr_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 0.872s 0.000us 0 20 0.00
sec_cm_compare_ctr_redun 0 5 0.00
rom_ctrl_sec_cm 0.905s 0.000us 0 5 0.00
sec_cm_fsm_sparse 0 5 0.00
rom_ctrl_sec_cm 0.905s 0.000us 0 5 0.00
sec_cm_mem_scramble 0 2 0.00
rom_ctrl_smoke 0.892s 0.000us 0 2 0.00
sec_cm_mem_digest 0 2 0.00
rom_ctrl_smoke 0.892s 0.000us 0 2 0.00
sec_cm_intersig_mubi 0 2 0.00
rom_ctrl_smoke 0.892s 0.000us 0 2 0.00
sec_cm_bus_integrity 0 25 0.00
rom_ctrl_tl_intg_err 0.888s 0.000us 0 25 0.00
sec_cm_bus_local_esc 0 22 0.00
rom_ctrl_corrupt_sig_fatal_chk 0.872s 0.000us 0 20 0.00
rom_ctrl_kmac_err_chk 0.889s 0.000us 0 2 0.00
sec_cm_mux_mubi 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 0.872s 0.000us 0 20 0.00
sec_cm_mux_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 0.872s 0.000us 0 20 0.00
sec_cm_ctrl_redun 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 0.872s 0.000us 0 20 0.00
sec_cm_ctrl_mem_integrity 0 5 0.00
rom_ctrl_passthru_mem_tl_intg_err 0.873s 0.000us 0 5 0.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
rom_ctrl_sec_cm 0.905s 0.000us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 20 0.00
rom_ctrl_stress_all_with_rand_reset 1.618s 0.000us 0 20 0.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 136 test runs
rom_ctrl_smoke 7035620791771490067211804875042659892593618668150726054982511684412514164686 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/0.rom_ctrl_smoke/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=2992299982 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/0.rom_ctrl_smoke.2992299982 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 0.rom_ctrl_smoke.2992299982 -covoverwrite +skip_middle_of_rom=1' seed=7035620791771490067211804875042659892593618668150726054982511684412514164686 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7035620791771490067211804875042659892593618668150726054982511684412514164686 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/0.rom_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_max_throughput_chk 30428687145276025324489976350742369873989593760884973032540831403388965382579 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/0.rom_ctrl_max_throughput_chk/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=675703219 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/0.rom_ctrl_max_throughput_chk.675703219 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 0.rom_ctrl_max_throughput_chk.675703219 -covoverwrite +skip_middle_of_rom=1' seed=30428687145276025324489976350742369873989593760884973032540831403388965382579 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30428687145276025324489976350742369873989593760884973032540831403388965382579 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/0.rom_ctrl_max_throughput_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 40751856098573672256859239926631766630328907416714209528751835981118628237217 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/0.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=2820738977 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.2820738977 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 0.rom_ctrl_corrupt_sig_fatal_chk.2820738977 -covoverwrite +skip_middle_of_rom=1' seed=40751856098573672256859239926631766630328907416714209528751835981118628237217 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40751856098573672256859239926631766630328907416714209528751835981118628237217 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/0.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_kmac_err_chk 79172638503087959097159593365929064280104865183769597063064030218283337541241 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/0.rom_ctrl_kmac_err_chk/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=460220025 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/0.rom_ctrl_kmac_err_chk.460220025 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 0.rom_ctrl_kmac_err_chk.460220025 -covoverwrite +skip_middle_of_rom=1' seed=79172638503087959097159593365929064280104865183769597063064030218283337541241 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79172638503087959097159593365929064280104865183769597063064030218283337541241 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/0.rom_ctrl_kmac_err_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_kmac_err_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 80921648123427926063450984879379555464122057450627589552188004151734409366110 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/0.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=438045278 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.438045278 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 0.rom_ctrl_stress_all_with_rand_reset.438045278 -covoverwrite +skip_middle_of_rom=1' seed=80921648123427926063450984879379555464122057450627589552188004151734409366110 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80921648123427926063450984879379555464122057450627589552188004151734409366110 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/0.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_sec_cm 105057355306385211249145919718010943346444347064852551713016692766816329862510 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/0.rom_ctrl_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=3898936686 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/0.rom_ctrl_sec_cm.3898936686 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 0.rom_ctrl_sec_cm.3898936686 -covoverwrite +skip_middle_of_rom=1' seed=105057355306385211249145919718010943346444347064852551713016692766816329862510 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105057355306385211249145919718010943346444347064852551713016692766816329862510 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/0.rom_ctrl_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_passthru_mem_tl_intg_err 65304082302388716521796920455523611004152206884005157149241048482273818921337 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/0.rom_ctrl_passthru_mem_tl_intg_err/latest run_opts='+run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1915046265 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.1915046265 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rom_ctrl_passthru_mem_tl_intg_err.1915046265 -covoverwrite +skip_middle_of_rom=1' seed=65304082302388716521796920455523611004152206884005157149241048482273818921337 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65304082302388716521796920455523611004152206884005157149241048482273818921337 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/0.rom_ctrl_passthru_mem_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 71735846600389037148983772553445882131389202157728751170964157094206947567213 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/0.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3409028717 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/0.rom_ctrl_tl_errors.3409028717 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rom_ctrl_tl_errors.3409028717 -covoverwrite +skip_middle_of_rom=1' seed=71735846600389037148983772553445882131389202157728751170964157094206947567213 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71735846600389037148983772553445882131389202157728751170964157094206947567213 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/0.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 61823143453691588189583780134589472536711376691144211446779959120527035506646 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/0.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3519586262 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.3519586262 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rom_ctrl_tl_intg_err.3519586262 -covoverwrite +skip_middle_of_rom=1' seed=61823143453691588189583780134589472536711376691144211446779959120527035506646 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61823143453691588189583780134589472536711376691144211446779959120527035506646 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/0.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_alert_test 101936692783580313187448643464620504667990538347849332592354004536532355192412 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/0.rom_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=4258469468 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/0.rom_ctrl_alert_test.4258469468 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 0.rom_ctrl_alert_test.4258469468 -covoverwrite +skip_middle_of_rom=1' seed=101936692783580313187448643464620504667990538347849332592354004536532355192412 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101936692783580313187448643464620504667990538347849332592354004536532355192412 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/0.rom_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_mem_walk 89783176705398967067244972987198720044767762338633251108095706026694664016964 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/0.rom_ctrl_mem_walk/latest run_opts='+csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3456128068 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/0.rom_ctrl_mem_walk.3456128068 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rom_ctrl_mem_walk.3456128068 -covoverwrite +skip_middle_of_rom=1' seed=89783176705398967067244972987198720044767762338633251108095706026694664016964 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89783176705398967067244972987198720044767762338633251108095706026694664016964 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/0.rom_ctrl_mem_walk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_mem_partial_access 74157354161662867417676782650711907074586529157755683447736356033429376859780 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/0.rom_ctrl_mem_partial_access/latest run_opts='+run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2181824132 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.2181824132 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rom_ctrl_mem_partial_access.2181824132 -covoverwrite +skip_middle_of_rom=1' seed=74157354161662867417676782650711907074586529157755683447736356033429376859780 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74157354161662867417676782650711907074586529157755683447736356033429376859780 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/0.rom_ctrl_mem_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_csr_hw_reset 98766829722936633418349207006223622136610094767623721752384100090127132362347 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/0.rom_ctrl_csr_hw_reset/latest run_opts='+csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2386527851 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2386527851 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rom_ctrl_csr_hw_reset.2386527851 -covoverwrite +skip_middle_of_rom=1' seed=98766829722936633418349207006223622136610094767623721752384100090127132362347 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98766829722936633418349207006223622136610094767623721752384100090127132362347 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/0.rom_ctrl_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_csr_rw 29253095738960928842892582268846205505224407015688907407113334360558304348417 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/0.rom_ctrl_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2133182721 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2133182721 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rom_ctrl_csr_rw.2133182721 -covoverwrite +skip_middle_of_rom=1' seed=29253095738960928842892582268846205505224407015688907407113334360558304348417 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29253095738960928842892582268846205505224407015688907407113334360558304348417 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/0.rom_ctrl_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_csr_bit_bash 11302931089039750742696842153925739856099249601741821306985271384948552614845 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/0.rom_ctrl_csr_bit_bash/latest run_opts='+csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2279719869 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.2279719869 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rom_ctrl_csr_bit_bash.2279719869 -covoverwrite +skip_middle_of_rom=1' seed=11302931089039750742696842153925739856099249601741821306985271384948552614845 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11302931089039750742696842153925739856099249601741821306985271384948552614845 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/0.rom_ctrl_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_csr_aliasing 56545326688054840759002682915339033020517883890628587005709716877161516427436 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/0.rom_ctrl_csr_aliasing/latest run_opts='+csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2883250348 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.2883250348 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rom_ctrl_csr_aliasing.2883250348 -covoverwrite +skip_middle_of_rom=1' seed=56545326688054840759002682915339033020517883890628587005709716877161516427436 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56545326688054840759002682915339033020517883890628587005709716877161516427436 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/0.rom_ctrl_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_same_csr_outstanding 80142599904849878079429445563155727469460200647536379772117645969767599933592 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/0.rom_ctrl_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2074314904 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.2074314904 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rom_ctrl_same_csr_outstanding.2074314904 -covoverwrite +skip_middle_of_rom=1' seed=80142599904849878079429445563155727469460200647536379772117645969767599933592 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80142599904849878079429445563155727469460200647536379772117645969767599933592 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/0.rom_ctrl_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_csr_mem_rw_with_rand_reset 22251089113989383005773924224441028388686615233393569274010566659634879779747 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2545406883 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.2545406883 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rom_ctrl_csr_mem_rw_with_rand_reset.2545406883 -covoverwrite +skip_middle_of_rom=1' seed=22251089113989383005773924224441028388686615233393569274010566659634879779747 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22251089113989383005773924224441028388686615233393569274010566659634879779747 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_smoke 82536135082417019752806894173251780030484941641939609142672017967330002660576 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/1.rom_ctrl_smoke/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=513731808 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/1.rom_ctrl_smoke.513731808 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 1.rom_ctrl_smoke.513731808 -covoverwrite +skip_middle_of_rom=1' seed=82536135082417019752806894173251780030484941641939609142672017967330002660576 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82536135082417019752806894173251780030484941641939609142672017967330002660576 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/1.rom_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_max_throughput_chk 60723229916698990038452039307871104003380996662343587125067478159932757404631 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/1.rom_ctrl_max_throughput_chk/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=4028656599 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/1.rom_ctrl_max_throughput_chk.4028656599 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 1.rom_ctrl_max_throughput_chk.4028656599 -covoverwrite +skip_middle_of_rom=1' seed=60723229916698990038452039307871104003380996662343587125067478159932757404631 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60723229916698990038452039307871104003380996662343587125067478159932757404631 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/1.rom_ctrl_max_throughput_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 76467064411592397500490971107902577609872739641446625078254874159835148360184 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/1.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=2112264696 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.2112264696 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 1.rom_ctrl_corrupt_sig_fatal_chk.2112264696 -covoverwrite +skip_middle_of_rom=1' seed=76467064411592397500490971107902577609872739641446625078254874159835148360184 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76467064411592397500490971107902577609872739641446625078254874159835148360184 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/1.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_kmac_err_chk 38401754360129551867101013393727967627990382619813997380964078863834377212788 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/1.rom_ctrl_kmac_err_chk/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=2831012724 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/1.rom_ctrl_kmac_err_chk.2831012724 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 1.rom_ctrl_kmac_err_chk.2831012724 -covoverwrite +skip_middle_of_rom=1' seed=38401754360129551867101013393727967627990382619813997380964078863834377212788 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38401754360129551867101013393727967627990382619813997380964078863834377212788 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/1.rom_ctrl_kmac_err_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_kmac_err_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 34062419480049968730322627619055273313205217489152642725623875944228804215027 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/1.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=845791475 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.845791475 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 1.rom_ctrl_stress_all_with_rand_reset.845791475 -covoverwrite +skip_middle_of_rom=1' seed=34062419480049968730322627619055273313205217489152642725623875944228804215027 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34062419480049968730322627619055273313205217489152642725623875944228804215027 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/1.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_sec_cm 92202978623302882055528925950032704967745443509197916687667248180839241506764 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/1.rom_ctrl_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=4160249804 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/1.rom_ctrl_sec_cm.4160249804 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 1.rom_ctrl_sec_cm.4160249804 -covoverwrite +skip_middle_of_rom=1' seed=92202978623302882055528925950032704967745443509197916687667248180839241506764 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92202978623302882055528925950032704967745443509197916687667248180839241506764 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/1.rom_ctrl_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_passthru_mem_tl_intg_err 10778148674519281785580733581516331264304027289629389870381607603388098895292 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/1.rom_ctrl_passthru_mem_tl_intg_err/latest run_opts='+run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2424921532 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.2424921532 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.rom_ctrl_passthru_mem_tl_intg_err.2424921532 -covoverwrite +skip_middle_of_rom=1' seed=10778148674519281785580733581516331264304027289629389870381607603388098895292 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10778148674519281785580733581516331264304027289629389870381607603388098895292 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/1.rom_ctrl_passthru_mem_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 5856160487605105210605248411015828953837361272802762614654371677004305637582 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/1.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3288965326 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/1.rom_ctrl_tl_errors.3288965326 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.rom_ctrl_tl_errors.3288965326 -covoverwrite +skip_middle_of_rom=1' seed=5856160487605105210605248411015828953837361272802762614654371677004305637582 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5856160487605105210605248411015828953837361272802762614654371677004305637582 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/1.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 98730442071404978872927321749679367782140773981780757118477063228393392424169 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/1.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1072940265 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.1072940265 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.rom_ctrl_tl_intg_err.1072940265 -covoverwrite +skip_middle_of_rom=1' seed=98730442071404978872927321749679367782140773981780757118477063228393392424169 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98730442071404978872927321749679367782140773981780757118477063228393392424169 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/1.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_alert_test 5044748516430325640025584804394843587070992129669568614326938275621642806202 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/1.rom_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=3330646970 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/1.rom_ctrl_alert_test.3330646970 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 1.rom_ctrl_alert_test.3330646970 -covoverwrite +skip_middle_of_rom=1' seed=5044748516430325640025584804394843587070992129669568614326938275621642806202 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5044748516430325640025584804394843587070992129669568614326938275621642806202 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/1.rom_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_csr_rw 71782973159883150913518625455977580194732291207782284516126142465794354645070 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/1.rom_ctrl_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3269396558 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/1.rom_ctrl_csr_rw.3269396558 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.rom_ctrl_csr_rw.3269396558 -covoverwrite +skip_middle_of_rom=1' seed=71782973159883150913518625455977580194732291207782284516126142465794354645070 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71782973159883150913518625455977580194732291207782284516126142465794354645070 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/1.rom_ctrl_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_same_csr_outstanding 48387555263421474312557173551966394134124598454990664483433269019715095397783 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/1.rom_ctrl_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3688531351 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.3688531351 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.rom_ctrl_same_csr_outstanding.3688531351 -covoverwrite +skip_middle_of_rom=1' seed=48387555263421474312557173551966394134124598454990664483433269019715095397783 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48387555263421474312557173551966394134124598454990664483433269019715095397783 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/1.rom_ctrl_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_csr_mem_rw_with_rand_reset 23966825298529897915824765688661313640688628242709750687280324471583424462229 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3631824277 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.3631824277 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.rom_ctrl_csr_mem_rw_with_rand_reset.3631824277 -covoverwrite +skip_middle_of_rom=1' seed=23966825298529897915824765688661313640688628242709750687280324471583424462229 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23966825298529897915824765688661313640688628242709750687280324471583424462229 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 76170038554990441476671997195231459611983582616237910915140899013351111171636 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/2.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=2279644724 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.2279644724 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 2.rom_ctrl_corrupt_sig_fatal_chk.2279644724 -covoverwrite +skip_middle_of_rom=1' seed=76170038554990441476671997195231459611983582616237910915140899013351111171636 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76170038554990441476671997195231459611983582616237910915140899013351111171636 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/2.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 35080117073188633699144237747063387787918128400429764429258290796822462795473 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/2.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=1637682897 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.1637682897 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 2.rom_ctrl_stress_all_with_rand_reset.1637682897 -covoverwrite +skip_middle_of_rom=1' seed=35080117073188633699144237747063387787918128400429764429258290796822462795473 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35080117073188633699144237747063387787918128400429764429258290796822462795473 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/2.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_sec_cm 86974711335643823703216178825612992985276912827497905241724393314492382942875 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/2.rom_ctrl_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=3085932187 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/2.rom_ctrl_sec_cm.3085932187 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 2.rom_ctrl_sec_cm.3085932187 -covoverwrite +skip_middle_of_rom=1' seed=86974711335643823703216178825612992985276912827497905241724393314492382942875 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86974711335643823703216178825612992985276912827497905241724393314492382942875 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/2.rom_ctrl_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_passthru_mem_tl_intg_err 37084542262163112194812323188085307947594682536393271832982367217731173136170 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/2.rom_ctrl_passthru_mem_tl_intg_err/latest run_opts='+run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3999577898 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.3999577898 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.rom_ctrl_passthru_mem_tl_intg_err.3999577898 -covoverwrite +skip_middle_of_rom=1' seed=37084542262163112194812323188085307947594682536393271832982367217731173136170 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37084542262163112194812323188085307947594682536393271832982367217731173136170 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/2.rom_ctrl_passthru_mem_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 51332496149942266179705442191510125149730668721373845197497973675034315486894 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/2.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4065228462 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/2.rom_ctrl_tl_errors.4065228462 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.rom_ctrl_tl_errors.4065228462 -covoverwrite +skip_middle_of_rom=1' seed=51332496149942266179705442191510125149730668721373845197497973675034315486894 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51332496149942266179705442191510125149730668721373845197497973675034315486894 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/2.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 72140663246545939574943037008674358939449689493386271228565376393742216839270 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/2.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2042085478 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2042085478 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.rom_ctrl_tl_intg_err.2042085478 -covoverwrite +skip_middle_of_rom=1' seed=72140663246545939574943037008674358939449689493386271228565376393742216839270 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72140663246545939574943037008674358939449689493386271228565376393742216839270 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/2.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_alert_test 43147070724378949127998442608018864441656934256320975348571962832983204065492 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/2.rom_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=1651798228 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/2.rom_ctrl_alert_test.1651798228 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 2.rom_ctrl_alert_test.1651798228 -covoverwrite +skip_middle_of_rom=1' seed=43147070724378949127998442608018864441656934256320975348571962832983204065492 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43147070724378949127998442608018864441656934256320975348571962832983204065492 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/2.rom_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_csr_rw 4112358947931685441145572953581691456626208516902997092877546872683040585068 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/2.rom_ctrl_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2987636076 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2987636076 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.rom_ctrl_csr_rw.2987636076 -covoverwrite +skip_middle_of_rom=1' seed=4112358947931685441145572953581691456626208516902997092877546872683040585068 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4112358947931685441145572953581691456626208516902997092877546872683040585068 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/2.rom_ctrl_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_same_csr_outstanding 31610269775721144941303740513353577622533672895193012664495397321808236335417 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/2.rom_ctrl_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2798473529 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.2798473529 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.rom_ctrl_same_csr_outstanding.2798473529 -covoverwrite +skip_middle_of_rom=1' seed=31610269775721144941303740513353577622533672895193012664495397321808236335417 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31610269775721144941303740513353577622533672895193012664495397321808236335417 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/2.rom_ctrl_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_csr_mem_rw_with_rand_reset 16824518301417940785407439667904462194426703148260451969209946113818017062735 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3477266255 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.3477266255 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.rom_ctrl_csr_mem_rw_with_rand_reset.3477266255 -covoverwrite +skip_middle_of_rom=1' seed=16824518301417940785407439667904462194426703148260451969209946113818017062735 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16824518301417940785407439667904462194426703148260451969209946113818017062735 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 98420707416722344312771867577899220792974048679463059584244139649987083682715 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/3.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=1012056987 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.1012056987 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 3.rom_ctrl_corrupt_sig_fatal_chk.1012056987 -covoverwrite +skip_middle_of_rom=1' seed=98420707416722344312771867577899220792974048679463059584244139649987083682715 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98420707416722344312771867577899220792974048679463059584244139649987083682715 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/3.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 91401789575916902202148914650869850866330852773522057703866832501077480948021 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/3.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=2030682421 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.2030682421 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 3.rom_ctrl_stress_all_with_rand_reset.2030682421 -covoverwrite +skip_middle_of_rom=1' seed=91401789575916902202148914650869850866330852773522057703866832501077480948021 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91401789575916902202148914650869850866330852773522057703866832501077480948021 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/3.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_sec_cm 51655957953959463212437881152375793499245980681742581382899174437525542544221 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/3.rom_ctrl_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=1969365853 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/3.rom_ctrl_sec_cm.1969365853 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 3.rom_ctrl_sec_cm.1969365853 -covoverwrite +skip_middle_of_rom=1' seed=51655957953959463212437881152375793499245980681742581382899174437525542544221 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51655957953959463212437881152375793499245980681742581382899174437525542544221 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/3.rom_ctrl_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_passthru_mem_tl_intg_err 23473585824169542112826156994154175017546717263248778615633431795655557687322 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/3.rom_ctrl_passthru_mem_tl_intg_err/latest run_opts='+run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3954616346 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3954616346 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.rom_ctrl_passthru_mem_tl_intg_err.3954616346 -covoverwrite +skip_middle_of_rom=1' seed=23473585824169542112826156994154175017546717263248778615633431795655557687322 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23473585824169542112826156994154175017546717263248778615633431795655557687322 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/3.rom_ctrl_passthru_mem_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 65954111769788624784824696117414955788367095775888258786677297514523715150395 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/3.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=37986875 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/3.rom_ctrl_tl_errors.37986875 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.rom_ctrl_tl_errors.37986875 -covoverwrite +skip_middle_of_rom=1' seed=65954111769788624784824696117414955788367095775888258786677297514523715150395 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65954111769788624784824696117414955788367095775888258786677297514523715150395 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/3.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 107992116086753266680613945509678709521087749200107089647111305010342718577582 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/3.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2521537454 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.2521537454 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.rom_ctrl_tl_intg_err.2521537454 -covoverwrite +skip_middle_of_rom=1' seed=107992116086753266680613945509678709521087749200107089647111305010342718577582 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107992116086753266680613945509678709521087749200107089647111305010342718577582 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/3.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_alert_test 25601813798991698517086584917412456900058454392729942073933728673507642504083 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/3.rom_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=1834546067 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/3.rom_ctrl_alert_test.1834546067 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 3.rom_ctrl_alert_test.1834546067 -covoverwrite +skip_middle_of_rom=1' seed=25601813798991698517086584917412456900058454392729942073933728673507642504083 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25601813798991698517086584917412456900058454392729942073933728673507642504083 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/3.rom_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_csr_rw 40174865877131479420251398988345212658287309270891127043235901552242097851107 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/3.rom_ctrl_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3042904803 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3042904803 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.rom_ctrl_csr_rw.3042904803 -covoverwrite +skip_middle_of_rom=1' seed=40174865877131479420251398988345212658287309270891127043235901552242097851107 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40174865877131479420251398988345212658287309270891127043235901552242097851107 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/3.rom_ctrl_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_same_csr_outstanding 7163571261964983626665736615186065635681018372811060616285990647988196094582 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/3.rom_ctrl_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2033594998 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.2033594998 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.rom_ctrl_same_csr_outstanding.2033594998 -covoverwrite +skip_middle_of_rom=1' seed=7163571261964983626665736615186065635681018372811060616285990647988196094582 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7163571261964983626665736615186065635681018372811060616285990647988196094582 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/3.rom_ctrl_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_csr_mem_rw_with_rand_reset 58054380788067689906347067414241554214078183176209011587363481801548327083658 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3270565514 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3270565514 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.rom_ctrl_csr_mem_rw_with_rand_reset.3270565514 -covoverwrite +skip_middle_of_rom=1' seed=58054380788067689906347067414241554214078183176209011587363481801548327083658 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58054380788067689906347067414241554214078183176209011587363481801548327083658 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 63334277912567932833317346949600927928216208397906430562609047284828903103692 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/4.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=3559709900 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.3559709900 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 4.rom_ctrl_corrupt_sig_fatal_chk.3559709900 -covoverwrite +skip_middle_of_rom=1' seed=63334277912567932833317346949600927928216208397906430562609047284828903103692 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63334277912567932833317346949600927928216208397906430562609047284828903103692 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/4.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 89596465733050257385393188552865987520347834497141310523573897486646039189735 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/4.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=4052130023 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.4052130023 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 4.rom_ctrl_stress_all_with_rand_reset.4052130023 -covoverwrite +skip_middle_of_rom=1' seed=89596465733050257385393188552865987520347834497141310523573897486646039189735 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89596465733050257385393188552865987520347834497141310523573897486646039189735 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/4.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_sec_cm 26821126503331710043916324090168481708139253364723219533680420378905204895871 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/4.rom_ctrl_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=730738815 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/4.rom_ctrl_sec_cm.730738815 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 4.rom_ctrl_sec_cm.730738815 -covoverwrite +skip_middle_of_rom=1' seed=26821126503331710043916324090168481708139253364723219533680420378905204895871 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26821126503331710043916324090168481708139253364723219533680420378905204895871 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/4.rom_ctrl_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_passthru_mem_tl_intg_err 51053222038285938576670164596430281076393774757915869642628509377247896017377 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/4.rom_ctrl_passthru_mem_tl_intg_err/latest run_opts='+run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1762793953 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.1762793953 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.rom_ctrl_passthru_mem_tl_intg_err.1762793953 -covoverwrite +skip_middle_of_rom=1' seed=51053222038285938576670164596430281076393774757915869642628509377247896017377 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51053222038285938576670164596430281076393774757915869642628509377247896017377 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/4.rom_ctrl_passthru_mem_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 50003177690848720089833587336939523912548595412652697563096380257167440323739 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/4.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2767430811 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/4.rom_ctrl_tl_errors.2767430811 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.rom_ctrl_tl_errors.2767430811 -covoverwrite +skip_middle_of_rom=1' seed=50003177690848720089833587336939523912548595412652697563096380257167440323739 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50003177690848720089833587336939523912548595412652697563096380257167440323739 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/4.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 59104227759993842985270009715877474182831635487517168909882822538089169383433 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/4.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3755175945 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.3755175945 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.rom_ctrl_tl_intg_err.3755175945 -covoverwrite +skip_middle_of_rom=1' seed=59104227759993842985270009715877474182831635487517168909882822538089169383433 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=59104227759993842985270009715877474182831635487517168909882822538089169383433 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/4.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_alert_test 54140986525079807238758259626480484866426933621022243075921563183126437519083 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/4.rom_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=1165057771 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/4.rom_ctrl_alert_test.1165057771 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 4.rom_ctrl_alert_test.1165057771 -covoverwrite +skip_middle_of_rom=1' seed=54140986525079807238758259626480484866426933621022243075921563183126437519083 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54140986525079807238758259626480484866426933621022243075921563183126437519083 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/4.rom_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_csr_rw 15475826710089247914995932680915482162429875268407925772476849501012314541488 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/4.rom_ctrl_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2831666608 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2831666608 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.rom_ctrl_csr_rw.2831666608 -covoverwrite +skip_middle_of_rom=1' seed=15475826710089247914995932680915482162429875268407925772476849501012314541488 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15475826710089247914995932680915482162429875268407925772476849501012314541488 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/4.rom_ctrl_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_same_csr_outstanding 106260256968943073121833475279882295782585753306676970070297768062148791801824 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/4.rom_ctrl_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3035404256 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.3035404256 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.rom_ctrl_same_csr_outstanding.3035404256 -covoverwrite +skip_middle_of_rom=1' seed=106260256968943073121833475279882295782585753306676970070297768062148791801824 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106260256968943073121833475279882295782585753306676970070297768062148791801824 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/4.rom_ctrl_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_csr_mem_rw_with_rand_reset 91490247103852110682002220943697647201812045300362011276590544463221326456998 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=207988902 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.207988902 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.rom_ctrl_csr_mem_rw_with_rand_reset.207988902 -covoverwrite +skip_middle_of_rom=1' seed=91490247103852110682002220943697647201812045300362011276590544463221326456998 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91490247103852110682002220943697647201812045300362011276590544463221326456998 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 103958931829140764078853772517015479802446794372541471422103546177124930879164 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/5.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=1609498300 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1609498300 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 5.rom_ctrl_corrupt_sig_fatal_chk.1609498300 -covoverwrite +skip_middle_of_rom=1' seed=103958931829140764078853772517015479802446794372541471422103546177124930879164 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103958931829140764078853772517015479802446794372541471422103546177124930879164 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/5.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 26151310717585626637988429002368906578963679591257920829080778547713369559175 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/5.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=3010842759 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.3010842759 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 5.rom_ctrl_stress_all_with_rand_reset.3010842759 -covoverwrite +skip_middle_of_rom=1' seed=26151310717585626637988429002368906578963679591257920829080778547713369559175 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26151310717585626637988429002368906578963679591257920829080778547713369559175 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/5.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 7055568456322852392430695561403080628001935514797101332185236425635563553102 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/5.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3813917006 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3813917006 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.rom_ctrl_tl_errors.3813917006 -covoverwrite +skip_middle_of_rom=1' seed=7055568456322852392430695561403080628001935514797101332185236425635563553102 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7055568456322852392430695561403080628001935514797101332185236425635563553102 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/5.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 36483898860453069318130851848403858768357226202203126130686364643364823062018 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/5.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2805159426 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2805159426 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.rom_ctrl_tl_intg_err.2805159426 -covoverwrite +skip_middle_of_rom=1' seed=36483898860453069318130851848403858768357226202203126130686364643364823062018 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36483898860453069318130851848403858768357226202203126130686364643364823062018 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/5.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_alert_test 72538220626495766146727446192912300903724395808163604942514613676280237758155 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/5.rom_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=774870731 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/5.rom_ctrl_alert_test.774870731 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 5.rom_ctrl_alert_test.774870731 -covoverwrite +skip_middle_of_rom=1' seed=72538220626495766146727446192912300903724395808163604942514613676280237758155 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72538220626495766146727446192912300903724395808163604942514613676280237758155 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/5.rom_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 27175577908015731503355836722058735345907328380401356350607358177105950605505 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/6.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=2948137153 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2948137153 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 6.rom_ctrl_corrupt_sig_fatal_chk.2948137153 -covoverwrite +skip_middle_of_rom=1' seed=27175577908015731503355836722058735345907328380401356350607358177105950605505 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27175577908015731503355836722058735345907328380401356350607358177105950605505 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/6.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 80045701649785511064558104647485146645545521980098792630330648505449623332087 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/6.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=3428590839 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.3428590839 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 6.rom_ctrl_stress_all_with_rand_reset.3428590839 -covoverwrite +skip_middle_of_rom=1' seed=80045701649785511064558104647485146645545521980098792630330648505449623332087 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80045701649785511064558104647485146645545521980098792630330648505449623332087 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/6.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 59297272588138579741949374404436854119850792600617740620501760326809393783371 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/6.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3109249611 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/6.rom_ctrl_tl_errors.3109249611 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.rom_ctrl_tl_errors.3109249611 -covoverwrite +skip_middle_of_rom=1' seed=59297272588138579741949374404436854119850792600617740620501760326809393783371 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=59297272588138579741949374404436854119850792600617740620501760326809393783371 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/6.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 50185503653360781942937364351168021283345225144186418911275350553323806403945 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/6.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2182884713 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.2182884713 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.rom_ctrl_tl_intg_err.2182884713 -covoverwrite +skip_middle_of_rom=1' seed=50185503653360781942937364351168021283345225144186418911275350553323806403945 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50185503653360781942937364351168021283345225144186418911275350553323806403945 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/6.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_alert_test 15859680348990046576566062094902898537658965287633752123410632348919169379021 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/6.rom_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=1111059149 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/6.rom_ctrl_alert_test.1111059149 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 6.rom_ctrl_alert_test.1111059149 -covoverwrite +skip_middle_of_rom=1' seed=15859680348990046576566062094902898537658965287633752123410632348919169379021 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15859680348990046576566062094902898537658965287633752123410632348919169379021 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/6.rom_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 110264450128724127034772456627111204752541143614328922527103511379616225931368 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/7.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=1898033256 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1898033256 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 7.rom_ctrl_corrupt_sig_fatal_chk.1898033256 -covoverwrite +skip_middle_of_rom=1' seed=110264450128724127034772456627111204752541143614328922527103511379616225931368 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110264450128724127034772456627111204752541143614328922527103511379616225931368 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/7.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 87690123119170818585826505439066296884786405083413456036014825579226312994128 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/7.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=3964398928 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.3964398928 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 7.rom_ctrl_stress_all_with_rand_reset.3964398928 -covoverwrite +skip_middle_of_rom=1' seed=87690123119170818585826505439066296884786405083413456036014825579226312994128 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87690123119170818585826505439066296884786405083413456036014825579226312994128 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/7.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 78835912424752811816947737686157326302619734876873571136447861540446944985990 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/7.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2607121286 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/7.rom_ctrl_tl_errors.2607121286 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.rom_ctrl_tl_errors.2607121286 -covoverwrite +skip_middle_of_rom=1' seed=78835912424752811816947737686157326302619734876873571136447861540446944985990 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78835912424752811816947737686157326302619734876873571136447861540446944985990 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/7.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 94604261966806029178544073068257378015501376404169791623655168328441675849056 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/7.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=451616096 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.451616096 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.rom_ctrl_tl_intg_err.451616096 -covoverwrite +skip_middle_of_rom=1' seed=94604261966806029178544073068257378015501376404169791623655168328441675849056 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94604261966806029178544073068257378015501376404169791623655168328441675849056 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/7.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_alert_test 40195414073045667640301961983464764830745916472799609610935527233842185487531 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/7.rom_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=3313747115 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/7.rom_ctrl_alert_test.3313747115 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 7.rom_ctrl_alert_test.3313747115 -covoverwrite +skip_middle_of_rom=1' seed=40195414073045667640301961983464764830745916472799609610935527233842185487531 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40195414073045667640301961983464764830745916472799609610935527233842185487531 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/7.rom_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 114432218011763823333518159102059313261886163773975663479515177470916835870740 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/8.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=3867346964 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.3867346964 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 8.rom_ctrl_corrupt_sig_fatal_chk.3867346964 -covoverwrite +skip_middle_of_rom=1' seed=114432218011763823333518159102059313261886163773975663479515177470916835870740 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114432218011763823333518159102059313261886163773975663479515177470916835870740 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/8.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 105176767458402558153661187151811112312652765356249844458916926520858578184884 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/8.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=2358962868 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.2358962868 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 8.rom_ctrl_stress_all_with_rand_reset.2358962868 -covoverwrite +skip_middle_of_rom=1' seed=105176767458402558153661187151811112312652765356249844458916926520858578184884 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105176767458402558153661187151811112312652765356249844458916926520858578184884 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/8.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 97713389404253785876790743271311413209894383116532032218027271620621573646606 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/8.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2724030734 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2724030734 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.rom_ctrl_tl_errors.2724030734 -covoverwrite +skip_middle_of_rom=1' seed=97713389404253785876790743271311413209894383116532032218027271620621573646606 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97713389404253785876790743271311413209894383116532032218027271620621573646606 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/8.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 88056627826995429310734106717346471876517753884770443889278651922366781343905 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/8.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2421835937 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.2421835937 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.rom_ctrl_tl_intg_err.2421835937 -covoverwrite +skip_middle_of_rom=1' seed=88056627826995429310734106717346471876517753884770443889278651922366781343905 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88056627826995429310734106717346471876517753884770443889278651922366781343905 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/8.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_alert_test 86258977479315919493818214269339122410219504783712842371095098497797601653240 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/8.rom_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=3878711800 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/8.rom_ctrl_alert_test.3878711800 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 8.rom_ctrl_alert_test.3878711800 -covoverwrite +skip_middle_of_rom=1' seed=86258977479315919493818214269339122410219504783712842371095098497797601653240 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86258977479315919493818214269339122410219504783712842371095098497797601653240 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/8.rom_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 2796163268252671359884082275764488642217625682651632798468700499634041628274 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/9.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=2514986610 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.2514986610 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 9.rom_ctrl_corrupt_sig_fatal_chk.2514986610 -covoverwrite +skip_middle_of_rom=1' seed=2796163268252671359884082275764488642217625682651632798468700499634041628274 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2796163268252671359884082275764488642217625682651632798468700499634041628274 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/9.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 59464496100295033576708006425365956862264340979996841652843377103578382384554 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/9.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=1607384490 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.1607384490 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 9.rom_ctrl_stress_all_with_rand_reset.1607384490 -covoverwrite +skip_middle_of_rom=1' seed=59464496100295033576708006425365956862264340979996841652843377103578382384554 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=59464496100295033576708006425365956862264340979996841652843377103578382384554 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/9.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 109223611633811679954427005483577223332017045482827529297049376943576213674167 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/9.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1935202487 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/9.rom_ctrl_tl_errors.1935202487 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.rom_ctrl_tl_errors.1935202487 -covoverwrite +skip_middle_of_rom=1' seed=109223611633811679954427005483577223332017045482827529297049376943576213674167 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109223611633811679954427005483577223332017045482827529297049376943576213674167 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/9.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 83066226249302767184645416557487210936249303410697019572844849961713063938603 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/9.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=571197995 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.571197995 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.rom_ctrl_tl_intg_err.571197995 -covoverwrite +skip_middle_of_rom=1' seed=83066226249302767184645416557487210936249303410697019572844849961713063938603 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83066226249302767184645416557487210936249303410697019572844849961713063938603 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/9.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_alert_test 30660343217119832677779162927629516024587803530732444952298909098115375976865 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/9.rom_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=845042081 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/9.rom_ctrl_alert_test.845042081 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 9.rom_ctrl_alert_test.845042081 -covoverwrite +skip_middle_of_rom=1' seed=30660343217119832677779162927629516024587803530732444952298909098115375976865 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30660343217119832677779162927629516024587803530732444952298909098115375976865 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/9.rom_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 76441155178075912858971559052404434206798344735433290826781709171400583690471 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/10.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=788281575 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.788281575 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 10.rom_ctrl_corrupt_sig_fatal_chk.788281575 -covoverwrite +skip_middle_of_rom=1' seed=76441155178075912858971559052404434206798344735433290826781709171400583690471 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76441155178075912858971559052404434206798344735433290826781709171400583690471 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/10.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 103444781238266262066298353464289694346013996452064005473890235765561867483432 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/10.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=4054432040 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.4054432040 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 10.rom_ctrl_stress_all_with_rand_reset.4054432040 -covoverwrite +skip_middle_of_rom=1' seed=103444781238266262066298353464289694346013996452064005473890235765561867483432 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103444781238266262066298353464289694346013996452064005473890235765561867483432 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/10.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 101604220555088498981534225018816667443603275636220898410134805923029557745443 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/10.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=28350243 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/10.rom_ctrl_tl_errors.28350243 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 10.rom_ctrl_tl_errors.28350243 -covoverwrite +skip_middle_of_rom=1' seed=101604220555088498981534225018816667443603275636220898410134805923029557745443 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101604220555088498981534225018816667443603275636220898410134805923029557745443 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/10.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 67037025314542966114183212385283253852910019827301254045924455708416340722891 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/10.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2050294987 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.2050294987 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 10.rom_ctrl_tl_intg_err.2050294987 -covoverwrite +skip_middle_of_rom=1' seed=67037025314542966114183212385283253852910019827301254045924455708416340722891 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67037025314542966114183212385283253852910019827301254045924455708416340722891 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/10.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 81634778340669984021375991302438662735657574564930406302630627399341501602643 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/11.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=962354003 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.962354003 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 11.rom_ctrl_corrupt_sig_fatal_chk.962354003 -covoverwrite +skip_middle_of_rom=1' seed=81634778340669984021375991302438662735657574564930406302630627399341501602643 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81634778340669984021375991302438662735657574564930406302630627399341501602643 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/11.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 62449073697401128984696218446953368823077803244906705464031719944613408219830 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/11.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=4098040502 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.4098040502 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 11.rom_ctrl_stress_all_with_rand_reset.4098040502 -covoverwrite +skip_middle_of_rom=1' seed=62449073697401128984696218446953368823077803244906705464031719944613408219830 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62449073697401128984696218446953368823077803244906705464031719944613408219830 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/11.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 91185521331537930845038823499389619761098327297011470730895594412564529582059 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/11.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3618410475 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/11.rom_ctrl_tl_errors.3618410475 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 11.rom_ctrl_tl_errors.3618410475 -covoverwrite +skip_middle_of_rom=1' seed=91185521331537930845038823499389619761098327297011470730895594412564529582059 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91185521331537930845038823499389619761098327297011470730895594412564529582059 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/11.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 55379604802267529807114384928929181353232561197982475501722109649273504216020 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/11.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2671850452 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.2671850452 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 11.rom_ctrl_tl_intg_err.2671850452 -covoverwrite +skip_middle_of_rom=1' seed=55379604802267529807114384928929181353232561197982475501722109649273504216020 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55379604802267529807114384928929181353232561197982475501722109649273504216020 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/11.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 68894931172814328067626770285179211079894209059768984331795007844230984470998 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/12.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=2647232982 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.2647232982 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 12.rom_ctrl_corrupt_sig_fatal_chk.2647232982 -covoverwrite +skip_middle_of_rom=1' seed=68894931172814328067626770285179211079894209059768984331795007844230984470998 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68894931172814328067626770285179211079894209059768984331795007844230984470998 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/12.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 97855362514646110475163844954158237746231084962049971488335791752818150304280 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/12.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=1134520856 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.1134520856 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 12.rom_ctrl_stress_all_with_rand_reset.1134520856 -covoverwrite +skip_middle_of_rom=1' seed=97855362514646110475163844954158237746231084962049971488335791752818150304280 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97855362514646110475163844954158237746231084962049971488335791752818150304280 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/12.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 44097679504935112323902354893061101739164576395938300847237178623998552143462 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/12.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2500032102 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/12.rom_ctrl_tl_errors.2500032102 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 12.rom_ctrl_tl_errors.2500032102 -covoverwrite +skip_middle_of_rom=1' seed=44097679504935112323902354893061101739164576395938300847237178623998552143462 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44097679504935112323902354893061101739164576395938300847237178623998552143462 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/12.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 62879095879890335498416955099043386466475404027605780400643270900207917676621 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/12.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2762946637 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2762946637 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 12.rom_ctrl_tl_intg_err.2762946637 -covoverwrite +skip_middle_of_rom=1' seed=62879095879890335498416955099043386466475404027605780400643270900207917676621 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62879095879890335498416955099043386466475404027605780400643270900207917676621 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/12.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 39765013476161925180034457435987596966639955068329165580817469024280913241009 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/13.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=3162629041 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3162629041 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 13.rom_ctrl_corrupt_sig_fatal_chk.3162629041 -covoverwrite +skip_middle_of_rom=1' seed=39765013476161925180034457435987596966639955068329165580817469024280913241009 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39765013476161925180034457435987596966639955068329165580817469024280913241009 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/13.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 115751326624191866998657236065591163307618857122274591395196812772146218434476 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/13.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=454983596 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.454983596 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 13.rom_ctrl_stress_all_with_rand_reset.454983596 -covoverwrite +skip_middle_of_rom=1' seed=115751326624191866998657236065591163307618857122274591395196812772146218434476 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115751326624191866998657236065591163307618857122274591395196812772146218434476 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/13.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 84703401304822020191167680104050844865350389189597476278791886894463397156925 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/13.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1606965309 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/13.rom_ctrl_tl_errors.1606965309 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 13.rom_ctrl_tl_errors.1606965309 -covoverwrite +skip_middle_of_rom=1' seed=84703401304822020191167680104050844865350389189597476278791886894463397156925 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84703401304822020191167680104050844865350389189597476278791886894463397156925 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/13.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 30132482280224938961953080661044327861627425458496837255151912283902712632116 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/13.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=635065140 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.635065140 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 13.rom_ctrl_tl_intg_err.635065140 -covoverwrite +skip_middle_of_rom=1' seed=30132482280224938961953080661044327861627425458496837255151912283902712632116 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30132482280224938961953080661044327861627425458496837255151912283902712632116 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/13.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 83359744278224385111559386745990738576673526104746956346232719267009857967232 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/14.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=3223180416 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.3223180416 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 14.rom_ctrl_corrupt_sig_fatal_chk.3223180416 -covoverwrite +skip_middle_of_rom=1' seed=83359744278224385111559386745990738576673526104746956346232719267009857967232 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83359744278224385111559386745990738576673526104746956346232719267009857967232 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/14.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 104602709647733360846724496133047721929889814401060561503768256281943194961255 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/14.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=3554379111 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.3554379111 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 14.rom_ctrl_stress_all_with_rand_reset.3554379111 -covoverwrite +skip_middle_of_rom=1' seed=104602709647733360846724496133047721929889814401060561503768256281943194961255 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104602709647733360846724496133047721929889814401060561503768256281943194961255 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/14.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 48703689051304991021124441848318856835490371938948099068848447597538139149522 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/14.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1742705874 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/14.rom_ctrl_tl_errors.1742705874 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 14.rom_ctrl_tl_errors.1742705874 -covoverwrite +skip_middle_of_rom=1' seed=48703689051304991021124441848318856835490371938948099068848447597538139149522 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48703689051304991021124441848318856835490371938948099068848447597538139149522 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/14.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 111483463473766984340968995213574991748049769709091302162350203764833520708850 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/14.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3115314418 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.3115314418 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 14.rom_ctrl_tl_intg_err.3115314418 -covoverwrite +skip_middle_of_rom=1' seed=111483463473766984340968995213574991748049769709091302162350203764833520708850 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111483463473766984340968995213574991748049769709091302162350203764833520708850 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/14.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 76314281916125668661786476149519353858593821618484139169854057137638249001095 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/15.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=22737031 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.22737031 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 15.rom_ctrl_corrupt_sig_fatal_chk.22737031 -covoverwrite +skip_middle_of_rom=1' seed=76314281916125668661786476149519353858593821618484139169854057137638249001095 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76314281916125668661786476149519353858593821618484139169854057137638249001095 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/15.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 21456071937785002393176298631554539996884664832556818491589771020938365893283 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/15.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=3382966947 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.3382966947 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 15.rom_ctrl_stress_all_with_rand_reset.3382966947 -covoverwrite +skip_middle_of_rom=1' seed=21456071937785002393176298631554539996884664832556818491589771020938365893283 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21456071937785002393176298631554539996884664832556818491589771020938365893283 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/15.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 27805295437315821136608915840077143269167474410846408008412177692717450453549 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/15.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3904823853 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3904823853 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 15.rom_ctrl_tl_errors.3904823853 -covoverwrite +skip_middle_of_rom=1' seed=27805295437315821136608915840077143269167474410846408008412177692717450453549 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27805295437315821136608915840077143269167474410846408008412177692717450453549 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/15.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 109405380238408954279637087171161045509429257725140899614570356260138682633784 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/15.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2436320824 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.2436320824 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 15.rom_ctrl_tl_intg_err.2436320824 -covoverwrite +skip_middle_of_rom=1' seed=109405380238408954279637087171161045509429257725140899614570356260138682633784 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109405380238408954279637087171161045509429257725140899614570356260138682633784 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/15.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 70247650265699674486713800403080729137638253808871769105874062869533204113224 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/16.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=2782619464 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.2782619464 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 16.rom_ctrl_corrupt_sig_fatal_chk.2782619464 -covoverwrite +skip_middle_of_rom=1' seed=70247650265699674486713800403080729137638253808871769105874062869533204113224 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70247650265699674486713800403080729137638253808871769105874062869533204113224 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/16.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 79716647211898015300481249494918719779722523785183812150949310365764666216848 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/16.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=2094223760 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.2094223760 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 16.rom_ctrl_stress_all_with_rand_reset.2094223760 -covoverwrite +skip_middle_of_rom=1' seed=79716647211898015300481249494918719779722523785183812150949310365764666216848 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79716647211898015300481249494918719779722523785183812150949310365764666216848 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/16.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 16418326142229092436019957116441255655603647418107687652705198505180883560266 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/16.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2307368778 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/16.rom_ctrl_tl_errors.2307368778 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 16.rom_ctrl_tl_errors.2307368778 -covoverwrite +skip_middle_of_rom=1' seed=16418326142229092436019957116441255655603647418107687652705198505180883560266 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16418326142229092436019957116441255655603647418107687652705198505180883560266 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/16.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 1699903654059906205702907929291743069964139152948584337834566881268852950829 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/16.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2150991661 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2150991661 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 16.rom_ctrl_tl_intg_err.2150991661 -covoverwrite +skip_middle_of_rom=1' seed=1699903654059906205702907929291743069964139152948584337834566881268852950829 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1699903654059906205702907929291743069964139152948584337834566881268852950829 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/16.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 99950335855847755006146890423688902432443574480587928758036671088649857915539 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/17.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=2607012499 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.2607012499 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 17.rom_ctrl_corrupt_sig_fatal_chk.2607012499 -covoverwrite +skip_middle_of_rom=1' seed=99950335855847755006146890423688902432443574480587928758036671088649857915539 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99950335855847755006146890423688902432443574480587928758036671088649857915539 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/17.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 114478690894378628240022099360725017223920158592546868616766339548282980263886 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/17.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=2304370638 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.2304370638 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 17.rom_ctrl_stress_all_with_rand_reset.2304370638 -covoverwrite +skip_middle_of_rom=1' seed=114478690894378628240022099360725017223920158592546868616766339548282980263886 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114478690894378628240022099360725017223920158592546868616766339548282980263886 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/17.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 40311731624653311551197245166160388394599402991031802440446277068126476782383 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/17.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3061009199 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/17.rom_ctrl_tl_errors.3061009199 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 17.rom_ctrl_tl_errors.3061009199 -covoverwrite +skip_middle_of_rom=1' seed=40311731624653311551197245166160388394599402991031802440446277068126476782383 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40311731624653311551197245166160388394599402991031802440446277068126476782383 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/17.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 77259048912674570382718849905144260788792127760694540040896820436864481283910 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/17.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1862979398 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.1862979398 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 17.rom_ctrl_tl_intg_err.1862979398 -covoverwrite +skip_middle_of_rom=1' seed=77259048912674570382718849905144260788792127760694540040896820436864481283910 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77259048912674570382718849905144260788792127760694540040896820436864481283910 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/17.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 43472039087147241386793964026473063854178755177349160164044901407679499324047 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/18.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=3255683727 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.3255683727 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 18.rom_ctrl_corrupt_sig_fatal_chk.3255683727 -covoverwrite +skip_middle_of_rom=1' seed=43472039087147241386793964026473063854178755177349160164044901407679499324047 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43472039087147241386793964026473063854178755177349160164044901407679499324047 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/18.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 53023426683719319258772947387556509720170340020686978437630008268867255470272 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/18.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=1756170432 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.1756170432 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 18.rom_ctrl_stress_all_with_rand_reset.1756170432 -covoverwrite +skip_middle_of_rom=1' seed=53023426683719319258772947387556509720170340020686978437630008268867255470272 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53023426683719319258772947387556509720170340020686978437630008268867255470272 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/18.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 106860120807116270323630964125735104047953531432815388153160964405642575233751 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/18.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3375645399 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/18.rom_ctrl_tl_errors.3375645399 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 18.rom_ctrl_tl_errors.3375645399 -covoverwrite +skip_middle_of_rom=1' seed=106860120807116270323630964125735104047953531432815388153160964405642575233751 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106860120807116270323630964125735104047953531432815388153160964405642575233751 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/18.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 63447428227515312502707599317925816333825596595975344775624884166278128462010 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/18.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1280960698 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.1280960698 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 18.rom_ctrl_tl_intg_err.1280960698 -covoverwrite +skip_middle_of_rom=1' seed=63447428227515312502707599317925816333825596595975344775624884166278128462010 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63447428227515312502707599317925816333825596595975344775624884166278128462010 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/18.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 40964176633160623690717905336919489989022624766025380345690705699893639810271 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/19.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=3415641311 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.3415641311 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 19.rom_ctrl_corrupt_sig_fatal_chk.3415641311 -covoverwrite +skip_middle_of_rom=1' seed=40964176633160623690717905336919489989022624766025380345690705699893639810271 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40964176633160623690717905336919489989022624766025380345690705699893639810271 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/19.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 53103732687369847465338942539397822144107475841080524136352320214632351634558 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/19.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=2947781758 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.2947781758 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope default -covtest 19.rom_ctrl_stress_all_with_rand_reset.2947781758 -covoverwrite +skip_middle_of_rom=1' seed=53103732687369847465338942539397822144107475841080524136352320214632351634558 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53103732687369847465338942539397822144107475841080524136352320214632351634558 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/19.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 39708829032094692076291189338732359437327508234569286043644360241414211540080 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/19.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3655767152 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/19.rom_ctrl_tl_errors.3655767152 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 19.rom_ctrl_tl_errors.3655767152 -covoverwrite +skip_middle_of_rom=1' seed=39708829032094692076291189338732359437327508234569286043644360241414211540080 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39708829032094692076291189338732359437327508234569286043644360241414211540080 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/19.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 81230296852784670207421157005636003710387099767468349547628600112040632688293 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/19.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1569234597 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.1569234597 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 19.rom_ctrl_tl_intg_err.1569234597 -covoverwrite +skip_middle_of_rom=1' seed=81230296852784670207421157005636003710387099767468349547628600112040632688293 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81230296852784670207421157005636003710387099767468349547628600112040632688293 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/19.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 18408802713769418018651712658589029295060862379445907476378877215150231228520 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/20.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2605158504 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/20.rom_ctrl_tl_errors.2605158504 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 20.rom_ctrl_tl_errors.2605158504 -covoverwrite +skip_middle_of_rom=1' seed=18408802713769418018651712658589029295060862379445907476378877215150231228520 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18408802713769418018651712658589029295060862379445907476378877215150231228520 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/20.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 82210890889201109820105136831867955630500994825118345884762953867151953769330 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/20.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=474362738 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/20.rom_ctrl_tl_intg_err.474362738 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 20.rom_ctrl_tl_intg_err.474362738 -covoverwrite +skip_middle_of_rom=1' seed=82210890889201109820105136831867955630500994825118345884762953867151953769330 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82210890889201109820105136831867955630500994825118345884762953867151953769330 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/20.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 22662172883580128233044929135565833839981436711570473291174352409927339470286 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/21.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3577474510 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/21.rom_ctrl_tl_errors.3577474510 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 21.rom_ctrl_tl_errors.3577474510 -covoverwrite +skip_middle_of_rom=1' seed=22662172883580128233044929135565833839981436711570473291174352409927339470286 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22662172883580128233044929135565833839981436711570473291174352409927339470286 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/21.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 108814708757783783104930567858891583912311684588007779846652533991615733930802 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/21.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3813382962 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/21.rom_ctrl_tl_intg_err.3813382962 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 21.rom_ctrl_tl_intg_err.3813382962 -covoverwrite +skip_middle_of_rom=1' seed=108814708757783783104930567858891583912311684588007779846652533991615733930802 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108814708757783783104930567858891583912311684588007779846652533991615733930802 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/21.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 29771328288827811942811490299320475843525723201664046103845402008737104752836 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/22.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=154104004 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/22.rom_ctrl_tl_errors.154104004 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 22.rom_ctrl_tl_errors.154104004 -covoverwrite +skip_middle_of_rom=1' seed=29771328288827811942811490299320475843525723201664046103845402008737104752836 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29771328288827811942811490299320475843525723201664046103845402008737104752836 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/22.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 830817958559935238444935302183747833810389442910041403843801499641510047850 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/22.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=284897386 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/22.rom_ctrl_tl_intg_err.284897386 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 22.rom_ctrl_tl_intg_err.284897386 -covoverwrite +skip_middle_of_rom=1' seed=830817958559935238444935302183747833810389442910041403843801499641510047850 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=830817958559935238444935302183747833810389442910041403843801499641510047850 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/22.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 78696441898164488421327915879697876244548748248009922041254017932465633822131 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/23.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1122305459 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/23.rom_ctrl_tl_errors.1122305459 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 23.rom_ctrl_tl_errors.1122305459 -covoverwrite +skip_middle_of_rom=1' seed=78696441898164488421327915879697876244548748248009922041254017932465633822131 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78696441898164488421327915879697876244548748248009922041254017932465633822131 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/23.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 6691108032026718826935027874138831871265236045888212301938235176641242970664 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/23.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=726252072 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/23.rom_ctrl_tl_intg_err.726252072 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 23.rom_ctrl_tl_intg_err.726252072 -covoverwrite +skip_middle_of_rom=1' seed=6691108032026718826935027874138831871265236045888212301938235176641242970664 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6691108032026718826935027874138831871265236045888212301938235176641242970664 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/23.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 101790955175916668536337362847789927129630528989912689989875692838148056714431 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/24.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=967740607 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/24.rom_ctrl_tl_errors.967740607 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 24.rom_ctrl_tl_errors.967740607 -covoverwrite +skip_middle_of_rom=1' seed=101790955175916668536337362847789927129630528989912689989875692838148056714431 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101790955175916668536337362847789927129630528989912689989875692838148056714431 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/24.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 101194946334023901545365011449593704471704987796462483083728060568284040677212 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/24.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=874923868 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage/cover_reg_top/24.rom_ctrl_tl_intg_err.874923868 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 24.rom_ctrl_tl_intg_err.874923868 -covoverwrite +skip_middle_of_rom=1' seed=101194946334023901545365011449593704471704987796462483083728060568284040677212 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101194946334023901545365011449593704471704987796462483083728060568284040677212 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_32kB-sim-xcelium/24.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
Job timed out after * minutes 6 test runs
rom_ctrl_stress_all 110457707822147161514686355452346097851914983640967182895894068983973317600273 None
rom_ctrl_stress_all 94068512195038118679769199665989052382609608370327950739891316609484464331488 None
rom_ctrl_stress_all 3327334892051479648609540393308141954915812423930604767650126144973667999559 None
rom_ctrl_stress_all 73576939675639797912588600053022260519772007166280882965182827829344167631287 None
rom_ctrl_stress_all 67162323214207122167727107185283465819275379785511243406580346914062185691101 None
rom_ctrl_stress_all 12832298982346098156998490341895629654456750866126499334022783690131093493001 None
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
rom_ctrl_stress_all 87079383508378031188878067846900750465264142930417885677467097272786827600431 87
UVM_INFO @ 1000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job returned a non-zero exit code: * 1 test run
rom_ctrl None None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk cov_merge cov_merge_cmd=imc cov_merge_opts='-64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl'
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:109: cov_merge] Error 126
Job cancelled because one of its dependencies failed or was killed. 1 test run
rom_ctrl None None