Simulation Results: rom_ctrl/64kb

 
28/08/2026 21:54:34 DVSim: v1.49.0 sha: a099412 json Branch: master Tool: xcelium [unknown]
Validation stages
V1
0.00%
V2
11.27%
V2S
0.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 0 2 0.00
rom_ctrl_smoke 0.832s 0.000us 0 2 0.00
csr_hw_reset 0 1 0.00
rom_ctrl_csr_hw_reset 0.871s 0.000us 0 1 0.00
csr_rw 0 5 0.00
rom_ctrl_csr_rw 0.832s 0.000us 0 5 0.00
csr_bit_bash 0 1 0.00
rom_ctrl_csr_bit_bash 0.822s 0.000us 0 1 0.00
csr_aliasing 0 1 0.00
rom_ctrl_csr_aliasing 0.845s 0.000us 0 1 0.00
csr_mem_rw_with_rand_reset 0 5 0.00
rom_ctrl_csr_mem_rw_with_rand_reset 1.533s 0.000us 0 5 0.00
regwen_csr_and_corresponding_lockable_csr 0 6 0.00
rom_ctrl_csr_rw 0.832s 0.000us 0 5 0.00
rom_ctrl_csr_aliasing 0.845s 0.000us 0 1 0.00
mem_walk 0 1 0.00
rom_ctrl_mem_walk 0.857s 0.000us 0 1 0.00
mem_partial_access 0 1 0.00
rom_ctrl_mem_partial_access 0.878s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 2 0.00
rom_ctrl_max_throughput_chk 0.908s 0.000us 0 2 0.00
stress_all 8 20 40.00
rom_ctrl_stress_all 10802.000s 0.000us 8 20 40.00
kmac_err_chk 0 2 0.00
rom_ctrl_kmac_err_chk 0.831s 0.000us 0 2 0.00
alert_test 0 10 0.00
rom_ctrl_alert_test 0.871s 0.000us 0 10 0.00
tl_d_oob_addr_access 0 25 0.00
rom_ctrl_tl_errors 1.385s 0.000us 0 25 0.00
tl_d_illegal_access 0 25 0.00
rom_ctrl_tl_errors 1.385s 0.000us 0 25 0.00
tl_d_outstanding_access 0 12 0.00
rom_ctrl_csr_hw_reset 0.871s 0.000us 0 1 0.00
rom_ctrl_csr_rw 0.832s 0.000us 0 5 0.00
rom_ctrl_csr_aliasing 0.845s 0.000us 0 1 0.00
rom_ctrl_same_csr_outstanding 0.888s 0.000us 0 5 0.00
tl_d_partial_access 0 12 0.00
rom_ctrl_csr_hw_reset 0.871s 0.000us 0 1 0.00
rom_ctrl_csr_rw 0.832s 0.000us 0 5 0.00
rom_ctrl_csr_aliasing 0.845s 0.000us 0 1 0.00
rom_ctrl_same_csr_outstanding 0.888s 0.000us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 1.552s 0.000us 0 20 0.00
passthru_mem_tl_intg_err 0 5 0.00
rom_ctrl_passthru_mem_tl_intg_err 0.857s 0.000us 0 5 0.00
tl_intg_err 0 30 0.00
rom_ctrl_sec_cm 0.864s 0.000us 0 5 0.00
rom_ctrl_tl_intg_err 0.880s 0.000us 0 25 0.00
prim_fsm_check 0 5 0.00
rom_ctrl_sec_cm 0.864s 0.000us 0 5 0.00
prim_count_check 0 5 0.00
rom_ctrl_sec_cm 0.864s 0.000us 0 5 0.00
sec_cm_checker_ctr_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 1.552s 0.000us 0 20 0.00
sec_cm_checker_ctrl_flow_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 1.552s 0.000us 0 20 0.00
sec_cm_checker_fsm_local_esc 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 1.552s 0.000us 0 20 0.00
sec_cm_compare_ctrl_flow_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 1.552s 0.000us 0 20 0.00
sec_cm_compare_ctr_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 1.552s 0.000us 0 20 0.00
sec_cm_compare_ctr_redun 0 5 0.00
rom_ctrl_sec_cm 0.864s 0.000us 0 5 0.00
sec_cm_fsm_sparse 0 5 0.00
rom_ctrl_sec_cm 0.864s 0.000us 0 5 0.00
sec_cm_mem_scramble 0 2 0.00
rom_ctrl_smoke 0.832s 0.000us 0 2 0.00
sec_cm_mem_digest 0 2 0.00
rom_ctrl_smoke 0.832s 0.000us 0 2 0.00
sec_cm_intersig_mubi 0 2 0.00
rom_ctrl_smoke 0.832s 0.000us 0 2 0.00
sec_cm_bus_integrity 0 25 0.00
rom_ctrl_tl_intg_err 0.880s 0.000us 0 25 0.00
sec_cm_bus_local_esc 0 22 0.00
rom_ctrl_corrupt_sig_fatal_chk 1.552s 0.000us 0 20 0.00
rom_ctrl_kmac_err_chk 0.831s 0.000us 0 2 0.00
sec_cm_mux_mubi 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 1.552s 0.000us 0 20 0.00
sec_cm_mux_consistency 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 1.552s 0.000us 0 20 0.00
sec_cm_ctrl_redun 0 20 0.00
rom_ctrl_corrupt_sig_fatal_chk 1.552s 0.000us 0 20 0.00
sec_cm_ctrl_mem_integrity 0 5 0.00
rom_ctrl_passthru_mem_tl_intg_err 0.857s 0.000us 0 5 0.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
rom_ctrl_sec_cm 0.864s 0.000us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 20 0.00
rom_ctrl_stress_all_with_rand_reset 1.634s 0.000us 0 20 0.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 136 test runs
rom_ctrl_smoke 56336623233676056689233905848395344769019011007337590282633770399838074528952 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/0.rom_ctrl_smoke/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=2214028472 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/0.rom_ctrl_smoke.2214028472 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 0.rom_ctrl_smoke.2214028472 -covoverwrite +skip_middle_of_rom=1' seed=56336623233676056689233905848395344769019011007337590282633770399838074528952 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56336623233676056689233905848395344769019011007337590282633770399838074528952 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/0.rom_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_max_throughput_chk 113808779361796014436663213681558527602379812797875012300958093287251218751832 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/0.rom_ctrl_max_throughput_chk/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=3467600216 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/0.rom_ctrl_max_throughput_chk.3467600216 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 0.rom_ctrl_max_throughput_chk.3467600216 -covoverwrite +skip_middle_of_rom=1' seed=113808779361796014436663213681558527602379812797875012300958093287251218751832 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113808779361796014436663213681558527602379812797875012300958093287251218751832 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/0.rom_ctrl_max_throughput_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 104159672581895350793505780799066294514834889440345311631233173214707555684306 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/0.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=790548434 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/0.rom_ctrl_corrupt_sig_fatal_chk.790548434 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 0.rom_ctrl_corrupt_sig_fatal_chk.790548434 -covoverwrite +skip_middle_of_rom=1' seed=104159672581895350793505780799066294514834889440345311631233173214707555684306 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104159672581895350793505780799066294514834889440345311631233173214707555684306 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/0.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_kmac_err_chk 105354893695217562516003487239008147287160576219535069971133872748922904203300 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/0.rom_ctrl_kmac_err_chk/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=3567472676 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/0.rom_ctrl_kmac_err_chk.3567472676 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 0.rom_ctrl_kmac_err_chk.3567472676 -covoverwrite +skip_middle_of_rom=1' seed=105354893695217562516003487239008147287160576219535069971133872748922904203300 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105354893695217562516003487239008147287160576219535069971133872748922904203300 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/0.rom_ctrl_kmac_err_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_kmac_err_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 2811659481275003908726162544834769654733063269402419010714914039563862595094 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/0.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=2631325206 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/0.rom_ctrl_stress_all_with_rand_reset.2631325206 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 0.rom_ctrl_stress_all_with_rand_reset.2631325206 -covoverwrite +skip_middle_of_rom=1' seed=2811659481275003908726162544834769654733063269402419010714914039563862595094 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2811659481275003908726162544834769654733063269402419010714914039563862595094 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/0.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_sec_cm 82625378048271724333914937397264393273591663459173457914291492452097329081449 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/0.rom_ctrl_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=3642633321 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/0.rom_ctrl_sec_cm.3642633321 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 0.rom_ctrl_sec_cm.3642633321 -covoverwrite +skip_middle_of_rom=1' seed=82625378048271724333914937397264393273591663459173457914291492452097329081449 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82625378048271724333914937397264393273591663459173457914291492452097329081449 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/0.rom_ctrl_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_passthru_mem_tl_intg_err 35689984103709529862833671801205108313778215434175162765241013759103885213205 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/0.rom_ctrl_passthru_mem_tl_intg_err/latest run_opts='+run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3603267093 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/0.rom_ctrl_passthru_mem_tl_intg_err.3603267093 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rom_ctrl_passthru_mem_tl_intg_err.3603267093 -covoverwrite +skip_middle_of_rom=1' seed=35689984103709529862833671801205108313778215434175162765241013759103885213205 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35689984103709529862833671801205108313778215434175162765241013759103885213205 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/0.rom_ctrl_passthru_mem_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 28886686597969691131200514303141318637832216543301648213194466473791461444145 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/0.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1107216945 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/0.rom_ctrl_tl_errors.1107216945 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rom_ctrl_tl_errors.1107216945 -covoverwrite +skip_middle_of_rom=1' seed=28886686597969691131200514303141318637832216543301648213194466473791461444145 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28886686597969691131200514303141318637832216543301648213194466473791461444145 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/0.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 51250913273041889892512647877335260119116244995269693043256235406964495788329 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/0.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=910993705 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/0.rom_ctrl_tl_intg_err.910993705 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rom_ctrl_tl_intg_err.910993705 -covoverwrite +skip_middle_of_rom=1' seed=51250913273041889892512647877335260119116244995269693043256235406964495788329 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51250913273041889892512647877335260119116244995269693043256235406964495788329 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/0.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_alert_test 90717699083217942205220436931507881106149425295144070030847341324320760198392 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/0.rom_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=2092496120 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/0.rom_ctrl_alert_test.2092496120 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 0.rom_ctrl_alert_test.2092496120 -covoverwrite +skip_middle_of_rom=1' seed=90717699083217942205220436931507881106149425295144070030847341324320760198392 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90717699083217942205220436931507881106149425295144070030847341324320760198392 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/0.rom_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_mem_walk 57578968816556474968815616932116274574716916758730747774219104400821156953021 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/0.rom_ctrl_mem_walk/latest run_opts='+csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2292038589 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/0.rom_ctrl_mem_walk.2292038589 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rom_ctrl_mem_walk.2292038589 -covoverwrite +skip_middle_of_rom=1' seed=57578968816556474968815616932116274574716916758730747774219104400821156953021 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57578968816556474968815616932116274574716916758730747774219104400821156953021 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/0.rom_ctrl_mem_walk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_mem_partial_access 57262055266262182575363748999513215185574763901118097520656436795210192411514 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/0.rom_ctrl_mem_partial_access/latest run_opts='+run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1163680634 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/0.rom_ctrl_mem_partial_access.1163680634 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rom_ctrl_mem_partial_access.1163680634 -covoverwrite +skip_middle_of_rom=1' seed=57262055266262182575363748999513215185574763901118097520656436795210192411514 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57262055266262182575363748999513215185574763901118097520656436795210192411514 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/0.rom_ctrl_mem_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_csr_hw_reset 28232258089667359137009759356392793034129467522819754315943815513946818265953 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/0.rom_ctrl_csr_hw_reset/latest run_opts='+csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2545337185 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/0.rom_ctrl_csr_hw_reset.2545337185 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rom_ctrl_csr_hw_reset.2545337185 -covoverwrite +skip_middle_of_rom=1' seed=28232258089667359137009759356392793034129467522819754315943815513946818265953 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28232258089667359137009759356392793034129467522819754315943815513946818265953 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/0.rom_ctrl_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_csr_rw 12652555708288202920245731398266876421601617262645993038709749670317170277291 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/0.rom_ctrl_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2789915563 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/0.rom_ctrl_csr_rw.2789915563 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rom_ctrl_csr_rw.2789915563 -covoverwrite +skip_middle_of_rom=1' seed=12652555708288202920245731398266876421601617262645993038709749670317170277291 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12652555708288202920245731398266876421601617262645993038709749670317170277291 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/0.rom_ctrl_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_csr_bit_bash 38032568213119865175697328519430633702519229379648335573572429002288931845811 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/0.rom_ctrl_csr_bit_bash/latest run_opts='+csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=237811379 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/0.rom_ctrl_csr_bit_bash.237811379 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rom_ctrl_csr_bit_bash.237811379 -covoverwrite +skip_middle_of_rom=1' seed=38032568213119865175697328519430633702519229379648335573572429002288931845811 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38032568213119865175697328519430633702519229379648335573572429002288931845811 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/0.rom_ctrl_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_csr_aliasing 106890562240303704618955352097890404225702834470920787247419401207528998450339 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/0.rom_ctrl_csr_aliasing/latest run_opts='+csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=792081571 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/0.rom_ctrl_csr_aliasing.792081571 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rom_ctrl_csr_aliasing.792081571 -covoverwrite +skip_middle_of_rom=1' seed=106890562240303704618955352097890404225702834470920787247419401207528998450339 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106890562240303704618955352097890404225702834470920787247419401207528998450339 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/0.rom_ctrl_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_same_csr_outstanding 53981206452699541374440775270778912929720182534728957775485138995225804744014 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/0.rom_ctrl_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=392504654 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/0.rom_ctrl_same_csr_outstanding.392504654 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rom_ctrl_same_csr_outstanding.392504654 -covoverwrite +skip_middle_of_rom=1' seed=53981206452699541374440775270778912929720182534728957775485138995225804744014 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53981206452699541374440775270778912929720182534728957775485138995225804744014 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/0.rom_ctrl_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_csr_mem_rw_with_rand_reset 15385088725499332264761350919185753061063577697416370497612123911712109943789 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=25353197 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/0.rom_ctrl_csr_mem_rw_with_rand_reset.25353197 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rom_ctrl_csr_mem_rw_with_rand_reset.25353197 -covoverwrite +skip_middle_of_rom=1' seed=15385088725499332264761350919185753061063577697416370497612123911712109943789 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15385088725499332264761350919185753061063577697416370497612123911712109943789 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/0.rom_ctrl_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_smoke 97146707829553290902497574177279139499407653183833026665532917570408474592908 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/1.rom_ctrl_smoke/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=4177118860 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/1.rom_ctrl_smoke.4177118860 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 1.rom_ctrl_smoke.4177118860 -covoverwrite +skip_middle_of_rom=1' seed=97146707829553290902497574177279139499407653183833026665532917570408474592908 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97146707829553290902497574177279139499407653183833026665532917570408474592908 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/1.rom_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_max_throughput_chk 85889857036782536760833358253759186825489224720161991083461083040510828812762 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/1.rom_ctrl_max_throughput_chk/latest run_opts='+zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=1507793370 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/1.rom_ctrl_max_throughput_chk.1507793370 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 1.rom_ctrl_max_throughput_chk.1507793370 -covoverwrite +skip_middle_of_rom=1' seed=85889857036782536760833358253759186825489224720161991083461083040510828812762 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85889857036782536760833358253759186825489224720161991083461083040510828812762 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/1.rom_ctrl_max_throughput_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 63284837149537579662394085720521218701835536785821651351012203719602004793053 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/1.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=3629618909 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/1.rom_ctrl_corrupt_sig_fatal_chk.3629618909 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 1.rom_ctrl_corrupt_sig_fatal_chk.3629618909 -covoverwrite +skip_middle_of_rom=1' seed=63284837149537579662394085720521218701835536785821651351012203719602004793053 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63284837149537579662394085720521218701835536785821651351012203719602004793053 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/1.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_kmac_err_chk 105141715556663119066825114416878374394850862792781234561603366538499656624280 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/1.rom_ctrl_kmac_err_chk/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=3820333208 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_kmac_err_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/1.rom_ctrl_kmac_err_chk.3820333208 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 1.rom_ctrl_kmac_err_chk.3820333208 -covoverwrite +skip_middle_of_rom=1' seed=105141715556663119066825114416878374394850862792781234561603366538499656624280 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105141715556663119066825114416878374394850862792781234561603366538499656624280 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/1.rom_ctrl_kmac_err_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_kmac_err_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 58685128200844206927373018248528800123516382043942769003085667989857909438082 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/1.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=3545593474 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/1.rom_ctrl_stress_all_with_rand_reset.3545593474 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 1.rom_ctrl_stress_all_with_rand_reset.3545593474 -covoverwrite +skip_middle_of_rom=1' seed=58685128200844206927373018248528800123516382043942769003085667989857909438082 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58685128200844206927373018248528800123516382043942769003085667989857909438082 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/1.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_sec_cm 13551049908993962009930280638237579118840796755121718502368505493346305861839 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/1.rom_ctrl_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=1382181071 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/1.rom_ctrl_sec_cm.1382181071 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 1.rom_ctrl_sec_cm.1382181071 -covoverwrite +skip_middle_of_rom=1' seed=13551049908993962009930280638237579118840796755121718502368505493346305861839 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13551049908993962009930280638237579118840796755121718502368505493346305861839 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/1.rom_ctrl_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_passthru_mem_tl_intg_err 112050084221423484501845890302086682728886983748568030533221428344748957009150 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/1.rom_ctrl_passthru_mem_tl_intg_err/latest run_opts='+run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1030784254 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/1.rom_ctrl_passthru_mem_tl_intg_err.1030784254 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.rom_ctrl_passthru_mem_tl_intg_err.1030784254 -covoverwrite +skip_middle_of_rom=1' seed=112050084221423484501845890302086682728886983748568030533221428344748957009150 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112050084221423484501845890302086682728886983748568030533221428344748957009150 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/1.rom_ctrl_passthru_mem_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 101470902791831382535113159359380844751075510716879795531012071702805108487583 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/1.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1970533791 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/1.rom_ctrl_tl_errors.1970533791 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.rom_ctrl_tl_errors.1970533791 -covoverwrite +skip_middle_of_rom=1' seed=101470902791831382535113159359380844751075510716879795531012071702805108487583 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101470902791831382535113159359380844751075510716879795531012071702805108487583 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/1.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 54439635105509366483816480928640245472166399005328043123534470326999416571581 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/1.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2901935805 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/1.rom_ctrl_tl_intg_err.2901935805 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.rom_ctrl_tl_intg_err.2901935805 -covoverwrite +skip_middle_of_rom=1' seed=54439635105509366483816480928640245472166399005328043123534470326999416571581 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54439635105509366483816480928640245472166399005328043123534470326999416571581 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/1.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_alert_test 109406173993499329911993282080200288202438053035461739364453104801083134262721 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/1.rom_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=2931768769 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/1.rom_ctrl_alert_test.2931768769 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 1.rom_ctrl_alert_test.2931768769 -covoverwrite +skip_middle_of_rom=1' seed=109406173993499329911993282080200288202438053035461739364453104801083134262721 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109406173993499329911993282080200288202438053035461739364453104801083134262721 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/1.rom_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_csr_rw 69101307364912897169630717672510423879703816732967260247987943654343327030525 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/1.rom_ctrl_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=732896509 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/1.rom_ctrl_csr_rw.732896509 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.rom_ctrl_csr_rw.732896509 -covoverwrite +skip_middle_of_rom=1' seed=69101307364912897169630717672510423879703816732967260247987943654343327030525 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69101307364912897169630717672510423879703816732967260247987943654343327030525 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/1.rom_ctrl_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_same_csr_outstanding 32227379964163576314666311648042493649622297344002825443280600147475578167426 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/1.rom_ctrl_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=66003074 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/1.rom_ctrl_same_csr_outstanding.66003074 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.rom_ctrl_same_csr_outstanding.66003074 -covoverwrite +skip_middle_of_rom=1' seed=32227379964163576314666311648042493649622297344002825443280600147475578167426 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32227379964163576314666311648042493649622297344002825443280600147475578167426 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/1.rom_ctrl_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_csr_mem_rw_with_rand_reset 17964616969030749375093413142605621444008178270569733927228630314274883414936 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2998447000 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/1.rom_ctrl_csr_mem_rw_with_rand_reset.2998447000 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.rom_ctrl_csr_mem_rw_with_rand_reset.2998447000 -covoverwrite +skip_middle_of_rom=1' seed=17964616969030749375093413142605621444008178270569733927228630314274883414936 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17964616969030749375093413142605621444008178270569733927228630314274883414936 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/1.rom_ctrl_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 86128643399546724454057123540722969959158644671977557982665667250758666532690 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/2.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=3757160274 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/2.rom_ctrl_corrupt_sig_fatal_chk.3757160274 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 2.rom_ctrl_corrupt_sig_fatal_chk.3757160274 -covoverwrite +skip_middle_of_rom=1' seed=86128643399546724454057123540722969959158644671977557982665667250758666532690 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86128643399546724454057123540722969959158644671977557982665667250758666532690 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/2.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 37476149285827593674777068986303725140367856987825129093837335208276596913806 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/2.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=2137552526 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/2.rom_ctrl_stress_all_with_rand_reset.2137552526 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 2.rom_ctrl_stress_all_with_rand_reset.2137552526 -covoverwrite +skip_middle_of_rom=1' seed=37476149285827593674777068986303725140367856987825129093837335208276596913806 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37476149285827593674777068986303725140367856987825129093837335208276596913806 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/2.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_sec_cm 85323365745175958769069592940387450643869816736557118389557406601679635957510 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/2.rom_ctrl_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=1132152582 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/2.rom_ctrl_sec_cm.1132152582 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 2.rom_ctrl_sec_cm.1132152582 -covoverwrite +skip_middle_of_rom=1' seed=85323365745175958769069592940387450643869816736557118389557406601679635957510 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85323365745175958769069592940387450643869816736557118389557406601679635957510 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/2.rom_ctrl_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_passthru_mem_tl_intg_err 15631083488620907600212777515146178340289661304363798756893159586370553876410 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/2.rom_ctrl_passthru_mem_tl_intg_err/latest run_opts='+run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2385481658 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/2.rom_ctrl_passthru_mem_tl_intg_err.2385481658 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.rom_ctrl_passthru_mem_tl_intg_err.2385481658 -covoverwrite +skip_middle_of_rom=1' seed=15631083488620907600212777515146178340289661304363798756893159586370553876410 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15631083488620907600212777515146178340289661304363798756893159586370553876410 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/2.rom_ctrl_passthru_mem_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 82476155367898356835580510911117340673566388105377164518790576267285480797979 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/2.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=286979867 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/2.rom_ctrl_tl_errors.286979867 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.rom_ctrl_tl_errors.286979867 -covoverwrite +skip_middle_of_rom=1' seed=82476155367898356835580510911117340673566388105377164518790576267285480797979 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82476155367898356835580510911117340673566388105377164518790576267285480797979 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/2.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 86901769525458489712593621877297126049143911701973069077705454656361574106319 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/2.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2885878991 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/2.rom_ctrl_tl_intg_err.2885878991 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.rom_ctrl_tl_intg_err.2885878991 -covoverwrite +skip_middle_of_rom=1' seed=86901769525458489712593621877297126049143911701973069077705454656361574106319 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86901769525458489712593621877297126049143911701973069077705454656361574106319 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/2.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_alert_test 37284184084995150966628897806284726806062637050760417965053462601947092922597 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/2.rom_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=1924444389 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/2.rom_ctrl_alert_test.1924444389 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 2.rom_ctrl_alert_test.1924444389 -covoverwrite +skip_middle_of_rom=1' seed=37284184084995150966628897806284726806062637050760417965053462601947092922597 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37284184084995150966628897806284726806062637050760417965053462601947092922597 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/2.rom_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_csr_rw 39628900685329501527052097348903152479814409468682198747553029742879178832643 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/2.rom_ctrl_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2112961283 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/2.rom_ctrl_csr_rw.2112961283 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.rom_ctrl_csr_rw.2112961283 -covoverwrite +skip_middle_of_rom=1' seed=39628900685329501527052097348903152479814409468682198747553029742879178832643 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39628900685329501527052097348903152479814409468682198747553029742879178832643 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/2.rom_ctrl_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_same_csr_outstanding 6782337881363262125520013047825236910556211330799473232627836893165048512794 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/2.rom_ctrl_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=362234138 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/2.rom_ctrl_same_csr_outstanding.362234138 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.rom_ctrl_same_csr_outstanding.362234138 -covoverwrite +skip_middle_of_rom=1' seed=6782337881363262125520013047825236910556211330799473232627836893165048512794 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6782337881363262125520013047825236910556211330799473232627836893165048512794 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/2.rom_ctrl_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_csr_mem_rw_with_rand_reset 24061574919253925018327657562728461579126162183633850003144185474227620597967 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2322649295 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/2.rom_ctrl_csr_mem_rw_with_rand_reset.2322649295 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.rom_ctrl_csr_mem_rw_with_rand_reset.2322649295 -covoverwrite +skip_middle_of_rom=1' seed=24061574919253925018327657562728461579126162183633850003144185474227620597967 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24061574919253925018327657562728461579126162183633850003144185474227620597967 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/2.rom_ctrl_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 85657660057632509038329028604033988826457989624412729236274704840673377279705 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/3.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=3849215705 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/3.rom_ctrl_corrupt_sig_fatal_chk.3849215705 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 3.rom_ctrl_corrupt_sig_fatal_chk.3849215705 -covoverwrite +skip_middle_of_rom=1' seed=85657660057632509038329028604033988826457989624412729236274704840673377279705 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85657660057632509038329028604033988826457989624412729236274704840673377279705 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/3.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 50527747729089605333970641605791941928306658995285404395730988865899136845167 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/3.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=3096741231 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/3.rom_ctrl_stress_all_with_rand_reset.3096741231 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 3.rom_ctrl_stress_all_with_rand_reset.3096741231 -covoverwrite +skip_middle_of_rom=1' seed=50527747729089605333970641605791941928306658995285404395730988865899136845167 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50527747729089605333970641605791941928306658995285404395730988865899136845167 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/3.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_sec_cm 76509672299732255505114561299854330676307960364752018363276141993092910906662 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/3.rom_ctrl_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=775126310 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/3.rom_ctrl_sec_cm.775126310 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 3.rom_ctrl_sec_cm.775126310 -covoverwrite +skip_middle_of_rom=1' seed=76509672299732255505114561299854330676307960364752018363276141993092910906662 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76509672299732255505114561299854330676307960364752018363276141993092910906662 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/3.rom_ctrl_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_passthru_mem_tl_intg_err 57563985730809152063757439020264173916489864365759049312398732965831472850498 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/3.rom_ctrl_passthru_mem_tl_intg_err/latest run_opts='+run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3404211778 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/3.rom_ctrl_passthru_mem_tl_intg_err.3404211778 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.rom_ctrl_passthru_mem_tl_intg_err.3404211778 -covoverwrite +skip_middle_of_rom=1' seed=57563985730809152063757439020264173916489864365759049312398732965831472850498 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57563985730809152063757439020264173916489864365759049312398732965831472850498 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/3.rom_ctrl_passthru_mem_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 30449245236555786541829509016705758125744359656179764948933878937750493059277 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/3.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1506138317 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/3.rom_ctrl_tl_errors.1506138317 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.rom_ctrl_tl_errors.1506138317 -covoverwrite +skip_middle_of_rom=1' seed=30449245236555786541829509016705758125744359656179764948933878937750493059277 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30449245236555786541829509016705758125744359656179764948933878937750493059277 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/3.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 47410551145608179960980705964299231259335987844186847582510377225882509933668 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/3.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3742268516 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/3.rom_ctrl_tl_intg_err.3742268516 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.rom_ctrl_tl_intg_err.3742268516 -covoverwrite +skip_middle_of_rom=1' seed=47410551145608179960980705964299231259335987844186847582510377225882509933668 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47410551145608179960980705964299231259335987844186847582510377225882509933668 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/3.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_alert_test 43273103007264858633828894899654178587249433597552209530946396562204073540586 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/3.rom_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=2699967466 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/3.rom_ctrl_alert_test.2699967466 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 3.rom_ctrl_alert_test.2699967466 -covoverwrite +skip_middle_of_rom=1' seed=43273103007264858633828894899654178587249433597552209530946396562204073540586 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43273103007264858633828894899654178587249433597552209530946396562204073540586 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/3.rom_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_csr_rw 81805684056643928949217280735714940417017602605546100897409580938502137227327 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/3.rom_ctrl_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3516966975 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/3.rom_ctrl_csr_rw.3516966975 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.rom_ctrl_csr_rw.3516966975 -covoverwrite +skip_middle_of_rom=1' seed=81805684056643928949217280735714940417017602605546100897409580938502137227327 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81805684056643928949217280735714940417017602605546100897409580938502137227327 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/3.rom_ctrl_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_same_csr_outstanding 76156355490906947111641051217592836052354003016683152087140407132491235882636 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/3.rom_ctrl_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3216144012 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/3.rom_ctrl_same_csr_outstanding.3216144012 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.rom_ctrl_same_csr_outstanding.3216144012 -covoverwrite +skip_middle_of_rom=1' seed=76156355490906947111641051217592836052354003016683152087140407132491235882636 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76156355490906947111641051217592836052354003016683152087140407132491235882636 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/3.rom_ctrl_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_csr_mem_rw_with_rand_reset 24413738817988316974701379146861481358296199571181791132773530710779030575276 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3238697132 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/3.rom_ctrl_csr_mem_rw_with_rand_reset.3238697132 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.rom_ctrl_csr_mem_rw_with_rand_reset.3238697132 -covoverwrite +skip_middle_of_rom=1' seed=24413738817988316974701379146861481358296199571181791132773530710779030575276 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24413738817988316974701379146861481358296199571181791132773530710779030575276 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/3.rom_ctrl_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 104702562691970877262935701908148758941912238029576095257731750871990944918255 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/4.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=1815866095 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/4.rom_ctrl_corrupt_sig_fatal_chk.1815866095 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 4.rom_ctrl_corrupt_sig_fatal_chk.1815866095 -covoverwrite +skip_middle_of_rom=1' seed=104702562691970877262935701908148758941912238029576095257731750871990944918255 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104702562691970877262935701908148758941912238029576095257731750871990944918255 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/4.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 26546503811122585159403922970457271562460330020456241750751653317217321984018 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/4.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=1346084882 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/4.rom_ctrl_stress_all_with_rand_reset.1346084882 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 4.rom_ctrl_stress_all_with_rand_reset.1346084882 -covoverwrite +skip_middle_of_rom=1' seed=26546503811122585159403922970457271562460330020456241750751653317217321984018 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26546503811122585159403922970457271562460330020456241750751653317217321984018 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/4.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_sec_cm 60930747739434780581914226818915052515388665634784858361085421059638397918835 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/4.rom_ctrl_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=3184156275 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/4.rom_ctrl_sec_cm.3184156275 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 4.rom_ctrl_sec_cm.3184156275 -covoverwrite +skip_middle_of_rom=1' seed=60930747739434780581914226818915052515388665634784858361085421059638397918835 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60930747739434780581914226818915052515388665634784858361085421059638397918835 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/4.rom_ctrl_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_passthru_mem_tl_intg_err 40480430963338611585380725509979310399565746247528497151402685824475544139800 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/4.rom_ctrl_passthru_mem_tl_intg_err/latest run_opts='+run_passthru_mem_tl_intg_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=259766296 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/4.rom_ctrl_passthru_mem_tl_intg_err.259766296 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.rom_ctrl_passthru_mem_tl_intg_err.259766296 -covoverwrite +skip_middle_of_rom=1' seed=40480430963338611585380725509979310399565746247528497151402685824475544139800 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40480430963338611585380725509979310399565746247528497151402685824475544139800 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/4.rom_ctrl_passthru_mem_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 96814965792483421582746400444638524662408610903946478405270617899355016751946 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/4.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4149177162 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/4.rom_ctrl_tl_errors.4149177162 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.rom_ctrl_tl_errors.4149177162 -covoverwrite +skip_middle_of_rom=1' seed=96814965792483421582746400444638524662408610903946478405270617899355016751946 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96814965792483421582746400444638524662408610903946478405270617899355016751946 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/4.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 25461218804669029433351321802536946261361106424051609044908221067001901001949 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/4.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2332994781 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/4.rom_ctrl_tl_intg_err.2332994781 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.rom_ctrl_tl_intg_err.2332994781 -covoverwrite +skip_middle_of_rom=1' seed=25461218804669029433351321802536946261361106424051609044908221067001901001949 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25461218804669029433351321802536946261361106424051609044908221067001901001949 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/4.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_alert_test 68196211018082216108800817999382073639325620230047279351622815891079310215376 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/4.rom_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=2802452688 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/4.rom_ctrl_alert_test.2802452688 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 4.rom_ctrl_alert_test.2802452688 -covoverwrite +skip_middle_of_rom=1' seed=68196211018082216108800817999382073639325620230047279351622815891079310215376 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68196211018082216108800817999382073639325620230047279351622815891079310215376 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/4.rom_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_csr_rw 82051880316012507785037190606074556355970508676511834210044459496632451246078 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/4.rom_ctrl_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2939070462 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/4.rom_ctrl_csr_rw.2939070462 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.rom_ctrl_csr_rw.2939070462 -covoverwrite +skip_middle_of_rom=1' seed=82051880316012507785037190606074556355970508676511834210044459496632451246078 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82051880316012507785037190606074556355970508676511834210044459496632451246078 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/4.rom_ctrl_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_same_csr_outstanding 72427478172796479661784274044208585590270533990183316239245850040588260742061 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/4.rom_ctrl_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1778783149 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/4.rom_ctrl_same_csr_outstanding.1778783149 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.rom_ctrl_same_csr_outstanding.1778783149 -covoverwrite +skip_middle_of_rom=1' seed=72427478172796479661784274044208585590270533990183316239245850040588260742061 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72427478172796479661784274044208585590270533990183316239245850040588260742061 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/4.rom_ctrl_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_csr_mem_rw_with_rand_reset 47176198614496229797851848268955533425302663584043005342209127838102098694649 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3351138809 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/4.rom_ctrl_csr_mem_rw_with_rand_reset.3351138809 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.rom_ctrl_csr_mem_rw_with_rand_reset.3351138809 -covoverwrite +skip_middle_of_rom=1' seed=47176198614496229797851848268955533425302663584043005342209127838102098694649 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47176198614496229797851848268955533425302663584043005342209127838102098694649 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/4.rom_ctrl_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 92617027914855630917352131671425853496110602414558410424130543957507012223948 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/5.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=1042736076 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/5.rom_ctrl_corrupt_sig_fatal_chk.1042736076 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 5.rom_ctrl_corrupt_sig_fatal_chk.1042736076 -covoverwrite +skip_middle_of_rom=1' seed=92617027914855630917352131671425853496110602414558410424130543957507012223948 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92617027914855630917352131671425853496110602414558410424130543957507012223948 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/5.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 30714511451331014163263361783893922499141029335017057987187362209332631520222 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/5.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=2814460894 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/5.rom_ctrl_stress_all_with_rand_reset.2814460894 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 5.rom_ctrl_stress_all_with_rand_reset.2814460894 -covoverwrite +skip_middle_of_rom=1' seed=30714511451331014163263361783893922499141029335017057987187362209332631520222 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30714511451331014163263361783893922499141029335017057987187362209332631520222 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/5.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 56277048866184476677850380548926527870344748853397313137080682229547012626060 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/5.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3772159628 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/5.rom_ctrl_tl_errors.3772159628 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.rom_ctrl_tl_errors.3772159628 -covoverwrite +skip_middle_of_rom=1' seed=56277048866184476677850380548926527870344748853397313137080682229547012626060 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56277048866184476677850380548926527870344748853397313137080682229547012626060 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/5.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 115062131256838769107796030400644035548122975862843844485144829296974823002600 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/5.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2667680232 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/5.rom_ctrl_tl_intg_err.2667680232 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.rom_ctrl_tl_intg_err.2667680232 -covoverwrite +skip_middle_of_rom=1' seed=115062131256838769107796030400644035548122975862843844485144829296974823002600 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115062131256838769107796030400644035548122975862843844485144829296974823002600 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/5.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_alert_test 5543354962565928470369526480989406677140648383592198237965396192538342631467 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/5.rom_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=2460395563 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/5.rom_ctrl_alert_test.2460395563 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 5.rom_ctrl_alert_test.2460395563 -covoverwrite +skip_middle_of_rom=1' seed=5543354962565928470369526480989406677140648383592198237965396192538342631467 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5543354962565928470369526480989406677140648383592198237965396192538342631467 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/5.rom_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 57873601003624758155527155548862511402793848860252418488734299774187281671772 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/6.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=2373543516 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/6.rom_ctrl_corrupt_sig_fatal_chk.2373543516 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 6.rom_ctrl_corrupt_sig_fatal_chk.2373543516 -covoverwrite +skip_middle_of_rom=1' seed=57873601003624758155527155548862511402793848860252418488734299774187281671772 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57873601003624758155527155548862511402793848860252418488734299774187281671772 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/6.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 72164503899457393633954410055565349655277557281092060445610466078320917595825 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/6.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=2822096561 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/6.rom_ctrl_stress_all_with_rand_reset.2822096561 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 6.rom_ctrl_stress_all_with_rand_reset.2822096561 -covoverwrite +skip_middle_of_rom=1' seed=72164503899457393633954410055565349655277557281092060445610466078320917595825 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72164503899457393633954410055565349655277557281092060445610466078320917595825 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/6.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 105583587450113077720071225881816025431991694844373303381284689705822919047514 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/6.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1286322522 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/6.rom_ctrl_tl_errors.1286322522 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.rom_ctrl_tl_errors.1286322522 -covoverwrite +skip_middle_of_rom=1' seed=105583587450113077720071225881816025431991694844373303381284689705822919047514 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105583587450113077720071225881816025431991694844373303381284689705822919047514 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/6.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 89842774871973870386670580147265185472495935977466411790952129439518866908961 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/6.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=110470945 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/6.rom_ctrl_tl_intg_err.110470945 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.rom_ctrl_tl_intg_err.110470945 -covoverwrite +skip_middle_of_rom=1' seed=89842774871973870386670580147265185472495935977466411790952129439518866908961 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89842774871973870386670580147265185472495935977466411790952129439518866908961 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/6.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_alert_test 103551769566525885430398460066078230774689349099722059724479066761971662091946 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/6.rom_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=3506992810 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/6.rom_ctrl_alert_test.3506992810 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 6.rom_ctrl_alert_test.3506992810 -covoverwrite +skip_middle_of_rom=1' seed=103551769566525885430398460066078230774689349099722059724479066761971662091946 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103551769566525885430398460066078230774689349099722059724479066761971662091946 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/6.rom_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 82927265182801819914809602183076703837560973274674958109883901256704008831420 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/7.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=1945027004 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/7.rom_ctrl_corrupt_sig_fatal_chk.1945027004 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 7.rom_ctrl_corrupt_sig_fatal_chk.1945027004 -covoverwrite +skip_middle_of_rom=1' seed=82927265182801819914809602183076703837560973274674958109883901256704008831420 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82927265182801819914809602183076703837560973274674958109883901256704008831420 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/7.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 62150958850989697710158989914123945229948903682921088693401718529763753809618 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/7.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=3151714002 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/7.rom_ctrl_stress_all_with_rand_reset.3151714002 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 7.rom_ctrl_stress_all_with_rand_reset.3151714002 -covoverwrite +skip_middle_of_rom=1' seed=62150958850989697710158989914123945229948903682921088693401718529763753809618 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62150958850989697710158989914123945229948903682921088693401718529763753809618 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/7.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 112885089069705941079058831525260034351055362116314831656820749053402663549617 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/7.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3034512049 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/7.rom_ctrl_tl_errors.3034512049 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.rom_ctrl_tl_errors.3034512049 -covoverwrite +skip_middle_of_rom=1' seed=112885089069705941079058831525260034351055362116314831656820749053402663549617 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112885089069705941079058831525260034351055362116314831656820749053402663549617 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/7.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 12529059016647369806288150284869677645064473094030056320304816848006691910391 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/7.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=555447031 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/7.rom_ctrl_tl_intg_err.555447031 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.rom_ctrl_tl_intg_err.555447031 -covoverwrite +skip_middle_of_rom=1' seed=12529059016647369806288150284869677645064473094030056320304816848006691910391 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12529059016647369806288150284869677645064473094030056320304816848006691910391 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/7.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_alert_test 11836741531572998088005415042160436702875630281540892646630526309495502203491 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/7.rom_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=3979012707 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/7.rom_ctrl_alert_test.3979012707 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 7.rom_ctrl_alert_test.3979012707 -covoverwrite +skip_middle_of_rom=1' seed=11836741531572998088005415042160436702875630281540892646630526309495502203491 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11836741531572998088005415042160436702875630281540892646630526309495502203491 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/7.rom_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 24895443408390548322753027963841130100445867739013914789161866999767265160466 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/8.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=2670963986 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/8.rom_ctrl_corrupt_sig_fatal_chk.2670963986 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 8.rom_ctrl_corrupt_sig_fatal_chk.2670963986 -covoverwrite +skip_middle_of_rom=1' seed=24895443408390548322753027963841130100445867739013914789161866999767265160466 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24895443408390548322753027963841130100445867739013914789161866999767265160466 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/8.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 88559499200104244490075744582376064747073019048733746733834947700615616936067 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/8.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=2301376643 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/8.rom_ctrl_stress_all_with_rand_reset.2301376643 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 8.rom_ctrl_stress_all_with_rand_reset.2301376643 -covoverwrite +skip_middle_of_rom=1' seed=88559499200104244490075744582376064747073019048733746733834947700615616936067 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88559499200104244490075744582376064747073019048733746733834947700615616936067 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/8.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 9940234158888140756464323610608408004460760181813108467494029039156705030673 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/8.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2698179089 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/8.rom_ctrl_tl_errors.2698179089 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.rom_ctrl_tl_errors.2698179089 -covoverwrite +skip_middle_of_rom=1' seed=9940234158888140756464323610608408004460760181813108467494029039156705030673 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9940234158888140756464323610608408004460760181813108467494029039156705030673 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/8.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 2800678870946642109825014334110389330482728937009572243285109238750101687100 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/8.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1337510716 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/8.rom_ctrl_tl_intg_err.1337510716 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.rom_ctrl_tl_intg_err.1337510716 -covoverwrite +skip_middle_of_rom=1' seed=2800678870946642109825014334110389330482728937009572243285109238750101687100 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2800678870946642109825014334110389330482728937009572243285109238750101687100 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/8.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_alert_test 89262065163101000059589758360018459202124715816708133794793473597850598114692 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/8.rom_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=2840462724 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/8.rom_ctrl_alert_test.2840462724 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 8.rom_ctrl_alert_test.2840462724 -covoverwrite +skip_middle_of_rom=1' seed=89262065163101000059589758360018459202124715816708133794793473597850598114692 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89262065163101000059589758360018459202124715816708133794793473597850598114692 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/8.rom_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 97634320377576316159369373183465407889194187865864859995302788009714289382342 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/9.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=916362182 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/9.rom_ctrl_corrupt_sig_fatal_chk.916362182 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 9.rom_ctrl_corrupt_sig_fatal_chk.916362182 -covoverwrite +skip_middle_of_rom=1' seed=97634320377576316159369373183465407889194187865864859995302788009714289382342 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97634320377576316159369373183465407889194187865864859995302788009714289382342 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/9.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 68375880149821057233276312108055327611069490280741201519673457989526989124137 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/9.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=2957849129 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/9.rom_ctrl_stress_all_with_rand_reset.2957849129 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 9.rom_ctrl_stress_all_with_rand_reset.2957849129 -covoverwrite +skip_middle_of_rom=1' seed=68375880149821057233276312108055327611069490280741201519673457989526989124137 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68375880149821057233276312108055327611069490280741201519673457989526989124137 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/9.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 397643103494237520962770834707997109733071957978085309373666807300919866063 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/9.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2982884047 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/9.rom_ctrl_tl_errors.2982884047 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.rom_ctrl_tl_errors.2982884047 -covoverwrite +skip_middle_of_rom=1' seed=397643103494237520962770834707997109733071957978085309373666807300919866063 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=397643103494237520962770834707997109733071957978085309373666807300919866063 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/9.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 44265951259880623402782518761658113581215659294350413951840280021187800754013 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/9.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=368207709 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/9.rom_ctrl_tl_intg_err.368207709 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.rom_ctrl_tl_intg_err.368207709 -covoverwrite +skip_middle_of_rom=1' seed=44265951259880623402782518761658113581215659294350413951840280021187800754013 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44265951259880623402782518761658113581215659294350413951840280021187800754013 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/9.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_alert_test 20076591484799137101386140203390131792363080300985455752467790693720606370081 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/9.rom_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=122415393 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/9.rom_ctrl_alert_test.122415393 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 9.rom_ctrl_alert_test.122415393 -covoverwrite +skip_middle_of_rom=1' seed=20076591484799137101386140203390131792363080300985455752467790693720606370081 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20076591484799137101386140203390131792363080300985455752467790693720606370081 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/9.rom_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 26412126600904769712808068477666483878378218798864794139703643589029775376456 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/10.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=1939177544 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/10.rom_ctrl_corrupt_sig_fatal_chk.1939177544 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 10.rom_ctrl_corrupt_sig_fatal_chk.1939177544 -covoverwrite +skip_middle_of_rom=1' seed=26412126600904769712808068477666483878378218798864794139703643589029775376456 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26412126600904769712808068477666483878378218798864794139703643589029775376456 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/10.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 33934423598992194220246343850732412358919278361011699223971990892923026542856 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/10.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=3088978184 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/10.rom_ctrl_stress_all_with_rand_reset.3088978184 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 10.rom_ctrl_stress_all_with_rand_reset.3088978184 -covoverwrite +skip_middle_of_rom=1' seed=33934423598992194220246343850732412358919278361011699223971990892923026542856 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33934423598992194220246343850732412358919278361011699223971990892923026542856 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/10.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 92753687608960653591986459445851643691236902355370179710761518250840322762974 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/10.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1694525662 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/10.rom_ctrl_tl_errors.1694525662 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 10.rom_ctrl_tl_errors.1694525662 -covoverwrite +skip_middle_of_rom=1' seed=92753687608960653591986459445851643691236902355370179710761518250840322762974 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92753687608960653591986459445851643691236902355370179710761518250840322762974 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/10.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 2504015834617196797014593575553441851267265865140498342289185840634679726367 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/10.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1250890015 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/10.rom_ctrl_tl_intg_err.1250890015 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 10.rom_ctrl_tl_intg_err.1250890015 -covoverwrite +skip_middle_of_rom=1' seed=2504015834617196797014593575553441851267265865140498342289185840634679726367 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2504015834617196797014593575553441851267265865140498342289185840634679726367 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/10.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 55546267394841887023912748200922252231071933517448602194146550922362537497552 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/11.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=1277547472 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/11.rom_ctrl_corrupt_sig_fatal_chk.1277547472 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 11.rom_ctrl_corrupt_sig_fatal_chk.1277547472 -covoverwrite +skip_middle_of_rom=1' seed=55546267394841887023912748200922252231071933517448602194146550922362537497552 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55546267394841887023912748200922252231071933517448602194146550922362537497552 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/11.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 23934449238418042641593305394821131550698953971705000665832389776692563141728 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/11.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=814998624 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/11.rom_ctrl_stress_all_with_rand_reset.814998624 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 11.rom_ctrl_stress_all_with_rand_reset.814998624 -covoverwrite +skip_middle_of_rom=1' seed=23934449238418042641593305394821131550698953971705000665832389776692563141728 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23934449238418042641593305394821131550698953971705000665832389776692563141728 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/11.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 29326798230787032071617593035688050484017744225626770797743447520077735582405 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/11.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2091178693 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/11.rom_ctrl_tl_errors.2091178693 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 11.rom_ctrl_tl_errors.2091178693 -covoverwrite +skip_middle_of_rom=1' seed=29326798230787032071617593035688050484017744225626770797743447520077735582405 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29326798230787032071617593035688050484017744225626770797743447520077735582405 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/11.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 73315235634494226935546526781364072093240977866736199113173502334370540577836 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/11.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3703465004 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/11.rom_ctrl_tl_intg_err.3703465004 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 11.rom_ctrl_tl_intg_err.3703465004 -covoverwrite +skip_middle_of_rom=1' seed=73315235634494226935546526781364072093240977866736199113173502334370540577836 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73315235634494226935546526781364072093240977866736199113173502334370540577836 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/11.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 76279534538145744130126599623455352832054469775755001452936674383921318634363 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/12.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=697213819 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/12.rom_ctrl_corrupt_sig_fatal_chk.697213819 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 12.rom_ctrl_corrupt_sig_fatal_chk.697213819 -covoverwrite +skip_middle_of_rom=1' seed=76279534538145744130126599623455352832054469775755001452936674383921318634363 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76279534538145744130126599623455352832054469775755001452936674383921318634363 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/12.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 28449783046860033276838002673598491379401143490618320212060353997091907740989 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/12.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=715040061 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/12.rom_ctrl_stress_all_with_rand_reset.715040061 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 12.rom_ctrl_stress_all_with_rand_reset.715040061 -covoverwrite +skip_middle_of_rom=1' seed=28449783046860033276838002673598491379401143490618320212060353997091907740989 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28449783046860033276838002673598491379401143490618320212060353997091907740989 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/12.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 70838794366456601732492930083291028104785486094337445179176693765060405538288 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/12.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=313306608 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/12.rom_ctrl_tl_errors.313306608 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 12.rom_ctrl_tl_errors.313306608 -covoverwrite +skip_middle_of_rom=1' seed=70838794366456601732492930083291028104785486094337445179176693765060405538288 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70838794366456601732492930083291028104785486094337445179176693765060405538288 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/12.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 104466211826902061169105195417709233852840301387947446659803342171368586413240 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/12.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2540897464 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/12.rom_ctrl_tl_intg_err.2540897464 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 12.rom_ctrl_tl_intg_err.2540897464 -covoverwrite +skip_middle_of_rom=1' seed=104466211826902061169105195417709233852840301387947446659803342171368586413240 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104466211826902061169105195417709233852840301387947446659803342171368586413240 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/12.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 108438838933742735327947686637254751413503509632968271005126505299815623200257 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/13.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=3131215361 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/13.rom_ctrl_corrupt_sig_fatal_chk.3131215361 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 13.rom_ctrl_corrupt_sig_fatal_chk.3131215361 -covoverwrite +skip_middle_of_rom=1' seed=108438838933742735327947686637254751413503509632968271005126505299815623200257 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108438838933742735327947686637254751413503509632968271005126505299815623200257 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/13.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 107347621320193020593310086063529179451407552410426647630408704597089369035754 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/13.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=4055733226 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/13.rom_ctrl_stress_all_with_rand_reset.4055733226 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 13.rom_ctrl_stress_all_with_rand_reset.4055733226 -covoverwrite +skip_middle_of_rom=1' seed=107347621320193020593310086063529179451407552410426647630408704597089369035754 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107347621320193020593310086063529179451407552410426647630408704597089369035754 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/13.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 61030518441545227659989039320653584274508592407206296057376547096583170500759 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/13.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2654283927 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/13.rom_ctrl_tl_errors.2654283927 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 13.rom_ctrl_tl_errors.2654283927 -covoverwrite +skip_middle_of_rom=1' seed=61030518441545227659989039320653584274508592407206296057376547096583170500759 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61030518441545227659989039320653584274508592407206296057376547096583170500759 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/13.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 72537449656250707886051068553469062283269304926563458632317085992651898978280 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/13.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=563052520 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/13.rom_ctrl_tl_intg_err.563052520 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 13.rom_ctrl_tl_intg_err.563052520 -covoverwrite +skip_middle_of_rom=1' seed=72537449656250707886051068553469062283269304926563458632317085992651898978280 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72537449656250707886051068553469062283269304926563458632317085992651898978280 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/13.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 77421950970032611458366069685024575151077625562793661174932446910480480510062 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/14.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=1765843054 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/14.rom_ctrl_corrupt_sig_fatal_chk.1765843054 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 14.rom_ctrl_corrupt_sig_fatal_chk.1765843054 -covoverwrite +skip_middle_of_rom=1' seed=77421950970032611458366069685024575151077625562793661174932446910480480510062 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77421950970032611458366069685024575151077625562793661174932446910480480510062 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/14.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 102879555394608796825653268864657659826076571451886567295449340061517195432398 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/14.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=1442501070 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/14.rom_ctrl_stress_all_with_rand_reset.1442501070 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 14.rom_ctrl_stress_all_with_rand_reset.1442501070 -covoverwrite +skip_middle_of_rom=1' seed=102879555394608796825653268864657659826076571451886567295449340061517195432398 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102879555394608796825653268864657659826076571451886567295449340061517195432398 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/14.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 67781743590163727261584649206241109333044194844801670536404659028558916784107 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/14.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=501387243 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/14.rom_ctrl_tl_errors.501387243 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 14.rom_ctrl_tl_errors.501387243 -covoverwrite +skip_middle_of_rom=1' seed=67781743590163727261584649206241109333044194844801670536404659028558916784107 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67781743590163727261584649206241109333044194844801670536404659028558916784107 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/14.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 75508442844658845681061220183412696644136937910522143876034672954514952006808 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/14.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1669180568 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/14.rom_ctrl_tl_intg_err.1669180568 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 14.rom_ctrl_tl_intg_err.1669180568 -covoverwrite +skip_middle_of_rom=1' seed=75508442844658845681061220183412696644136937910522143876034672954514952006808 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75508442844658845681061220183412696644136937910522143876034672954514952006808 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/14.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 101513618402631124981823045689060775820135870562988419614049024210039622786313 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/15.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=2090523913 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/15.rom_ctrl_corrupt_sig_fatal_chk.2090523913 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 15.rom_ctrl_corrupt_sig_fatal_chk.2090523913 -covoverwrite +skip_middle_of_rom=1' seed=101513618402631124981823045689060775820135870562988419614049024210039622786313 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101513618402631124981823045689060775820135870562988419614049024210039622786313 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/15.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 11961902833586773425876290628713177079157120472674523212091905565189116044003 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/15.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=1917100771 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/15.rom_ctrl_stress_all_with_rand_reset.1917100771 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 15.rom_ctrl_stress_all_with_rand_reset.1917100771 -covoverwrite +skip_middle_of_rom=1' seed=11961902833586773425876290628713177079157120472674523212091905565189116044003 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11961902833586773425876290628713177079157120472674523212091905565189116044003 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/15.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 23748459912646695964124777795219548918520943704263518356620287740125838075160 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/15.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3471074584 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/15.rom_ctrl_tl_errors.3471074584 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 15.rom_ctrl_tl_errors.3471074584 -covoverwrite +skip_middle_of_rom=1' seed=23748459912646695964124777795219548918520943704263518356620287740125838075160 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23748459912646695964124777795219548918520943704263518356620287740125838075160 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/15.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 61004751270256339999841558617154402798128834390774596701804734421382772346082 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/15.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1506331874 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/15.rom_ctrl_tl_intg_err.1506331874 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 15.rom_ctrl_tl_intg_err.1506331874 -covoverwrite +skip_middle_of_rom=1' seed=61004751270256339999841558617154402798128834390774596701804734421382772346082 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61004751270256339999841558617154402798128834390774596701804734421382772346082 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/15.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 7159255855337485029337079443007782217832028784409911842769407540424946140420 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/16.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=422233348 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/16.rom_ctrl_corrupt_sig_fatal_chk.422233348 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 16.rom_ctrl_corrupt_sig_fatal_chk.422233348 -covoverwrite +skip_middle_of_rom=1' seed=7159255855337485029337079443007782217832028784409911842769407540424946140420 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7159255855337485029337079443007782217832028784409911842769407540424946140420 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/16.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 33848449786173734420084032990146906901057530971488700611027809297715377509697 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/16.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=906532161 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/16.rom_ctrl_stress_all_with_rand_reset.906532161 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 16.rom_ctrl_stress_all_with_rand_reset.906532161 -covoverwrite +skip_middle_of_rom=1' seed=33848449786173734420084032990146906901057530971488700611027809297715377509697 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33848449786173734420084032990146906901057530971488700611027809297715377509697 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/16.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 98573624754776728931124769177474654389290347654644769188202515921031977993607 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/16.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1184597383 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/16.rom_ctrl_tl_errors.1184597383 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 16.rom_ctrl_tl_errors.1184597383 -covoverwrite +skip_middle_of_rom=1' seed=98573624754776728931124769177474654389290347654644769188202515921031977993607 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98573624754776728931124769177474654389290347654644769188202515921031977993607 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/16.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 55129049559170255087369456468874418933652824809876266563943805819135497269224 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/16.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2579689448 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/16.rom_ctrl_tl_intg_err.2579689448 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 16.rom_ctrl_tl_intg_err.2579689448 -covoverwrite +skip_middle_of_rom=1' seed=55129049559170255087369456468874418933652824809876266563943805819135497269224 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55129049559170255087369456468874418933652824809876266563943805819135497269224 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/16.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 20704953004143432623567596281022774805215453723423445034181612126072085504190 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/17.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=1012752574 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/17.rom_ctrl_corrupt_sig_fatal_chk.1012752574 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 17.rom_ctrl_corrupt_sig_fatal_chk.1012752574 -covoverwrite +skip_middle_of_rom=1' seed=20704953004143432623567596281022774805215453723423445034181612126072085504190 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20704953004143432623567596281022774805215453723423445034181612126072085504190 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/17.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 66140161028089011389716829809153751951958943681122409567927968423150866985496 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/17.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=3425497624 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/17.rom_ctrl_stress_all_with_rand_reset.3425497624 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 17.rom_ctrl_stress_all_with_rand_reset.3425497624 -covoverwrite +skip_middle_of_rom=1' seed=66140161028089011389716829809153751951958943681122409567927968423150866985496 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66140161028089011389716829809153751951958943681122409567927968423150866985496 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/17.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 37581243168046531760719560138740723019905099706737427917554050934466786498394 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/17.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1412044634 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/17.rom_ctrl_tl_errors.1412044634 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 17.rom_ctrl_tl_errors.1412044634 -covoverwrite +skip_middle_of_rom=1' seed=37581243168046531760719560138740723019905099706737427917554050934466786498394 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37581243168046531760719560138740723019905099706737427917554050934466786498394 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/17.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 65447019483767893490295896064677170740588281527761135353877686198279334235731 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/17.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3362229843 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/17.rom_ctrl_tl_intg_err.3362229843 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 17.rom_ctrl_tl_intg_err.3362229843 -covoverwrite +skip_middle_of_rom=1' seed=65447019483767893490295896064677170740588281527761135353877686198279334235731 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65447019483767893490295896064677170740588281527761135353877686198279334235731 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/17.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 8584477296097844996775374722410724639572584946666416480135603308544431474192 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/18.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=445105680 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/18.rom_ctrl_corrupt_sig_fatal_chk.445105680 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 18.rom_ctrl_corrupt_sig_fatal_chk.445105680 -covoverwrite +skip_middle_of_rom=1' seed=8584477296097844996775374722410724639572584946666416480135603308544431474192 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8584477296097844996775374722410724639572584946666416480135603308544431474192 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/18.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 7556394049490393475865617077509814587487373905720519400618613619095276062828 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/18.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=29067372 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/18.rom_ctrl_stress_all_with_rand_reset.29067372 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 18.rom_ctrl_stress_all_with_rand_reset.29067372 -covoverwrite +skip_middle_of_rom=1' seed=7556394049490393475865617077509814587487373905720519400618613619095276062828 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7556394049490393475865617077509814587487373905720519400618613619095276062828 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/18.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 50346589945703934868917586094151980968546121036468818663329806091253201402294 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/18.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2508356022 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/18.rom_ctrl_tl_errors.2508356022 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 18.rom_ctrl_tl_errors.2508356022 -covoverwrite +skip_middle_of_rom=1' seed=50346589945703934868917586094151980968546121036468818663329806091253201402294 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50346589945703934868917586094151980968546121036468818663329806091253201402294 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/18.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 109137190275497269090980635058897878278503321745120487024468875386650933377564 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/18.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2328934940 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/18.rom_ctrl_tl_intg_err.2328934940 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 18.rom_ctrl_tl_intg_err.2328934940 -covoverwrite +skip_middle_of_rom=1' seed=109137190275497269090980635058897878278503321745120487024468875386650933377564 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109137190275497269090980635058897878278503321745120487024468875386650933377564 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/18.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_corrupt_sig_fatal_chk 73949721820460594783939471333840841713397120186854874594632280047735553504561 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/19.rom_ctrl_corrupt_sig_fatal_chk/latest run_opts='+skip_middle_of_rom=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=1844557105 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_corrupt_sig_fatal_chk_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/19.rom_ctrl_corrupt_sig_fatal_chk.1844557105 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 19.rom_ctrl_corrupt_sig_fatal_chk.1844557105 -covoverwrite +skip_middle_of_rom=1' seed=73949721820460594783939471333840841713397120186854874594632280047735553504561 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73949721820460594783939471333840841713397120186854874594632280047735553504561 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/19.rom_ctrl_corrupt_sig_fatal_chk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_corrupt_sig_fatal_chk_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_stress_all_with_rand_reset 63715709750253665585132812758255523026640165618662351168613325686081665156602 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/19.rom_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rom_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/default/xcelium.d -r tb +SVSEED=543475194 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/default/19.rom_ctrl_stress_all_with_rand_reset.543475194 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope default -covtest 19.rom_ctrl_stress_all_with_rand_reset.543475194 -covoverwrite +skip_middle_of_rom=1' seed=63715709750253665585132812758255523026640165618662351168613325686081665156602 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63715709750253665585132812758255523026640165618662351168613325686081665156602 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/19.rom_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 101638741749563662984790968617319929796899893285140888476392864660416492931441 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/19.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=721881457 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/19.rom_ctrl_tl_errors.721881457 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 19.rom_ctrl_tl_errors.721881457 -covoverwrite +skip_middle_of_rom=1' seed=101638741749563662984790968617319929796899893285140888476392864660416492931441 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101638741749563662984790968617319929796899893285140888476392864660416492931441 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/19.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 60754121296860286757056621676765294409469972930004473241565434992686767174810 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/19.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3690624154 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/19.rom_ctrl_tl_intg_err.3690624154 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 19.rom_ctrl_tl_intg_err.3690624154 -covoverwrite +skip_middle_of_rom=1' seed=60754121296860286757056621676765294409469972930004473241565434992686767174810 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60754121296860286757056621676765294409469972930004473241565434992686767174810 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/19.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 53493260385549131055877584660022417464826461705370649511105119814712584513663 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/20.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1759193215 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/20.rom_ctrl_tl_errors.1759193215 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 20.rom_ctrl_tl_errors.1759193215 -covoverwrite +skip_middle_of_rom=1' seed=53493260385549131055877584660022417464826461705370649511105119814712584513663 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53493260385549131055877584660022417464826461705370649511105119814712584513663 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/20.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 11238577559785955737899523685051584572532445353287348484622516713326800863665 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/20.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1176830385 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/20.rom_ctrl_tl_intg_err.1176830385 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 20.rom_ctrl_tl_intg_err.1176830385 -covoverwrite +skip_middle_of_rom=1' seed=11238577559785955737899523685051584572532445353287348484622516713326800863665 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11238577559785955737899523685051584572532445353287348484622516713326800863665 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/20.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 46168630453342314968034882612582487789546121408981504892337646070377821843679 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/21.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4196217055 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/21.rom_ctrl_tl_errors.4196217055 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 21.rom_ctrl_tl_errors.4196217055 -covoverwrite +skip_middle_of_rom=1' seed=46168630453342314968034882612582487789546121408981504892337646070377821843679 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46168630453342314968034882612582487789546121408981504892337646070377821843679 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/21.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 61709597923004369217340838739051352677584171059996352456096760396009339806343 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/21.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1540547207 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/21.rom_ctrl_tl_intg_err.1540547207 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 21.rom_ctrl_tl_intg_err.1540547207 -covoverwrite +skip_middle_of_rom=1' seed=61709597923004369217340838739051352677584171059996352456096760396009339806343 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61709597923004369217340838739051352677584171059996352456096760396009339806343 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/21.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 91935389172658785658972987421106239397709902532801307869221978585831682895956 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/22.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1092907092 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/22.rom_ctrl_tl_errors.1092907092 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 22.rom_ctrl_tl_errors.1092907092 -covoverwrite +skip_middle_of_rom=1' seed=91935389172658785658972987421106239397709902532801307869221978585831682895956 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91935389172658785658972987421106239397709902532801307869221978585831682895956 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/22.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 112958416447141668190398601305274752062084172236039750506417556380228122976504 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/22.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1500913912 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/22.rom_ctrl_tl_intg_err.1500913912 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 22.rom_ctrl_tl_intg_err.1500913912 -covoverwrite +skip_middle_of_rom=1' seed=112958416447141668190398601305274752062084172236039750506417556380228122976504 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112958416447141668190398601305274752062084172236039750506417556380228122976504 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/22.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 10534000074306791861198726236283638929266602436768266538835498746409473839627 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/23.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2870776331 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/23.rom_ctrl_tl_errors.2870776331 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 23.rom_ctrl_tl_errors.2870776331 -covoverwrite +skip_middle_of_rom=1' seed=10534000074306791861198726236283638929266602436768266538835498746409473839627 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10534000074306791861198726236283638929266602436768266538835498746409473839627 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/23.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 79531988873095132579614059937463845914355084633885410228911098150118161205838 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/23.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1157974606 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/23.rom_ctrl_tl_intg_err.1157974606 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 23.rom_ctrl_tl_intg_err.1157974606 -covoverwrite +skip_middle_of_rom=1' seed=79531988873095132579614059937463845914355084633885410228911098150118161205838 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79531988873095132579614059937463845914355084633885410228911098150118161205838 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/23.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_errors 54289041364953358990861846512092972949238289976790666588806621550886277502189 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/24.rom_ctrl_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=280909037 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/24.rom_ctrl_tl_errors.280909037 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 24.rom_ctrl_tl_errors.280909037 -covoverwrite +skip_middle_of_rom=1' seed=54289041364953358990861846512092972949238289976790666588806621550886277502189 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54289041364953358990861846512092972949238289976790666588806621550886277502189 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/24.rom_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rom_ctrl_tl_intg_err 71886681622584710164443324088187218255230312297935443478292551619081238232758 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/24.rom_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2354593462 +UVM_TESTNAME=rom_ctrl_base_test +UVM_TEST_SEQ=rom_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage/cover_reg_top/24.rom_ctrl_tl_intg_err.2354593462 -covworkdir /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/coverage -covscope cover_reg_top -covtest 24.rom_ctrl_tl_intg_err.2354593462 -covoverwrite +skip_middle_of_rom=1' seed=71886681622584710164443324088187218255230312297935443478292551619081238232758 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71886681622584710164443324088187218255230312297935443478292551619081238232758 --run-dir=/nightly/current_run/scratch/master/rom_ctrl_64kB-sim-xcelium/24.rom_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rom_ctrl_base_test uvm_test_seq=rom_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
Job timed out after * minutes 12 test runs
rom_ctrl_stress_all 35450892126685472635454503863372276147763352590376071232238696668666339427268 None
rom_ctrl_stress_all 73067153301843524665391013887364254439735527690779759077505904758645449108617 None
rom_ctrl_stress_all 1729361011324772622641027045907365037681448961989967125616450153787118080955 None
rom_ctrl_stress_all 44113539097851294583026811681611885593640658923636441265996769867168530179348 None
rom_ctrl_stress_all 52851643852784781953731994684093965541893539681683448099136789971572287884345 None
rom_ctrl_stress_all 110537214222488684160040884944879310268370992073276202890079799170444419185216 None
rom_ctrl_stress_all 13013895769118997017023399325436026264271452600930408488671793605524122998407 None
rom_ctrl_stress_all 96181151301940801913261151948497864008748224344579439795698878861875570163867 None
rom_ctrl_stress_all 81134584253210537492635489844449390377602044874874173075449744076869692710603 None
rom_ctrl_stress_all 45656028078560558557959866404232859921694411742741734831763037238238565602838 None
rom_ctrl_stress_all 77123027284946338521055614769225652346412716158004622736855358887308904592121 None
rom_ctrl_stress_all 57241011533498947187143405713418194701542354747430863301094249628647520949338 None
Job returned a non-zero exit code: * 1 test run
rom_ctrl None None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk cov_merge cov_merge_cmd=imc cov_merge_opts='-64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl'
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:109: cov_merge] Error 126
Job cancelled because one of its dependencies failed or was killed. 1 test run
rom_ctrl None None