Simulation Results: rstmgr

 
28/08/2026 21:54:34 DVSim: v1.49.0 sha: a099412 json Branch: master Tool: vcs [unknown]
Validation stages
V1
0.00%
V2
6.94%
V2S
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 0 5 0.00
rstmgr_smoke 1.430s 0.000us 0 5 0.00
csr_hw_reset 0 1 0.00
rstmgr_csr_hw_reset 0.818s 0.000us 0 1 0.00
csr_rw 0 5 0.00
rstmgr_csr_rw 1.510s 0.000us 0 5 0.00
csr_bit_bash 0 1 0.00
rstmgr_csr_bit_bash 0.849s 0.000us 0 1 0.00
csr_aliasing 0 1 0.00
rstmgr_csr_aliasing 0.848s 0.000us 0 1 0.00
csr_mem_rw_with_rand_reset 0 5 0.00
rstmgr_csr_mem_rw_with_rand_reset 0.851s 0.000us 0 5 0.00
regwen_csr_and_corresponding_lockable_csr 0 6 0.00
rstmgr_csr_rw 1.510s 0.000us 0 5 0.00
rstmgr_csr_aliasing 0.848s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 0 5 0.00
rstmgr_por_stretcher 1.559s 0.000us 0 5 0.00
sw_rst 0 5 0.00
rstmgr_sw_rst 0.884s 0.000us 0 5 0.00
sw_rst_reset_race 0 5 0.00
rstmgr_sw_rst_reset_race 0.869s 0.000us 0 5 0.00
reset_info 0 5 0.00
rstmgr_reset 1.434s 0.000us 0 5 0.00
cpu_info 0 5 0.00
rstmgr_reset 1.434s 0.000us 0 5 0.00
alert_info 0 5 0.00
rstmgr_reset 1.434s 0.000us 0 5 0.00
reset_info_capture 0 5 0.00
rstmgr_reset 1.434s 0.000us 0 5 0.00
stress_all 5 5 100.00
rstmgr_stress_all 45.370s 3724.806us 5 5 100.00
alert_test 0 10 0.00
rstmgr_alert_test 1.561s 0.000us 0 10 0.00
tl_d_oob_addr_access 0 25 0.00
rstmgr_tl_errors 1.543s 0.000us 0 25 0.00
tl_d_illegal_access 0 25 0.00
rstmgr_tl_errors 1.543s 0.000us 0 25 0.00
tl_d_outstanding_access 0 12 0.00
rstmgr_csr_hw_reset 0.818s 0.000us 0 1 0.00
rstmgr_csr_rw 1.510s 0.000us 0 5 0.00
rstmgr_csr_aliasing 0.848s 0.000us 0 1 0.00
rstmgr_same_csr_outstanding 1.423s 0.000us 0 5 0.00
tl_d_partial_access 0 12 0.00
rstmgr_csr_hw_reset 0.818s 0.000us 0 1 0.00
rstmgr_csr_rw 1.510s 0.000us 0 5 0.00
rstmgr_csr_aliasing 0.848s 0.000us 0 1 0.00
rstmgr_same_csr_outstanding 1.423s 0.000us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 30 0.00
rstmgr_sec_cm 1.555s 0.000us 0 5 0.00
rstmgr_tl_intg_err 1.544s 0.000us 0 25 0.00
prim_count_check 0 5 0.00
rstmgr_sec_cm 1.555s 0.000us 0 5 0.00
prim_fsm_check 0 5 0.00
rstmgr_sec_cm 1.555s 0.000us 0 5 0.00
sec_cm_bus_integrity 0 25 0.00
rstmgr_tl_intg_err 1.544s 0.000us 0 25 0.00
sec_cm_scan_intersig_mubi 0 5 0.00
rstmgr_sec_cm_scan_intersig_mubi 2.135s 0.000us 0 5 0.00
sec_cm_leaf_rst_bkgn_chk 0 25 0.00
rstmgr_leaf_rst_cnsty 0.872s 0.000us 0 25 0.00
sec_cm_leaf_rst_shadow 0 5 0.00
rstmgr_leaf_rst_shadow_attack 0.897s 0.000us 0 5 0.00
sec_cm_leaf_fsm_sparse 0 5 0.00
rstmgr_sec_cm 1.555s 0.000us 0 5 0.00
sec_cm_sw_rst_config_regwen 0 5 0.00
rstmgr_csr_rw 1.510s 0.000us 0 5 0.00
sec_cm_dump_ctrl_config_regwen 0 5 0.00
rstmgr_csr_rw 1.510s 0.000us 0 5 0.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 143 test runs
rstmgr_smoke 46553590466753820067183603433370722024303944740822006125879181141593850219563 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/0.rstmgr_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=234458155 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.234458155' seed=46553590466753820067183603433370722024303944740822006125879181141593850219563 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46553590466753820067183603433370722024303944740822006125879181141593850219563 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/0.rstmgr_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_por_stretcher 9606283048285211376574645038032877437910835301452394220358100009693968670458 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/0.rstmgr_por_stretcher/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2087788282 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.2087788282' seed=9606283048285211376574645038032877437910835301452394220358100009693968670458 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9606283048285211376574645038032877437910835301452394220358100009693968670458 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/0.rstmgr_por_stretcher/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_por_stretcher_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_reset 36124324136294501054504208153235426640607250134968852904402916046348437331844 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/0.rstmgr_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2154733444 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.2154733444' seed=36124324136294501054504208153235426640607250134968852904402916046348437331844 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36124324136294501054504208153235426640607250134968852904402916046348437331844 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/0.rstmgr_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_sw_rst_reset_race 66340849093362903538594170231533206359759619194762537148705482074858040319393 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/0.rstmgr_sw_rst_reset_race/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4102544801 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.4102544801' seed=66340849093362903538594170231533206359759619194762537148705482074858040319393 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66340849093362903538594170231533206359759619194762537148705482074858040319393 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/0.rstmgr_sw_rst_reset_race/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_sw_rst_reset_race_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_sw_rst 9004717500051011347091439918066699550764270434162634448810083440166894150862 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/0.rstmgr_sw_rst/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=136422606 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.136422606' seed=9004717500051011347091439918066699550764270434162634448810083440166894150862 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9004717500051011347091439918066699550764270434162634448810083440166894150862 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/0.rstmgr_sw_rst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_sw_rst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_sec_cm_scan_intersig_mubi 78543392616917899714657454682493854196743207149479444284384474172445362322457 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/0.rstmgr_sec_cm_scan_intersig_mubi/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1268349977 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.1268349977' seed=78543392616917899714657454682493854196743207149479444284384474172445362322457 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78543392616917899714657454682493854196743207149479444284384474172445362322457 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/0.rstmgr_sec_cm_scan_intersig_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_sec_cm_scan_intersig_mubi_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_leaf_rst_cnsty 108202842937055233244389643668800939776299951766224730824077400118626508828581 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/0.rstmgr_leaf_rst_cnsty/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3743903653 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.3743903653' seed=108202842937055233244389643668800939776299951766224730824077400118626508828581 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108202842937055233244389643668800939776299951766224730824077400118626508828581 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/0.rstmgr_leaf_rst_cnsty/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_leaf_rst_cnsty_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_leaf_rst_shadow_attack 15806009118426996389336715581313502760095657512036978726580010549905305468075 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/0.rstmgr_leaf_rst_shadow_attack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2289401003 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.2289401003' seed=15806009118426996389336715581313502760095657512036978726580010549905305468075 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15806009118426996389336715581313502760095657512036978726580010549905305468075 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/0.rstmgr_leaf_rst_shadow_attack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_leaf_rst_shadow_attack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_sec_cm 80323914492936794322282514602924991667061498599941975009765409092583851577977 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/0.rstmgr_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1563185785 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.1563185785' seed=80323914492936794322282514602924991667061498599941975009765409092583851577977 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80323914492936794322282514602924991667061498599941975009765409092583851577977 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/0.rstmgr_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_errors 7647997523770490164988008299929049352070780130573657101160774153356210960126 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/0.rstmgr_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2738976510 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.2738976510' seed=7647997523770490164988008299929049352070780130573657101160774153356210960126 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7647997523770490164988008299929049352070780130573657101160774153356210960126 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/0.rstmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_intg_err 54758977829321913643315236976250583284592979529153827914217790221362636632662 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/0.rstmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1004909142 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err.1004909142' seed=54758977829321913643315236976250583284592979529153827914217790221362636632662 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54758977829321913643315236976250583284592979529153827914217790221362636632662 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/0.rstmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_alert_test 24588488597906179881080158865331441289933524092816384538816194969208200867115 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/0.rstmgr_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2817764651 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.2817764651' seed=24588488597906179881080158865331441289933524092816384538816194969208200867115 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24588488597906179881080158865331441289933524092816384538816194969208200867115 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/0.rstmgr_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_csr_hw_reset 64914947110452586874601389634165823116303336436858962410270155194875773347252 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/0.rstmgr_csr_hw_reset/latest run_opts='+csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2066113972 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.2066113972' seed=64914947110452586874601389634165823116303336436858962410270155194875773347252 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64914947110452586874601389634165823116303336436858962410270155194875773347252 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/0.rstmgr_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_csr_rw 50990406135110565547809341706529555559041805803123207479654761180534824268434 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/0.rstmgr_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1912369810 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.1912369810' seed=50990406135110565547809341706529555559041805803123207479654761180534824268434 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50990406135110565547809341706529555559041805803123207479654761180534824268434 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/0.rstmgr_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_csr_bit_bash 38869742594205751661803692389755509461926540084473906617843519489904448156813 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/0.rstmgr_csr_bit_bash/latest run_opts='+csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=183809165 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.183809165' seed=38869742594205751661803692389755509461926540084473906617843519489904448156813 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38869742594205751661803692389755509461926540084473906617843519489904448156813 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/0.rstmgr_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_csr_aliasing 67987868041820894029405773393607888736303506521389969459774425807339751349897 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/0.rstmgr_csr_aliasing/latest run_opts='+csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1859788425 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.1859788425' seed=67987868041820894029405773393607888736303506521389969459774425807339751349897 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67987868041820894029405773393607888736303506521389969459774425807339751349897 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/0.rstmgr_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_same_csr_outstanding 67882557265216163496762908373152812351551309975976970154492438595037126785975 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/0.rstmgr_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3064003511 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_same_csr_outstanding.3064003511' seed=67882557265216163496762908373152812351551309975976970154492438595037126785975 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67882557265216163496762908373152812351551309975976970154492438595037126785975 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/0.rstmgr_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_csr_mem_rw_with_rand_reset 1825947698810115719376951114770332324790252225566880050046176003588881097381 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/0.rstmgr_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=296460965 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.296460965' seed=1825947698810115719376951114770332324790252225566880050046176003588881097381 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1825947698810115719376951114770332324790252225566880050046176003588881097381 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/0.rstmgr_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_smoke 51003083723417729735199246380756473236422397673572502486960355107492344025223 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/1.rstmgr_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3003043975 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.3003043975' seed=51003083723417729735199246380756473236422397673572502486960355107492344025223 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51003083723417729735199246380756473236422397673572502486960355107492344025223 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/1.rstmgr_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_por_stretcher 111426925184801034773630009010927992546534810284012030255159505615991115461453 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/1.rstmgr_por_stretcher/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=497922893 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.497922893' seed=111426925184801034773630009010927992546534810284012030255159505615991115461453 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111426925184801034773630009010927992546534810284012030255159505615991115461453 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/1.rstmgr_por_stretcher/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_por_stretcher_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_reset 30766843876562899343663974121708484421555885221597706306842468736941773544915 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/1.rstmgr_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3484147155 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.3484147155' seed=30766843876562899343663974121708484421555885221597706306842468736941773544915 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30766843876562899343663974121708484421555885221597706306842468736941773544915 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/1.rstmgr_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_sw_rst_reset_race 99261739144312134677602317010808319921872160181161818953604081101768056887961 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/1.rstmgr_sw_rst_reset_race/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=658496153 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.658496153' seed=99261739144312134677602317010808319921872160181161818953604081101768056887961 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99261739144312134677602317010808319921872160181161818953604081101768056887961 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/1.rstmgr_sw_rst_reset_race/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_sw_rst_reset_race_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_sw_rst 39123302944545218005945865063160045013403040738583148263032748235447226221325 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/1.rstmgr_sw_rst/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1462125325 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.1462125325' seed=39123302944545218005945865063160045013403040738583148263032748235447226221325 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39123302944545218005945865063160045013403040738583148263032748235447226221325 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/1.rstmgr_sw_rst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_sw_rst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_sec_cm_scan_intersig_mubi 57588286342319060791664983425780620919983428531970760670670846766512762582478 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/1.rstmgr_sec_cm_scan_intersig_mubi/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3076584910 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.3076584910' seed=57588286342319060791664983425780620919983428531970760670670846766512762582478 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57588286342319060791664983425780620919983428531970760670670846766512762582478 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/1.rstmgr_sec_cm_scan_intersig_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_sec_cm_scan_intersig_mubi_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_leaf_rst_cnsty 93865230039702497647473658217700463941780054420358139661870857397652315263628 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/1.rstmgr_leaf_rst_cnsty/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3447280268 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.3447280268' seed=93865230039702497647473658217700463941780054420358139661870857397652315263628 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93865230039702497647473658217700463941780054420358139661870857397652315263628 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/1.rstmgr_leaf_rst_cnsty/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_leaf_rst_cnsty_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_leaf_rst_shadow_attack 6026133938248346724989830037797433358824833510578250102650964719936394959817 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/1.rstmgr_leaf_rst_shadow_attack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4265024457 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.4265024457' seed=6026133938248346724989830037797433358824833510578250102650964719936394959817 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6026133938248346724989830037797433358824833510578250102650964719936394959817 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/1.rstmgr_leaf_rst_shadow_attack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_leaf_rst_shadow_attack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_sec_cm 90657829687587354558137909392000851706408674934102173939036321189286314956977 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/1.rstmgr_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=543611057 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.543611057' seed=90657829687587354558137909392000851706408674934102173939036321189286314956977 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90657829687587354558137909392000851706408674934102173939036321189286314956977 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/1.rstmgr_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_errors 12876593505167149557691283959346553414442049733901390198303584542475708943258 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/1.rstmgr_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=970869658 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.970869658' seed=12876593505167149557691283959346553414442049733901390198303584542475708943258 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12876593505167149557691283959346553414442049733901390198303584542475708943258 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/1.rstmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_intg_err 110836452803442666286591717422198822405465456555091403952524914538104141503290 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/1.rstmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2644106042 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err.2644106042' seed=110836452803442666286591717422198822405465456555091403952524914538104141503290 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110836452803442666286591717422198822405465456555091403952524914538104141503290 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/1.rstmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_alert_test 36101462338935047231641423656405857210389906367121183798423615616472437023910 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/1.rstmgr_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2440619174 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.2440619174' seed=36101462338935047231641423656405857210389906367121183798423615616472437023910 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36101462338935047231641423656405857210389906367121183798423615616472437023910 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/1.rstmgr_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_csr_rw 19648818335235826222510559344631499348563610609758462862586950142342749464154 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/1.rstmgr_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3242960474 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.3242960474' seed=19648818335235826222510559344631499348563610609758462862586950142342749464154 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19648818335235826222510559344631499348563610609758462862586950142342749464154 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/1.rstmgr_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_same_csr_outstanding 108395402676630157581116152139500862212898770023874622594403600110586772815886 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/1.rstmgr_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1043824654 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_same_csr_outstanding.1043824654' seed=108395402676630157581116152139500862212898770023874622594403600110586772815886 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108395402676630157581116152139500862212898770023874622594403600110586772815886 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/1.rstmgr_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_csr_mem_rw_with_rand_reset 104952359143737654170374362943076149767765071365956468591734338168212002273297 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/1.rstmgr_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1322350609 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.1322350609' seed=104952359143737654170374362943076149767765071365956468591734338168212002273297 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104952359143737654170374362943076149767765071365956468591734338168212002273297 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/1.rstmgr_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_smoke 47217893564259295223327334564275849658919853741655415587229266253772630372081 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/2.rstmgr_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1309781745 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.1309781745' seed=47217893564259295223327334564275849658919853741655415587229266253772630372081 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47217893564259295223327334564275849658919853741655415587229266253772630372081 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/2.rstmgr_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_por_stretcher 40193427806436307518373223973195589216536448512831363553065006929765940436860 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/2.rstmgr_por_stretcher/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2823135100 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.2823135100' seed=40193427806436307518373223973195589216536448512831363553065006929765940436860 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40193427806436307518373223973195589216536448512831363553065006929765940436860 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/2.rstmgr_por_stretcher/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_por_stretcher_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_reset 81585544178232973215225967153749188682430794974781141677843099219823359499719 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/2.rstmgr_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1047600583 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.1047600583' seed=81585544178232973215225967153749188682430794974781141677843099219823359499719 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81585544178232973215225967153749188682430794974781141677843099219823359499719 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/2.rstmgr_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_sw_rst_reset_race 113542845727375352995480715516609936294225847545916318027059806181100524840232 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/2.rstmgr_sw_rst_reset_race/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4132873512 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.4132873512' seed=113542845727375352995480715516609936294225847545916318027059806181100524840232 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113542845727375352995480715516609936294225847545916318027059806181100524840232 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/2.rstmgr_sw_rst_reset_race/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_sw_rst_reset_race_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_sw_rst 27997397718106982262940289148773952315437368782895025949456810617685697845631 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/2.rstmgr_sw_rst/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1189828991 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.1189828991' seed=27997397718106982262940289148773952315437368782895025949456810617685697845631 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27997397718106982262940289148773952315437368782895025949456810617685697845631 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/2.rstmgr_sw_rst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_sw_rst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_sec_cm_scan_intersig_mubi 70939538768693201642937109690599843480905850050876181142291239103514229076383 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/2.rstmgr_sec_cm_scan_intersig_mubi/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=379056543 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.379056543' seed=70939538768693201642937109690599843480905850050876181142291239103514229076383 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70939538768693201642937109690599843480905850050876181142291239103514229076383 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/2.rstmgr_sec_cm_scan_intersig_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_sec_cm_scan_intersig_mubi_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_leaf_rst_cnsty 46874977001377382766301246747653911276398533999710071710269841107968771778245 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/2.rstmgr_leaf_rst_cnsty/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3946342085 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.3946342085' seed=46874977001377382766301246747653911276398533999710071710269841107968771778245 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46874977001377382766301246747653911276398533999710071710269841107968771778245 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/2.rstmgr_leaf_rst_cnsty/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_leaf_rst_cnsty_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_leaf_rst_shadow_attack 69105175046052365058100368694012807445178896398657376906171690877190553457878 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/2.rstmgr_leaf_rst_shadow_attack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=141022422 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.141022422' seed=69105175046052365058100368694012807445178896398657376906171690877190553457878 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69105175046052365058100368694012807445178896398657376906171690877190553457878 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/2.rstmgr_leaf_rst_shadow_attack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_leaf_rst_shadow_attack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_sec_cm 28671999607046209663589423822447102659282598685324355834869112840310647173806 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/2.rstmgr_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3341562542 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.3341562542' seed=28671999607046209663589423822447102659282598685324355834869112840310647173806 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28671999607046209663589423822447102659282598685324355834869112840310647173806 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/2.rstmgr_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_errors 1523994836831235525735452700539137559021713714606291567812473315829428027004 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/2.rstmgr_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4029709948 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.4029709948' seed=1523994836831235525735452700539137559021713714606291567812473315829428027004 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1523994836831235525735452700539137559021713714606291567812473315829428027004 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/2.rstmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_intg_err 11036957886218056196730804942652810471819841257895035930095200467257709515928 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/2.rstmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3745207448 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err.3745207448' seed=11036957886218056196730804942652810471819841257895035930095200467257709515928 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11036957886218056196730804942652810471819841257895035930095200467257709515928 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/2.rstmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_alert_test 47695402781749638965814605358083546205258702410973000957040102171368917181067 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/2.rstmgr_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1111892619 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.1111892619' seed=47695402781749638965814605358083546205258702410973000957040102171368917181067 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47695402781749638965814605358083546205258702410973000957040102171368917181067 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/2.rstmgr_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_csr_rw 20139678779040239460432117716897630643738861174552822526195656836071814650727 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/2.rstmgr_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=68737895 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.68737895' seed=20139678779040239460432117716897630643738861174552822526195656836071814650727 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20139678779040239460432117716897630643738861174552822526195656836071814650727 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/2.rstmgr_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_same_csr_outstanding 51224961080351495671186629571147238266044014998934109445943711359660590239693 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/2.rstmgr_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3078754253 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_same_csr_outstanding.3078754253' seed=51224961080351495671186629571147238266044014998934109445943711359660590239693 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51224961080351495671186629571147238266044014998934109445943711359660590239693 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/2.rstmgr_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_csr_mem_rw_with_rand_reset 36544206458972725222645964556075332306870995501667382990226663088561249168715 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/2.rstmgr_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=787066187 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.787066187' seed=36544206458972725222645964556075332306870995501667382990226663088561249168715 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36544206458972725222645964556075332306870995501667382990226663088561249168715 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/2.rstmgr_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_smoke 60904851952575202618030635569691357939717947675458231952390673914250972976193 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/3.rstmgr_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3467203649 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.3467203649' seed=60904851952575202618030635569691357939717947675458231952390673914250972976193 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60904851952575202618030635569691357939717947675458231952390673914250972976193 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/3.rstmgr_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_por_stretcher 8324866157106990398795795678903582816080553575497314055445341012067475931880 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/3.rstmgr_por_stretcher/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2570732264 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.2570732264' seed=8324866157106990398795795678903582816080553575497314055445341012067475931880 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8324866157106990398795795678903582816080553575497314055445341012067475931880 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/3.rstmgr_por_stretcher/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_por_stretcher_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_reset 21355727809508731582050114481830678100086701212215213277388628942960579189620 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/3.rstmgr_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3103660916 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.3103660916' seed=21355727809508731582050114481830678100086701212215213277388628942960579189620 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21355727809508731582050114481830678100086701212215213277388628942960579189620 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/3.rstmgr_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_sw_rst_reset_race 84695912659489228202411455136032988880979829151410766056553324438021122533824 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/3.rstmgr_sw_rst_reset_race/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2695342528 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.2695342528' seed=84695912659489228202411455136032988880979829151410766056553324438021122533824 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84695912659489228202411455136032988880979829151410766056553324438021122533824 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/3.rstmgr_sw_rst_reset_race/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_sw_rst_reset_race_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_sw_rst 8481835455731830650491567473042383883545335731827143973956254201303187506993 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/3.rstmgr_sw_rst/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1887356721 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.1887356721' seed=8481835455731830650491567473042383883545335731827143973956254201303187506993 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8481835455731830650491567473042383883545335731827143973956254201303187506993 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/3.rstmgr_sw_rst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_sw_rst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_sec_cm_scan_intersig_mubi 36039969865826152916497526474140398849861953617339985514077152983134412644520 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/3.rstmgr_sec_cm_scan_intersig_mubi/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4003373224 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.4003373224' seed=36039969865826152916497526474140398849861953617339985514077152983134412644520 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36039969865826152916497526474140398849861953617339985514077152983134412644520 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/3.rstmgr_sec_cm_scan_intersig_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_sec_cm_scan_intersig_mubi_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_leaf_rst_cnsty 52124693791607877334390957460808101934919260491237778385431814453662181105781 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/3.rstmgr_leaf_rst_cnsty/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3595444341 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.3595444341' seed=52124693791607877334390957460808101934919260491237778385431814453662181105781 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=52124693791607877334390957460808101934919260491237778385431814453662181105781 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/3.rstmgr_leaf_rst_cnsty/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_leaf_rst_cnsty_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_leaf_rst_shadow_attack 65835808035782512334122349037337585588686728270491815120457299115955524339320 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/3.rstmgr_leaf_rst_shadow_attack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2805073528 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.2805073528' seed=65835808035782512334122349037337585588686728270491815120457299115955524339320 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65835808035782512334122349037337585588686728270491815120457299115955524339320 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/3.rstmgr_leaf_rst_shadow_attack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_leaf_rst_shadow_attack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_sec_cm 39290999653512658145479944212847906173976880918016412906282232097354686742289 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/3.rstmgr_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3721477905 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3721477905' seed=39290999653512658145479944212847906173976880918016412906282232097354686742289 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39290999653512658145479944212847906173976880918016412906282232097354686742289 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/3.rstmgr_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_errors 25314188234240984279249804411865947978148223893254140517829300834299667177640 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/3.rstmgr_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3286130856 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.3286130856' seed=25314188234240984279249804411865947978148223893254140517829300834299667177640 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25314188234240984279249804411865947978148223893254140517829300834299667177640 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/3.rstmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_intg_err 93342585038991711210977591501751331789665362597194331467287153040783062464292 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/3.rstmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=143783716 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.143783716' seed=93342585038991711210977591501751331789665362597194331467287153040783062464292 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93342585038991711210977591501751331789665362597194331467287153040783062464292 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/3.rstmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_alert_test 72715073797722550086421517726471153054686594967958944303142187165138685684376 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/3.rstmgr_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2928306840 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.2928306840' seed=72715073797722550086421517726471153054686594967958944303142187165138685684376 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72715073797722550086421517726471153054686594967958944303142187165138685684376 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/3.rstmgr_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_csr_rw 106309749296712439611068691689336381804885830629973973454903266390171654384609 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/3.rstmgr_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1469672417 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.1469672417' seed=106309749296712439611068691689336381804885830629973973454903266390171654384609 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106309749296712439611068691689336381804885830629973973454903266390171654384609 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/3.rstmgr_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_same_csr_outstanding 44014959696300027229861631989731578610373608458062143702857419945212111207975 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/3.rstmgr_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2156379687 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_same_csr_outstanding.2156379687' seed=44014959696300027229861631989731578610373608458062143702857419945212111207975 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44014959696300027229861631989731578610373608458062143702857419945212111207975 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/3.rstmgr_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_csr_mem_rw_with_rand_reset 5543888849876493488758680819596616882861763221859559266953539654231749599860 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/3.rstmgr_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3715932788 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.3715932788' seed=5543888849876493488758680819596616882861763221859559266953539654231749599860 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5543888849876493488758680819596616882861763221859559266953539654231749599860 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/3.rstmgr_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_smoke 54057573873296072825831362055942632136842936075582956983767802342989516462302 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/4.rstmgr_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1998805214 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.1998805214' seed=54057573873296072825831362055942632136842936075582956983767802342989516462302 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54057573873296072825831362055942632136842936075582956983767802342989516462302 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/4.rstmgr_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_por_stretcher 63585453114831790168739836047255256861028490423550196357751796252825780581826 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/4.rstmgr_por_stretcher/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3884545474 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.3884545474' seed=63585453114831790168739836047255256861028490423550196357751796252825780581826 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63585453114831790168739836047255256861028490423550196357751796252825780581826 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/4.rstmgr_por_stretcher/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_por_stretcher_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_reset 113427340161570166198095264434602556812933042867378908107190907606662432607315 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/4.rstmgr_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=187354195 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.187354195' seed=113427340161570166198095264434602556812933042867378908107190907606662432607315 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113427340161570166198095264434602556812933042867378908107190907606662432607315 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/4.rstmgr_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_sw_rst_reset_race 22879412264980932783905548794534349592507011141166981269379067331973801275826 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/4.rstmgr_sw_rst_reset_race/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=815755698 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.815755698' seed=22879412264980932783905548794534349592507011141166981269379067331973801275826 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22879412264980932783905548794534349592507011141166981269379067331973801275826 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/4.rstmgr_sw_rst_reset_race/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_sw_rst_reset_race_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_sw_rst 113784402046052482616667832573725586467067029492727304219129916763591671665115 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/4.rstmgr_sw_rst/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4108177883 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.4108177883' seed=113784402046052482616667832573725586467067029492727304219129916763591671665115 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113784402046052482616667832573725586467067029492727304219129916763591671665115 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/4.rstmgr_sw_rst/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_sw_rst_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_sec_cm_scan_intersig_mubi 114508913014880167896894787517781773682150191269627292870093264242084364517395 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/4.rstmgr_sec_cm_scan_intersig_mubi/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=341147667 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.341147667' seed=114508913014880167896894787517781773682150191269627292870093264242084364517395 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114508913014880167896894787517781773682150191269627292870093264242084364517395 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/4.rstmgr_sec_cm_scan_intersig_mubi/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_sec_cm_scan_intersig_mubi_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_leaf_rst_cnsty 105930373456553162885161676806234686175496141898455235644533132999674174542221 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/4.rstmgr_leaf_rst_cnsty/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4011757965 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.4011757965' seed=105930373456553162885161676806234686175496141898455235644533132999674174542221 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105930373456553162885161676806234686175496141898455235644533132999674174542221 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/4.rstmgr_leaf_rst_cnsty/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_leaf_rst_cnsty_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_leaf_rst_shadow_attack 1715289423410549562394814458697112630998252074108490459782621441721926644410 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/4.rstmgr_leaf_rst_shadow_attack/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=576942778 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.576942778' seed=1715289423410549562394814458697112630998252074108490459782621441721926644410 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1715289423410549562394814458697112630998252074108490459782621441721926644410 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/4.rstmgr_leaf_rst_shadow_attack/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_leaf_rst_shadow_attack_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_sec_cm 18632954113484935457525838745350649943092761395065941913626532458656157159761 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/4.rstmgr_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1643925841 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.1643925841' seed=18632954113484935457525838745350649943092761395065941913626532458656157159761 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18632954113484935457525838745350649943092761395065941913626532458656157159761 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/4.rstmgr_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_errors 10379782200913411548364971642402520165233489064122903095248278071864738627286 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/4.rstmgr_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2097594070 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.2097594070' seed=10379782200913411548364971642402520165233489064122903095248278071864738627286 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10379782200913411548364971642402520165233489064122903095248278071864738627286 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/4.rstmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_intg_err 97960063982448802978759784838933695404654899770609257936874112095570236088279 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/4.rstmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1111039959 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err.1111039959' seed=97960063982448802978759784838933695404654899770609257936874112095570236088279 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97960063982448802978759784838933695404654899770609257936874112095570236088279 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/4.rstmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_alert_test 66743649388913600348269551483612372728085423756665176131525400334062857819361 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/4.rstmgr_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=336925921 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.336925921' seed=66743649388913600348269551483612372728085423756665176131525400334062857819361 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66743649388913600348269551483612372728085423756665176131525400334062857819361 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/4.rstmgr_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_csr_rw 20266033374235352198081192079755160162161236441762496504287063830199980801058 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/4.rstmgr_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1072184354 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.1072184354' seed=20266033374235352198081192079755160162161236441762496504287063830199980801058 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20266033374235352198081192079755160162161236441762496504287063830199980801058 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/4.rstmgr_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_same_csr_outstanding 47144824232464145112583602413501245727111287672528946829920092541490877429421 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/4.rstmgr_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3493590701 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_same_csr_outstanding.3493590701' seed=47144824232464145112583602413501245727111287672528946829920092541490877429421 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47144824232464145112583602413501245727111287672528946829920092541490877429421 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/4.rstmgr_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_csr_mem_rw_with_rand_reset 71898896222772266544919030226159124137940100533848121457216953767267106567905 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/4.rstmgr_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=860370657 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.860370657' seed=71898896222772266544919030226159124137940100533848121457216953767267106567905 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71898896222772266544919030226159124137940100533848121457216953767267106567905 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/4.rstmgr_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_leaf_rst_cnsty 86584908291431950557980149967990710734797614471027800927699379383946544453739 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/5.rstmgr_leaf_rst_cnsty/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=45127787 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.45127787' seed=86584908291431950557980149967990710734797614471027800927699379383946544453739 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86584908291431950557980149967990710734797614471027800927699379383946544453739 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/5.rstmgr_leaf_rst_cnsty/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_leaf_rst_cnsty_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_errors 92422917503335955681643884055338202745648094511006158990703653732347789273121 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/5.rstmgr_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2022008865 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.2022008865' seed=92422917503335955681643884055338202745648094511006158990703653732347789273121 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92422917503335955681643884055338202745648094511006158990703653732347789273121 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/5.rstmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_intg_err 75079113351863841391723301693478421574750118229006134515233559145455417183148 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/5.rstmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1942899628 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err.1942899628' seed=75079113351863841391723301693478421574750118229006134515233559145455417183148 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75079113351863841391723301693478421574750118229006134515233559145455417183148 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/5.rstmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_alert_test 99444929536317722256546888229151302342678544242095117688569035529863292758200 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/5.rstmgr_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2025826488 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.2025826488' seed=99444929536317722256546888229151302342678544242095117688569035529863292758200 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99444929536317722256546888229151302342678544242095117688569035529863292758200 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/5.rstmgr_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_leaf_rst_cnsty 21556795726492258924135866492084016521762807961414749681360690622669599631660 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/6.rstmgr_leaf_rst_cnsty/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3364972844 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.3364972844' seed=21556795726492258924135866492084016521762807961414749681360690622669599631660 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21556795726492258924135866492084016521762807961414749681360690622669599631660 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/6.rstmgr_leaf_rst_cnsty/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_leaf_rst_cnsty_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_errors 80965331220692451735210269538793141979790483598552989649886071649115191348609 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/6.rstmgr_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=271289729 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.271289729' seed=80965331220692451735210269538793141979790483598552989649886071649115191348609 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80965331220692451735210269538793141979790483598552989649886071649115191348609 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/6.rstmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_intg_err 108542062087711531796510901117591416061896780789395240327678612455974585515649 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/6.rstmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2666806913 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err.2666806913' seed=108542062087711531796510901117591416061896780789395240327678612455974585515649 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108542062087711531796510901117591416061896780789395240327678612455974585515649 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/6.rstmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_alert_test 54117287014164267313870581326044588853494170543100813082348614337780152953843 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/6.rstmgr_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1313762291 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.1313762291' seed=54117287014164267313870581326044588853494170543100813082348614337780152953843 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54117287014164267313870581326044588853494170543100813082348614337780152953843 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/6.rstmgr_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_leaf_rst_cnsty 12994546627432385679737170800510382973969387278147282044854014004903082174807 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/7.rstmgr_leaf_rst_cnsty/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1449896279 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.1449896279' seed=12994546627432385679737170800510382973969387278147282044854014004903082174807 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12994546627432385679737170800510382973969387278147282044854014004903082174807 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/7.rstmgr_leaf_rst_cnsty/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_leaf_rst_cnsty_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_errors 19234399497736952793307843482872871603120171669981564567848252273163128595053 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/7.rstmgr_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2118443629 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.2118443629' seed=19234399497736952793307843482872871603120171669981564567848252273163128595053 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19234399497736952793307843482872871603120171669981564567848252273163128595053 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/7.rstmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_intg_err 6628770682648228556519250087021252175255699036096050875622431209939747987735 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/7.rstmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3861111063 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err.3861111063' seed=6628770682648228556519250087021252175255699036096050875622431209939747987735 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6628770682648228556519250087021252175255699036096050875622431209939747987735 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/7.rstmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_alert_test 13613774769303580856510956064310012045866699079857940418043332633839442514172 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/7.rstmgr_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=592105724 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.592105724' seed=13613774769303580856510956064310012045866699079857940418043332633839442514172 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13613774769303580856510956064310012045866699079857940418043332633839442514172 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/7.rstmgr_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_leaf_rst_cnsty 61137441502418158619533539632033992796187423124438882602267500836528126373391 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/8.rstmgr_leaf_rst_cnsty/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4044303887 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.4044303887' seed=61137441502418158619533539632033992796187423124438882602267500836528126373391 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61137441502418158619533539632033992796187423124438882602267500836528126373391 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/8.rstmgr_leaf_rst_cnsty/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_leaf_rst_cnsty_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_errors 23118126650899454620710068033793216207165525929530633696583774707721616357624 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/8.rstmgr_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2557343992 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.2557343992' seed=23118126650899454620710068033793216207165525929530633696583774707721616357624 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23118126650899454620710068033793216207165525929530633696583774707721616357624 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/8.rstmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_intg_err 12324532338566165698852943244710222050789527763140999438871058704122505310818 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/8.rstmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4072911458 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.4072911458' seed=12324532338566165698852943244710222050789527763140999438871058704122505310818 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12324532338566165698852943244710222050789527763140999438871058704122505310818 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/8.rstmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_alert_test 11366319478372286503031366116592484341705051297593594592466212820355322112184 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/8.rstmgr_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=268069048 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.268069048' seed=11366319478372286503031366116592484341705051297593594592466212820355322112184 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11366319478372286503031366116592484341705051297593594592466212820355322112184 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/8.rstmgr_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_leaf_rst_cnsty 35298274802635489936232481085110073608511927994179135879242536480080542092638 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/9.rstmgr_leaf_rst_cnsty/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3098594654 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.3098594654' seed=35298274802635489936232481085110073608511927994179135879242536480080542092638 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35298274802635489936232481085110073608511927994179135879242536480080542092638 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/9.rstmgr_leaf_rst_cnsty/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_leaf_rst_cnsty_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_errors 88727772523548295699726202547901325924513491295185431406279306571699602605256 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/9.rstmgr_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=465323208 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.465323208' seed=88727772523548295699726202547901325924513491295185431406279306571699602605256 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88727772523548295699726202547901325924513491295185431406279306571699602605256 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/9.rstmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_intg_err 31957925126478438759068693625721542170853600874379612141457234203923558948516 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/9.rstmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2422202020 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err.2422202020' seed=31957925126478438759068693625721542170853600874379612141457234203923558948516 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31957925126478438759068693625721542170853600874379612141457234203923558948516 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/9.rstmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_alert_test 22871917335272960637443275895479986198190989053064641438728267918379121055754 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/9.rstmgr_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4084144138 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.4084144138' seed=22871917335272960637443275895479986198190989053064641438728267918379121055754 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22871917335272960637443275895479986198190989053064641438728267918379121055754 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/9.rstmgr_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_leaf_rst_cnsty 68790506400080159486160809894216266752668659846674429940179633742680083860454 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/10.rstmgr_leaf_rst_cnsty/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3100838886 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.3100838886' seed=68790506400080159486160809894216266752668659846674429940179633742680083860454 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68790506400080159486160809894216266752668659846674429940179633742680083860454 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/10.rstmgr_leaf_rst_cnsty/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_leaf_rst_cnsty_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_errors 82375202434824078770759871756985674406495886579491784204737489646466556745071 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/10.rstmgr_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=252171631 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.252171631' seed=82375202434824078770759871756985674406495886579491784204737489646466556745071 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82375202434824078770759871756985674406495886579491784204737489646466556745071 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/10.rstmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_intg_err 109060324556410672153625171632830161053246149290922288286096236870520661775419 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/10.rstmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1980666939 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_err.1980666939' seed=109060324556410672153625171632830161053246149290922288286096236870520661775419 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109060324556410672153625171632830161053246149290922288286096236870520661775419 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/10.rstmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_leaf_rst_cnsty 65831366918712376752486496422511735964865667353843084378401722768770016633753 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/11.rstmgr_leaf_rst_cnsty/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3883557785 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.3883557785' seed=65831366918712376752486496422511735964865667353843084378401722768770016633753 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65831366918712376752486496422511735964865667353843084378401722768770016633753 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/11.rstmgr_leaf_rst_cnsty/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_leaf_rst_cnsty_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_errors 103971830705090923074300071208926589271842134337237381435681531160666709560218 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/11.rstmgr_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=566627226 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.566627226' seed=103971830705090923074300071208926589271842134337237381435681531160666709560218 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103971830705090923074300071208926589271842134337237381435681531160666709560218 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/11.rstmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_intg_err 103081322215532840221111127556766118563464396985564391873479078426296877654023 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/11.rstmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3643613191 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_err.3643613191' seed=103081322215532840221111127556766118563464396985564391873479078426296877654023 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103081322215532840221111127556766118563464396985564391873479078426296877654023 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/11.rstmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_leaf_rst_cnsty 49682446655574517176657706456176027349724716332043038656360340982707213531723 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/12.rstmgr_leaf_rst_cnsty/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4003691083 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.4003691083' seed=49682446655574517176657706456176027349724716332043038656360340982707213531723 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49682446655574517176657706456176027349724716332043038656360340982707213531723 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/12.rstmgr_leaf_rst_cnsty/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_leaf_rst_cnsty_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_errors 30924756204414158812072819387800729368414189809156695211066219008501550425455 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/12.rstmgr_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3193709935 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.3193709935' seed=30924756204414158812072819387800729368414189809156695211066219008501550425455 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30924756204414158812072819387800729368414189809156695211066219008501550425455 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/12.rstmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_intg_err 113393072995336315618558546274480558991889246691573199462386238583606650861178 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/12.rstmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=204469882 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_err.204469882' seed=113393072995336315618558546274480558991889246691573199462386238583606650861178 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113393072995336315618558546274480558991889246691573199462386238583606650861178 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/12.rstmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_leaf_rst_cnsty 6332361188607088502576562225655085431494752843757796093647502084183928005025 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/13.rstmgr_leaf_rst_cnsty/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=138076577 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.138076577' seed=6332361188607088502576562225655085431494752843757796093647502084183928005025 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6332361188607088502576562225655085431494752843757796093647502084183928005025 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/13.rstmgr_leaf_rst_cnsty/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_leaf_rst_cnsty_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_errors 64025542202308674221431466088168942704198498625394583160501725081171512376780 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/13.rstmgr_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2399518156 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.2399518156' seed=64025542202308674221431466088168942704198498625394583160501725081171512376780 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64025542202308674221431466088168942704198498625394583160501725081171512376780 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/13.rstmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_intg_err 99759730251294719411159250022239814332157767749215149309138114602245174027311 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/13.rstmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1108829231 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_err.1108829231' seed=99759730251294719411159250022239814332157767749215149309138114602245174027311 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99759730251294719411159250022239814332157767749215149309138114602245174027311 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/13.rstmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_leaf_rst_cnsty 24835886644687842319408877819077448104529160397469147218166614286760642628437 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/14.rstmgr_leaf_rst_cnsty/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3094104917 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.3094104917' seed=24835886644687842319408877819077448104529160397469147218166614286760642628437 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24835886644687842319408877819077448104529160397469147218166614286760642628437 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/14.rstmgr_leaf_rst_cnsty/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_leaf_rst_cnsty_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_errors 78808106923004975936352163652857528431379747063482973645446898629027895987792 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/14.rstmgr_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=4277161552 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.4277161552' seed=78808106923004975936352163652857528431379747063482973645446898629027895987792 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78808106923004975936352163652857528431379747063482973645446898629027895987792 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/14.rstmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_intg_err 85184751843955246516356321926107459270459078159392670794878229099157656881443 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/14.rstmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1236453667 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_err.1236453667' seed=85184751843955246516356321926107459270459078159392670794878229099157656881443 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85184751843955246516356321926107459270459078159392670794878229099157656881443 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/14.rstmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_leaf_rst_cnsty 23051108273624489486775328249754202970368965170882540586327284809324974413285 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/15.rstmgr_leaf_rst_cnsty/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1254987237 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.1254987237' seed=23051108273624489486775328249754202970368965170882540586327284809324974413285 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23051108273624489486775328249754202970368965170882540586327284809324974413285 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/15.rstmgr_leaf_rst_cnsty/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_leaf_rst_cnsty_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_errors 70339911817081503874129131900216037819139938000093367589973679302415468291643 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/15.rstmgr_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=625043003 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.625043003' seed=70339911817081503874129131900216037819139938000093367589973679302415468291643 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70339911817081503874129131900216037819139938000093367589973679302415468291643 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/15.rstmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_intg_err 90168786898778147275590918116411366332632677032922374215111858468401361552193 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/15.rstmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3301540673 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_err.3301540673' seed=90168786898778147275590918116411366332632677032922374215111858468401361552193 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90168786898778147275590918116411366332632677032922374215111858468401361552193 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/15.rstmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_leaf_rst_cnsty 99105241550089050723851239736361886404171148609159739149197536377486121597324 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/16.rstmgr_leaf_rst_cnsty/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3554638220 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.3554638220' seed=99105241550089050723851239736361886404171148609159739149197536377486121597324 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99105241550089050723851239736361886404171148609159739149197536377486121597324 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/16.rstmgr_leaf_rst_cnsty/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_leaf_rst_cnsty_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_errors 14913438055870839161001354121231909623266234694414213272122184872334712817123 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/16.rstmgr_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2751645155 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.2751645155' seed=14913438055870839161001354121231909623266234694414213272122184872334712817123 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=14913438055870839161001354121231909623266234694414213272122184872334712817123 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/16.rstmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_intg_err 57754088792662830258549101220008794444782866002085578008790421183558846739051 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/16.rstmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2816701035 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err.2816701035' seed=57754088792662830258549101220008794444782866002085578008790421183558846739051 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57754088792662830258549101220008794444782866002085578008790421183558846739051 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/16.rstmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_leaf_rst_cnsty 68438415270453464013077333107282293570653410706670259317810676818980770951067 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/17.rstmgr_leaf_rst_cnsty/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3483381659 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.3483381659' seed=68438415270453464013077333107282293570653410706670259317810676818980770951067 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68438415270453464013077333107282293570653410706670259317810676818980770951067 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/17.rstmgr_leaf_rst_cnsty/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_leaf_rst_cnsty_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_errors 61033551502264176329611859071071216231015286448959337678388921082592181234344 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/17.rstmgr_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=605170344 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.605170344' seed=61033551502264176329611859071071216231015286448959337678388921082592181234344 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61033551502264176329611859071071216231015286448959337678388921082592181234344 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/17.rstmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_intg_err 78642990697854302845394066711392925279291859510733171810081375638513133040330 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/17.rstmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2065969866 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_err.2065969866' seed=78642990697854302845394066711392925279291859510733171810081375638513133040330 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78642990697854302845394066711392925279291859510733171810081375638513133040330 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/17.rstmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_leaf_rst_cnsty 110029987348035296691170842569437703129553863215074825467051957397733048824971 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/18.rstmgr_leaf_rst_cnsty/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2330965131 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.2330965131' seed=110029987348035296691170842569437703129553863215074825467051957397733048824971 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110029987348035296691170842569437703129553863215074825467051957397733048824971 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/18.rstmgr_leaf_rst_cnsty/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_leaf_rst_cnsty_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_errors 68680579708926233147723118710220649921654201814061549358633789317098427794380 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/18.rstmgr_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1509049292 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.1509049292' seed=68680579708926233147723118710220649921654201814061549358633789317098427794380 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68680579708926233147723118710220649921654201814061549358633789317098427794380 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/18.rstmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_intg_err 105764612018131065208405591242450717485604464512819598458288840337636163223208 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/18.rstmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2678488744 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_err.2678488744' seed=105764612018131065208405591242450717485604464512819598458288840337636163223208 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105764612018131065208405591242450717485604464512819598458288840337636163223208 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/18.rstmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_leaf_rst_cnsty 7477897276108387474795185658779467172336881201786093787256497719724704433125 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/19.rstmgr_leaf_rst_cnsty/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3012985829 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.3012985829' seed=7477897276108387474795185658779467172336881201786093787256497719724704433125 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7477897276108387474795185658779467172336881201786093787256497719724704433125 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/19.rstmgr_leaf_rst_cnsty/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_leaf_rst_cnsty_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_errors 70753757293858400434675294097432081390534720163929752319096088470066634845980 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/19.rstmgr_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1441165084 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.1441165084' seed=70753757293858400434675294097432081390534720163929752319096088470066634845980 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70753757293858400434675294097432081390534720163929752319096088470066634845980 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/19.rstmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_intg_err 54074796558999398790475417258181099810453207759896371025916929417685883703704 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/19.rstmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3380629912 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_err.3380629912' seed=54074796558999398790475417258181099810453207759896371025916929417685883703704 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54074796558999398790475417258181099810453207759896371025916929417685883703704 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/19.rstmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_leaf_rst_cnsty 2981326298851907480153972676169452763396918574401704251699482045758301970820 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/20.rstmgr_leaf_rst_cnsty/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=704553348 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.704553348' seed=2981326298851907480153972676169452763396918574401704251699482045758301970820 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2981326298851907480153972676169452763396918574401704251699482045758301970820 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/20.rstmgr_leaf_rst_cnsty/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_leaf_rst_cnsty_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_errors 8937478249118100826480538969451050743765604206516364718071641481221957253980 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/20.rstmgr_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2857663324 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rstmgr_tl_errors.2857663324' seed=8937478249118100826480538969451050743765604206516364718071641481221957253980 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8937478249118100826480538969451050743765604206516364718071641481221957253980 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/20.rstmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_intg_err 71614770002086867592220342737376831913768172539873472458345132935256993133674 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/20.rstmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=322401386 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.rstmgr_tl_intg_err.322401386' seed=71614770002086867592220342737376831913768172539873472458345132935256993133674 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71614770002086867592220342737376831913768172539873472458345132935256993133674 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/20.rstmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_leaf_rst_cnsty 65575387043683058525428065008035680144908598272190971565504694811001846489209 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/21.rstmgr_leaf_rst_cnsty/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2249711737 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.2249711737' seed=65575387043683058525428065008035680144908598272190971565504694811001846489209 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65575387043683058525428065008035680144908598272190971565504694811001846489209 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/21.rstmgr_leaf_rst_cnsty/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_leaf_rst_cnsty_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_errors 90115047598478662103638343512274618793647417420865736990220768050768017572892 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/21.rstmgr_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1037517852 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rstmgr_tl_errors.1037517852' seed=90115047598478662103638343512274618793647417420865736990220768050768017572892 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90115047598478662103638343512274618793647417420865736990220768050768017572892 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/21.rstmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_intg_err 96530858487386661608454659574645399096726767218819977375317328440332241271362 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/21.rstmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2170223170 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.rstmgr_tl_intg_err.2170223170' seed=96530858487386661608454659574645399096726767218819977375317328440332241271362 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96530858487386661608454659574645399096726767218819977375317328440332241271362 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/21.rstmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_leaf_rst_cnsty 66865142514085551152775167719770774195490985128938448006129144575996681170451 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/22.rstmgr_leaf_rst_cnsty/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3193875987 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.3193875987' seed=66865142514085551152775167719770774195490985128938448006129144575996681170451 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66865142514085551152775167719770774195490985128938448006129144575996681170451 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/22.rstmgr_leaf_rst_cnsty/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_leaf_rst_cnsty_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_errors 36348800560390281103248799232921512186518331279421781815706968018086901634875 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/22.rstmgr_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=336910139 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rstmgr_tl_errors.336910139' seed=36348800560390281103248799232921512186518331279421781815706968018086901634875 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36348800560390281103248799232921512186518331279421781815706968018086901634875 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/22.rstmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_intg_err 47822392993408893752184581724213692326514563431971246028963609203314960869361 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/22.rstmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1692903409 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.rstmgr_tl_intg_err.1692903409' seed=47822392993408893752184581724213692326514563431971246028963609203314960869361 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47822392993408893752184581724213692326514563431971246028963609203314960869361 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/22.rstmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_leaf_rst_cnsty 77556151326801292692779435209891104588426675929369861636913068039515054191734 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/23.rstmgr_leaf_rst_cnsty/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1268954230 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.1268954230' seed=77556151326801292692779435209891104588426675929369861636913068039515054191734 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77556151326801292692779435209891104588426675929369861636913068039515054191734 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/23.rstmgr_leaf_rst_cnsty/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_leaf_rst_cnsty_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_errors 20325172218489157616019756440298583107309284641123465572659444266979566243938 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/23.rstmgr_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=1265061986 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rstmgr_tl_errors.1265061986' seed=20325172218489157616019756440298583107309284641123465572659444266979566243938 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20325172218489157616019756440298583107309284641123465572659444266979566243938 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/23.rstmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_intg_err 75620683564598900831192269191347243840280480835194741265834550309105817769100 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/23.rstmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2908116108 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.rstmgr_tl_intg_err.2908116108' seed=75620683564598900831192269191347243840280480835194741265834550309105817769100 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75620683564598900831192269191347243840280480835194741265834550309105817769100 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/23.rstmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_leaf_rst_cnsty 91621661983441313237225105221232334933251587381809959088007856497812103952022 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/default/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/24.rstmgr_leaf_rst_cnsty/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=2199320214 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.2199320214' seed=91621661983441313237225105221232334933251587381809959088007856497812103952022 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91621661983441313237225105221232334933251587381809959088007856497812103952022 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/24.rstmgr_leaf_rst_cnsty/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_leaf_rst_cnsty_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_errors 21236524779916555026488955288887874327929980419232241445225428374405216950541 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/24.rstmgr_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=701978893 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rstmgr_tl_errors.701978893' seed=21236524779916555026488955288887874327929980419232241445225428374405216950541 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21236524779916555026488955288887874327929980419232241445225428374405216950541 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/24.rstmgr_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rstmgr_tl_intg_err 28553994760914286545483401476562468682342033434178925859711487932033200168517 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=/nightly/current_run/scratch/master/rstmgr-sim-vcs/cover_reg_top/simv run_dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/24.rstmgr_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /nightly/current_run/opentitan/hw/dv/tools/sim.tcl +ntb_random_seed=3490324037 -xlrm hier_inst_seed -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.rstmgr_tl_intg_err.3490324037' seed=28553994760914286545483401476562468682342033434178925859711487932033200168517 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28553994760914286545483401476562468682342033434178925859711487932033200168517 --run-dir=/nightly/current_run/scratch/master/rstmgr-sim-vcs/24.rstmgr_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rstmgr_base_test uvm_test_seq=rstmgr_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
Job returned a non-zero exit code: * 1 test run
rstmgr None None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk cov_merge cov_merge_cmd=urg cov_merge_opts='-lca -full64 -noreport +urg+lic+wait -merge_across_libs -show tests -flex_merge union -dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/default.vdb -dir /nightly/current_run/scratch/master/rstmgr-sim-vcs/coverage/cover_reg_top.vdb -dbname /nightly/current_run/scratch/master/rstmgr-sim-vcs/cov_merge/merged.vdb'
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:109: cov_merge] Error 126
Job cancelled because one of its dependencies failed or was killed. 1 test run
rstmgr None None