Simulation Results: rv_timer

 
28/08/2026 21:54:34 DVSim: v1.49.0 sha: a099412 json Branch: master Tool: xcelium [unknown]
Validation stages
V1
0.00%
V2
15.75%
V2S
0.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
random 0 20 0.00
rv_timer_random 1.659s 0.000us 0 20 0.00
csr_hw_reset 0 1 0.00
rv_timer_csr_hw_reset 0.872s 0.000us 0 1 0.00
csr_rw 0 5 0.00
rv_timer_csr_rw 0.879s 0.000us 0 5 0.00
csr_bit_bash 0 1 0.00
rv_timer_csr_bit_bash 0.847s 0.000us 0 1 0.00
csr_aliasing 0 1 0.00
rv_timer_csr_aliasing 0.842s 0.000us 0 1 0.00
csr_mem_rw_with_rand_reset 0 5 0.00
rv_timer_csr_mem_rw_with_rand_reset 0.876s 0.000us 0 5 0.00
regwen_csr_and_corresponding_lockable_csr 0 6 0.00
rv_timer_csr_rw 0.879s 0.000us 0 5 0.00
rv_timer_csr_aliasing 0.842s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 20 0.00
rv_timer_random_reset 1.664s 0.000us 0 20 0.00
disabled 0 20 0.00
rv_timer_disabled 1.401s 0.000us 0 20 0.00
cfg_update_on_fly 0 10 0.00
rv_timer_cfg_update_on_fly 1.531s 0.000us 0 10 0.00
no_interrupt_test 0 10 0.00
rv_timer_cfg_update_on_fly 1.531s 0.000us 0 10 0.00
stress 20 20 100.00
rv_timer_stress_all 12.000s 5958.026us 20 20 100.00
alert_test 0 10 0.00
rv_timer_alert_test 1.852s 0.000us 0 10 0.00
intr_test 0 10 0.00
rv_timer_intr_test 1.314s 0.000us 0 10 0.00
tl_d_oob_addr_access 0 25 0.00
rv_timer_tl_errors 1.850s 0.000us 0 25 0.00
tl_d_illegal_access 0 25 0.00
rv_timer_tl_errors 1.850s 0.000us 0 25 0.00
tl_d_outstanding_access 0 12 0.00
rv_timer_csr_hw_reset 0.872s 0.000us 0 1 0.00
rv_timer_csr_rw 0.879s 0.000us 0 5 0.00
rv_timer_csr_aliasing 0.842s 0.000us 0 1 0.00
rv_timer_same_csr_outstanding 0.846s 0.000us 0 5 0.00
tl_d_partial_access 0 12 0.00
rv_timer_csr_hw_reset 0.872s 0.000us 0 1 0.00
rv_timer_csr_rw 0.879s 0.000us 0 5 0.00
rv_timer_csr_aliasing 0.842s 0.000us 0 1 0.00
rv_timer_same_csr_outstanding 0.846s 0.000us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 30 0.00
rv_timer_sec_cm 0.921s 0.000us 0 5 0.00
rv_timer_tl_intg_err 1.325s 0.000us 0 25 0.00
sec_cm_bus_integrity 0 25 0.00
rv_timer_tl_intg_err 1.325s 0.000us 0 25 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 10 0.00
rv_timer_min 1.561s 0.000us 0 10 0.00
max_value 0 10 0.00
rv_timer_max 1.324s 0.000us 0 10 0.00
stress_all_with_rand_reset 0 20 0.00
rv_timer_stress_all_with_rand_reset 1.521s 0.000us 0 20 0.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 203 test runs
rv_timer_random 46599236170080877685161554179376443620123286246769246968828821210848406032304 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/0.rv_timer_random/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3143651248 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/0.rv_timer_random.3143651248 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 0.rv_timer_random.3143651248 -covoverwrite' seed=46599236170080877685161554179376443620123286246769246968828821210848406032304 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46599236170080877685161554179376443620123286246769246968828821210848406032304 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/0.rv_timer_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_min 88258469449397608729931581395576674769238738098327764232824162296793264148165 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/0.rv_timer_min/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3046231749 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_min_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/0.rv_timer_min.3046231749 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 0.rv_timer_min.3046231749 -covoverwrite' seed=88258469449397608729931581395576674769238738098327764232824162296793264148165 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88258469449397608729931581395576674769238738098327764232824162296793264148165 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/0.rv_timer_min/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_min_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_max 91824343200674140107432704045972653510835008973217035914249783118814570485575 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/0.rv_timer_max/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=971642695 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_max_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/0.rv_timer_max.971642695 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 0.rv_timer_max.971642695 -covoverwrite' seed=91824343200674140107432704045972653510835008973217035914249783118814570485575 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91824343200674140107432704045972653510835008973217035914249783118814570485575 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/0.rv_timer_max/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_max_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_disabled 47820138572892844561271313459338605114735554332630636874013268643560101208900 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/0.rv_timer_disabled/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=2103141188 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/0.rv_timer_disabled.2103141188 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 0.rv_timer_disabled.2103141188 -covoverwrite' seed=47820138572892844561271313459338605114735554332630636874013268643560101208900 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47820138572892844561271313459338605114735554332630636874013268643560101208900 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/0.rv_timer_disabled/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_disabled_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_cfg_update_on_fly 53247989225971137667350953790682233483605234240450207763111002224434242842491 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/0.rv_timer_cfg_update_on_fly/latest run_opts='+zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=2400907131 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/0.rv_timer_cfg_update_on_fly.2400907131 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 0.rv_timer_cfg_update_on_fly.2400907131 -covoverwrite' seed=53247989225971137667350953790682233483605234240450207763111002224434242842491 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53247989225971137667350953790682233483605234240450207763111002224434242842491 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/0.rv_timer_cfg_update_on_fly/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_cfg_update_on_fly_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random_reset 44043017227790290175936240230701418848656069651818545400307657811216761647418 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/0.rv_timer_random_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=1749315898 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/0.rv_timer_random_reset.1749315898 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 0.rv_timer_random_reset.1749315898 -covoverwrite' seed=44043017227790290175936240230701418848656069651818545400307657811216761647418 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44043017227790290175936240230701418848656069651818545400307657811216761647418 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/0.rv_timer_random_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_stress_all_with_rand_reset 58044414522094715396822929196668531480991663616353163525131277533082932263063 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/0.rv_timer_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=4142184599 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/0.rv_timer_stress_all_with_rand_reset.4142184599 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 0.rv_timer_stress_all_with_rand_reset.4142184599 -covoverwrite' seed=58044414522094715396822929196668531480991663616353163525131277533082932263063 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58044414522094715396822929196668531480991663616353163525131277533082932263063 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/0.rv_timer_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_sec_cm 37193689330457590781155188195168853154215299316143873530117707568847240438427 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/0.rv_timer_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=718938779 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/0.rv_timer_sec_cm.718938779 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 0.rv_timer_sec_cm.718938779 -covoverwrite' seed=37193689330457590781155188195168853154215299316143873530117707568847240438427 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37193689330457590781155188195168853154215299316143873530117707568847240438427 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/0.rv_timer_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_errors 30949279443306926645078681934278206295594752862257390456203806081132687555288 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/0.rv_timer_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3980950232 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/0.rv_timer_tl_errors.3980950232 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rv_timer_tl_errors.3980950232 -covoverwrite' seed=30949279443306926645078681934278206295594752862257390456203806081132687555288 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30949279443306926645078681934278206295594752862257390456203806081132687555288 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/0.rv_timer_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_intg_err 70681658942719842229847693059656468917585819263410480858022575056182612837462 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/0.rv_timer_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3646932054 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/0.rv_timer_tl_intg_err.3646932054 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rv_timer_tl_intg_err.3646932054 -covoverwrite' seed=70681658942719842229847693059656468917585819263410480858022575056182612837462 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70681658942719842229847693059656468917585819263410480858022575056182612837462 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/0.rv_timer_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_intr_test 103554457245442882231404438657035311282548245125045882168741918426577019575192 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/0.rv_timer_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1794874264 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/0.rv_timer_intr_test.1794874264 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rv_timer_intr_test.1794874264 -covoverwrite' seed=103554457245442882231404438657035311282548245125045882168741918426577019575192 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103554457245442882231404438657035311282548245125045882168741918426577019575192 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/0.rv_timer_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_alert_test 79489507383744836192497489337378254467597819360212076727562209668170081893969 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/0.rv_timer_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=2623012433 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/0.rv_timer_alert_test.2623012433 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 0.rv_timer_alert_test.2623012433 -covoverwrite' seed=79489507383744836192497489337378254467597819360212076727562209668170081893969 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79489507383744836192497489337378254467597819360212076727562209668170081893969 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/0.rv_timer_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_csr_hw_reset 48928239440780969147371453693142702527160451755521971063160197365437826507200 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/0.rv_timer_csr_hw_reset/latest run_opts='+csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3883311552 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/0.rv_timer_csr_hw_reset.3883311552 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rv_timer_csr_hw_reset.3883311552 -covoverwrite' seed=48928239440780969147371453693142702527160451755521971063160197365437826507200 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48928239440780969147371453693142702527160451755521971063160197365437826507200 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/0.rv_timer_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_csr_rw 2453823863752885443485547742742364781499991856559957393165228488193946843439 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/0.rv_timer_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1604745519 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/0.rv_timer_csr_rw.1604745519 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rv_timer_csr_rw.1604745519 -covoverwrite' seed=2453823863752885443485547742742364781499991856559957393165228488193946843439 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2453823863752885443485547742742364781499991856559957393165228488193946843439 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/0.rv_timer_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_csr_bit_bash 70028836122730007444979527035066390544981299644023020102554681316995146989037 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/0.rv_timer_csr_bit_bash/latest run_opts='+csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3780394477 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/0.rv_timer_csr_bit_bash.3780394477 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rv_timer_csr_bit_bash.3780394477 -covoverwrite' seed=70028836122730007444979527035066390544981299644023020102554681316995146989037 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70028836122730007444979527035066390544981299644023020102554681316995146989037 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/0.rv_timer_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_csr_aliasing 14693115411850297636091625818224228358770368501207003577429015300855416273493 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/0.rv_timer_csr_aliasing/latest run_opts='+csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=135051861 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/0.rv_timer_csr_aliasing.135051861 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rv_timer_csr_aliasing.135051861 -covoverwrite' seed=14693115411850297636091625818224228358770368501207003577429015300855416273493 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=14693115411850297636091625818224228358770368501207003577429015300855416273493 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/0.rv_timer_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_same_csr_outstanding 40425181348466640513033998404410967082432053639962553157653379881694376265755 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/0.rv_timer_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1160546331 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/0.rv_timer_same_csr_outstanding.1160546331 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rv_timer_same_csr_outstanding.1160546331 -covoverwrite' seed=40425181348466640513033998404410967082432053639962553157653379881694376265755 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40425181348466640513033998404410967082432053639962553157653379881694376265755 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/0.rv_timer_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_csr_mem_rw_with_rand_reset 27143548608226241133326736077632219405685053962326081138916365303979349358710 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/0.rv_timer_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2033694838 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/0.rv_timer_csr_mem_rw_with_rand_reset.2033694838 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.rv_timer_csr_mem_rw_with_rand_reset.2033694838 -covoverwrite' seed=27143548608226241133326736077632219405685053962326081138916365303979349358710 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27143548608226241133326736077632219405685053962326081138916365303979349358710 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/0.rv_timer_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random 5201870638471587570582571695249279695214066679303180532340127740794297667155 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/1.rv_timer_random/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3703590483 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/1.rv_timer_random.3703590483 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 1.rv_timer_random.3703590483 -covoverwrite' seed=5201870638471587570582571695249279695214066679303180532340127740794297667155 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5201870638471587570582571695249279695214066679303180532340127740794297667155 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/1.rv_timer_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_min 101569609527828638199397897515102618149874555770517866672378498092316197894028 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/1.rv_timer_min/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3422271372 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_min_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/1.rv_timer_min.3422271372 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 1.rv_timer_min.3422271372 -covoverwrite' seed=101569609527828638199397897515102618149874555770517866672378498092316197894028 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101569609527828638199397897515102618149874555770517866672378498092316197894028 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/1.rv_timer_min/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_min_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_max 38363870209866181437083366850480605054590393489290585770327400450860635343937 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/1.rv_timer_max/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=153570369 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_max_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/1.rv_timer_max.153570369 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 1.rv_timer_max.153570369 -covoverwrite' seed=38363870209866181437083366850480605054590393489290585770327400450860635343937 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38363870209866181437083366850480605054590393489290585770327400450860635343937 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/1.rv_timer_max/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_max_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_disabled 13654826605447416631156390999145383872560897829048832830054317555842552408692 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/1.rv_timer_disabled/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=1367845492 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/1.rv_timer_disabled.1367845492 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 1.rv_timer_disabled.1367845492 -covoverwrite' seed=13654826605447416631156390999145383872560897829048832830054317555842552408692 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13654826605447416631156390999145383872560897829048832830054317555842552408692 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/1.rv_timer_disabled/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_disabled_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_cfg_update_on_fly 33247466532041739246430757235130509976737200108258448831073008508040969382219 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/1.rv_timer_cfg_update_on_fly/latest run_opts='+zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=2627397963 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/1.rv_timer_cfg_update_on_fly.2627397963 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 1.rv_timer_cfg_update_on_fly.2627397963 -covoverwrite' seed=33247466532041739246430757235130509976737200108258448831073008508040969382219 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33247466532041739246430757235130509976737200108258448831073008508040969382219 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/1.rv_timer_cfg_update_on_fly/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_cfg_update_on_fly_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random_reset 47416077243923145270208122753319532483370409574954561657570536419270181127700 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/1.rv_timer_random_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3759801876 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/1.rv_timer_random_reset.3759801876 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 1.rv_timer_random_reset.3759801876 -covoverwrite' seed=47416077243923145270208122753319532483370409574954561657570536419270181127700 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47416077243923145270208122753319532483370409574954561657570536419270181127700 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/1.rv_timer_random_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_stress_all_with_rand_reset 10330393584154980423431233909901011571406646623258051092325457098420610524698 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/1.rv_timer_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=2723538458 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/1.rv_timer_stress_all_with_rand_reset.2723538458 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 1.rv_timer_stress_all_with_rand_reset.2723538458 -covoverwrite' seed=10330393584154980423431233909901011571406646623258051092325457098420610524698 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10330393584154980423431233909901011571406646623258051092325457098420610524698 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/1.rv_timer_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_sec_cm 36294699937219146096315948535319512388782456316029075949949521985695884970273 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/1.rv_timer_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3437431073 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/1.rv_timer_sec_cm.3437431073 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 1.rv_timer_sec_cm.3437431073 -covoverwrite' seed=36294699937219146096315948535319512388782456316029075949949521985695884970273 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36294699937219146096315948535319512388782456316029075949949521985695884970273 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/1.rv_timer_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_errors 61479854645718304881712898563287902561384004101388868682015773520289851379635 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/1.rv_timer_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2688683955 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/1.rv_timer_tl_errors.2688683955 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.rv_timer_tl_errors.2688683955 -covoverwrite' seed=61479854645718304881712898563287902561384004101388868682015773520289851379635 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61479854645718304881712898563287902561384004101388868682015773520289851379635 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/1.rv_timer_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_intg_err 91346311016134857593586999502311371386615390755970211013872606927587917971396 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/1.rv_timer_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4026286020 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/1.rv_timer_tl_intg_err.4026286020 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.rv_timer_tl_intg_err.4026286020 -covoverwrite' seed=91346311016134857593586999502311371386615390755970211013872606927587917971396 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91346311016134857593586999502311371386615390755970211013872606927587917971396 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/1.rv_timer_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_intr_test 52329619991065715223602448332101773537856719143203605485613081710606395167729 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/1.rv_timer_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3777287153 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/1.rv_timer_intr_test.3777287153 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.rv_timer_intr_test.3777287153 -covoverwrite' seed=52329619991065715223602448332101773537856719143203605485613081710606395167729 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=52329619991065715223602448332101773537856719143203605485613081710606395167729 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/1.rv_timer_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_alert_test 113720997004656989032374396025669457645464197017679863517076033092430531008406 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/1.rv_timer_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=2287867798 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/1.rv_timer_alert_test.2287867798 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 1.rv_timer_alert_test.2287867798 -covoverwrite' seed=113720997004656989032374396025669457645464197017679863517076033092430531008406 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113720997004656989032374396025669457645464197017679863517076033092430531008406 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/1.rv_timer_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_csr_rw 27954823403265380103910267437624191310531329786450429201369410035728838478735 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/1.rv_timer_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3664169871 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/1.rv_timer_csr_rw.3664169871 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.rv_timer_csr_rw.3664169871 -covoverwrite' seed=27954823403265380103910267437624191310531329786450429201369410035728838478735 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27954823403265380103910267437624191310531329786450429201369410035728838478735 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/1.rv_timer_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_same_csr_outstanding 82936013774642815504236609860593515924246300861158871448601952503985054070694 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/1.rv_timer_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3037640614 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/1.rv_timer_same_csr_outstanding.3037640614 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.rv_timer_same_csr_outstanding.3037640614 -covoverwrite' seed=82936013774642815504236609860593515924246300861158871448601952503985054070694 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82936013774642815504236609860593515924246300861158871448601952503985054070694 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/1.rv_timer_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_csr_mem_rw_with_rand_reset 35600163359625776503452322870882777603126332941279186851891002569960865244395 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/1.rv_timer_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1566680299 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/1.rv_timer_csr_mem_rw_with_rand_reset.1566680299 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.rv_timer_csr_mem_rw_with_rand_reset.1566680299 -covoverwrite' seed=35600163359625776503452322870882777603126332941279186851891002569960865244395 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35600163359625776503452322870882777603126332941279186851891002569960865244395 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/1.rv_timer_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random 60121073759639055014903595184311058427769551709455106788279124945793219254262 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/2.rv_timer_random/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=1769953270 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/2.rv_timer_random.1769953270 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 2.rv_timer_random.1769953270 -covoverwrite' seed=60121073759639055014903595184311058427769551709455106788279124945793219254262 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60121073759639055014903595184311058427769551709455106788279124945793219254262 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/2.rv_timer_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_min 56649480348045723117233268816575365802849120656283888502355751799772535169395 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/2.rv_timer_min/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=2375655795 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_min_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/2.rv_timer_min.2375655795 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 2.rv_timer_min.2375655795 -covoverwrite' seed=56649480348045723117233268816575365802849120656283888502355751799772535169395 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56649480348045723117233268816575365802849120656283888502355751799772535169395 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/2.rv_timer_min/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_min_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_max 112921101331617327337935163036352239497080933590037266998038656163395393273065 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/2.rv_timer_max/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3214916841 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_max_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/2.rv_timer_max.3214916841 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 2.rv_timer_max.3214916841 -covoverwrite' seed=112921101331617327337935163036352239497080933590037266998038656163395393273065 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112921101331617327337935163036352239497080933590037266998038656163395393273065 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/2.rv_timer_max/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_max_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_disabled 113315752303668283382061822997362772096611120021973909193410420651154621271842 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/2.rv_timer_disabled/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3075936034 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/2.rv_timer_disabled.3075936034 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 2.rv_timer_disabled.3075936034 -covoverwrite' seed=113315752303668283382061822997362772096611120021973909193410420651154621271842 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113315752303668283382061822997362772096611120021973909193410420651154621271842 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/2.rv_timer_disabled/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_disabled_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_cfg_update_on_fly 56215889578657250609926166979720155794253987202655674612206757322816536749880 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/2.rv_timer_cfg_update_on_fly/latest run_opts='+zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3069224760 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/2.rv_timer_cfg_update_on_fly.3069224760 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 2.rv_timer_cfg_update_on_fly.3069224760 -covoverwrite' seed=56215889578657250609926166979720155794253987202655674612206757322816536749880 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56215889578657250609926166979720155794253987202655674612206757322816536749880 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/2.rv_timer_cfg_update_on_fly/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_cfg_update_on_fly_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random_reset 106168900247936712362076989692003836639257292820283116729014086379370572982516 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/2.rv_timer_random_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=4228163828 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/2.rv_timer_random_reset.4228163828 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 2.rv_timer_random_reset.4228163828 -covoverwrite' seed=106168900247936712362076989692003836639257292820283116729014086379370572982516 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106168900247936712362076989692003836639257292820283116729014086379370572982516 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/2.rv_timer_random_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_stress_all_with_rand_reset 92397021433018531565721465782713539504396183396582311695355756959876517201173 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/2.rv_timer_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3490972949 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/2.rv_timer_stress_all_with_rand_reset.3490972949 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 2.rv_timer_stress_all_with_rand_reset.3490972949 -covoverwrite' seed=92397021433018531565721465782713539504396183396582311695355756959876517201173 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92397021433018531565721465782713539504396183396582311695355756959876517201173 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/2.rv_timer_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_sec_cm 60023394333054402453890461443948596752792570936927992591173728202514234702324 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/2.rv_timer_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=594901492 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/2.rv_timer_sec_cm.594901492 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 2.rv_timer_sec_cm.594901492 -covoverwrite' seed=60023394333054402453890461443948596752792570936927992591173728202514234702324 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60023394333054402453890461443948596752792570936927992591173728202514234702324 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/2.rv_timer_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_errors 29724214237440134978692090931531152609403005959369167875041194614297523746630 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/2.rv_timer_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=318863174 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/2.rv_timer_tl_errors.318863174 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.rv_timer_tl_errors.318863174 -covoverwrite' seed=29724214237440134978692090931531152609403005959369167875041194614297523746630 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29724214237440134978692090931531152609403005959369167875041194614297523746630 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/2.rv_timer_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_intg_err 66622946831393514797095428696144010280852567126903445495860375461671462573664 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/2.rv_timer_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=580720224 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/2.rv_timer_tl_intg_err.580720224 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.rv_timer_tl_intg_err.580720224 -covoverwrite' seed=66622946831393514797095428696144010280852567126903445495860375461671462573664 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66622946831393514797095428696144010280852567126903445495860375461671462573664 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/2.rv_timer_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_intr_test 88280427483851203337645207452319842150202477594627555953837664821238738385154 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/2.rv_timer_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3166107906 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/2.rv_timer_intr_test.3166107906 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.rv_timer_intr_test.3166107906 -covoverwrite' seed=88280427483851203337645207452319842150202477594627555953837664821238738385154 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88280427483851203337645207452319842150202477594627555953837664821238738385154 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/2.rv_timer_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_alert_test 15168797597058237131008335007177410296388430792991192091674212944976752574827 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/2.rv_timer_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=2956099947 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/2.rv_timer_alert_test.2956099947 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 2.rv_timer_alert_test.2956099947 -covoverwrite' seed=15168797597058237131008335007177410296388430792991192091674212944976752574827 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15168797597058237131008335007177410296388430792991192091674212944976752574827 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/2.rv_timer_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_csr_rw 50284259974149375854310348184344539588555660817883350317330864201471990463517 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/2.rv_timer_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=23362589 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/2.rv_timer_csr_rw.23362589 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.rv_timer_csr_rw.23362589 -covoverwrite' seed=50284259974149375854310348184344539588555660817883350317330864201471990463517 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50284259974149375854310348184344539588555660817883350317330864201471990463517 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/2.rv_timer_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_same_csr_outstanding 115499133106342063902775003786459159837168870494429390812959329064633017791597 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/2.rv_timer_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=273118317 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/2.rv_timer_same_csr_outstanding.273118317 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.rv_timer_same_csr_outstanding.273118317 -covoverwrite' seed=115499133106342063902775003786459159837168870494429390812959329064633017791597 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115499133106342063902775003786459159837168870494429390812959329064633017791597 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/2.rv_timer_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_csr_mem_rw_with_rand_reset 47959699132618239973062139160494295496146613876690209480275682491149160795243 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/2.rv_timer_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2306853995 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/2.rv_timer_csr_mem_rw_with_rand_reset.2306853995 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.rv_timer_csr_mem_rw_with_rand_reset.2306853995 -covoverwrite' seed=47959699132618239973062139160494295496146613876690209480275682491149160795243 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47959699132618239973062139160494295496146613876690209480275682491149160795243 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/2.rv_timer_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random 46741428591942981642666546732131154068967095712158070288137973455226560198607 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/3.rv_timer_random/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=912406479 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/3.rv_timer_random.912406479 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 3.rv_timer_random.912406479 -covoverwrite' seed=46741428591942981642666546732131154068967095712158070288137973455226560198607 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46741428591942981642666546732131154068967095712158070288137973455226560198607 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/3.rv_timer_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_min 88232101712371492764536604200240903659190810187410717009154021724320987987172 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/3.rv_timer_min/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=1715584228 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_min_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/3.rv_timer_min.1715584228 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 3.rv_timer_min.1715584228 -covoverwrite' seed=88232101712371492764536604200240903659190810187410717009154021724320987987172 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88232101712371492764536604200240903659190810187410717009154021724320987987172 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/3.rv_timer_min/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_min_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_max 37238792402353493144891167077505364685307756701406429475837405143135268403271 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/3.rv_timer_max/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=1320187975 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_max_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/3.rv_timer_max.1320187975 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 3.rv_timer_max.1320187975 -covoverwrite' seed=37238792402353493144891167077505364685307756701406429475837405143135268403271 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37238792402353493144891167077505364685307756701406429475837405143135268403271 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/3.rv_timer_max/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_max_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_disabled 113071722412357945459515426156017250284906701469176488105147683207362809550665 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/3.rv_timer_disabled/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=507369289 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/3.rv_timer_disabled.507369289 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 3.rv_timer_disabled.507369289 -covoverwrite' seed=113071722412357945459515426156017250284906701469176488105147683207362809550665 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113071722412357945459515426156017250284906701469176488105147683207362809550665 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/3.rv_timer_disabled/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_disabled_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_cfg_update_on_fly 105227026314477778571316487280522683394552378356467800466892551390787893618158 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/3.rv_timer_cfg_update_on_fly/latest run_opts='+zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3833751022 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/3.rv_timer_cfg_update_on_fly.3833751022 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 3.rv_timer_cfg_update_on_fly.3833751022 -covoverwrite' seed=105227026314477778571316487280522683394552378356467800466892551390787893618158 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105227026314477778571316487280522683394552378356467800466892551390787893618158 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/3.rv_timer_cfg_update_on_fly/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_cfg_update_on_fly_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random_reset 34351160593796728404726629654063374332666222388926978249667951321086552582729 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/3.rv_timer_random_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3564776009 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/3.rv_timer_random_reset.3564776009 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 3.rv_timer_random_reset.3564776009 -covoverwrite' seed=34351160593796728404726629654063374332666222388926978249667951321086552582729 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34351160593796728404726629654063374332666222388926978249667951321086552582729 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/3.rv_timer_random_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_stress_all_with_rand_reset 50957804550819412008219627572271919008760357919785027955049502594399256906192 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/3.rv_timer_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=634587600 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/3.rv_timer_stress_all_with_rand_reset.634587600 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 3.rv_timer_stress_all_with_rand_reset.634587600 -covoverwrite' seed=50957804550819412008219627572271919008760357919785027955049502594399256906192 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50957804550819412008219627572271919008760357919785027955049502594399256906192 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/3.rv_timer_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_sec_cm 446401308387049259330815202662997320678090864309304745589727130500493479645 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/3.rv_timer_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=2885160669 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/3.rv_timer_sec_cm.2885160669 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 3.rv_timer_sec_cm.2885160669 -covoverwrite' seed=446401308387049259330815202662997320678090864309304745589727130500493479645 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=446401308387049259330815202662997320678090864309304745589727130500493479645 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/3.rv_timer_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_errors 4102140232170939667634826814827261976277897864881175590483128374746809398912 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/3.rv_timer_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1260418688 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/3.rv_timer_tl_errors.1260418688 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.rv_timer_tl_errors.1260418688 -covoverwrite' seed=4102140232170939667634826814827261976277897864881175590483128374746809398912 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4102140232170939667634826814827261976277897864881175590483128374746809398912 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/3.rv_timer_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_intg_err 60255951115171593244566108407283683636230928086376226088581638294234285804818 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/3.rv_timer_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=935136530 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/3.rv_timer_tl_intg_err.935136530 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.rv_timer_tl_intg_err.935136530 -covoverwrite' seed=60255951115171593244566108407283683636230928086376226088581638294234285804818 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60255951115171593244566108407283683636230928086376226088581638294234285804818 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/3.rv_timer_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_intr_test 35172047511771289828543837382842662955869777090195346386456730537076371801564 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/3.rv_timer_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1573176796 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/3.rv_timer_intr_test.1573176796 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.rv_timer_intr_test.1573176796 -covoverwrite' seed=35172047511771289828543837382842662955869777090195346386456730537076371801564 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35172047511771289828543837382842662955869777090195346386456730537076371801564 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/3.rv_timer_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_alert_test 90898960753916908293646806652656756576123604304581572993665927152557306054609 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/3.rv_timer_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=1345750993 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/3.rv_timer_alert_test.1345750993 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 3.rv_timer_alert_test.1345750993 -covoverwrite' seed=90898960753916908293646806652656756576123604304581572993665927152557306054609 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90898960753916908293646806652656756576123604304581572993665927152557306054609 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/3.rv_timer_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_csr_rw 34374633149524012673694875209471166767088828663437947749974472294217566485507 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/3.rv_timer_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1058896899 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/3.rv_timer_csr_rw.1058896899 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.rv_timer_csr_rw.1058896899 -covoverwrite' seed=34374633149524012673694875209471166767088828663437947749974472294217566485507 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34374633149524012673694875209471166767088828663437947749974472294217566485507 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/3.rv_timer_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_same_csr_outstanding 45315495508008479235735226152677381495598798371402281449856627286466363237786 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/3.rv_timer_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2919081370 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/3.rv_timer_same_csr_outstanding.2919081370 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.rv_timer_same_csr_outstanding.2919081370 -covoverwrite' seed=45315495508008479235735226152677381495598798371402281449856627286466363237786 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45315495508008479235735226152677381495598798371402281449856627286466363237786 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/3.rv_timer_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_csr_mem_rw_with_rand_reset 9042008148913234199152152230491278494105189375308565228394823594487579818514 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/3.rv_timer_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3264363026 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/3.rv_timer_csr_mem_rw_with_rand_reset.3264363026 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.rv_timer_csr_mem_rw_with_rand_reset.3264363026 -covoverwrite' seed=9042008148913234199152152230491278494105189375308565228394823594487579818514 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9042008148913234199152152230491278494105189375308565228394823594487579818514 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/3.rv_timer_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random 8357745727170081248581393643744320377772117964245589018926017233869466378012 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/4.rv_timer_random/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=2208177948 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/4.rv_timer_random.2208177948 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 4.rv_timer_random.2208177948 -covoverwrite' seed=8357745727170081248581393643744320377772117964245589018926017233869466378012 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8357745727170081248581393643744320377772117964245589018926017233869466378012 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/4.rv_timer_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_min 57781416451976931595818950424609971128604177561664801858178705841218343592899 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/4.rv_timer_min/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=2012931011 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_min_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/4.rv_timer_min.2012931011 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 4.rv_timer_min.2012931011 -covoverwrite' seed=57781416451976931595818950424609971128604177561664801858178705841218343592899 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57781416451976931595818950424609971128604177561664801858178705841218343592899 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/4.rv_timer_min/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_min_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_max 48492837952126641072697977688071350028061409425719681079154505224475196804285 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/4.rv_timer_max/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=1182289085 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_max_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/4.rv_timer_max.1182289085 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 4.rv_timer_max.1182289085 -covoverwrite' seed=48492837952126641072697977688071350028061409425719681079154505224475196804285 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48492837952126641072697977688071350028061409425719681079154505224475196804285 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/4.rv_timer_max/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_max_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_disabled 48045309515426309733651477529636650520015612639592904923386983011423589332979 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/4.rv_timer_disabled/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=1356429299 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/4.rv_timer_disabled.1356429299 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 4.rv_timer_disabled.1356429299 -covoverwrite' seed=48045309515426309733651477529636650520015612639592904923386983011423589332979 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48045309515426309733651477529636650520015612639592904923386983011423589332979 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/4.rv_timer_disabled/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_disabled_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_cfg_update_on_fly 35864243571724127444979079888549436072797326931502280401332873017185960753849 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/4.rv_timer_cfg_update_on_fly/latest run_opts='+zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3931142841 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/4.rv_timer_cfg_update_on_fly.3931142841 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 4.rv_timer_cfg_update_on_fly.3931142841 -covoverwrite' seed=35864243571724127444979079888549436072797326931502280401332873017185960753849 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35864243571724127444979079888549436072797326931502280401332873017185960753849 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/4.rv_timer_cfg_update_on_fly/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_cfg_update_on_fly_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random_reset 30753824089439799326017962198737778097153634144121176799536041932256730996531 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/4.rv_timer_random_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=4191477555 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/4.rv_timer_random_reset.4191477555 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 4.rv_timer_random_reset.4191477555 -covoverwrite' seed=30753824089439799326017962198737778097153634144121176799536041932256730996531 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30753824089439799326017962198737778097153634144121176799536041932256730996531 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/4.rv_timer_random_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_stress_all_with_rand_reset 41726905545823034979610070994145444711428758260580766690822440263698477005358 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/4.rv_timer_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=798013998 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/4.rv_timer_stress_all_with_rand_reset.798013998 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 4.rv_timer_stress_all_with_rand_reset.798013998 -covoverwrite' seed=41726905545823034979610070994145444711428758260580766690822440263698477005358 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41726905545823034979610070994145444711428758260580766690822440263698477005358 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/4.rv_timer_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_sec_cm 70645466238336624049208757512616382051761645295438705431276738685357692951048 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/4.rv_timer_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=2722241032 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/4.rv_timer_sec_cm.2722241032 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 4.rv_timer_sec_cm.2722241032 -covoverwrite' seed=70645466238336624049208757512616382051761645295438705431276738685357692951048 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70645466238336624049208757512616382051761645295438705431276738685357692951048 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/4.rv_timer_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_errors 2468829115070611518340108111096079313634975124848767233122674199787928016831 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/4.rv_timer_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3613382591 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/4.rv_timer_tl_errors.3613382591 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.rv_timer_tl_errors.3613382591 -covoverwrite' seed=2468829115070611518340108111096079313634975124848767233122674199787928016831 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2468829115070611518340108111096079313634975124848767233122674199787928016831 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/4.rv_timer_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_intg_err 93552916806589742552223708422519948056843826695597912413226383740582674408276 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/4.rv_timer_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=580756308 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/4.rv_timer_tl_intg_err.580756308 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.rv_timer_tl_intg_err.580756308 -covoverwrite' seed=93552916806589742552223708422519948056843826695597912413226383740582674408276 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93552916806589742552223708422519948056843826695597912413226383740582674408276 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/4.rv_timer_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_intr_test 95846230771576432173272610704507608728565274882952762630533107732024756724975 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/4.rv_timer_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2239948015 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/4.rv_timer_intr_test.2239948015 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.rv_timer_intr_test.2239948015 -covoverwrite' seed=95846230771576432173272610704507608728565274882952762630533107732024756724975 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95846230771576432173272610704507608728565274882952762630533107732024756724975 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/4.rv_timer_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_alert_test 43363303491403212197572987389036989892116466828374126478278349596387575519916 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/4.rv_timer_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=2475350700 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/4.rv_timer_alert_test.2475350700 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 4.rv_timer_alert_test.2475350700 -covoverwrite' seed=43363303491403212197572987389036989892116466828374126478278349596387575519916 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43363303491403212197572987389036989892116466828374126478278349596387575519916 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/4.rv_timer_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_csr_rw 109523151107854519218819411348159227977032626128129891741339664987614175947693 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/4.rv_timer_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2357849005 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/4.rv_timer_csr_rw.2357849005 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.rv_timer_csr_rw.2357849005 -covoverwrite' seed=109523151107854519218819411348159227977032626128129891741339664987614175947693 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109523151107854519218819411348159227977032626128129891741339664987614175947693 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/4.rv_timer_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_same_csr_outstanding 19778659876115149238616119727043153042792284870795371318399110635256557351641 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/4.rv_timer_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3109565145 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/4.rv_timer_same_csr_outstanding.3109565145 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.rv_timer_same_csr_outstanding.3109565145 -covoverwrite' seed=19778659876115149238616119727043153042792284870795371318399110635256557351641 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19778659876115149238616119727043153042792284870795371318399110635256557351641 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/4.rv_timer_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_csr_mem_rw_with_rand_reset 71411513949848911009982335178987114650287443200313697492283970549269794501357 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/4.rv_timer_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=388608749 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/4.rv_timer_csr_mem_rw_with_rand_reset.388608749 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.rv_timer_csr_mem_rw_with_rand_reset.388608749 -covoverwrite' seed=71411513949848911009982335178987114650287443200313697492283970549269794501357 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71411513949848911009982335178987114650287443200313697492283970549269794501357 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/4.rv_timer_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random 10495935025206726359724952553738452218036998980417860799304018978469936256482 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/5.rv_timer_random/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3205387746 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/5.rv_timer_random.3205387746 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 5.rv_timer_random.3205387746 -covoverwrite' seed=10495935025206726359724952553738452218036998980417860799304018978469936256482 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10495935025206726359724952553738452218036998980417860799304018978469936256482 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/5.rv_timer_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_min 3658917087105749935615346890237764781932104197511447424782103596212287819158 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/5.rv_timer_min/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=1291177366 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_min_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/5.rv_timer_min.1291177366 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 5.rv_timer_min.1291177366 -covoverwrite' seed=3658917087105749935615346890237764781932104197511447424782103596212287819158 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3658917087105749935615346890237764781932104197511447424782103596212287819158 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/5.rv_timer_min/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_min_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_max 25929590064393254450384557618941904373449248686587962886217690141221643477145 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/5.rv_timer_max/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3027099801 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_max_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/5.rv_timer_max.3027099801 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 5.rv_timer_max.3027099801 -covoverwrite' seed=25929590064393254450384557618941904373449248686587962886217690141221643477145 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25929590064393254450384557618941904373449248686587962886217690141221643477145 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/5.rv_timer_max/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_max_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_disabled 38284563355437392275247024600566330837737966774717354663056459627226049146511 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/5.rv_timer_disabled/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=4194430607 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/5.rv_timer_disabled.4194430607 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 5.rv_timer_disabled.4194430607 -covoverwrite' seed=38284563355437392275247024600566330837737966774717354663056459627226049146511 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38284563355437392275247024600566330837737966774717354663056459627226049146511 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/5.rv_timer_disabled/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_disabled_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_cfg_update_on_fly 74639856458542235305944053728450376629231850110799491702637591522290348140319 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/5.rv_timer_cfg_update_on_fly/latest run_opts='+zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=4202768159 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/5.rv_timer_cfg_update_on_fly.4202768159 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 5.rv_timer_cfg_update_on_fly.4202768159 -covoverwrite' seed=74639856458542235305944053728450376629231850110799491702637591522290348140319 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74639856458542235305944053728450376629231850110799491702637591522290348140319 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/5.rv_timer_cfg_update_on_fly/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_cfg_update_on_fly_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random_reset 18480390095614342543601567135849488124226380304469307734076954511315711987597 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/5.rv_timer_random_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=512397197 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/5.rv_timer_random_reset.512397197 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 5.rv_timer_random_reset.512397197 -covoverwrite' seed=18480390095614342543601567135849488124226380304469307734076954511315711987597 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18480390095614342543601567135849488124226380304469307734076954511315711987597 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/5.rv_timer_random_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_stress_all_with_rand_reset 15169727444825117624819729494690105800426818029530246016183531133704394450398 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/5.rv_timer_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=455550430 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/5.rv_timer_stress_all_with_rand_reset.455550430 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 5.rv_timer_stress_all_with_rand_reset.455550430 -covoverwrite' seed=15169727444825117624819729494690105800426818029530246016183531133704394450398 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15169727444825117624819729494690105800426818029530246016183531133704394450398 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/5.rv_timer_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_errors 34236993749011793052217577643608498540115661270827751853905038166600309095764 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/5.rv_timer_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4032380244 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/5.rv_timer_tl_errors.4032380244 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.rv_timer_tl_errors.4032380244 -covoverwrite' seed=34236993749011793052217577643608498540115661270827751853905038166600309095764 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34236993749011793052217577643608498540115661270827751853905038166600309095764 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/5.rv_timer_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_intg_err 89131716917709720862842951125721892881173335094036645362110383806485809044034 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/5.rv_timer_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2707135042 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/5.rv_timer_tl_intg_err.2707135042 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.rv_timer_tl_intg_err.2707135042 -covoverwrite' seed=89131716917709720862842951125721892881173335094036645362110383806485809044034 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89131716917709720862842951125721892881173335094036645362110383806485809044034 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/5.rv_timer_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_intr_test 91064831667629471721846329401759483093033781752912388870392161201624996604167 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/5.rv_timer_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2214816007 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/5.rv_timer_intr_test.2214816007 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.rv_timer_intr_test.2214816007 -covoverwrite' seed=91064831667629471721846329401759483093033781752912388870392161201624996604167 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91064831667629471721846329401759483093033781752912388870392161201624996604167 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/5.rv_timer_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_alert_test 28583393999448186000519143334081674456975253469199938627061048509395713942488 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/5.rv_timer_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=2055234520 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/5.rv_timer_alert_test.2055234520 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 5.rv_timer_alert_test.2055234520 -covoverwrite' seed=28583393999448186000519143334081674456975253469199938627061048509395713942488 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28583393999448186000519143334081674456975253469199938627061048509395713942488 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/5.rv_timer_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random 41713708299909169736185326867659958060020780960920146396309616548920159702880 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/6.rv_timer_random/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3925413728 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/6.rv_timer_random.3925413728 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 6.rv_timer_random.3925413728 -covoverwrite' seed=41713708299909169736185326867659958060020780960920146396309616548920159702880 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41713708299909169736185326867659958060020780960920146396309616548920159702880 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/6.rv_timer_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_min 780564957585520515082176856539650212718098364059984018340392284721493401870 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/6.rv_timer_min/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=2071814414 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_min_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/6.rv_timer_min.2071814414 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 6.rv_timer_min.2071814414 -covoverwrite' seed=780564957585520515082176856539650212718098364059984018340392284721493401870 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=780564957585520515082176856539650212718098364059984018340392284721493401870 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/6.rv_timer_min/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_min_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_max 26218095662437790815495985289735232039608999120864634155726415382892831497312 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/6.rv_timer_max/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=2272713824 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_max_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/6.rv_timer_max.2272713824 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 6.rv_timer_max.2272713824 -covoverwrite' seed=26218095662437790815495985289735232039608999120864634155726415382892831497312 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26218095662437790815495985289735232039608999120864634155726415382892831497312 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/6.rv_timer_max/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_max_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_disabled 68170640806067701967909937699411316457460661234621752459411018815623587941843 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/6.rv_timer_disabled/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3734752723 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/6.rv_timer_disabled.3734752723 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 6.rv_timer_disabled.3734752723 -covoverwrite' seed=68170640806067701967909937699411316457460661234621752459411018815623587941843 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68170640806067701967909937699411316457460661234621752459411018815623587941843 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/6.rv_timer_disabled/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_disabled_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_cfg_update_on_fly 98062068377459749691161411361913662694729200311182732866950587673019933289360 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/6.rv_timer_cfg_update_on_fly/latest run_opts='+zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3482086288 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/6.rv_timer_cfg_update_on_fly.3482086288 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 6.rv_timer_cfg_update_on_fly.3482086288 -covoverwrite' seed=98062068377459749691161411361913662694729200311182732866950587673019933289360 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98062068377459749691161411361913662694729200311182732866950587673019933289360 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/6.rv_timer_cfg_update_on_fly/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_cfg_update_on_fly_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random_reset 99038830812861798069443422530333339560678099122151589338531849008910495395035 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/6.rv_timer_random_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=31730907 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/6.rv_timer_random_reset.31730907 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 6.rv_timer_random_reset.31730907 -covoverwrite' seed=99038830812861798069443422530333339560678099122151589338531849008910495395035 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99038830812861798069443422530333339560678099122151589338531849008910495395035 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/6.rv_timer_random_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_stress_all_with_rand_reset 29572047112531388185549242415582974559625001851833092884625276819519327699281 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/6.rv_timer_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3423600977 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/6.rv_timer_stress_all_with_rand_reset.3423600977 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 6.rv_timer_stress_all_with_rand_reset.3423600977 -covoverwrite' seed=29572047112531388185549242415582974559625001851833092884625276819519327699281 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29572047112531388185549242415582974559625001851833092884625276819519327699281 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/6.rv_timer_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_errors 21977899092411424946334635887451535913298563335454006268048265374725885955901 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/6.rv_timer_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2769063741 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/6.rv_timer_tl_errors.2769063741 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.rv_timer_tl_errors.2769063741 -covoverwrite' seed=21977899092411424946334635887451535913298563335454006268048265374725885955901 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21977899092411424946334635887451535913298563335454006268048265374725885955901 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/6.rv_timer_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_intg_err 68344710297983060364016848054614875504019267912098505607340731201872281940241 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/6.rv_timer_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=665268497 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/6.rv_timer_tl_intg_err.665268497 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.rv_timer_tl_intg_err.665268497 -covoverwrite' seed=68344710297983060364016848054614875504019267912098505607340731201872281940241 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68344710297983060364016848054614875504019267912098505607340731201872281940241 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/6.rv_timer_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_intr_test 34743140751853245243991355674301689514369679531573469619013616931784405765912 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/6.rv_timer_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1041977112 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/6.rv_timer_intr_test.1041977112 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.rv_timer_intr_test.1041977112 -covoverwrite' seed=34743140751853245243991355674301689514369679531573469619013616931784405765912 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34743140751853245243991355674301689514369679531573469619013616931784405765912 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/6.rv_timer_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_alert_test 88602161523121679751522998357959722542165051750981113951817643225676863180769 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/6.rv_timer_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=794496993 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/6.rv_timer_alert_test.794496993 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 6.rv_timer_alert_test.794496993 -covoverwrite' seed=88602161523121679751522998357959722542165051750981113951817643225676863180769 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88602161523121679751522998357959722542165051750981113951817643225676863180769 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/6.rv_timer_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random 88178628880192578217110438554497266291347418507948007538212492267507560342980 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/7.rv_timer_random/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=1688856004 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/7.rv_timer_random.1688856004 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 7.rv_timer_random.1688856004 -covoverwrite' seed=88178628880192578217110438554497266291347418507948007538212492267507560342980 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88178628880192578217110438554497266291347418507948007538212492267507560342980 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/7.rv_timer_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_min 55824625995946792066302093220107647716329948086579289825420191785625739492121 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/7.rv_timer_min/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3119151897 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_min_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/7.rv_timer_min.3119151897 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 7.rv_timer_min.3119151897 -covoverwrite' seed=55824625995946792066302093220107647716329948086579289825420191785625739492121 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55824625995946792066302093220107647716329948086579289825420191785625739492121 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/7.rv_timer_min/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_min_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_max 71959975738852441468460564079747376469264487808426392976335562207294760409818 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/7.rv_timer_max/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3023035098 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_max_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/7.rv_timer_max.3023035098 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 7.rv_timer_max.3023035098 -covoverwrite' seed=71959975738852441468460564079747376469264487808426392976335562207294760409818 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71959975738852441468460564079747376469264487808426392976335562207294760409818 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/7.rv_timer_max/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_max_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_disabled 109302184564512980778463707117680917588834410741610563004331622396155904986592 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/7.rv_timer_disabled/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=2719288800 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/7.rv_timer_disabled.2719288800 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 7.rv_timer_disabled.2719288800 -covoverwrite' seed=109302184564512980778463707117680917588834410741610563004331622396155904986592 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109302184564512980778463707117680917588834410741610563004331622396155904986592 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/7.rv_timer_disabled/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_disabled_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_cfg_update_on_fly 67205978731566379809971662157400879922386134176724312608764869157287123216390 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/7.rv_timer_cfg_update_on_fly/latest run_opts='+zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=995878918 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/7.rv_timer_cfg_update_on_fly.995878918 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 7.rv_timer_cfg_update_on_fly.995878918 -covoverwrite' seed=67205978731566379809971662157400879922386134176724312608764869157287123216390 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67205978731566379809971662157400879922386134176724312608764869157287123216390 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/7.rv_timer_cfg_update_on_fly/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_cfg_update_on_fly_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random_reset 39378951066100442002510576537330827874053729882053391085581994408820230964004 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/7.rv_timer_random_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3950363428 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/7.rv_timer_random_reset.3950363428 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 7.rv_timer_random_reset.3950363428 -covoverwrite' seed=39378951066100442002510576537330827874053729882053391085581994408820230964004 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39378951066100442002510576537330827874053729882053391085581994408820230964004 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/7.rv_timer_random_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_stress_all_with_rand_reset 103036017060977296620905228894644985086394576020034855024448779766062892489404 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/7.rv_timer_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=2812058300 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/7.rv_timer_stress_all_with_rand_reset.2812058300 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 7.rv_timer_stress_all_with_rand_reset.2812058300 -covoverwrite' seed=103036017060977296620905228894644985086394576020034855024448779766062892489404 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103036017060977296620905228894644985086394576020034855024448779766062892489404 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/7.rv_timer_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_errors 32573185971909301275815621524027947148887096833190110805685770584359974952534 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/7.rv_timer_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=393961046 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/7.rv_timer_tl_errors.393961046 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.rv_timer_tl_errors.393961046 -covoverwrite' seed=32573185971909301275815621524027947148887096833190110805685770584359974952534 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32573185971909301275815621524027947148887096833190110805685770584359974952534 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/7.rv_timer_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_intg_err 75701356997672647547760582263897557864459315965000073635995162499658439454534 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/7.rv_timer_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=183758662 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/7.rv_timer_tl_intg_err.183758662 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.rv_timer_tl_intg_err.183758662 -covoverwrite' seed=75701356997672647547760582263897557864459315965000073635995162499658439454534 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75701356997672647547760582263897557864459315965000073635995162499658439454534 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/7.rv_timer_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_intr_test 85741326022725677886104222802254324870559005594956335969390676566092243177695 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/7.rv_timer_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4164063455 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/7.rv_timer_intr_test.4164063455 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.rv_timer_intr_test.4164063455 -covoverwrite' seed=85741326022725677886104222802254324870559005594956335969390676566092243177695 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85741326022725677886104222802254324870559005594956335969390676566092243177695 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/7.rv_timer_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_alert_test 38423942016173935772825740375352585736809612855402327718964894425612687371067 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/7.rv_timer_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=2324556603 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/7.rv_timer_alert_test.2324556603 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 7.rv_timer_alert_test.2324556603 -covoverwrite' seed=38423942016173935772825740375352585736809612855402327718964894425612687371067 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38423942016173935772825740375352585736809612855402327718964894425612687371067 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/7.rv_timer_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random 42573006822532030714455011295270821045986236156353390621743438786218821150244 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/8.rv_timer_random/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3431458340 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/8.rv_timer_random.3431458340 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 8.rv_timer_random.3431458340 -covoverwrite' seed=42573006822532030714455011295270821045986236156353390621743438786218821150244 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42573006822532030714455011295270821045986236156353390621743438786218821150244 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/8.rv_timer_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_min 100437311420993530168099617858610475170376866453529083622162778262370068071171 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/8.rv_timer_min/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=1056834307 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_min_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/8.rv_timer_min.1056834307 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 8.rv_timer_min.1056834307 -covoverwrite' seed=100437311420993530168099617858610475170376866453529083622162778262370068071171 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100437311420993530168099617858610475170376866453529083622162778262370068071171 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/8.rv_timer_min/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_min_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_max 76071070928362499136795427841864262882237994271449092779949181495506926842229 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/8.rv_timer_max/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=759705973 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_max_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/8.rv_timer_max.759705973 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 8.rv_timer_max.759705973 -covoverwrite' seed=76071070928362499136795427841864262882237994271449092779949181495506926842229 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76071070928362499136795427841864262882237994271449092779949181495506926842229 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/8.rv_timer_max/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_max_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_disabled 17441235404246302069540859635840581839323405307228177557672113131027026505588 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/8.rv_timer_disabled/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=1352494964 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/8.rv_timer_disabled.1352494964 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 8.rv_timer_disabled.1352494964 -covoverwrite' seed=17441235404246302069540859635840581839323405307228177557672113131027026505588 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17441235404246302069540859635840581839323405307228177557672113131027026505588 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/8.rv_timer_disabled/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_disabled_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_cfg_update_on_fly 93544749780939717761258404053295393771989925140663632802729240471500285267156 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/8.rv_timer_cfg_update_on_fly/latest run_opts='+zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=2652884180 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/8.rv_timer_cfg_update_on_fly.2652884180 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 8.rv_timer_cfg_update_on_fly.2652884180 -covoverwrite' seed=93544749780939717761258404053295393771989925140663632802729240471500285267156 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93544749780939717761258404053295393771989925140663632802729240471500285267156 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/8.rv_timer_cfg_update_on_fly/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_cfg_update_on_fly_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random_reset 30564965831426303588193842831876559993865097485513993785929798566942745629413 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/8.rv_timer_random_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=188551909 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/8.rv_timer_random_reset.188551909 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 8.rv_timer_random_reset.188551909 -covoverwrite' seed=30564965831426303588193842831876559993865097485513993785929798566942745629413 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30564965831426303588193842831876559993865097485513993785929798566942745629413 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/8.rv_timer_random_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_stress_all_with_rand_reset 50414377561650305509779456349193659321990762799129914847961687339047675707336 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/8.rv_timer_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=1287339976 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/8.rv_timer_stress_all_with_rand_reset.1287339976 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 8.rv_timer_stress_all_with_rand_reset.1287339976 -covoverwrite' seed=50414377561650305509779456349193659321990762799129914847961687339047675707336 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50414377561650305509779456349193659321990762799129914847961687339047675707336 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/8.rv_timer_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_errors 46698789464308966678528046348709870970460798947449389168798721144828726962582 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/8.rv_timer_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3550046614 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/8.rv_timer_tl_errors.3550046614 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.rv_timer_tl_errors.3550046614 -covoverwrite' seed=46698789464308966678528046348709870970460798947449389168798721144828726962582 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46698789464308966678528046348709870970460798947449389168798721144828726962582 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/8.rv_timer_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_intg_err 82373715668421034102265235340036273209858644406227024785927206004623269563468 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/8.rv_timer_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=600706124 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/8.rv_timer_tl_intg_err.600706124 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.rv_timer_tl_intg_err.600706124 -covoverwrite' seed=82373715668421034102265235340036273209858644406227024785927206004623269563468 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82373715668421034102265235340036273209858644406227024785927206004623269563468 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/8.rv_timer_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_intr_test 79379411091510850157877316548264132938366757583841339764444402216267028167779 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/8.rv_timer_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=688454755 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/8.rv_timer_intr_test.688454755 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.rv_timer_intr_test.688454755 -covoverwrite' seed=79379411091510850157877316548264132938366757583841339764444402216267028167779 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79379411091510850157877316548264132938366757583841339764444402216267028167779 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/8.rv_timer_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_alert_test 107355520566512102021912738389648859717940664175190226919528188239220471212890 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/8.rv_timer_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=1570483034 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/8.rv_timer_alert_test.1570483034 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 8.rv_timer_alert_test.1570483034 -covoverwrite' seed=107355520566512102021912738389648859717940664175190226919528188239220471212890 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107355520566512102021912738389648859717940664175190226919528188239220471212890 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/8.rv_timer_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random 30499677884422748012650095610395960954385470591996384736432453469545108452540 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/9.rv_timer_random/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=1969599676 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/9.rv_timer_random.1969599676 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 9.rv_timer_random.1969599676 -covoverwrite' seed=30499677884422748012650095610395960954385470591996384736432453469545108452540 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30499677884422748012650095610395960954385470591996384736432453469545108452540 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/9.rv_timer_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_min 13059143498590887990722836163768069946661205021484574025486649833837307834063 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/9.rv_timer_min/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=4282068687 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_min_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/9.rv_timer_min.4282068687 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 9.rv_timer_min.4282068687 -covoverwrite' seed=13059143498590887990722836163768069946661205021484574025486649833837307834063 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13059143498590887990722836163768069946661205021484574025486649833837307834063 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/9.rv_timer_min/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_min_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_max 61523880149361058066752722315418536735619868243442520071223490901306209669793 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/9.rv_timer_max/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=4276294305 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_max_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/9.rv_timer_max.4276294305 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 9.rv_timer_max.4276294305 -covoverwrite' seed=61523880149361058066752722315418536735619868243442520071223490901306209669793 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61523880149361058066752722315418536735619868243442520071223490901306209669793 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/9.rv_timer_max/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_max_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_disabled 46545897220339478977837346907394153454014997148145285522313966301943032050536 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/9.rv_timer_disabled/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=2629170024 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/9.rv_timer_disabled.2629170024 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 9.rv_timer_disabled.2629170024 -covoverwrite' seed=46545897220339478977837346907394153454014997148145285522313966301943032050536 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46545897220339478977837346907394153454014997148145285522313966301943032050536 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/9.rv_timer_disabled/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_disabled_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_cfg_update_on_fly 103890883607114681219143545976284925860161252241676602744598993678482284529451 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/9.rv_timer_cfg_update_on_fly/latest run_opts='+zero_delays=1 +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=471648043 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_cfg_update_on_fly_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/9.rv_timer_cfg_update_on_fly.471648043 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 9.rv_timer_cfg_update_on_fly.471648043 -covoverwrite' seed=103890883607114681219143545976284925860161252241676602744598993678482284529451 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103890883607114681219143545976284925860161252241676602744598993678482284529451 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/9.rv_timer_cfg_update_on_fly/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_cfg_update_on_fly_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random_reset 60148458271634473445403135497905514392905792447959347298316798356901935459073 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/9.rv_timer_random_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=814230273 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/9.rv_timer_random_reset.814230273 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 9.rv_timer_random_reset.814230273 -covoverwrite' seed=60148458271634473445403135497905514392905792447959347298316798356901935459073 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60148458271634473445403135497905514392905792447959347298316798356901935459073 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/9.rv_timer_random_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_stress_all_with_rand_reset 91148767921014014706897614007271376788375793626640119079596594841808251112074 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/9.rv_timer_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3582708362 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/9.rv_timer_stress_all_with_rand_reset.3582708362 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 9.rv_timer_stress_all_with_rand_reset.3582708362 -covoverwrite' seed=91148767921014014706897614007271376788375793626640119079596594841808251112074 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91148767921014014706897614007271376788375793626640119079596594841808251112074 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/9.rv_timer_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_errors 114403024314621574617689481885338146714005373397325019031801728193265874958506 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/9.rv_timer_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1016264874 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/9.rv_timer_tl_errors.1016264874 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.rv_timer_tl_errors.1016264874 -covoverwrite' seed=114403024314621574617689481885338146714005373397325019031801728193265874958506 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114403024314621574617689481885338146714005373397325019031801728193265874958506 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/9.rv_timer_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_intg_err 41346488121102213553291547113005359287458802321725742023478710520523977506562 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/9.rv_timer_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1751498498 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/9.rv_timer_tl_intg_err.1751498498 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.rv_timer_tl_intg_err.1751498498 -covoverwrite' seed=41346488121102213553291547113005359287458802321725742023478710520523977506562 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41346488121102213553291547113005359287458802321725742023478710520523977506562 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/9.rv_timer_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_intr_test 28929320416972253889011923719579144824135353573088526550197196278370818492574 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/9.rv_timer_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1399752862 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/9.rv_timer_intr_test.1399752862 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.rv_timer_intr_test.1399752862 -covoverwrite' seed=28929320416972253889011923719579144824135353573088526550197196278370818492574 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28929320416972253889011923719579144824135353573088526550197196278370818492574 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/9.rv_timer_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_alert_test 14498453202906849634380777101681744171580271085919638022332201574851019428053 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/9.rv_timer_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3692712149 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/9.rv_timer_alert_test.3692712149 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 9.rv_timer_alert_test.3692712149 -covoverwrite' seed=14498453202906849634380777101681744171580271085919638022332201574851019428053 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=14498453202906849634380777101681744171580271085919638022332201574851019428053 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/9.rv_timer_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random 8766360484788850582017316864157799185655394140929890520586311014072418417997 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/10.rv_timer_random/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=2894970189 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/10.rv_timer_random.2894970189 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 10.rv_timer_random.2894970189 -covoverwrite' seed=8766360484788850582017316864157799185655394140929890520586311014072418417997 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8766360484788850582017316864157799185655394140929890520586311014072418417997 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/10.rv_timer_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_disabled 102151341612291051338731651702804784367842382706782067134781694212483036181177 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/10.rv_timer_disabled/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3369562809 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/10.rv_timer_disabled.3369562809 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 10.rv_timer_disabled.3369562809 -covoverwrite' seed=102151341612291051338731651702804784367842382706782067134781694212483036181177 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102151341612291051338731651702804784367842382706782067134781694212483036181177 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/10.rv_timer_disabled/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_disabled_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random_reset 48861882616438487656677846532448372848863080264251816559983057789393876155427 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/10.rv_timer_random_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=1310850083 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/10.rv_timer_random_reset.1310850083 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 10.rv_timer_random_reset.1310850083 -covoverwrite' seed=48861882616438487656677846532448372848863080264251816559983057789393876155427 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48861882616438487656677846532448372848863080264251816559983057789393876155427 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/10.rv_timer_random_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_stress_all_with_rand_reset 73861888616891089659873120276215082618123776892557722725940498876329408020619 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/10.rv_timer_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3649519755 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/10.rv_timer_stress_all_with_rand_reset.3649519755 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 10.rv_timer_stress_all_with_rand_reset.3649519755 -covoverwrite' seed=73861888616891089659873120276215082618123776892557722725940498876329408020619 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73861888616891089659873120276215082618123776892557722725940498876329408020619 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/10.rv_timer_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_errors 40739107017175241567630570575504605060722453218608457860297715610955837561514 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/10.rv_timer_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1905744554 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/10.rv_timer_tl_errors.1905744554 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 10.rv_timer_tl_errors.1905744554 -covoverwrite' seed=40739107017175241567630570575504605060722453218608457860297715610955837561514 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40739107017175241567630570575504605060722453218608457860297715610955837561514 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/10.rv_timer_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_intg_err 65732091527929939641923763426085398189303005210849701268666101836508647861618 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/10.rv_timer_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=700919154 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/10.rv_timer_tl_intg_err.700919154 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 10.rv_timer_tl_intg_err.700919154 -covoverwrite' seed=65732091527929939641923763426085398189303005210849701268666101836508647861618 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65732091527929939641923763426085398189303005210849701268666101836508647861618 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/10.rv_timer_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random 107629883575091529835840615844006726167694990597960842152405474199210491586886 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/11.rv_timer_random/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=810756422 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/11.rv_timer_random.810756422 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 11.rv_timer_random.810756422 -covoverwrite' seed=107629883575091529835840615844006726167694990597960842152405474199210491586886 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107629883575091529835840615844006726167694990597960842152405474199210491586886 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/11.rv_timer_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_disabled 1520067649656775764510965045172795425482017256244554427893818829155410604205 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/11.rv_timer_disabled/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=313487533 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/11.rv_timer_disabled.313487533 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 11.rv_timer_disabled.313487533 -covoverwrite' seed=1520067649656775764510965045172795425482017256244554427893818829155410604205 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1520067649656775764510965045172795425482017256244554427893818829155410604205 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/11.rv_timer_disabled/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_disabled_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random_reset 6458255253214289594306574079554793045460605300048692102522319647207695947609 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/11.rv_timer_random_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3587282777 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/11.rv_timer_random_reset.3587282777 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 11.rv_timer_random_reset.3587282777 -covoverwrite' seed=6458255253214289594306574079554793045460605300048692102522319647207695947609 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6458255253214289594306574079554793045460605300048692102522319647207695947609 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/11.rv_timer_random_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_stress_all_with_rand_reset 85920826855537755155280555365436776648026758721717551891941319260333746860837 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/11.rv_timer_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=2957947685 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/11.rv_timer_stress_all_with_rand_reset.2957947685 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 11.rv_timer_stress_all_with_rand_reset.2957947685 -covoverwrite' seed=85920826855537755155280555365436776648026758721717551891941319260333746860837 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85920826855537755155280555365436776648026758721717551891941319260333746860837 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/11.rv_timer_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_errors 77714634807682726132557764355222299726156381421627082602747039655014770548612 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/11.rv_timer_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2617384836 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/11.rv_timer_tl_errors.2617384836 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 11.rv_timer_tl_errors.2617384836 -covoverwrite' seed=77714634807682726132557764355222299726156381421627082602747039655014770548612 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77714634807682726132557764355222299726156381421627082602747039655014770548612 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/11.rv_timer_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_intg_err 7281743250420670148755322373908619295825626430912500424628190686583808656665 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/11.rv_timer_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3651732761 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/11.rv_timer_tl_intg_err.3651732761 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 11.rv_timer_tl_intg_err.3651732761 -covoverwrite' seed=7281743250420670148755322373908619295825626430912500424628190686583808656665 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7281743250420670148755322373908619295825626430912500424628190686583808656665 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/11.rv_timer_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random 100424433240733208898764859442665531927032401496544817670322575173915290780602 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/12.rv_timer_random/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3967959994 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/12.rv_timer_random.3967959994 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 12.rv_timer_random.3967959994 -covoverwrite' seed=100424433240733208898764859442665531927032401496544817670322575173915290780602 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100424433240733208898764859442665531927032401496544817670322575173915290780602 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/12.rv_timer_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_disabled 61148264980912082922990691863201679658353214549834125785812410653093382318110 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/12.rv_timer_disabled/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=1405610014 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/12.rv_timer_disabled.1405610014 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 12.rv_timer_disabled.1405610014 -covoverwrite' seed=61148264980912082922990691863201679658353214549834125785812410653093382318110 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61148264980912082922990691863201679658353214549834125785812410653093382318110 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/12.rv_timer_disabled/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_disabled_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random_reset 13284939084020988833485548914409383358052741002389549998996540163849551657328 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/12.rv_timer_random_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=920172912 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/12.rv_timer_random_reset.920172912 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 12.rv_timer_random_reset.920172912 -covoverwrite' seed=13284939084020988833485548914409383358052741002389549998996540163849551657328 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13284939084020988833485548914409383358052741002389549998996540163849551657328 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/12.rv_timer_random_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_stress_all_with_rand_reset 27876134680088741132047479452933490459258288086442725210883215745719839611176 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/12.rv_timer_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3540375848 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/12.rv_timer_stress_all_with_rand_reset.3540375848 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 12.rv_timer_stress_all_with_rand_reset.3540375848 -covoverwrite' seed=27876134680088741132047479452933490459258288086442725210883215745719839611176 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27876134680088741132047479452933490459258288086442725210883215745719839611176 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/12.rv_timer_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_errors 37495045825695475708266582089122716907897694272833821752554559818014181434131 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/12.rv_timer_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=59646739 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/12.rv_timer_tl_errors.59646739 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 12.rv_timer_tl_errors.59646739 -covoverwrite' seed=37495045825695475708266582089122716907897694272833821752554559818014181434131 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37495045825695475708266582089122716907897694272833821752554559818014181434131 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/12.rv_timer_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_intg_err 46898906583498197165344260444415200757655823586240187958673636516823474194041 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/12.rv_timer_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2019640953 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/12.rv_timer_tl_intg_err.2019640953 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 12.rv_timer_tl_intg_err.2019640953 -covoverwrite' seed=46898906583498197165344260444415200757655823586240187958673636516823474194041 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46898906583498197165344260444415200757655823586240187958673636516823474194041 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/12.rv_timer_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random 49922648934415890547803034654430876083780314417589399196384407194655199416099 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/13.rv_timer_random/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=689524515 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/13.rv_timer_random.689524515 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 13.rv_timer_random.689524515 -covoverwrite' seed=49922648934415890547803034654430876083780314417589399196384407194655199416099 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49922648934415890547803034654430876083780314417589399196384407194655199416099 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/13.rv_timer_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_disabled 521231486902461911372497382775226725802528116375667283941781538802498057707 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/13.rv_timer_disabled/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=629716459 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/13.rv_timer_disabled.629716459 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 13.rv_timer_disabled.629716459 -covoverwrite' seed=521231486902461911372497382775226725802528116375667283941781538802498057707 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=521231486902461911372497382775226725802528116375667283941781538802498057707 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/13.rv_timer_disabled/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_disabled_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random_reset 46323444362533288648917826275074642364383386587882571121174168651797600969271 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/13.rv_timer_random_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3243549239 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/13.rv_timer_random_reset.3243549239 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 13.rv_timer_random_reset.3243549239 -covoverwrite' seed=46323444362533288648917826275074642364383386587882571121174168651797600969271 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46323444362533288648917826275074642364383386587882571121174168651797600969271 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/13.rv_timer_random_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_stress_all_with_rand_reset 54557424957508740398737238009895771017586351202387552320221488577327023512535 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/13.rv_timer_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=2950683607 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/13.rv_timer_stress_all_with_rand_reset.2950683607 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 13.rv_timer_stress_all_with_rand_reset.2950683607 -covoverwrite' seed=54557424957508740398737238009895771017586351202387552320221488577327023512535 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54557424957508740398737238009895771017586351202387552320221488577327023512535 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/13.rv_timer_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_errors 65744274536350039495813150891213103237479531970144433778015013514571955949811 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/13.rv_timer_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=785764595 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/13.rv_timer_tl_errors.785764595 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 13.rv_timer_tl_errors.785764595 -covoverwrite' seed=65744274536350039495813150891213103237479531970144433778015013514571955949811 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65744274536350039495813150891213103237479531970144433778015013514571955949811 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/13.rv_timer_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_intg_err 87103583567839470101731492915250443845834129282207149539764868429893144265346 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/13.rv_timer_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=327271042 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/13.rv_timer_tl_intg_err.327271042 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 13.rv_timer_tl_intg_err.327271042 -covoverwrite' seed=87103583567839470101731492915250443845834129282207149539764868429893144265346 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87103583567839470101731492915250443845834129282207149539764868429893144265346 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/13.rv_timer_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random 74230233285080361754412609344341544427078806559997290405289010817465683801595 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/14.rv_timer_random/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=1417147899 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/14.rv_timer_random.1417147899 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 14.rv_timer_random.1417147899 -covoverwrite' seed=74230233285080361754412609344341544427078806559997290405289010817465683801595 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74230233285080361754412609344341544427078806559997290405289010817465683801595 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/14.rv_timer_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_disabled 28410285192432406551952409976348421316808867279266672160902184476106907234150 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/14.rv_timer_disabled/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=337162086 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/14.rv_timer_disabled.337162086 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 14.rv_timer_disabled.337162086 -covoverwrite' seed=28410285192432406551952409976348421316808867279266672160902184476106907234150 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28410285192432406551952409976348421316808867279266672160902184476106907234150 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/14.rv_timer_disabled/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_disabled_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random_reset 13790902505560004286138118673273351052227273083963452249824184747990162058786 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/14.rv_timer_random_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=2249436706 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/14.rv_timer_random_reset.2249436706 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 14.rv_timer_random_reset.2249436706 -covoverwrite' seed=13790902505560004286138118673273351052227273083963452249824184747990162058786 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13790902505560004286138118673273351052227273083963452249824184747990162058786 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/14.rv_timer_random_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_stress_all_with_rand_reset 23131303624642068508587575946069510498939192034005924317010118515609570108742 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/14.rv_timer_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=46916934 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/14.rv_timer_stress_all_with_rand_reset.46916934 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 14.rv_timer_stress_all_with_rand_reset.46916934 -covoverwrite' seed=23131303624642068508587575946069510498939192034005924317010118515609570108742 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23131303624642068508587575946069510498939192034005924317010118515609570108742 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/14.rv_timer_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_errors 94910837620509854675203729115166723093924958543790868371846992376725424752228 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/14.rv_timer_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=480691812 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/14.rv_timer_tl_errors.480691812 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 14.rv_timer_tl_errors.480691812 -covoverwrite' seed=94910837620509854675203729115166723093924958543790868371846992376725424752228 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94910837620509854675203729115166723093924958543790868371846992376725424752228 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/14.rv_timer_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_intg_err 94136549959096669376768287010120402981789973298258246457105713277287316284806 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/14.rv_timer_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=41641350 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/14.rv_timer_tl_intg_err.41641350 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 14.rv_timer_tl_intg_err.41641350 -covoverwrite' seed=94136549959096669376768287010120402981789973298258246457105713277287316284806 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94136549959096669376768287010120402981789973298258246457105713277287316284806 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/14.rv_timer_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random 96336929990015423387676766230754478033191279411841543593449059397407058951804 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/15.rv_timer_random/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=844627580 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/15.rv_timer_random.844627580 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 15.rv_timer_random.844627580 -covoverwrite' seed=96336929990015423387676766230754478033191279411841543593449059397407058951804 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96336929990015423387676766230754478033191279411841543593449059397407058951804 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/15.rv_timer_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_disabled 23467063576863914251568967139932602298325864114314300396119648967325910734008 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/15.rv_timer_disabled/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=515544248 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/15.rv_timer_disabled.515544248 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 15.rv_timer_disabled.515544248 -covoverwrite' seed=23467063576863914251568967139932602298325864114314300396119648967325910734008 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23467063576863914251568967139932602298325864114314300396119648967325910734008 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/15.rv_timer_disabled/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_disabled_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random_reset 96308330449669493083054899583739220308377438206564884029085991839446213379292 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/15.rv_timer_random_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=169395420 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/15.rv_timer_random_reset.169395420 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 15.rv_timer_random_reset.169395420 -covoverwrite' seed=96308330449669493083054899583739220308377438206564884029085991839446213379292 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96308330449669493083054899583739220308377438206564884029085991839446213379292 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/15.rv_timer_random_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_stress_all_with_rand_reset 93487250343665552955992428697369813634245835582187300495904154136906181638741 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/15.rv_timer_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=1211890261 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/15.rv_timer_stress_all_with_rand_reset.1211890261 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 15.rv_timer_stress_all_with_rand_reset.1211890261 -covoverwrite' seed=93487250343665552955992428697369813634245835582187300495904154136906181638741 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93487250343665552955992428697369813634245835582187300495904154136906181638741 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/15.rv_timer_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_errors 42547733357983701014348424938286638643078196837068812936414683160841863538057 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/15.rv_timer_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3228804489 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/15.rv_timer_tl_errors.3228804489 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 15.rv_timer_tl_errors.3228804489 -covoverwrite' seed=42547733357983701014348424938286638643078196837068812936414683160841863538057 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42547733357983701014348424938286638643078196837068812936414683160841863538057 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/15.rv_timer_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_intg_err 87045625737105670666013205616822637741962568986902671824447252459929721266662 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/15.rv_timer_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3098173926 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/15.rv_timer_tl_intg_err.3098173926 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 15.rv_timer_tl_intg_err.3098173926 -covoverwrite' seed=87045625737105670666013205616822637741962568986902671824447252459929721266662 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87045625737105670666013205616822637741962568986902671824447252459929721266662 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/15.rv_timer_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random 75220596404417997149791770260237373259002816382024051647643751870983690084435 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/16.rv_timer_random/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=2102485075 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/16.rv_timer_random.2102485075 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 16.rv_timer_random.2102485075 -covoverwrite' seed=75220596404417997149791770260237373259002816382024051647643751870983690084435 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75220596404417997149791770260237373259002816382024051647643751870983690084435 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/16.rv_timer_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_disabled 68840276913417169037696032784577903044500121246736324495110777845282651124764 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/16.rv_timer_disabled/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=2063217692 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/16.rv_timer_disabled.2063217692 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 16.rv_timer_disabled.2063217692 -covoverwrite' seed=68840276913417169037696032784577903044500121246736324495110777845282651124764 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68840276913417169037696032784577903044500121246736324495110777845282651124764 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/16.rv_timer_disabled/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_disabled_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random_reset 88648118694490192396741070498190884586985350801509323458798869076892727163966 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/16.rv_timer_random_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=276347966 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/16.rv_timer_random_reset.276347966 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 16.rv_timer_random_reset.276347966 -covoverwrite' seed=88648118694490192396741070498190884586985350801509323458798869076892727163966 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88648118694490192396741070498190884586985350801509323458798869076892727163966 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/16.rv_timer_random_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_stress_all_with_rand_reset 52427232214334976432376218849929509068667242941667091207999278346055603518760 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/16.rv_timer_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=1987902760 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/16.rv_timer_stress_all_with_rand_reset.1987902760 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 16.rv_timer_stress_all_with_rand_reset.1987902760 -covoverwrite' seed=52427232214334976432376218849929509068667242941667091207999278346055603518760 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=52427232214334976432376218849929509068667242941667091207999278346055603518760 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/16.rv_timer_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_errors 3558329436901146010455245956342447546460785017272560307631486588830687955886 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/16.rv_timer_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=640682926 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/16.rv_timer_tl_errors.640682926 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 16.rv_timer_tl_errors.640682926 -covoverwrite' seed=3558329436901146010455245956342447546460785017272560307631486588830687955886 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3558329436901146010455245956342447546460785017272560307631486588830687955886 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/16.rv_timer_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_intg_err 50973609882643507072670058821495908487773873288444604684855317674818458736190 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/16.rv_timer_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2462963262 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/16.rv_timer_tl_intg_err.2462963262 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 16.rv_timer_tl_intg_err.2462963262 -covoverwrite' seed=50973609882643507072670058821495908487773873288444604684855317674818458736190 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50973609882643507072670058821495908487773873288444604684855317674818458736190 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/16.rv_timer_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random 37161310147759634880173699423835018066587203556102978700013625938642617224584 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/17.rv_timer_random/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3422014856 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/17.rv_timer_random.3422014856 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 17.rv_timer_random.3422014856 -covoverwrite' seed=37161310147759634880173699423835018066587203556102978700013625938642617224584 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37161310147759634880173699423835018066587203556102978700013625938642617224584 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/17.rv_timer_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_disabled 17411304475267041915301844658758397680776823876077898000792895256605074431617 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/17.rv_timer_disabled/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=4289240705 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/17.rv_timer_disabled.4289240705 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 17.rv_timer_disabled.4289240705 -covoverwrite' seed=17411304475267041915301844658758397680776823876077898000792895256605074431617 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17411304475267041915301844658758397680776823876077898000792895256605074431617 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/17.rv_timer_disabled/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_disabled_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random_reset 81312312193439529001407191575615876046568450387900129332667805107942346985929 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/17.rv_timer_random_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3346797001 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/17.rv_timer_random_reset.3346797001 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 17.rv_timer_random_reset.3346797001 -covoverwrite' seed=81312312193439529001407191575615876046568450387900129332667805107942346985929 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81312312193439529001407191575615876046568450387900129332667805107942346985929 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/17.rv_timer_random_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_stress_all_with_rand_reset 69484096830520937692514234959667667785761122269439622314813211604615684018772 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/17.rv_timer_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3447837268 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/17.rv_timer_stress_all_with_rand_reset.3447837268 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 17.rv_timer_stress_all_with_rand_reset.3447837268 -covoverwrite' seed=69484096830520937692514234959667667785761122269439622314813211604615684018772 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69484096830520937692514234959667667785761122269439622314813211604615684018772 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/17.rv_timer_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_errors 96600952487788744432732325236324562398263640005502555722497684058109257614717 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/17.rv_timer_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4083844477 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/17.rv_timer_tl_errors.4083844477 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 17.rv_timer_tl_errors.4083844477 -covoverwrite' seed=96600952487788744432732325236324562398263640005502555722497684058109257614717 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96600952487788744432732325236324562398263640005502555722497684058109257614717 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/17.rv_timer_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_intg_err 94449990281558277417563319782082700306566119593283605025606930313908961073869 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/17.rv_timer_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1788009165 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/17.rv_timer_tl_intg_err.1788009165 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 17.rv_timer_tl_intg_err.1788009165 -covoverwrite' seed=94449990281558277417563319782082700306566119593283605025606930313908961073869 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94449990281558277417563319782082700306566119593283605025606930313908961073869 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/17.rv_timer_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random 21905836969560897263168158069886607943914502878717845153254596077475525748361 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/18.rv_timer_random/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=590014089 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/18.rv_timer_random.590014089 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 18.rv_timer_random.590014089 -covoverwrite' seed=21905836969560897263168158069886607943914502878717845153254596077475525748361 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21905836969560897263168158069886607943914502878717845153254596077475525748361 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/18.rv_timer_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_disabled 50675114488663106349002341807804368172160819088871191745913997104762755938828 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/18.rv_timer_disabled/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=103741964 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/18.rv_timer_disabled.103741964 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 18.rv_timer_disabled.103741964 -covoverwrite' seed=50675114488663106349002341807804368172160819088871191745913997104762755938828 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50675114488663106349002341807804368172160819088871191745913997104762755938828 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/18.rv_timer_disabled/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_disabled_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random_reset 54391147755062683129103938871406062698622116693144346156594799477211124037144 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/18.rv_timer_random_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=278492696 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/18.rv_timer_random_reset.278492696 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 18.rv_timer_random_reset.278492696 -covoverwrite' seed=54391147755062683129103938871406062698622116693144346156594799477211124037144 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54391147755062683129103938871406062698622116693144346156594799477211124037144 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/18.rv_timer_random_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_stress_all_with_rand_reset 69025477555751594642338575827662574835757009074736878521221330993490437199371 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/18.rv_timer_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=2943211019 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/18.rv_timer_stress_all_with_rand_reset.2943211019 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 18.rv_timer_stress_all_with_rand_reset.2943211019 -covoverwrite' seed=69025477555751594642338575827662574835757009074736878521221330993490437199371 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69025477555751594642338575827662574835757009074736878521221330993490437199371 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/18.rv_timer_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_errors 111338112871675731666267446995891445853836870671333198162110702051813537935968 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/18.rv_timer_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2081485408 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/18.rv_timer_tl_errors.2081485408 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 18.rv_timer_tl_errors.2081485408 -covoverwrite' seed=111338112871675731666267446995891445853836870671333198162110702051813537935968 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111338112871675731666267446995891445853836870671333198162110702051813537935968 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/18.rv_timer_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_intg_err 34363914091295223656239045787585557052740946582892211464995707705655021402230 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/18.rv_timer_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3686922358 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/18.rv_timer_tl_intg_err.3686922358 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 18.rv_timer_tl_intg_err.3686922358 -covoverwrite' seed=34363914091295223656239045787585557052740946582892211464995707705655021402230 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34363914091295223656239045787585557052740946582892211464995707705655021402230 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/18.rv_timer_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random 89679937481830980960440561305836220160818468165531528859016666270342990431506 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/19.rv_timer_random/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3480388882 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/19.rv_timer_random.3480388882 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 19.rv_timer_random.3480388882 -covoverwrite' seed=89679937481830980960440561305836220160818468165531528859016666270342990431506 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89679937481830980960440561305836220160818468165531528859016666270342990431506 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/19.rv_timer_random/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_disabled 75220632649615596055794224133307249487769297556280552587910386630054931933929 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/19.rv_timer_disabled/latest run_opts='+test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=4060949225 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_disabled_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/19.rv_timer_disabled.4060949225 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 19.rv_timer_disabled.4060949225 -covoverwrite' seed=75220632649615596055794224133307249487769297556280552587910386630054931933929 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75220632649615596055794224133307249487769297556280552587910386630054931933929 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/19.rv_timer_disabled/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_disabled_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_random_reset 53273462399145338606106445115742237908030887735251964220533841521388612602402 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/19.rv_timer_random_reset/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=3755592226 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_random_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/19.rv_timer_random_reset.3755592226 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 19.rv_timer_random_reset.3755592226 -covoverwrite' seed=53273462399145338606106445115742237908030887735251964220533841521388612602402 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53273462399145338606106445115742237908030887735251964220533841521388612602402 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/19.rv_timer_random_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_random_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_stress_all_with_rand_reset 33994093384483566493455086574675702165138676274475163754880818083164994512951 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/19.rv_timer_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=rv_timer_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/default/xcelium.d -r tb +SVSEED=1949935671 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/default/19.rv_timer_stress_all_with_rand_reset.1949935671 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope default -covtest 19.rv_timer_stress_all_with_rand_reset.1949935671 -covoverwrite' seed=33994093384483566493455086574675702165138676274475163754880818083164994512951 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33994093384483566493455086574675702165138676274475163754880818083164994512951 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/19.rv_timer_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_errors 567285831146763014765106375120130320332113826621519935631464964043469899258 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/19.rv_timer_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3845539322 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/19.rv_timer_tl_errors.3845539322 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 19.rv_timer_tl_errors.3845539322 -covoverwrite' seed=567285831146763014765106375120130320332113826621519935631464964043469899258 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=567285831146763014765106375120130320332113826621519935631464964043469899258 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/19.rv_timer_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_intg_err 90473085708338417355932997477163805609683651432066656791394853324224873660414 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/19.rv_timer_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1713143806 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/19.rv_timer_tl_intg_err.1713143806 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 19.rv_timer_tl_intg_err.1713143806 -covoverwrite' seed=90473085708338417355932997477163805609683651432066656791394853324224873660414 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90473085708338417355932997477163805609683651432066656791394853324224873660414 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/19.rv_timer_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_errors 38876140372474841117828906719744719396020566645831113657678029824201307293046 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/20.rv_timer_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=286885238 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/20.rv_timer_tl_errors.286885238 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 20.rv_timer_tl_errors.286885238 -covoverwrite' seed=38876140372474841117828906719744719396020566645831113657678029824201307293046 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38876140372474841117828906719744719396020566645831113657678029824201307293046 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/20.rv_timer_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_intg_err 62478809923078464659580205673663198975252807367697309706742112141734086715438 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/20.rv_timer_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4275316782 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/20.rv_timer_tl_intg_err.4275316782 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 20.rv_timer_tl_intg_err.4275316782 -covoverwrite' seed=62478809923078464659580205673663198975252807367697309706742112141734086715438 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62478809923078464659580205673663198975252807367697309706742112141734086715438 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/20.rv_timer_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_errors 83044305725858278552374459157570910727094330423567383509807039239899218484866 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/21.rv_timer_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3310132866 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/21.rv_timer_tl_errors.3310132866 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 21.rv_timer_tl_errors.3310132866 -covoverwrite' seed=83044305725858278552374459157570910727094330423567383509807039239899218484866 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83044305725858278552374459157570910727094330423567383509807039239899218484866 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/21.rv_timer_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_intg_err 41767914457837767062309885212934072133761206814145551813147868815551963486938 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/21.rv_timer_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3182058202 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/21.rv_timer_tl_intg_err.3182058202 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 21.rv_timer_tl_intg_err.3182058202 -covoverwrite' seed=41767914457837767062309885212934072133761206814145551813147868815551963486938 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41767914457837767062309885212934072133761206814145551813147868815551963486938 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/21.rv_timer_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_errors 18376861329511517017737934060331411461750890427387627771137898955470453474137 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/22.rv_timer_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2829714265 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/22.rv_timer_tl_errors.2829714265 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 22.rv_timer_tl_errors.2829714265 -covoverwrite' seed=18376861329511517017737934060331411461750890427387627771137898955470453474137 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18376861329511517017737934060331411461750890427387627771137898955470453474137 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/22.rv_timer_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_intg_err 36628101597909973537003663060993041066217884894390433968129572906618163217282 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/22.rv_timer_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=276480898 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/22.rv_timer_tl_intg_err.276480898 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 22.rv_timer_tl_intg_err.276480898 -covoverwrite' seed=36628101597909973537003663060993041066217884894390433968129572906618163217282 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36628101597909973537003663060993041066217884894390433968129572906618163217282 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/22.rv_timer_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_errors 82765628495238444727596928201875641831463707240189400396787634735188130290132 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/23.rv_timer_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=920541652 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/23.rv_timer_tl_errors.920541652 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 23.rv_timer_tl_errors.920541652 -covoverwrite' seed=82765628495238444727596928201875641831463707240189400396787634735188130290132 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82765628495238444727596928201875641831463707240189400396787634735188130290132 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/23.rv_timer_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_intg_err 53549528977124250113824023803146398050862930705986203454581560290456076297208 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/23.rv_timer_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3056346104 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/23.rv_timer_tl_intg_err.3056346104 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 23.rv_timer_tl_intg_err.3056346104 -covoverwrite' seed=53549528977124250113824023803146398050862930705986203454581560290456076297208 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53549528977124250113824023803146398050862930705986203454581560290456076297208 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/23.rv_timer_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_errors 86867005973970939574346677453476074697940389636699136521533981038653883645050 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/24.rv_timer_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3531439226 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/24.rv_timer_tl_errors.3531439226 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 24.rv_timer_tl_errors.3531439226 -covoverwrite' seed=86867005973970939574346677453476074697940389636699136521533981038653883645050 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86867005973970939574346677453476074697940389636699136521533981038653883645050 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/24.rv_timer_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
rv_timer_tl_intg_err 36835668316537913708513726966468803378061590913903360865634532004227771776382 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/24.rv_timer_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/rv_timer-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2409610622 +UVM_TESTNAME=rv_timer_base_test +UVM_TEST_SEQ=rv_timer_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage/cover_reg_top/24.rv_timer_tl_intg_err.2409610622 -covworkdir /nightly/current_run/scratch/master/rv_timer-sim-xcelium/coverage -covscope cover_reg_top -covtest 24.rv_timer_tl_intg_err.2409610622 -covoverwrite' seed=36835668316537913708513726966468803378061590913903360865634532004227771776382 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36835668316537913708513726966468803378061590913903360865634532004227771776382 --run-dir=/nightly/current_run/scratch/master/rv_timer-sim-xcelium/24.rv_timer_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=rv_timer_base_test uvm_test_seq=rv_timer_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
Job cancelled because one of its dependencies failed or was killed. 2 test runs
rv_timer None None
rv_timer None None
Job returned a non-zero exit code: * 1 test run
rv_timer None None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk cov_merge cov_merge_cmd=imc cov_merge_opts='-64bit -licqueue -exec /nightly/current_run/opentitan/hw/dv/tools/xcelium/cov_merge.tcl'
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:109: cov_merge] Error 126