Simulation Results: spi_host

 
28/08/2026 21:54:34 DVSim: v1.49.0 sha: a099412 json Branch: master Tool: xcelium [unknown]
Validation stages
V1
0.00%
V2
0.00%
V2S
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 0 10 0.00
spi_host_smoke 1.833s 0.000us 0 10 0.00
csr_hw_reset 0 1 0.00
spi_host_csr_hw_reset 0.892s 0.000us 0 1 0.00
csr_rw 0 5 0.00
spi_host_csr_rw 1.366s 0.000us 0 5 0.00
csr_bit_bash 0 1 0.00
spi_host_csr_bit_bash 0.713s 0.000us 0 1 0.00
csr_aliasing 0 1 0.00
spi_host_csr_aliasing 0.880s 0.000us 0 1 0.00
csr_mem_rw_with_rand_reset 0 5 0.00
spi_host_csr_mem_rw_with_rand_reset 0.901s 0.000us 0 5 0.00
regwen_csr_and_corresponding_lockable_csr 0 6 0.00
spi_host_csr_rw 1.366s 0.000us 0 5 0.00
spi_host_csr_aliasing 0.880s 0.000us 0 1 0.00
mem_walk 0 1 0.00
spi_host_mem_walk 1.544s 0.000us 0 1 0.00
mem_partial_access 0 1 0.00
spi_host_mem_partial_access 0.834s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 0 10 0.00
spi_host_performance 0.868s 0.000us 0 10 0.00
error_event_intr 0 30 0.00
spi_host_overflow_underflow 1.530s 0.000us 0 10 0.00
spi_host_error_cmd 1.954s 0.000us 0 10 0.00
spi_host_event 0.846s 0.000us 0 10 0.00
clock_rate 0 10 0.00
spi_host_speed 0.875s 0.000us 0 10 0.00
speed 0 10 0.00
spi_host_speed 0.875s 0.000us 0 10 0.00
chip_select_timing 0 10 0.00
spi_host_speed 0.875s 0.000us 0 10 0.00
upper_range_clkdiv 0 5 0.00
spi_host_upper_range_clkdiv 0.885s 0.000us 0 5 0.00
sw_reset 0 10 0.00
spi_host_sw_reset 0.861s 0.000us 0 10 0.00
passthrough_mode 0 10 0.00
spi_host_passthrough_mode 0.878s 0.000us 0 10 0.00
cpol_cpha 0 10 0.00
spi_host_speed 0.875s 0.000us 0 10 0.00
full_cycle 0 10 0.00
spi_host_speed 0.875s 0.000us 0 10 0.00
duplex 0 10 0.00
spi_host_smoke 1.833s 0.000us 0 10 0.00
tx_rx_only 0 10 0.00
spi_host_smoke 1.833s 0.000us 0 10 0.00
stress_all 0 10 0.00
spi_host_stress_all 0.898s 0.000us 0 10 0.00
spien 0 10 0.00
spi_host_spien 0.855s 0.000us 0 10 0.00
stall 0 10 0.00
spi_host_status_stall 1.542s 0.000us 0 10 0.00
Idlecsbactive 0 10 0.00
spi_host_idlecsbactive 1.404s 0.000us 0 10 0.00
data_fifo_status 0 10 0.00
spi_host_overflow_underflow 1.530s 0.000us 0 10 0.00
alert_test 0 10 0.00
spi_host_alert_test 1.594s 0.000us 0 10 0.00
intr_test 0 10 0.00
spi_host_intr_test 1.525s 0.000us 0 10 0.00
tl_d_oob_addr_access 0 25 0.00
spi_host_tl_errors 1.627s 0.000us 0 25 0.00
tl_d_illegal_access 0 25 0.00
spi_host_tl_errors 1.627s 0.000us 0 25 0.00
tl_d_outstanding_access 0 12 0.00
spi_host_csr_hw_reset 0.892s 0.000us 0 1 0.00
spi_host_csr_rw 1.366s 0.000us 0 5 0.00
spi_host_csr_aliasing 0.880s 0.000us 0 1 0.00
spi_host_same_csr_outstanding 0.882s 0.000us 0 5 0.00
tl_d_partial_access 0 12 0.00
spi_host_csr_hw_reset 0.892s 0.000us 0 1 0.00
spi_host_csr_rw 1.366s 0.000us 0 5 0.00
spi_host_csr_aliasing 0.880s 0.000us 0 1 0.00
spi_host_same_csr_outstanding 0.882s 0.000us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 30 0.00
spi_host_tl_intg_err 2.115s 0.000us 0 25 0.00
spi_host_sec_cm 0.855s 0.000us 0 5 0.00
sec_cm_bus_integrity 0 25 0.00
spi_host_tl_intg_err 2.115s 0.000us 0 25 0.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 220 test runs
spi_host_smoke 19522243938388495883970502417600032180084218379851337231889815208259963883948 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=4139815340 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/0.spi_host_smoke.4139815340 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 0.spi_host_smoke.4139815340 -covoverwrite' seed=19522243938388495883970502417600032180084218379851337231889815208259963883948 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19522243938388495883970502417600032180084218379851337231889815208259963883948 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_speed 76564229219579971626876016956114059191157740118576385269816296917629884422916 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_speed/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=4272937732 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_speed_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/0.spi_host_speed.4272937732 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 0.spi_host_speed.4272937732 -covoverwrite' seed=76564229219579971626876016956114059191157740118576385269816296917629884422916 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76564229219579971626876016956114059191157740118576385269816296917629884422916 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_speed/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_speed_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_upper_range_clkdiv 35059560774987952025147814174411361879896102728415128022666110047140031377579 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=2785423531 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_upper_range_clkdiv_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/0.spi_host_upper_range_clkdiv.2785423531 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 0.spi_host_upper_range_clkdiv.2785423531 -covoverwrite' seed=35059560774987952025147814174411361879896102728415128022666110047140031377579 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35059560774987952025147814174411361879896102728415128022666110047140031377579 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_upper_range_clkdiv/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_upper_range_clkdiv_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_performance 89430607298935899046248862792199475887822418744301210068040848350686315979363 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_performance/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=2062721635 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_performance_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/0.spi_host_performance.2062721635 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 0.spi_host_performance.2062721635 -covoverwrite' seed=89430607298935899046248862792199475887822418744301210068040848350686315979363 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89430607298935899046248862792199475887822418744301210068040848350686315979363 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_performance/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_performance_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_sw_reset 36102640390304850678462390494834293576913451518831839777759802367597750762169 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_sw_reset/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=2001975993 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_sw_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/0.spi_host_sw_reset.2001975993 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 0.spi_host_sw_reset.2001975993 -covoverwrite' seed=36102640390304850678462390494834293576913451518831839777759802367597750762169 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36102640390304850678462390494834293576913451518831839777759802367597750762169 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_sw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_sw_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_overflow_underflow 80054993011420150364228416735176354522788338915168363363111231138442910020764 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_overflow_underflow/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=4224890012 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_overflow_underflow_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/0.spi_host_overflow_underflow.4224890012 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 0.spi_host_overflow_underflow.4224890012 -covoverwrite' seed=80054993011420150364228416735176354522788338915168363363111231138442910020764 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80054993011420150364228416735176354522788338915168363363111231138442910020764 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_overflow_underflow/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_overflow_underflow_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_error_cmd 20322282230997124368598279055445365086947907995178842766277725911496293403916 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_error_cmd/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=3336883468 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_error_cmd_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/0.spi_host_error_cmd.3336883468 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 0.spi_host_error_cmd.3336883468 -covoverwrite' seed=20322282230997124368598279055445365086947907995178842766277725911496293403916 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20322282230997124368598279055445365086947907995178842766277725911496293403916 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_error_cmd/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_error_cmd_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_event 71828934453617158650587934828048020657586855447765878842248445303351410948835 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_event/latest run_opts='+en_scb=0 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=2269379299 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_event_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/0.spi_host_event.2269379299 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 0.spi_host_event.2269379299 -covoverwrite' seed=71828934453617158650587934828048020657586855447765878842248445303351410948835 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71828934453617158650587934828048020657586855447765878842248445303351410948835 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_event/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_event_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_passthrough_mode 40246244754788325773390802035609554237261361349203993258209673955882914293134 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_passthrough_mode/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=3259508110 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_passthrough_mode_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/0.spi_host_passthrough_mode.3259508110 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 0.spi_host_passthrough_mode.3259508110 -covoverwrite' seed=40246244754788325773390802035609554237261361349203993258209673955882914293134 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40246244754788325773390802035609554237261361349203993258209673955882914293134 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_passthrough_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_passthrough_mode_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_status_stall 23698371309198322504891697100723093177432728361305435225225855380274452828188 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_status_stall/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=3810988060 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_status_stall_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/0.spi_host_status_stall.3810988060 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 0.spi_host_status_stall.3810988060 -covoverwrite' seed=23698371309198322504891697100723093177432728361305435225225855380274452828188 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23698371309198322504891697100723093177432728361305435225225855380274452828188 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_status_stall/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_status_stall_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_idlecsbactive 72966503521565641325299785011237261221696056261790330866854606559306608446561 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_idlecsbactive/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=7507041 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_idlecsbactive_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/0.spi_host_idlecsbactive.7507041 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 0.spi_host_idlecsbactive.7507041 -covoverwrite' seed=72966503521565641325299785011237261221696056261790330866854606559306608446561 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72966503521565641325299785011237261221696056261790330866854606559306608446561 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_idlecsbactive/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_idlecsbactive_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_stress_all 34332988126352689632914732764078148461358410172875457283512580332806849313479 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_stress_all/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=933378759 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/0.spi_host_stress_all.933378759 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 0.spi_host_stress_all.933378759 -covoverwrite' seed=34332988126352689632914732764078148461358410172875457283512580332806849313479 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34332988126352689632914732764078148461358410172875457283512580332806849313479 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_spien 12755650304495961482106170937989059270734594135640381056475371108004532760904 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_spien/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=906408264 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_spien_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/0.spi_host_spien.906408264 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 0.spi_host_spien.906408264 -covoverwrite' seed=12755650304495961482106170937989059270734594135640381056475371108004532760904 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12755650304495961482106170937989059270734594135640381056475371108004532760904 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_spien/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_spien_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_errors 82037835714448058262128467663126178371907776908119957782596766625873952106940 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=588900796 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/0.spi_host_tl_errors.588900796 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.spi_host_tl_errors.588900796 -covoverwrite' seed=82037835714448058262128467663126178371907776908119957782596766625873952106940 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82037835714448058262128467663126178371907776908119957782596766625873952106940 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_intg_err 13920016402530729727032577422966919216743409028359515589412372055173408187323 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1441227707 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/0.spi_host_tl_intg_err.1441227707 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.spi_host_tl_intg_err.1441227707 -covoverwrite' seed=13920016402530729727032577422966919216743409028359515589412372055173408187323 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13920016402530729727032577422966919216743409028359515589412372055173408187323 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_sec_cm 103332415350511067494151951174339550059555769342882963852167370417372172052287 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=3232687935 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/0.spi_host_sec_cm.3232687935 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 0.spi_host_sec_cm.3232687935 -covoverwrite' seed=103332415350511067494151951174339550059555769342882963852167370417372172052287 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103332415350511067494151951174339550059555769342882963852167370417372172052287 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_intr_test 15207746038541561837055201920550174308967190193837818208354674343100478170267 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3036980379 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/0.spi_host_intr_test.3036980379 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.spi_host_intr_test.3036980379 -covoverwrite' seed=15207746038541561837055201920550174308967190193837818208354674343100478170267 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15207746038541561837055201920550174308967190193837818208354674343100478170267 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_alert_test 12917008419549448463908075194949065585886150599913729010748377461463134716849 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=3590013873 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/0.spi_host_alert_test.3590013873 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 0.spi_host_alert_test.3590013873 -covoverwrite' seed=12917008419549448463908075194949065585886150599913729010748377461463134716849 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12917008419549448463908075194949065585886150599913729010748377461463134716849 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_mem_walk 7592631163830636398654963346341770127335919109335264373581165279638803754018 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_mem_walk/latest run_opts='+csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3566513186 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/0.spi_host_mem_walk.3566513186 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.spi_host_mem_walk.3566513186 -covoverwrite' seed=7592631163830636398654963346341770127335919109335264373581165279638803754018 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7592631163830636398654963346341770127335919109335264373581165279638803754018 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_mem_walk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_mem_partial_access 27714063957914684315484002426698398748435359076345745602118240626224970244403 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_mem_partial_access/latest run_opts='+run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3025576243 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/0.spi_host_mem_partial_access.3025576243 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.spi_host_mem_partial_access.3025576243 -covoverwrite' seed=27714063957914684315484002426698398748435359076345745602118240626224970244403 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27714063957914684315484002426698398748435359076345745602118240626224970244403 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_mem_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_csr_hw_reset 30806672208472711170640599744234733065844468144091923548507213485474690586814 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_csr_hw_reset/latest run_opts='+csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2150586558 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/0.spi_host_csr_hw_reset.2150586558 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.spi_host_csr_hw_reset.2150586558 -covoverwrite' seed=30806672208472711170640599744234733065844468144091923548507213485474690586814 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30806672208472711170640599744234733065844468144091923548507213485474690586814 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_csr_rw 59348831275402669060002194488500744500492359421910951898341977674659504224835 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=773487171 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/0.spi_host_csr_rw.773487171 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.spi_host_csr_rw.773487171 -covoverwrite' seed=59348831275402669060002194488500744500492359421910951898341977674659504224835 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=59348831275402669060002194488500744500492359421910951898341977674659504224835 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_csr_bit_bash 60276745149410445352694298703126417882376333496133337341368776273179179731074 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_csr_bit_bash/latest run_opts='+csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2576074882 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/0.spi_host_csr_bit_bash.2576074882 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.spi_host_csr_bit_bash.2576074882 -covoverwrite' seed=60276745149410445352694298703126417882376333496133337341368776273179179731074 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60276745149410445352694298703126417882376333496133337341368776273179179731074 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_csr_aliasing 12784578826933994767200664634624215614046900780937786981199249925608942370083 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_csr_aliasing/latest run_opts='+csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=421821731 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/0.spi_host_csr_aliasing.421821731 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.spi_host_csr_aliasing.421821731 -covoverwrite' seed=12784578826933994767200664634624215614046900780937786981199249925608942370083 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12784578826933994767200664634624215614046900780937786981199249925608942370083 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_same_csr_outstanding 61271211587232029322331009992709297936666785100602368002985609831889261241097 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=421733129 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/0.spi_host_same_csr_outstanding.421733129 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.spi_host_same_csr_outstanding.421733129 -covoverwrite' seed=61271211587232029322331009992709297936666785100602368002985609831889261241097 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61271211587232029322331009992709297936666785100602368002985609831889261241097 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_csr_mem_rw_with_rand_reset 62613075474990215815897124356350253006834272536081413491692922098611774492142 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3873639918 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/0.spi_host_csr_mem_rw_with_rand_reset.3873639918 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.spi_host_csr_mem_rw_with_rand_reset.3873639918 -covoverwrite' seed=62613075474990215815897124356350253006834272536081413491692922098611774492142 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62613075474990215815897124356350253006834272536081413491692922098611774492142 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_smoke 73643065101486808334168861330614962305907656095768232522236039951408482942894 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=290914222 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/1.spi_host_smoke.290914222 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 1.spi_host_smoke.290914222 -covoverwrite' seed=73643065101486808334168861330614962305907656095768232522236039951408482942894 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73643065101486808334168861330614962305907656095768232522236039951408482942894 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_speed 61819328170116172698189140770804201673484513364957072614673417675436044758710 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_speed/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=780054198 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_speed_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/1.spi_host_speed.780054198 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 1.spi_host_speed.780054198 -covoverwrite' seed=61819328170116172698189140770804201673484513364957072614673417675436044758710 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61819328170116172698189140770804201673484513364957072614673417675436044758710 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_speed/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_speed_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_upper_range_clkdiv 19381366258873774950025558744323301050533866893876524189587724645254126617930 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=3402614090 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_upper_range_clkdiv_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/1.spi_host_upper_range_clkdiv.3402614090 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 1.spi_host_upper_range_clkdiv.3402614090 -covoverwrite' seed=19381366258873774950025558744323301050533866893876524189587724645254126617930 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19381366258873774950025558744323301050533866893876524189587724645254126617930 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_upper_range_clkdiv/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_upper_range_clkdiv_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_performance 24922485673681499817202062510939360400738864388610333010924959516915066277428 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_performance/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=179375668 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_performance_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/1.spi_host_performance.179375668 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 1.spi_host_performance.179375668 -covoverwrite' seed=24922485673681499817202062510939360400738864388610333010924959516915066277428 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24922485673681499817202062510939360400738864388610333010924959516915066277428 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_performance/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_performance_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_sw_reset 100097112960424448217812589011326678473248320775045268047115492037374952330147 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_sw_reset/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=3683373987 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_sw_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/1.spi_host_sw_reset.3683373987 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 1.spi_host_sw_reset.3683373987 -covoverwrite' seed=100097112960424448217812589011326678473248320775045268047115492037374952330147 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100097112960424448217812589011326678473248320775045268047115492037374952330147 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_sw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_sw_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_overflow_underflow 91696051456242693612047446154919879409584535482816711030888204328531108883911 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_overflow_underflow/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=1255730631 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_overflow_underflow_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/1.spi_host_overflow_underflow.1255730631 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 1.spi_host_overflow_underflow.1255730631 -covoverwrite' seed=91696051456242693612047446154919879409584535482816711030888204328531108883911 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91696051456242693612047446154919879409584535482816711030888204328531108883911 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_overflow_underflow/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_overflow_underflow_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_error_cmd 74792077872754683729488737166880433742163902261000054407040201998444647108971 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_error_cmd/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=811553131 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_error_cmd_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/1.spi_host_error_cmd.811553131 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 1.spi_host_error_cmd.811553131 -covoverwrite' seed=74792077872754683729488737166880433742163902261000054407040201998444647108971 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74792077872754683729488737166880433742163902261000054407040201998444647108971 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_error_cmd/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_error_cmd_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_event 100338969235718798948545012803260216530665526214706482856672552678811709946504 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_event/latest run_opts='+en_scb=0 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=3059432072 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_event_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/1.spi_host_event.3059432072 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 1.spi_host_event.3059432072 -covoverwrite' seed=100338969235718798948545012803260216530665526214706482856672552678811709946504 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100338969235718798948545012803260216530665526214706482856672552678811709946504 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_event/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_event_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_passthrough_mode 87557752959020577826348085472973599123619561009659781945868137958799535385149 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_passthrough_mode/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=413280829 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_passthrough_mode_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/1.spi_host_passthrough_mode.413280829 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 1.spi_host_passthrough_mode.413280829 -covoverwrite' seed=87557752959020577826348085472973599123619561009659781945868137958799535385149 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87557752959020577826348085472973599123619561009659781945868137958799535385149 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_passthrough_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_passthrough_mode_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_status_stall 105836168689650894163473318453029441192715551374248632017100555370423013859007 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_status_stall/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=4063223487 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_status_stall_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/1.spi_host_status_stall.4063223487 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 1.spi_host_status_stall.4063223487 -covoverwrite' seed=105836168689650894163473318453029441192715551374248632017100555370423013859007 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105836168689650894163473318453029441192715551374248632017100555370423013859007 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_status_stall/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_status_stall_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_idlecsbactive 82766034349884776696593736321915606008619058634620579357934875515139011911929 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_idlecsbactive/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=121643257 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_idlecsbactive_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/1.spi_host_idlecsbactive.121643257 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 1.spi_host_idlecsbactive.121643257 -covoverwrite' seed=82766034349884776696593736321915606008619058634620579357934875515139011911929 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82766034349884776696593736321915606008619058634620579357934875515139011911929 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_idlecsbactive/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_idlecsbactive_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_stress_all 41847924933574026423029496125144830225140228015345089859493355589398152865250 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_stress_all/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=843048418 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/1.spi_host_stress_all.843048418 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 1.spi_host_stress_all.843048418 -covoverwrite' seed=41847924933574026423029496125144830225140228015345089859493355589398152865250 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41847924933574026423029496125144830225140228015345089859493355589398152865250 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_spien 64760719669447318459472968871630033229143355468443114199155386167165332316014 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_spien/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=997810030 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_spien_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/1.spi_host_spien.997810030 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 1.spi_host_spien.997810030 -covoverwrite' seed=64760719669447318459472968871630033229143355468443114199155386167165332316014 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64760719669447318459472968871630033229143355468443114199155386167165332316014 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_spien/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_spien_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_errors 41847933036523110729362918117571267118647964590547471677917349253397915073137 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=883391089 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/1.spi_host_tl_errors.883391089 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.spi_host_tl_errors.883391089 -covoverwrite' seed=41847933036523110729362918117571267118647964590547471677917349253397915073137 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41847933036523110729362918117571267118647964590547471677917349253397915073137 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_intg_err 98643628316752083480946105692550871617089269413313283029388994957346074032240 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=437811312 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/1.spi_host_tl_intg_err.437811312 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.spi_host_tl_intg_err.437811312 -covoverwrite' seed=98643628316752083480946105692550871617089269413313283029388994957346074032240 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98643628316752083480946105692550871617089269413313283029388994957346074032240 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_sec_cm 68078700738045192544969606579116919181112711668065720425996813207786257596933 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=3710337541 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/1.spi_host_sec_cm.3710337541 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 1.spi_host_sec_cm.3710337541 -covoverwrite' seed=68078700738045192544969606579116919181112711668065720425996813207786257596933 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68078700738045192544969606579116919181112711668065720425996813207786257596933 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_intr_test 70955617225673092387891758845455697621132829140926140021815292976838514575203 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1234175843 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/1.spi_host_intr_test.1234175843 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.spi_host_intr_test.1234175843 -covoverwrite' seed=70955617225673092387891758845455697621132829140926140021815292976838514575203 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70955617225673092387891758845455697621132829140926140021815292976838514575203 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_alert_test 48604783960263673698809307646692087720235182232243511798943946266241861360871 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=1345527015 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/1.spi_host_alert_test.1345527015 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 1.spi_host_alert_test.1345527015 -covoverwrite' seed=48604783960263673698809307646692087720235182232243511798943946266241861360871 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48604783960263673698809307646692087720235182232243511798943946266241861360871 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_csr_rw 27486033751285618256635418818520580229205843828813262264286648367098855361655 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=403377271 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/1.spi_host_csr_rw.403377271 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.spi_host_csr_rw.403377271 -covoverwrite' seed=27486033751285618256635418818520580229205843828813262264286648367098855361655 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27486033751285618256635418818520580229205843828813262264286648367098855361655 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_same_csr_outstanding 96867219636497463021602259196710290031537445929349827297273887767902462224051 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2441422515 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/1.spi_host_same_csr_outstanding.2441422515 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.spi_host_same_csr_outstanding.2441422515 -covoverwrite' seed=96867219636497463021602259196710290031537445929349827297273887767902462224051 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96867219636497463021602259196710290031537445929349827297273887767902462224051 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_csr_mem_rw_with_rand_reset 80397402561945378500283580520138460137947728400749381199234079047999373915809 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=128661153 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/1.spi_host_csr_mem_rw_with_rand_reset.128661153 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.spi_host_csr_mem_rw_with_rand_reset.128661153 -covoverwrite' seed=80397402561945378500283580520138460137947728400749381199234079047999373915809 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80397402561945378500283580520138460137947728400749381199234079047999373915809 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/1.spi_host_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_smoke 112790860041143820695345543616250711696551720612603998833427291345900004516608 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=620045056 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/2.spi_host_smoke.620045056 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 2.spi_host_smoke.620045056 -covoverwrite' seed=112790860041143820695345543616250711696551720612603998833427291345900004516608 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112790860041143820695345543616250711696551720612603998833427291345900004516608 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_speed 50011483801688039756312872895284438286093915061076586002639997759259236854335 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_speed/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=3288820287 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_speed_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/2.spi_host_speed.3288820287 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 2.spi_host_speed.3288820287 -covoverwrite' seed=50011483801688039756312872895284438286093915061076586002639997759259236854335 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50011483801688039756312872895284438286093915061076586002639997759259236854335 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_speed/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_speed_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_upper_range_clkdiv 55545244003676998981353128110383242256408581678000333006518835042570695783897 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=264156633 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_upper_range_clkdiv_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/2.spi_host_upper_range_clkdiv.264156633 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 2.spi_host_upper_range_clkdiv.264156633 -covoverwrite' seed=55545244003676998981353128110383242256408581678000333006518835042570695783897 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55545244003676998981353128110383242256408581678000333006518835042570695783897 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_upper_range_clkdiv/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_upper_range_clkdiv_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_performance 101854608644726338225275135434750103083543189720676345335535652781163012792177 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_performance/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=399351665 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_performance_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/2.spi_host_performance.399351665 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 2.spi_host_performance.399351665 -covoverwrite' seed=101854608644726338225275135434750103083543189720676345335535652781163012792177 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101854608644726338225275135434750103083543189720676345335535652781163012792177 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_performance/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_performance_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_sw_reset 85707073242335736150899621199660052202740065586222057770756608514669805343540 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_sw_reset/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=3085734708 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_sw_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/2.spi_host_sw_reset.3085734708 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 2.spi_host_sw_reset.3085734708 -covoverwrite' seed=85707073242335736150899621199660052202740065586222057770756608514669805343540 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85707073242335736150899621199660052202740065586222057770756608514669805343540 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_sw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_sw_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_overflow_underflow 78453364848183998041255997094194431656329591820503359748020927905119850594288 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_overflow_underflow/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=2084962288 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_overflow_underflow_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/2.spi_host_overflow_underflow.2084962288 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 2.spi_host_overflow_underflow.2084962288 -covoverwrite' seed=78453364848183998041255997094194431656329591820503359748020927905119850594288 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78453364848183998041255997094194431656329591820503359748020927905119850594288 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_overflow_underflow/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_overflow_underflow_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_error_cmd 42710884834520013147888745371370323637274361759332359954906026491131548344031 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_error_cmd/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=2764775135 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_error_cmd_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/2.spi_host_error_cmd.2764775135 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 2.spi_host_error_cmd.2764775135 -covoverwrite' seed=42710884834520013147888745371370323637274361759332359954906026491131548344031 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42710884834520013147888745371370323637274361759332359954906026491131548344031 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_error_cmd/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_error_cmd_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_event 100396237590245056768569247123651092971026411000795840786442387622712098101514 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_event/latest run_opts='+en_scb=0 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=3613595914 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_event_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/2.spi_host_event.3613595914 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 2.spi_host_event.3613595914 -covoverwrite' seed=100396237590245056768569247123651092971026411000795840786442387622712098101514 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100396237590245056768569247123651092971026411000795840786442387622712098101514 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_event/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_event_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_passthrough_mode 79516529220410026423299241647475480251049283779378851784522419723020555372837 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_passthrough_mode/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=2804533541 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_passthrough_mode_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/2.spi_host_passthrough_mode.2804533541 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 2.spi_host_passthrough_mode.2804533541 -covoverwrite' seed=79516529220410026423299241647475480251049283779378851784522419723020555372837 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79516529220410026423299241647475480251049283779378851784522419723020555372837 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_passthrough_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_passthrough_mode_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_status_stall 75661054522439030971561588975497539849314455416396930261831181388921747676772 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_status_stall/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=2142379620 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_status_stall_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/2.spi_host_status_stall.2142379620 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 2.spi_host_status_stall.2142379620 -covoverwrite' seed=75661054522439030971561588975497539849314455416396930261831181388921747676772 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75661054522439030971561588975497539849314455416396930261831181388921747676772 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_status_stall/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_status_stall_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_idlecsbactive 30612480840944667531262423960374737417857826837404216436168497503064162633594 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_idlecsbactive/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=3761571706 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_idlecsbactive_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/2.spi_host_idlecsbactive.3761571706 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 2.spi_host_idlecsbactive.3761571706 -covoverwrite' seed=30612480840944667531262423960374737417857826837404216436168497503064162633594 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30612480840944667531262423960374737417857826837404216436168497503064162633594 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_idlecsbactive/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_idlecsbactive_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_stress_all 81710074115227018921883661518404489464066265885288747893035798277588737065370 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_stress_all/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=1319109018 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/2.spi_host_stress_all.1319109018 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 2.spi_host_stress_all.1319109018 -covoverwrite' seed=81710074115227018921883661518404489464066265885288747893035798277588737065370 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81710074115227018921883661518404489464066265885288747893035798277588737065370 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_spien 87467377804880200677619335029233995488343884392333635388604827080552424438349 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_spien/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=3713301069 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_spien_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/2.spi_host_spien.3713301069 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 2.spi_host_spien.3713301069 -covoverwrite' seed=87467377804880200677619335029233995488343884392333635388604827080552424438349 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87467377804880200677619335029233995488343884392333635388604827080552424438349 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_spien/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_spien_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_errors 59756633181438531569314083912836184696412241262043922189837184613846712752271 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3120732303 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/2.spi_host_tl_errors.3120732303 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.spi_host_tl_errors.3120732303 -covoverwrite' seed=59756633181438531569314083912836184696412241262043922189837184613846712752271 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=59756633181438531569314083912836184696412241262043922189837184613846712752271 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_intg_err 21732307894996160872077592184873855387817766730083844731826068288703106237126 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=39436998 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/2.spi_host_tl_intg_err.39436998 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.spi_host_tl_intg_err.39436998 -covoverwrite' seed=21732307894996160872077592184873855387817766730083844731826068288703106237126 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21732307894996160872077592184873855387817766730083844731826068288703106237126 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_sec_cm 111470928110760961597765832156946668091228869150240699890943851692907174231336 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=4067622184 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/2.spi_host_sec_cm.4067622184 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 2.spi_host_sec_cm.4067622184 -covoverwrite' seed=111470928110760961597765832156946668091228869150240699890943851692907174231336 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111470928110760961597765832156946668091228869150240699890943851692907174231336 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_intr_test 105586758317240022274333198868528748889994576835822603316532486517284749149488 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=585073968 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/2.spi_host_intr_test.585073968 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.spi_host_intr_test.585073968 -covoverwrite' seed=105586758317240022274333198868528748889994576835822603316532486517284749149488 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105586758317240022274333198868528748889994576835822603316532486517284749149488 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_alert_test 100357903891796834606008889968976398265051613561400710587394436513374962714419 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=1831077683 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/2.spi_host_alert_test.1831077683 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 2.spi_host_alert_test.1831077683 -covoverwrite' seed=100357903891796834606008889968976398265051613561400710587394436513374962714419 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100357903891796834606008889968976398265051613561400710587394436513374962714419 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_csr_rw 12790792854189863660733487478026712382951814119417275128443741876546998220666 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2282862458 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/2.spi_host_csr_rw.2282862458 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.spi_host_csr_rw.2282862458 -covoverwrite' seed=12790792854189863660733487478026712382951814119417275128443741876546998220666 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12790792854189863660733487478026712382951814119417275128443741876546998220666 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_same_csr_outstanding 38652007366282954462734232898695607680065572337185525074380634326101379197749 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1613179701 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/2.spi_host_same_csr_outstanding.1613179701 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.spi_host_same_csr_outstanding.1613179701 -covoverwrite' seed=38652007366282954462734232898695607680065572337185525074380634326101379197749 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38652007366282954462734232898695607680065572337185525074380634326101379197749 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_csr_mem_rw_with_rand_reset 112013773554769564456276476902991929292077021121737928023725635548280611712685 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=369929901 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/2.spi_host_csr_mem_rw_with_rand_reset.369929901 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.spi_host_csr_mem_rw_with_rand_reset.369929901 -covoverwrite' seed=112013773554769564456276476902991929292077021121737928023725635548280611712685 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112013773554769564456276476902991929292077021121737928023725635548280611712685 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/2.spi_host_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_smoke 67119388031809551181442510608653080287174861035110467996747447957835792339504 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=4144845360 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/3.spi_host_smoke.4144845360 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 3.spi_host_smoke.4144845360 -covoverwrite' seed=67119388031809551181442510608653080287174861035110467996747447957835792339504 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67119388031809551181442510608653080287174861035110467996747447957835792339504 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_speed 92949317453862098226554657320681766340248483278418301691115015729788228969500 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_speed/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=1888723996 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_speed_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/3.spi_host_speed.1888723996 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 3.spi_host_speed.1888723996 -covoverwrite' seed=92949317453862098226554657320681766340248483278418301691115015729788228969500 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92949317453862098226554657320681766340248483278418301691115015729788228969500 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_speed/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_speed_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_upper_range_clkdiv 92514351666150142855699059379214968151593556219525958516069691469572386648684 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_upper_range_clkdiv/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=2039280236 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_upper_range_clkdiv_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/3.spi_host_upper_range_clkdiv.2039280236 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 3.spi_host_upper_range_clkdiv.2039280236 -covoverwrite' seed=92514351666150142855699059379214968151593556219525958516069691469572386648684 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92514351666150142855699059379214968151593556219525958516069691469572386648684 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_upper_range_clkdiv/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_upper_range_clkdiv_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_performance 39857737969904640439861660297652706353174373839423084071266254478832683921678 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_performance/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=21180686 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_performance_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/3.spi_host_performance.21180686 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 3.spi_host_performance.21180686 -covoverwrite' seed=39857737969904640439861660297652706353174373839423084071266254478832683921678 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39857737969904640439861660297652706353174373839423084071266254478832683921678 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_performance/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_performance_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_sw_reset 10806170365178031120302955462271873197998264661772643178297586026289304837650 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_sw_reset/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=1683103250 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_sw_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/3.spi_host_sw_reset.1683103250 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 3.spi_host_sw_reset.1683103250 -covoverwrite' seed=10806170365178031120302955462271873197998264661772643178297586026289304837650 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10806170365178031120302955462271873197998264661772643178297586026289304837650 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_sw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_sw_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_overflow_underflow 87331391210028310941095061580856420548231590579989883214855042804376763468940 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_overflow_underflow/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=462261388 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_overflow_underflow_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/3.spi_host_overflow_underflow.462261388 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 3.spi_host_overflow_underflow.462261388 -covoverwrite' seed=87331391210028310941095061580856420548231590579989883214855042804376763468940 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87331391210028310941095061580856420548231590579989883214855042804376763468940 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_overflow_underflow/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_overflow_underflow_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_error_cmd 29926380556781611520721777370003870416367565240036628711679967806698056022392 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_error_cmd/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=1299937656 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_error_cmd_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/3.spi_host_error_cmd.1299937656 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 3.spi_host_error_cmd.1299937656 -covoverwrite' seed=29926380556781611520721777370003870416367565240036628711679967806698056022392 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29926380556781611520721777370003870416367565240036628711679967806698056022392 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_error_cmd/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_error_cmd_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_event 95851322019155019571543321167872781504275686147991424698562193613449482834856 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_event/latest run_opts='+en_scb=0 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=166826920 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_event_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/3.spi_host_event.166826920 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 3.spi_host_event.166826920 -covoverwrite' seed=95851322019155019571543321167872781504275686147991424698562193613449482834856 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95851322019155019571543321167872781504275686147991424698562193613449482834856 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_event/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_event_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_passthrough_mode 84855247780421588255621653178638414065690607671795764020412055288406897058895 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_passthrough_mode/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=3669746767 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_passthrough_mode_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/3.spi_host_passthrough_mode.3669746767 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 3.spi_host_passthrough_mode.3669746767 -covoverwrite' seed=84855247780421588255621653178638414065690607671795764020412055288406897058895 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84855247780421588255621653178638414065690607671795764020412055288406897058895 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_passthrough_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_passthrough_mode_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_status_stall 23027745751933499590464101091798790461384114831884527071312354431840120478465 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_status_stall/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=2260212481 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_status_stall_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/3.spi_host_status_stall.2260212481 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 3.spi_host_status_stall.2260212481 -covoverwrite' seed=23027745751933499590464101091798790461384114831884527071312354431840120478465 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23027745751933499590464101091798790461384114831884527071312354431840120478465 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_status_stall/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_status_stall_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_idlecsbactive 56005184421571504418438276960306173377167242833954032864722812105318608728524 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_idlecsbactive/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=1877537228 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_idlecsbactive_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/3.spi_host_idlecsbactive.1877537228 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 3.spi_host_idlecsbactive.1877537228 -covoverwrite' seed=56005184421571504418438276960306173377167242833954032864722812105318608728524 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56005184421571504418438276960306173377167242833954032864722812105318608728524 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_idlecsbactive/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_idlecsbactive_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_stress_all 72643958546676522489639133835178336101644793511168515250277125243181258934620 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_stress_all/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=3958278492 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/3.spi_host_stress_all.3958278492 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 3.spi_host_stress_all.3958278492 -covoverwrite' seed=72643958546676522489639133835178336101644793511168515250277125243181258934620 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72643958546676522489639133835178336101644793511168515250277125243181258934620 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_spien 99474541523097302791128953409271319683753122850905088719256557246627773424120 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_spien/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=2887262712 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_spien_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/3.spi_host_spien.2887262712 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 3.spi_host_spien.2887262712 -covoverwrite' seed=99474541523097302791128953409271319683753122850905088719256557246627773424120 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99474541523097302791128953409271319683753122850905088719256557246627773424120 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_spien/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_spien_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_errors 101093776376246942556894824772744886134318462607484092176490611580446317557218 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2780640738 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/3.spi_host_tl_errors.2780640738 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.spi_host_tl_errors.2780640738 -covoverwrite' seed=101093776376246942556894824772744886134318462607484092176490611580446317557218 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101093776376246942556894824772744886134318462607484092176490611580446317557218 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_intg_err 51889361678783841883473435318568373165490482487596666951294605324326398174080 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2216010624 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/3.spi_host_tl_intg_err.2216010624 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.spi_host_tl_intg_err.2216010624 -covoverwrite' seed=51889361678783841883473435318568373165490482487596666951294605324326398174080 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51889361678783841883473435318568373165490482487596666951294605324326398174080 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_sec_cm 99943280993568437629016691573015480835289430000422698546714237552381453383855 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=4164663471 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/3.spi_host_sec_cm.4164663471 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 3.spi_host_sec_cm.4164663471 -covoverwrite' seed=99943280993568437629016691573015480835289430000422698546714237552381453383855 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99943280993568437629016691573015480835289430000422698546714237552381453383855 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_intr_test 99912850956581283179365577111084389068569948594879285324690010788839911337326 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3447467374 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/3.spi_host_intr_test.3447467374 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.spi_host_intr_test.3447467374 -covoverwrite' seed=99912850956581283179365577111084389068569948594879285324690010788839911337326 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99912850956581283179365577111084389068569948594879285324690010788839911337326 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_alert_test 91957179724641690428473882533914726254417984940346548037093201694960385789887 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=2738622399 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/3.spi_host_alert_test.2738622399 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 3.spi_host_alert_test.2738622399 -covoverwrite' seed=91957179724641690428473882533914726254417984940346548037093201694960385789887 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91957179724641690428473882533914726254417984940346548037093201694960385789887 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_csr_rw 88738416816484562529693430571391385579982079162814103673405870708909148353434 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3412210586 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/3.spi_host_csr_rw.3412210586 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.spi_host_csr_rw.3412210586 -covoverwrite' seed=88738416816484562529693430571391385579982079162814103673405870708909148353434 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88738416816484562529693430571391385579982079162814103673405870708909148353434 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_same_csr_outstanding 48543778089348571468158825948084384221178905289331544702149210466480837061917 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1935633693 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/3.spi_host_same_csr_outstanding.1935633693 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.spi_host_same_csr_outstanding.1935633693 -covoverwrite' seed=48543778089348571468158825948084384221178905289331544702149210466480837061917 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48543778089348571468158825948084384221178905289331544702149210466480837061917 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_csr_mem_rw_with_rand_reset 33336759521564381755700918137561354729532019222025587620858473291513316860007 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=840786023 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/3.spi_host_csr_mem_rw_with_rand_reset.840786023 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.spi_host_csr_mem_rw_with_rand_reset.840786023 -covoverwrite' seed=33336759521564381755700918137561354729532019222025587620858473291513316860007 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33336759521564381755700918137561354729532019222025587620858473291513316860007 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/3.spi_host_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_smoke 18868623005850462569231221123812052106918549667378538312394956234171572440744 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=1133661864 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/4.spi_host_smoke.1133661864 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 4.spi_host_smoke.1133661864 -covoverwrite' seed=18868623005850462569231221123812052106918549667378538312394956234171572440744 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18868623005850462569231221123812052106918549667378538312394956234171572440744 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_speed 108209654461540641864702030067968926333543410471988460301794086303933863577537 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_speed/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=3538962369 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_speed_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/4.spi_host_speed.3538962369 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 4.spi_host_speed.3538962369 -covoverwrite' seed=108209654461540641864702030067968926333543410471988460301794086303933863577537 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108209654461540641864702030067968926333543410471988460301794086303933863577537 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_speed/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_speed_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_upper_range_clkdiv 51562588533774867406439833363360364387214230909583221036985658719770250196621 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_upper_range_clkdiv/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=193869453 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_upper_range_clkdiv_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/4.spi_host_upper_range_clkdiv.193869453 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 4.spi_host_upper_range_clkdiv.193869453 -covoverwrite' seed=51562588533774867406439833363360364387214230909583221036985658719770250196621 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51562588533774867406439833363360364387214230909583221036985658719770250196621 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_upper_range_clkdiv/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_upper_range_clkdiv_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_performance 5149278694078741278890439606920366321681232048520798904640386638933301010382 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_performance/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=1891508174 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_performance_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/4.spi_host_performance.1891508174 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 4.spi_host_performance.1891508174 -covoverwrite' seed=5149278694078741278890439606920366321681232048520798904640386638933301010382 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5149278694078741278890439606920366321681232048520798904640386638933301010382 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_performance/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_performance_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_sw_reset 65309979237839118876056317256705450340549414339601653998555132904185864519156 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_sw_reset/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=36306420 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_sw_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/4.spi_host_sw_reset.36306420 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 4.spi_host_sw_reset.36306420 -covoverwrite' seed=65309979237839118876056317256705450340549414339601653998555132904185864519156 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65309979237839118876056317256705450340549414339601653998555132904185864519156 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_sw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_sw_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_overflow_underflow 115095702753521067998883141008405517323156267186553385509399845451280288310901 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_overflow_underflow/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=376956533 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_overflow_underflow_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/4.spi_host_overflow_underflow.376956533 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 4.spi_host_overflow_underflow.376956533 -covoverwrite' seed=115095702753521067998883141008405517323156267186553385509399845451280288310901 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115095702753521067998883141008405517323156267186553385509399845451280288310901 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_overflow_underflow/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_overflow_underflow_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_error_cmd 77292943784882181062480445235162794839258966355433783937394783626256184927199 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_error_cmd/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=2870633439 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_error_cmd_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/4.spi_host_error_cmd.2870633439 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 4.spi_host_error_cmd.2870633439 -covoverwrite' seed=77292943784882181062480445235162794839258966355433783937394783626256184927199 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77292943784882181062480445235162794839258966355433783937394783626256184927199 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_error_cmd/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_error_cmd_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_event 20428165876920560088518675270508848150605765518960359688468920044530054197638 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_event/latest run_opts='+en_scb=0 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=3074158982 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_event_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/4.spi_host_event.3074158982 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 4.spi_host_event.3074158982 -covoverwrite' seed=20428165876920560088518675270508848150605765518960359688468920044530054197638 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20428165876920560088518675270508848150605765518960359688468920044530054197638 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_event/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_event_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_passthrough_mode 16155331622214761647553972185890792081214761171319985510362943919892152248289 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_passthrough_mode/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=2471552993 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_passthrough_mode_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/4.spi_host_passthrough_mode.2471552993 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 4.spi_host_passthrough_mode.2471552993 -covoverwrite' seed=16155331622214761647553972185890792081214761171319985510362943919892152248289 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16155331622214761647553972185890792081214761171319985510362943919892152248289 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_passthrough_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_passthrough_mode_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_status_stall 62111822071940144160152930212395134947115225854995288081671362710630730680391 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_status_stall/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=615630919 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_status_stall_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/4.spi_host_status_stall.615630919 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 4.spi_host_status_stall.615630919 -covoverwrite' seed=62111822071940144160152930212395134947115225854995288081671362710630730680391 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62111822071940144160152930212395134947115225854995288081671362710630730680391 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_status_stall/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_status_stall_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_idlecsbactive 17887482686457310376489625127926903582301565836051873644165894999048192679267 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_idlecsbactive/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=2764725603 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_idlecsbactive_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/4.spi_host_idlecsbactive.2764725603 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 4.spi_host_idlecsbactive.2764725603 -covoverwrite' seed=17887482686457310376489625127926903582301565836051873644165894999048192679267 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17887482686457310376489625127926903582301565836051873644165894999048192679267 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_idlecsbactive/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_idlecsbactive_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_stress_all 67717146100948596597567981096891041779130364715676063787227798143294750686575 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_stress_all/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=3724901743 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/4.spi_host_stress_all.3724901743 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 4.spi_host_stress_all.3724901743 -covoverwrite' seed=67717146100948596597567981096891041779130364715676063787227798143294750686575 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67717146100948596597567981096891041779130364715676063787227798143294750686575 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_spien 74910858353359128597716999411825867065210834020398501758516899818398945995240 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_spien/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=1473866216 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_spien_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/4.spi_host_spien.1473866216 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 4.spi_host_spien.1473866216 -covoverwrite' seed=74910858353359128597716999411825867065210834020398501758516899818398945995240 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74910858353359128597716999411825867065210834020398501758516899818398945995240 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_spien/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_spien_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_errors 87145366998883153336940094855370040074757257957340718121247903235002347012317 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2696134877 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/4.spi_host_tl_errors.2696134877 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.spi_host_tl_errors.2696134877 -covoverwrite' seed=87145366998883153336940094855370040074757257957340718121247903235002347012317 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87145366998883153336940094855370040074757257957340718121247903235002347012317 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_intg_err 11379516287830489609692806117126688299012351793894922491447422109525817762532 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=623452900 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/4.spi_host_tl_intg_err.623452900 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.spi_host_tl_intg_err.623452900 -covoverwrite' seed=11379516287830489609692806117126688299012351793894922491447422109525817762532 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11379516287830489609692806117126688299012351793894922491447422109525817762532 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_sec_cm 6239745916803370808560082179737795073650323084881307805300578162782052221293 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=1608712557 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/4.spi_host_sec_cm.1608712557 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 4.spi_host_sec_cm.1608712557 -covoverwrite' seed=6239745916803370808560082179737795073650323084881307805300578162782052221293 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6239745916803370808560082179737795073650323084881307805300578162782052221293 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_intr_test 67764792342069471926943252392715993868315506286267800016815400943566823469250 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=618246338 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/4.spi_host_intr_test.618246338 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.spi_host_intr_test.618246338 -covoverwrite' seed=67764792342069471926943252392715993868315506286267800016815400943566823469250 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67764792342069471926943252392715993868315506286267800016815400943566823469250 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_alert_test 17960750923666681608121066997957895995846050529419858589127787456275270826557 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=1046968893 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/4.spi_host_alert_test.1046968893 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 4.spi_host_alert_test.1046968893 -covoverwrite' seed=17960750923666681608121066997957895995846050529419858589127787456275270826557 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17960750923666681608121066997957895995846050529419858589127787456275270826557 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_csr_rw 69151805130488736720998136621825075644017784941200024639835447372244284289429 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_csr_rw/latest run_opts='+csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3682283925 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/4.spi_host_csr_rw.3682283925 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.spi_host_csr_rw.3682283925 -covoverwrite' seed=69151805130488736720998136621825075644017784941200024639835447372244284289429 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69151805130488736720998136621825075644017784941200024639835447372244284289429 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_same_csr_outstanding 109293038509748926565260527644867653072966910621574005067985756101381877726163 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1369766867 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/4.spi_host_same_csr_outstanding.1369766867 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.spi_host_same_csr_outstanding.1369766867 -covoverwrite' seed=109293038509748926565260527644867653072966910621574005067985756101381877726163 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109293038509748926565260527644867653072966910621574005067985756101381877726163 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_csr_mem_rw_with_rand_reset 56893540613807733265632727490077672472906373343122793581065465483582102300581 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3531597733 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/4.spi_host_csr_mem_rw_with_rand_reset.3531597733 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.spi_host_csr_mem_rw_with_rand_reset.3531597733 -covoverwrite' seed=56893540613807733265632727490077672472906373343122793581065465483582102300581 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56893540613807733265632727490077672472906373343122793581065465483582102300581 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/4.spi_host_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_smoke 15796620072420154486798984807712222228295067955621192353164047077147356888699 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/5.spi_host_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=65994363 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/5.spi_host_smoke.65994363 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 5.spi_host_smoke.65994363 -covoverwrite' seed=15796620072420154486798984807712222228295067955621192353164047077147356888699 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15796620072420154486798984807712222228295067955621192353164047077147356888699 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/5.spi_host_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_speed 82396778531241101782059572845909813953552157536591594053703353345369453145081 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/5.spi_host_speed/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=3120868345 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_speed_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/5.spi_host_speed.3120868345 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 5.spi_host_speed.3120868345 -covoverwrite' seed=82396778531241101782059572845909813953552157536591594053703353345369453145081 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82396778531241101782059572845909813953552157536591594053703353345369453145081 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/5.spi_host_speed/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_speed_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_performance 8532504710514432197856533291804396667977713959668507591977379102415954904706 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/5.spi_host_performance/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=1199572610 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_performance_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/5.spi_host_performance.1199572610 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 5.spi_host_performance.1199572610 -covoverwrite' seed=8532504710514432197856533291804396667977713959668507591977379102415954904706 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8532504710514432197856533291804396667977713959668507591977379102415954904706 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/5.spi_host_performance/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_performance_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_sw_reset 8971906205175599093060576380077948794952717534367515789167635650172640098567 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/5.spi_host_sw_reset/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=637335815 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_sw_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/5.spi_host_sw_reset.637335815 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 5.spi_host_sw_reset.637335815 -covoverwrite' seed=8971906205175599093060576380077948794952717534367515789167635650172640098567 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8971906205175599093060576380077948794952717534367515789167635650172640098567 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/5.spi_host_sw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_sw_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_overflow_underflow 85722043473468237482613862747524947045068690809777497251912605541617644037640 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/5.spi_host_overflow_underflow/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=746808840 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_overflow_underflow_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/5.spi_host_overflow_underflow.746808840 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 5.spi_host_overflow_underflow.746808840 -covoverwrite' seed=85722043473468237482613862747524947045068690809777497251912605541617644037640 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85722043473468237482613862747524947045068690809777497251912605541617644037640 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/5.spi_host_overflow_underflow/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_overflow_underflow_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_error_cmd 106864617049437232649498388922995114307054411568455219889558565963276059325957 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/5.spi_host_error_cmd/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=3792090629 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_error_cmd_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/5.spi_host_error_cmd.3792090629 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 5.spi_host_error_cmd.3792090629 -covoverwrite' seed=106864617049437232649498388922995114307054411568455219889558565963276059325957 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106864617049437232649498388922995114307054411568455219889558565963276059325957 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/5.spi_host_error_cmd/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_error_cmd_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_event 2453045653760506209701494166885991466107655325557334672075682120291502576728 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/5.spi_host_event/latest run_opts='+en_scb=0 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=157602904 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_event_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/5.spi_host_event.157602904 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 5.spi_host_event.157602904 -covoverwrite' seed=2453045653760506209701494166885991466107655325557334672075682120291502576728 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2453045653760506209701494166885991466107655325557334672075682120291502576728 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/5.spi_host_event/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_event_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_passthrough_mode 56672410839967249332394624993302103216080427386321817260328820436732135801183 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/5.spi_host_passthrough_mode/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=927138143 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_passthrough_mode_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/5.spi_host_passthrough_mode.927138143 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 5.spi_host_passthrough_mode.927138143 -covoverwrite' seed=56672410839967249332394624993302103216080427386321817260328820436732135801183 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56672410839967249332394624993302103216080427386321817260328820436732135801183 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/5.spi_host_passthrough_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_passthrough_mode_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_status_stall 80914549678485088259576287820739147785406287234453310511825442488107220663702 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/5.spi_host_status_stall/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=2698837398 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_status_stall_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/5.spi_host_status_stall.2698837398 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 5.spi_host_status_stall.2698837398 -covoverwrite' seed=80914549678485088259576287820739147785406287234453310511825442488107220663702 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80914549678485088259576287820739147785406287234453310511825442488107220663702 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/5.spi_host_status_stall/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_status_stall_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_idlecsbactive 6714845563322276139972003557030800405477316149988970476843067799638609743509 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/5.spi_host_idlecsbactive/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=1359466133 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_idlecsbactive_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/5.spi_host_idlecsbactive.1359466133 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 5.spi_host_idlecsbactive.1359466133 -covoverwrite' seed=6714845563322276139972003557030800405477316149988970476843067799638609743509 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6714845563322276139972003557030800405477316149988970476843067799638609743509 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/5.spi_host_idlecsbactive/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_idlecsbactive_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_stress_all 31220975376521027815628157746004090972842130355397069302729651548825343922353 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/5.spi_host_stress_all/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=2583072945 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/5.spi_host_stress_all.2583072945 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 5.spi_host_stress_all.2583072945 -covoverwrite' seed=31220975376521027815628157746004090972842130355397069302729651548825343922353 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31220975376521027815628157746004090972842130355397069302729651548825343922353 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/5.spi_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_spien 112858130640420387557679832846959781484438822381764773268249124411476532701895 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/5.spi_host_spien/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=3447368391 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_spien_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/5.spi_host_spien.3447368391 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 5.spi_host_spien.3447368391 -covoverwrite' seed=112858130640420387557679832846959781484438822381764773268249124411476532701895 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112858130640420387557679832846959781484438822381764773268249124411476532701895 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/5.spi_host_spien/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_spien_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_errors 11374306692577826040813324564814157912982640445005263714912252673761241492093 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/5.spi_host_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3831261821 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/5.spi_host_tl_errors.3831261821 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.spi_host_tl_errors.3831261821 -covoverwrite' seed=11374306692577826040813324564814157912982640445005263714912252673761241492093 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11374306692577826040813324564814157912982640445005263714912252673761241492093 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/5.spi_host_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_intg_err 99299155015895324473776288458474806650532489832380688497625736434346324109409 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/5.spi_host_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3436161121 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/5.spi_host_tl_intg_err.3436161121 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.spi_host_tl_intg_err.3436161121 -covoverwrite' seed=99299155015895324473776288458474806650532489832380688497625736434346324109409 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=99299155015895324473776288458474806650532489832380688497625736434346324109409 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/5.spi_host_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_intr_test 3906911103071443071093445764411934326386429005598995908113850714443062157540 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/5.spi_host_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3450314980 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/5.spi_host_intr_test.3450314980 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.spi_host_intr_test.3450314980 -covoverwrite' seed=3906911103071443071093445764411934326386429005598995908113850714443062157540 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3906911103071443071093445764411934326386429005598995908113850714443062157540 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/5.spi_host_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_alert_test 95173380749327041980633457783270482758007980238979933636557294182829105026111 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/5.spi_host_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=988222527 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/5.spi_host_alert_test.988222527 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 5.spi_host_alert_test.988222527 -covoverwrite' seed=95173380749327041980633457783270482758007980238979933636557294182829105026111 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95173380749327041980633457783270482758007980238979933636557294182829105026111 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/5.spi_host_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_smoke 104341967128077187451168873108279409469189083025968885033816428514731116199156 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/6.spi_host_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=4287888628 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/6.spi_host_smoke.4287888628 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 6.spi_host_smoke.4287888628 -covoverwrite' seed=104341967128077187451168873108279409469189083025968885033816428514731116199156 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104341967128077187451168873108279409469189083025968885033816428514731116199156 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/6.spi_host_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_speed 22020756351772674484986324318670638611410141807707464986561911062362430843199 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/6.spi_host_speed/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=3478071615 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_speed_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/6.spi_host_speed.3478071615 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 6.spi_host_speed.3478071615 -covoverwrite' seed=22020756351772674484986324318670638611410141807707464986561911062362430843199 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22020756351772674484986324318670638611410141807707464986561911062362430843199 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/6.spi_host_speed/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_speed_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_performance 94413622199878299448128346280678565833570138571973607650581545606482809352259 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/6.spi_host_performance/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=36991043 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_performance_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/6.spi_host_performance.36991043 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 6.spi_host_performance.36991043 -covoverwrite' seed=94413622199878299448128346280678565833570138571973607650581545606482809352259 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94413622199878299448128346280678565833570138571973607650581545606482809352259 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/6.spi_host_performance/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_performance_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_sw_reset 25379712669172053181915752092109524033637263605438465751932763385573917005681 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/6.spi_host_sw_reset/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=2825590641 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_sw_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/6.spi_host_sw_reset.2825590641 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 6.spi_host_sw_reset.2825590641 -covoverwrite' seed=25379712669172053181915752092109524033637263605438465751932763385573917005681 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25379712669172053181915752092109524033637263605438465751932763385573917005681 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/6.spi_host_sw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_sw_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_overflow_underflow 2411220063001765370405085761286530429845243340256998573566277072265016977839 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/6.spi_host_overflow_underflow/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=3601541551 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_overflow_underflow_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/6.spi_host_overflow_underflow.3601541551 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 6.spi_host_overflow_underflow.3601541551 -covoverwrite' seed=2411220063001765370405085761286530429845243340256998573566277072265016977839 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2411220063001765370405085761286530429845243340256998573566277072265016977839 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/6.spi_host_overflow_underflow/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_overflow_underflow_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_error_cmd 92804995741285915604208845609739892515998814944678863432714410847558547047180 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/6.spi_host_error_cmd/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=972063500 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_error_cmd_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/6.spi_host_error_cmd.972063500 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 6.spi_host_error_cmd.972063500 -covoverwrite' seed=92804995741285915604208845609739892515998814944678863432714410847558547047180 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92804995741285915604208845609739892515998814944678863432714410847558547047180 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/6.spi_host_error_cmd/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_error_cmd_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_event 35933547929373568710781106347660623214770961805623783160691477028026238113397 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/6.spi_host_event/latest run_opts='+en_scb=0 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=2713720437 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_event_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/6.spi_host_event.2713720437 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 6.spi_host_event.2713720437 -covoverwrite' seed=35933547929373568710781106347660623214770961805623783160691477028026238113397 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35933547929373568710781106347660623214770961805623783160691477028026238113397 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/6.spi_host_event/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_event_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_passthrough_mode 44116854482252726394617946680259903620683172157708639207799468854165109940131 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/6.spi_host_passthrough_mode/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=1045634979 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_passthrough_mode_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/6.spi_host_passthrough_mode.1045634979 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 6.spi_host_passthrough_mode.1045634979 -covoverwrite' seed=44116854482252726394617946680259903620683172157708639207799468854165109940131 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44116854482252726394617946680259903620683172157708639207799468854165109940131 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/6.spi_host_passthrough_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_passthrough_mode_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_status_stall 114458692659052052586865539398821824409398056245673181673861808735637964210574 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/6.spi_host_status_stall/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=1560428942 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_status_stall_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/6.spi_host_status_stall.1560428942 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 6.spi_host_status_stall.1560428942 -covoverwrite' seed=114458692659052052586865539398821824409398056245673181673861808735637964210574 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114458692659052052586865539398821824409398056245673181673861808735637964210574 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/6.spi_host_status_stall/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_status_stall_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_idlecsbactive 19182504089193680905302345120288807170546431857865707258018766687595301804099 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/6.spi_host_idlecsbactive/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=955357251 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_idlecsbactive_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/6.spi_host_idlecsbactive.955357251 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 6.spi_host_idlecsbactive.955357251 -covoverwrite' seed=19182504089193680905302345120288807170546431857865707258018766687595301804099 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19182504089193680905302345120288807170546431857865707258018766687595301804099 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/6.spi_host_idlecsbactive/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_idlecsbactive_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_stress_all 82991687426895118557162626796539283463860253258465241576618000471433927494992 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/6.spi_host_stress_all/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=3157298512 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/6.spi_host_stress_all.3157298512 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 6.spi_host_stress_all.3157298512 -covoverwrite' seed=82991687426895118557162626796539283463860253258465241576618000471433927494992 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82991687426895118557162626796539283463860253258465241576618000471433927494992 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/6.spi_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_spien 104344224175799623215556109746840152875771333195134276587481203968879885443083 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/6.spi_host_spien/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=1452433419 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_spien_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/6.spi_host_spien.1452433419 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 6.spi_host_spien.1452433419 -covoverwrite' seed=104344224175799623215556109746840152875771333195134276587481203968879885443083 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104344224175799623215556109746840152875771333195134276587481203968879885443083 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/6.spi_host_spien/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_spien_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_errors 4308624946208680077588399615407705069395001574504774474330767501913075800181 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/6.spi_host_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1853413493 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/6.spi_host_tl_errors.1853413493 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.spi_host_tl_errors.1853413493 -covoverwrite' seed=4308624946208680077588399615407705069395001574504774474330767501913075800181 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4308624946208680077588399615407705069395001574504774474330767501913075800181 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/6.spi_host_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_intg_err 55625535293614879855215739780078593852210586947088231228226957443805432689495 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/6.spi_host_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1325314903 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/6.spi_host_tl_intg_err.1325314903 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.spi_host_tl_intg_err.1325314903 -covoverwrite' seed=55625535293614879855215739780078593852210586947088231228226957443805432689495 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55625535293614879855215739780078593852210586947088231228226957443805432689495 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/6.spi_host_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_intr_test 39781869897156117688978110311655564670144443184819939612858732991320070625554 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/6.spi_host_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3605600530 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/6.spi_host_intr_test.3605600530 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.spi_host_intr_test.3605600530 -covoverwrite' seed=39781869897156117688978110311655564670144443184819939612858732991320070625554 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39781869897156117688978110311655564670144443184819939612858732991320070625554 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/6.spi_host_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_alert_test 115751970665132699951217103474998696917235019994266677996985271654088652188994 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/6.spi_host_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=3676925250 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/6.spi_host_alert_test.3676925250 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 6.spi_host_alert_test.3676925250 -covoverwrite' seed=115751970665132699951217103474998696917235019994266677996985271654088652188994 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115751970665132699951217103474998696917235019994266677996985271654088652188994 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/6.spi_host_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_smoke 61029523835956224503088368598823020634660356133695019081224343557542632237325 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/7.spi_host_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=3147835661 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/7.spi_host_smoke.3147835661 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 7.spi_host_smoke.3147835661 -covoverwrite' seed=61029523835956224503088368598823020634660356133695019081224343557542632237325 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61029523835956224503088368598823020634660356133695019081224343557542632237325 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/7.spi_host_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_speed 55249937156238671318540158034644384693827383201431669296325612656913904758278 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/7.spi_host_speed/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=443477510 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_speed_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/7.spi_host_speed.443477510 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 7.spi_host_speed.443477510 -covoverwrite' seed=55249937156238671318540158034644384693827383201431669296325612656913904758278 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55249937156238671318540158034644384693827383201431669296325612656913904758278 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/7.spi_host_speed/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_speed_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_performance 52733186001856731699141317088722570080745934596294276159890388246340693808993 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/7.spi_host_performance/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=2708363105 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_performance_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/7.spi_host_performance.2708363105 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 7.spi_host_performance.2708363105 -covoverwrite' seed=52733186001856731699141317088722570080745934596294276159890388246340693808993 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=52733186001856731699141317088722570080745934596294276159890388246340693808993 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/7.spi_host_performance/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_performance_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_sw_reset 34835368136843475108044398649487593565928945009056992860787323577922979210975 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/7.spi_host_sw_reset/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=1849796319 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_sw_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/7.spi_host_sw_reset.1849796319 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 7.spi_host_sw_reset.1849796319 -covoverwrite' seed=34835368136843475108044398649487593565928945009056992860787323577922979210975 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34835368136843475108044398649487593565928945009056992860787323577922979210975 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/7.spi_host_sw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_sw_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_overflow_underflow 47530900110019133164204849851345934487506887311866446282655768168787726208017 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/7.spi_host_overflow_underflow/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=3675425809 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_overflow_underflow_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/7.spi_host_overflow_underflow.3675425809 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 7.spi_host_overflow_underflow.3675425809 -covoverwrite' seed=47530900110019133164204849851345934487506887311866446282655768168787726208017 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47530900110019133164204849851345934487506887311866446282655768168787726208017 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/7.spi_host_overflow_underflow/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_overflow_underflow_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_error_cmd 93042493167758394850290474277686680059928203589947191124371410941313263220112 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/7.spi_host_error_cmd/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=2063742352 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_error_cmd_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/7.spi_host_error_cmd.2063742352 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 7.spi_host_error_cmd.2063742352 -covoverwrite' seed=93042493167758394850290474277686680059928203589947191124371410941313263220112 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93042493167758394850290474277686680059928203589947191124371410941313263220112 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/7.spi_host_error_cmd/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_error_cmd_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_event 16565628576804835999234857474133515597734364538969895851239898311333668831290 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/7.spi_host_event/latest run_opts='+en_scb=0 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=3762667578 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_event_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/7.spi_host_event.3762667578 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 7.spi_host_event.3762667578 -covoverwrite' seed=16565628576804835999234857474133515597734364538969895851239898311333668831290 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16565628576804835999234857474133515597734364538969895851239898311333668831290 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/7.spi_host_event/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_event_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_passthrough_mode 64520522921272016081057087780481512754475245454764807062015530740745433814727 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/7.spi_host_passthrough_mode/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=2147784391 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_passthrough_mode_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/7.spi_host_passthrough_mode.2147784391 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 7.spi_host_passthrough_mode.2147784391 -covoverwrite' seed=64520522921272016081057087780481512754475245454764807062015530740745433814727 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64520522921272016081057087780481512754475245454764807062015530740745433814727 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/7.spi_host_passthrough_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_passthrough_mode_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_status_stall 114465858223431635039776146422532533664793083397906806360694782640019896878875 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/7.spi_host_status_stall/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=2769110811 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_status_stall_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/7.spi_host_status_stall.2769110811 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 7.spi_host_status_stall.2769110811 -covoverwrite' seed=114465858223431635039776146422532533664793083397906806360694782640019896878875 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114465858223431635039776146422532533664793083397906806360694782640019896878875 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/7.spi_host_status_stall/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_status_stall_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_idlecsbactive 42707656779717309094885674536233063596876705270785664758591759040717859195379 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/7.spi_host_idlecsbactive/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=61475315 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_idlecsbactive_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/7.spi_host_idlecsbactive.61475315 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 7.spi_host_idlecsbactive.61475315 -covoverwrite' seed=42707656779717309094885674536233063596876705270785664758591759040717859195379 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42707656779717309094885674536233063596876705270785664758591759040717859195379 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/7.spi_host_idlecsbactive/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_idlecsbactive_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_stress_all 55739832985078915425289330162133250029953307275152254089280666224743138632815 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/7.spi_host_stress_all/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=2086315119 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/7.spi_host_stress_all.2086315119 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 7.spi_host_stress_all.2086315119 -covoverwrite' seed=55739832985078915425289330162133250029953307275152254089280666224743138632815 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55739832985078915425289330162133250029953307275152254089280666224743138632815 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/7.spi_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_spien 67482838216605852314368176096497369123578916658991280535492886332892273181911 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/7.spi_host_spien/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=1900020951 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_spien_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/7.spi_host_spien.1900020951 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 7.spi_host_spien.1900020951 -covoverwrite' seed=67482838216605852314368176096497369123578916658991280535492886332892273181911 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67482838216605852314368176096497369123578916658991280535492886332892273181911 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/7.spi_host_spien/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_spien_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_errors 60698437108848751499279830727463825801913248064832160591823044891030024870968 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/7.spi_host_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=538434616 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/7.spi_host_tl_errors.538434616 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.spi_host_tl_errors.538434616 -covoverwrite' seed=60698437108848751499279830727463825801913248064832160591823044891030024870968 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60698437108848751499279830727463825801913248064832160591823044891030024870968 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/7.spi_host_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_intg_err 42136330658061608026872977893575541654521575698093041927585767841016057389958 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/7.spi_host_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=938959750 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/7.spi_host_tl_intg_err.938959750 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.spi_host_tl_intg_err.938959750 -covoverwrite' seed=42136330658061608026872977893575541654521575698093041927585767841016057389958 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42136330658061608026872977893575541654521575698093041927585767841016057389958 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/7.spi_host_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_intr_test 51889999788142666215188759378704674700465810872532283698235379525676933563747 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/7.spi_host_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1758446947 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/7.spi_host_intr_test.1758446947 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.spi_host_intr_test.1758446947 -covoverwrite' seed=51889999788142666215188759378704674700465810872532283698235379525676933563747 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51889999788142666215188759378704674700465810872532283698235379525676933563747 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/7.spi_host_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_alert_test 62932910620266559162523678601193271746588513396796077657881519111745389855887 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/7.spi_host_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=58066063 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/7.spi_host_alert_test.58066063 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 7.spi_host_alert_test.58066063 -covoverwrite' seed=62932910620266559162523678601193271746588513396796077657881519111745389855887 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62932910620266559162523678601193271746588513396796077657881519111745389855887 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/7.spi_host_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_smoke 20598730728926619152416145439603777433688051155901684602253882151820249467287 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/8.spi_host_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=2181237143 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/8.spi_host_smoke.2181237143 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 8.spi_host_smoke.2181237143 -covoverwrite' seed=20598730728926619152416145439603777433688051155901684602253882151820249467287 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20598730728926619152416145439603777433688051155901684602253882151820249467287 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/8.spi_host_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_speed 105633142477531019930273799867813435836782940488521454146559714399172687816846 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/8.spi_host_speed/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=1551886478 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_speed_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/8.spi_host_speed.1551886478 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 8.spi_host_speed.1551886478 -covoverwrite' seed=105633142477531019930273799867813435836782940488521454146559714399172687816846 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105633142477531019930273799867813435836782940488521454146559714399172687816846 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/8.spi_host_speed/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_speed_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_performance 56370691147641884589123301149219038620041623178167309892310117440857246278847 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/8.spi_host_performance/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=4158661823 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_performance_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/8.spi_host_performance.4158661823 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 8.spi_host_performance.4158661823 -covoverwrite' seed=56370691147641884589123301149219038620041623178167309892310117440857246278847 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56370691147641884589123301149219038620041623178167309892310117440857246278847 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/8.spi_host_performance/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_performance_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_sw_reset 31676132771455743996921892403948698518654542323725536708862656292847888682817 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/8.spi_host_sw_reset/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=1749077825 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_sw_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/8.spi_host_sw_reset.1749077825 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 8.spi_host_sw_reset.1749077825 -covoverwrite' seed=31676132771455743996921892403948698518654542323725536708862656292847888682817 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31676132771455743996921892403948698518654542323725536708862656292847888682817 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/8.spi_host_sw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_sw_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_overflow_underflow 85566334703923999947315381048631513926462997930047465577666539403558353479844 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/8.spi_host_overflow_underflow/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=2013636772 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_overflow_underflow_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/8.spi_host_overflow_underflow.2013636772 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 8.spi_host_overflow_underflow.2013636772 -covoverwrite' seed=85566334703923999947315381048631513926462997930047465577666539403558353479844 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85566334703923999947315381048631513926462997930047465577666539403558353479844 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/8.spi_host_overflow_underflow/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_overflow_underflow_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_error_cmd 17351890223059678649729553264742431007648757171573703425494509189175077164328 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/8.spi_host_error_cmd/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=562746664 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_error_cmd_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/8.spi_host_error_cmd.562746664 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 8.spi_host_error_cmd.562746664 -covoverwrite' seed=17351890223059678649729553264742431007648757171573703425494509189175077164328 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17351890223059678649729553264742431007648757171573703425494509189175077164328 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/8.spi_host_error_cmd/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_error_cmd_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_event 91463215218775577825798536731997113928898460154208095151812951475785610453657 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/8.spi_host_event/latest run_opts='+en_scb=0 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=2520933017 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_event_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/8.spi_host_event.2520933017 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 8.spi_host_event.2520933017 -covoverwrite' seed=91463215218775577825798536731997113928898460154208095151812951475785610453657 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91463215218775577825798536731997113928898460154208095151812951475785610453657 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/8.spi_host_event/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_event_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_passthrough_mode 71471701942977591942942905432493954431668544167390588473084892095246602721468 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/8.spi_host_passthrough_mode/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=3053574332 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_passthrough_mode_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/8.spi_host_passthrough_mode.3053574332 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 8.spi_host_passthrough_mode.3053574332 -covoverwrite' seed=71471701942977591942942905432493954431668544167390588473084892095246602721468 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71471701942977591942942905432493954431668544167390588473084892095246602721468 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/8.spi_host_passthrough_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_passthrough_mode_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_status_stall 38870083249721300558167728430866749856538930273739592675974474389009439539498 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/8.spi_host_status_stall/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=2404794666 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_status_stall_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/8.spi_host_status_stall.2404794666 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 8.spi_host_status_stall.2404794666 -covoverwrite' seed=38870083249721300558167728430866749856538930273739592675974474389009439539498 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38870083249721300558167728430866749856538930273739592675974474389009439539498 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/8.spi_host_status_stall/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_status_stall_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_idlecsbactive 114755783559480000549488866585596006379327993647705222272996243710623727859640 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/8.spi_host_idlecsbactive/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=1952036792 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_idlecsbactive_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/8.spi_host_idlecsbactive.1952036792 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 8.spi_host_idlecsbactive.1952036792 -covoverwrite' seed=114755783559480000549488866585596006379327993647705222272996243710623727859640 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114755783559480000549488866585596006379327993647705222272996243710623727859640 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/8.spi_host_idlecsbactive/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_idlecsbactive_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_stress_all 34950688858582243972873628562869860427875575976289172530428229834664848871996 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/8.spi_host_stress_all/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=3386069564 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/8.spi_host_stress_all.3386069564 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 8.spi_host_stress_all.3386069564 -covoverwrite' seed=34950688858582243972873628562869860427875575976289172530428229834664848871996 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34950688858582243972873628562869860427875575976289172530428229834664848871996 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/8.spi_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_spien 85218144645648093720948023983822515239388351391218303724371769668966280315086 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/8.spi_host_spien/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=3811819726 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_spien_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/8.spi_host_spien.3811819726 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 8.spi_host_spien.3811819726 -covoverwrite' seed=85218144645648093720948023983822515239388351391218303724371769668966280315086 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85218144645648093720948023983822515239388351391218303724371769668966280315086 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/8.spi_host_spien/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_spien_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_errors 18577120558862715903010089208530545274598053139775235961986886934096130550217 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/8.spi_host_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3419613641 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/8.spi_host_tl_errors.3419613641 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.spi_host_tl_errors.3419613641 -covoverwrite' seed=18577120558862715903010089208530545274598053139775235961986886934096130550217 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18577120558862715903010089208530545274598053139775235961986886934096130550217 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/8.spi_host_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_intg_err 28240985650421564068177074686451556214394985816926791691376065790402442166907 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/8.spi_host_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=720503419 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/8.spi_host_tl_intg_err.720503419 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.spi_host_tl_intg_err.720503419 -covoverwrite' seed=28240985650421564068177074686451556214394985816926791691376065790402442166907 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28240985650421564068177074686451556214394985816926791691376065790402442166907 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/8.spi_host_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_intr_test 1396214211720588614590220412989696358036453906717889646873187572210737043909 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/8.spi_host_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2340116933 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/8.spi_host_intr_test.2340116933 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.spi_host_intr_test.2340116933 -covoverwrite' seed=1396214211720588614590220412989696358036453906717889646873187572210737043909 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1396214211720588614590220412989696358036453906717889646873187572210737043909 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/8.spi_host_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_alert_test 98497745551854230073840571472988555828362679254463871827521691943545486916059 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/8.spi_host_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=3385014747 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/8.spi_host_alert_test.3385014747 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 8.spi_host_alert_test.3385014747 -covoverwrite' seed=98497745551854230073840571472988555828362679254463871827521691943545486916059 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98497745551854230073840571472988555828362679254463871827521691943545486916059 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/8.spi_host_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_smoke 48264331759390069326265862035375377711671387292177800453332177145924070155335 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/9.spi_host_smoke/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=342631495 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/9.spi_host_smoke.342631495 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 9.spi_host_smoke.342631495 -covoverwrite' seed=48264331759390069326265862035375377711671387292177800453332177145924070155335 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48264331759390069326265862035375377711671387292177800453332177145924070155335 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/9.spi_host_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_speed 7451886323906351868131941936598587476097988946972653026650092886650038837972 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/9.spi_host_speed/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=823714516 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_speed_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/9.spi_host_speed.823714516 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 9.spi_host_speed.823714516 -covoverwrite' seed=7451886323906351868131941936598587476097988946972653026650092886650038837972 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7451886323906351868131941936598587476097988946972653026650092886650038837972 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/9.spi_host_speed/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_speed_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_performance 26116588895404255126529099423018545082387829895905051200782306975238317934419 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/9.spi_host_performance/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=2386560851 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_performance_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/9.spi_host_performance.2386560851 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 9.spi_host_performance.2386560851 -covoverwrite' seed=26116588895404255126529099423018545082387829895905051200782306975238317934419 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26116588895404255126529099423018545082387829895905051200782306975238317934419 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/9.spi_host_performance/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_performance_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_sw_reset 31538685636451824192199522219131485996717573084581281098339550159141192247595 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/9.spi_host_sw_reset/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=408856875 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_sw_reset_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/9.spi_host_sw_reset.408856875 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 9.spi_host_sw_reset.408856875 -covoverwrite' seed=31538685636451824192199522219131485996717573084581281098339550159141192247595 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31538685636451824192199522219131485996717573084581281098339550159141192247595 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/9.spi_host_sw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_sw_reset_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_overflow_underflow 74924546847897466486138801438673072958179364183214401539577844775219364727243 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/9.spi_host_overflow_underflow/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=4119693771 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_overflow_underflow_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/9.spi_host_overflow_underflow.4119693771 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 9.spi_host_overflow_underflow.4119693771 -covoverwrite' seed=74924546847897466486138801438673072958179364183214401539577844775219364727243 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74924546847897466486138801438673072958179364183214401539577844775219364727243 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/9.spi_host_overflow_underflow/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_overflow_underflow_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_error_cmd 25131366586619349753128034231081336179295274255048506982166613153530110860573 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/9.spi_host_error_cmd/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=295755037 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_error_cmd_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/9.spi_host_error_cmd.295755037 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 9.spi_host_error_cmd.295755037 -covoverwrite' seed=25131366586619349753128034231081336179295274255048506982166613153530110860573 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25131366586619349753128034231081336179295274255048506982166613153530110860573 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/9.spi_host_error_cmd/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_error_cmd_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_event 69595486236313896943407012342271563065518742990484646141528252559158552536328 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/9.spi_host_event/latest run_opts='+en_scb=0 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=3031147784 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_event_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/9.spi_host_event.3031147784 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 9.spi_host_event.3031147784 -covoverwrite' seed=69595486236313896943407012342271563065518742990484646141528252559158552536328 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69595486236313896943407012342271563065518742990484646141528252559158552536328 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/9.spi_host_event/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_event_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_passthrough_mode 1728059034379886396584740667913644486262801639463689633518181429824641097875 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/9.spi_host_passthrough_mode/latest run_opts='+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=2958876819 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_passthrough_mode_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/9.spi_host_passthrough_mode.2958876819 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 9.spi_host_passthrough_mode.2958876819 -covoverwrite' seed=1728059034379886396584740667913644486262801639463689633518181429824641097875 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1728059034379886396584740667913644486262801639463689633518181429824641097875 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/9.spi_host_passthrough_mode/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_passthrough_mode_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_status_stall 45546809575083569125797166091459321778344033601126128996475400702760791419225 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/9.spi_host_status_stall/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=1653188953 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_status_stall_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/9.spi_host_status_stall.1653188953 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 9.spi_host_status_stall.1653188953 -covoverwrite' seed=45546809575083569125797166091459321778344033601126128996475400702760791419225 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45546809575083569125797166091459321778344033601126128996475400702760791419225 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/9.spi_host_status_stall/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_status_stall_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_idlecsbactive 29648031314448357029563892907602670945365157052750571204935477417243612746919 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/9.spi_host_idlecsbactive/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=2951419047 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_idlecsbactive_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/9.spi_host_idlecsbactive.2951419047 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 9.spi_host_idlecsbactive.2951419047 -covoverwrite' seed=29648031314448357029563892907602670945365157052750571204935477417243612746919 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29648031314448357029563892907602670945365157052750571204935477417243612746919 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/9.spi_host_idlecsbactive/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_idlecsbactive_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_stress_all 39855377451578164950508274497118259243938353122508973579665484067191086290769 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/9.spi_host_stress_all/latest run_opts='+test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=3485636433 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/9.spi_host_stress_all.3485636433 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 9.spi_host_stress_all.3485636433 -covoverwrite' seed=39855377451578164950508274497118259243938353122508973579665484067191086290769 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39855377451578164950508274497118259243938353122508973579665484067191086290769 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/9.spi_host_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_spien 53277320392683146062345406845270190750428546374183457171220901872189620854722 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/9.spi_host_spien/latest run_opts='+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=3069681602 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_spien_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/9.spi_host_spien.3069681602 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 9.spi_host_spien.3069681602 -covoverwrite' seed=53277320392683146062345406845270190750428546374183457171220901872189620854722 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53277320392683146062345406845270190750428546374183457171220901872189620854722 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/9.spi_host_spien/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_spien_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_errors 96507824635000896219791136350711942239032753813731047979121443789815370675430 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/9.spi_host_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=524219622 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/9.spi_host_tl_errors.524219622 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.spi_host_tl_errors.524219622 -covoverwrite' seed=96507824635000896219791136350711942239032753813731047979121443789815370675430 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96507824635000896219791136350711942239032753813731047979121443789815370675430 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/9.spi_host_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_intg_err 86554795823801258681016411119782022422783928873402747941195304690451118824455 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/9.spi_host_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=128982023 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/9.spi_host_tl_intg_err.128982023 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.spi_host_tl_intg_err.128982023 -covoverwrite' seed=86554795823801258681016411119782022422783928873402747941195304690451118824455 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86554795823801258681016411119782022422783928873402747941195304690451118824455 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/9.spi_host_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_intr_test 41484845905042507493218968529420026305167600144939964297657437233058371854070 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/9.spi_host_intr_test/latest run_opts='+run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2207506166 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/9.spi_host_intr_test.2207506166 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.spi_host_intr_test.2207506166 -covoverwrite' seed=41484845905042507493218968529420026305167600144939964297657437233058371854070 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41484845905042507493218968529420026305167600144939964297657437233058371854070 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/9.spi_host_intr_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_alert_test 43073675170068556354596498935681035644882773293804974063881872401241155211260 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/9.spi_host_alert_test/latest run_opts='+run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/default/xcelium.d -r tb +SVSEED=3341717500 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/default/9.spi_host_alert_test.3341717500 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope default -covtest 9.spi_host_alert_test.3341717500 -covoverwrite' seed=43073675170068556354596498935681035644882773293804974063881872401241155211260 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43073675170068556354596498935681035644882773293804974063881872401241155211260 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/9.spi_host_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_errors 11790940571030769449188866603015547715938795129094246839579867189405098271821 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/10.spi_host_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3077137485 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/10.spi_host_tl_errors.3077137485 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 10.spi_host_tl_errors.3077137485 -covoverwrite' seed=11790940571030769449188866603015547715938795129094246839579867189405098271821 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11790940571030769449188866603015547715938795129094246839579867189405098271821 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/10.spi_host_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_intg_err 110061474752672413762437323958698652557601892941015868769383779492351035690101 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/10.spi_host_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3118058613 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/10.spi_host_tl_intg_err.3118058613 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 10.spi_host_tl_intg_err.3118058613 -covoverwrite' seed=110061474752672413762437323958698652557601892941015868769383779492351035690101 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110061474752672413762437323958698652557601892941015868769383779492351035690101 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/10.spi_host_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_errors 81115406150958686853047769682826845891313843079034099876112288297390836517219 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/11.spi_host_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3971713379 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/11.spi_host_tl_errors.3971713379 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 11.spi_host_tl_errors.3971713379 -covoverwrite' seed=81115406150958686853047769682826845891313843079034099876112288297390836517219 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81115406150958686853047769682826845891313843079034099876112288297390836517219 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/11.spi_host_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_intg_err 50791390837937897398336804935078832187877368264753607559384389271166581960047 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/11.spi_host_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2714463599 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/11.spi_host_tl_intg_err.2714463599 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 11.spi_host_tl_intg_err.2714463599 -covoverwrite' seed=50791390837937897398336804935078832187877368264753607559384389271166581960047 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50791390837937897398336804935078832187877368264753607559384389271166581960047 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/11.spi_host_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_errors 86890535836188517067717302844214505998426245783248337330413267245562901320946 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/12.spi_host_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3827062002 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/12.spi_host_tl_errors.3827062002 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 12.spi_host_tl_errors.3827062002 -covoverwrite' seed=86890535836188517067717302844214505998426245783248337330413267245562901320946 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86890535836188517067717302844214505998426245783248337330413267245562901320946 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/12.spi_host_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_intg_err 97183644332408882984192919109707339919432638025986017446426609144823520873026 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/12.spi_host_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1055050306 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/12.spi_host_tl_intg_err.1055050306 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 12.spi_host_tl_intg_err.1055050306 -covoverwrite' seed=97183644332408882984192919109707339919432638025986017446426609144823520873026 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97183644332408882984192919109707339919432638025986017446426609144823520873026 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/12.spi_host_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_errors 97141808096713409852032117531187291225111467229678433491709503900634417328196 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/13.spi_host_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2724065348 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/13.spi_host_tl_errors.2724065348 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 13.spi_host_tl_errors.2724065348 -covoverwrite' seed=97141808096713409852032117531187291225111467229678433491709503900634417328196 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97141808096713409852032117531187291225111467229678433491709503900634417328196 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/13.spi_host_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_intg_err 44630086441792075540481098626584310937682776356708856236719747450906453194765 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/13.spi_host_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4220237837 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/13.spi_host_tl_intg_err.4220237837 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 13.spi_host_tl_intg_err.4220237837 -covoverwrite' seed=44630086441792075540481098626584310937682776356708856236719747450906453194765 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44630086441792075540481098626584310937682776356708856236719747450906453194765 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/13.spi_host_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_errors 48185345508327372387132874599426385296353554753423280599154747587441390414215 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/14.spi_host_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1965451655 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/14.spi_host_tl_errors.1965451655 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 14.spi_host_tl_errors.1965451655 -covoverwrite' seed=48185345508327372387132874599426385296353554753423280599154747587441390414215 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48185345508327372387132874599426385296353554753423280599154747587441390414215 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/14.spi_host_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_intg_err 13417628701968374906933165794535595590641286671540819227302001157496844909537 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/14.spi_host_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3474783201 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/14.spi_host_tl_intg_err.3474783201 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 14.spi_host_tl_intg_err.3474783201 -covoverwrite' seed=13417628701968374906933165794535595590641286671540819227302001157496844909537 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13417628701968374906933165794535595590641286671540819227302001157496844909537 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/14.spi_host_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_errors 74629096862087243145591475431027651173011802545664016075954499965560052088574 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/15.spi_host_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=979205886 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/15.spi_host_tl_errors.979205886 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 15.spi_host_tl_errors.979205886 -covoverwrite' seed=74629096862087243145591475431027651173011802545664016075954499965560052088574 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74629096862087243145591475431027651173011802545664016075954499965560052088574 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/15.spi_host_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_intg_err 115578982281877703792883085344401865435859619374069198144247153530158458003132 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/15.spi_host_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3870219964 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/15.spi_host_tl_intg_err.3870219964 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 15.spi_host_tl_intg_err.3870219964 -covoverwrite' seed=115578982281877703792883085344401865435859619374069198144247153530158458003132 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115578982281877703792883085344401865435859619374069198144247153530158458003132 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/15.spi_host_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_errors 65133158050707759940775521550411086537958216337350607996378765542111138761208 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/16.spi_host_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4197403128 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/16.spi_host_tl_errors.4197403128 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 16.spi_host_tl_errors.4197403128 -covoverwrite' seed=65133158050707759940775521550411086537958216337350607996378765542111138761208 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65133158050707759940775521550411086537958216337350607996378765542111138761208 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/16.spi_host_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_intg_err 76086038513618624711691370284451700520718516811417342258505847367185826589754 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/16.spi_host_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2567449658 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/16.spi_host_tl_intg_err.2567449658 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 16.spi_host_tl_intg_err.2567449658 -covoverwrite' seed=76086038513618624711691370284451700520718516811417342258505847367185826589754 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76086038513618624711691370284451700520718516811417342258505847367185826589754 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/16.spi_host_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_errors 62029267204746190955477182821150715887920674151385904136796810350188867238183 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/17.spi_host_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4278860071 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/17.spi_host_tl_errors.4278860071 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 17.spi_host_tl_errors.4278860071 -covoverwrite' seed=62029267204746190955477182821150715887920674151385904136796810350188867238183 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62029267204746190955477182821150715887920674151385904136796810350188867238183 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/17.spi_host_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_intg_err 31398795455588505648931423026967723447279064016818916645604677193578060873361 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/17.spi_host_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3851320977 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/17.spi_host_tl_intg_err.3851320977 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 17.spi_host_tl_intg_err.3851320977 -covoverwrite' seed=31398795455588505648931423026967723447279064016818916645604677193578060873361 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31398795455588505648931423026967723447279064016818916645604677193578060873361 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/17.spi_host_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_errors 79589441403312827197920308717852760912538520300987382854494003248770956126816 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/18.spi_host_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3515083360 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/18.spi_host_tl_errors.3515083360 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 18.spi_host_tl_errors.3515083360 -covoverwrite' seed=79589441403312827197920308717852760912538520300987382854494003248770956126816 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79589441403312827197920308717852760912538520300987382854494003248770956126816 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/18.spi_host_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_intg_err 95436482968716574244731461735212257892996289825265956290767383518308386893960 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/18.spi_host_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4062081160 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/18.spi_host_tl_intg_err.4062081160 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 18.spi_host_tl_intg_err.4062081160 -covoverwrite' seed=95436482968716574244731461735212257892996289825265956290767383518308386893960 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95436482968716574244731461735212257892996289825265956290767383518308386893960 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/18.spi_host_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_errors 71073102635269525174318162502756547878516163796975574850661937155988841981106 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/19.spi_host_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=276980914 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/19.spi_host_tl_errors.276980914 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 19.spi_host_tl_errors.276980914 -covoverwrite' seed=71073102635269525174318162502756547878516163796975574850661937155988841981106 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71073102635269525174318162502756547878516163796975574850661937155988841981106 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/19.spi_host_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_intg_err 114941586797685272098842059649701000346707384792994345822747279215705819805030 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/19.spi_host_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2426762598 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/19.spi_host_tl_intg_err.2426762598 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 19.spi_host_tl_intg_err.2426762598 -covoverwrite' seed=114941586797685272098842059649701000346707384792994345822747279215705819805030 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=114941586797685272098842059649701000346707384792994345822747279215705819805030 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/19.spi_host_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_errors 68842369436999757388035566048802538319363805295940666663966422879415683768794 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/20.spi_host_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=945807834 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/20.spi_host_tl_errors.945807834 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 20.spi_host_tl_errors.945807834 -covoverwrite' seed=68842369436999757388035566048802538319363805295940666663966422879415683768794 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68842369436999757388035566048802538319363805295940666663966422879415683768794 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/20.spi_host_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_intg_err 6168259917585209861736507374426576738924428863563632293555786096803413354663 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/20.spi_host_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3648120999 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/20.spi_host_tl_intg_err.3648120999 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 20.spi_host_tl_intg_err.3648120999 -covoverwrite' seed=6168259917585209861736507374426576738924428863563632293555786096803413354663 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6168259917585209861736507374426576738924428863563632293555786096803413354663 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/20.spi_host_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_errors 76182451210461679799232914678246052695972944910222684915368152621659585446237 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/21.spi_host_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1849622877 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/21.spi_host_tl_errors.1849622877 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 21.spi_host_tl_errors.1849622877 -covoverwrite' seed=76182451210461679799232914678246052695972944910222684915368152621659585446237 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76182451210461679799232914678246052695972944910222684915368152621659585446237 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/21.spi_host_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_intg_err 77869177828181667297009659144154627376458392748869555222966545167628276474487 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/21.spi_host_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=260973175 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/21.spi_host_tl_intg_err.260973175 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 21.spi_host_tl_intg_err.260973175 -covoverwrite' seed=77869177828181667297009659144154627376458392748869555222966545167628276474487 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=77869177828181667297009659144154627376458392748869555222966545167628276474487 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/21.spi_host_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_errors 83390838757309680359784867657461342919511533349457269632042094954611587615251 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/22.spi_host_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4225698323 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/22.spi_host_tl_errors.4225698323 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 22.spi_host_tl_errors.4225698323 -covoverwrite' seed=83390838757309680359784867657461342919511533349457269632042094954611587615251 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83390838757309680359784867657461342919511533349457269632042094954611587615251 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/22.spi_host_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_intg_err 81632666900889257220966213360696380880271782374168727225091965445970964925490 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/22.spi_host_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4150152242 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/22.spi_host_tl_intg_err.4150152242 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 22.spi_host_tl_intg_err.4150152242 -covoverwrite' seed=81632666900889257220966213360696380880271782374168727225091965445970964925490 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81632666900889257220966213360696380880271782374168727225091965445970964925490 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/22.spi_host_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_errors 95810035231886018434712731935511090672692571509008956826529665971815862768447 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/23.spi_host_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2094011199 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/23.spi_host_tl_errors.2094011199 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 23.spi_host_tl_errors.2094011199 -covoverwrite' seed=95810035231886018434712731935511090672692571509008956826529665971815862768447 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95810035231886018434712731935511090672692571509008956826529665971815862768447 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/23.spi_host_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_intg_err 112278211663665002302841918243152884029730172474877391234976141614107205033736 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/23.spi_host_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2510544648 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/23.spi_host_tl_intg_err.2510544648 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 23.spi_host_tl_intg_err.2510544648 -covoverwrite' seed=112278211663665002302841918243152884029730172474877391234976141614107205033736 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112278211663665002302841918243152884029730172474877391234976141614107205033736 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/23.spi_host_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_errors 66423941001476263047525345968036121726465517826420181805784601257567923595817 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/24.spi_host_tl_errors/latest run_opts='+run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=788130345 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/24.spi_host_tl_errors.788130345 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 24.spi_host_tl_errors.788130345 -covoverwrite' seed=66423941001476263047525345968036121726465517826420181805784601257567923595817 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66423941001476263047525345968036121726465517826420181805784601257567923595817 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/24.spi_host_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
spi_host_tl_intg_err 21274692605089053662819592711327847298173404849375366678703954163616867866007 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/24.spi_host_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/spi_host-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2657015191 +UVM_TESTNAME=spi_host_base_test +UVM_TEST_SEQ=spi_host_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage/cover_reg_top/24.spi_host_tl_intg_err.2657015191 -covworkdir /nightly/current_run/scratch/master/spi_host-sim-xcelium/coverage -covscope cover_reg_top -covtest 24.spi_host_tl_intg_err.2657015191 -covoverwrite' seed=21274692605089053662819592711327847298173404849375366678703954163616867866007 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21274692605089053662819592711327847298173404849375366678703954163616867866007 --run-dir=/nightly/current_run/scratch/master/spi_host-sim-xcelium/24.spi_host_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=spi_host_base_test uvm_test_seq=spi_host_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
Job cancelled because all of its dependencies failed or were killed. 1 test run
spi_host None None
Job cancelled because one of its dependencies failed or was killed. 1 test run
spi_host None None