Simulation Results: sram_ctrl/main

 
28/08/2026 21:54:34 DVSim: v1.49.0 sha: a099412 json Branch: master Tool: xcelium [unknown]
Validation stages
V1
0.00%
V2
0.00%
V2S
0.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 0 8 0.00
sram_ctrl_smoke 1.362s 0.000us 0 8 0.00
csr_hw_reset 0 1 0.00
sram_ctrl_csr_hw_reset 1.369s 0.000us 0 1 0.00
csr_rw 0 5 0.00
sram_ctrl_csr_rw 1.364s 0.000us 0 5 0.00
csr_bit_bash 0 1 0.00
sram_ctrl_csr_bit_bash 0.880s 0.000us 0 1 0.00
csr_aliasing 0 1 0.00
sram_ctrl_csr_aliasing 0.826s 0.000us 0 1 0.00
csr_mem_rw_with_rand_reset 0 5 0.00
sram_ctrl_csr_mem_rw_with_rand_reset 0.884s 0.000us 0 5 0.00
regwen_csr_and_corresponding_lockable_csr 0 6 0.00
sram_ctrl_csr_rw 1.364s 0.000us 0 5 0.00
sram_ctrl_csr_aliasing 0.826s 0.000us 0 1 0.00
mem_walk 0 8 0.00
sram_ctrl_mem_walk 1.557s 0.000us 0 8 0.00
mem_partial_access 0 8 0.00
sram_ctrl_mem_partial_access 1.901s 0.000us 0 8 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 0 8 0.00
sram_ctrl_multiple_keys 1.533s 0.000us 0 8 0.00
stress_pipeline 0 8 0.00
sram_ctrl_stress_pipeline 1.593s 0.000us 0 8 0.00
bijection 0 8 0.00
sram_ctrl_bijection 1.572s 0.000us 0 8 0.00
access_during_key_req 0 8 0.00
sram_ctrl_access_during_key_req 1.305s 0.000us 0 8 0.00
lc_escalation 0 8 0.00
sram_ctrl_lc_escalation 0.882s 0.000us 0 8 0.00
executable 0 8 0.00
sram_ctrl_executable 1.885s 0.000us 0 8 0.00
partial_access 0 16 0.00
sram_ctrl_partial_access 1.400s 0.000us 0 8 0.00
sram_ctrl_partial_access_b2b 2.030s 0.000us 0 8 0.00
max_throughput 0 24 0.00
sram_ctrl_max_throughput 1.621s 0.000us 0 8 0.00
sram_ctrl_throughput_w_partial_write 0.890s 0.000us 0 8 0.00
sram_ctrl_throughput_w_readback 1.557s 0.000us 0 8 0.00
regwen 0 8 0.00
sram_ctrl_regwen 1.400s 0.000us 0 8 0.00
ram_cfg 0 8 0.00
sram_ctrl_ram_cfg 1.442s 0.000us 0 8 0.00
non_pow2_mem_size 0 24 0.00
sram_ctrl_smoke 1.362s 0.000us 0 8 0.00
sram_ctrl_partial_access 1.400s 0.000us 0 8 0.00
sram_ctrl_access_during_key_req 1.305s 0.000us 0 8 0.00
stress_all 0 8 0.00
sram_ctrl_stress_all 0.606s 0.000us 0 8 0.00
alert_test 0 10 0.00
sram_ctrl_alert_test 1.565s 0.000us 0 10 0.00
tl_d_oob_addr_access 0 25 0.00
sram_ctrl_tl_errors 2.668s 0.000us 0 25 0.00
tl_d_illegal_access 0 25 0.00
sram_ctrl_tl_errors 2.668s 0.000us 0 25 0.00
tl_d_outstanding_access 0 12 0.00
sram_ctrl_csr_hw_reset 1.369s 0.000us 0 1 0.00
sram_ctrl_csr_rw 1.364s 0.000us 0 5 0.00
sram_ctrl_csr_aliasing 0.826s 0.000us 0 1 0.00
sram_ctrl_same_csr_outstanding 0.868s 0.000us 0 5 0.00
tl_d_partial_access 0 12 0.00
sram_ctrl_csr_hw_reset 1.369s 0.000us 0 1 0.00
sram_ctrl_csr_rw 1.364s 0.000us 0 5 0.00
sram_ctrl_csr_aliasing 0.826s 0.000us 0 1 0.00
sram_ctrl_same_csr_outstanding 0.868s 0.000us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 0 5 0.00
sram_ctrl_passthru_mem_tl_intg_err 1.837s 0.000us 0 5 0.00
tl_intg_err 0 30 0.00
sram_ctrl_sec_cm 1.824s 0.000us 0 5 0.00
sram_ctrl_tl_intg_err 2.490s 0.000us 0 25 0.00
prim_count_check 0 5 0.00
sram_ctrl_sec_cm 1.824s 0.000us 0 5 0.00
sec_cm_bus_integrity 0 25 0.00
sram_ctrl_tl_intg_err 2.490s 0.000us 0 25 0.00
sec_cm_ctrl_config_regwen 0 8 0.00
sram_ctrl_regwen 1.400s 0.000us 0 8 0.00
sec_cm_readback_config_regwen 0 8 0.00
sram_ctrl_regwen 1.400s 0.000us 0 8 0.00
sec_cm_exec_config_regwen 0 5 0.00
sram_ctrl_csr_rw 1.364s 0.000us 0 5 0.00
sec_cm_exec_config_mubi 0 8 0.00
sram_ctrl_executable 1.885s 0.000us 0 8 0.00
sec_cm_exec_intersig_mubi 0 8 0.00
sram_ctrl_executable 1.885s 0.000us 0 8 0.00
sec_cm_lc_hw_debug_en_intersig_mubi 0 8 0.00
sram_ctrl_executable 1.885s 0.000us 0 8 0.00
sec_cm_lc_escalate_en_intersig_mubi 0 8 0.00
sram_ctrl_lc_escalation 0.882s 0.000us 0 8 0.00
sec_cm_prim_ram_ctrl_mubi 0 8 0.00
sram_ctrl_mubi_enc_err 1.435s 0.000us 0 8 0.00
sec_cm_mem_integrity 0 5 0.00
sram_ctrl_passthru_mem_tl_intg_err 1.837s 0.000us 0 5 0.00
sec_cm_mem_readback 0 8 0.00
sram_ctrl_readback_err 1.427s 0.000us 0 8 0.00
sec_cm_mem_scramble 0 8 0.00
sram_ctrl_smoke 1.362s 0.000us 0 8 0.00
sec_cm_addr_scramble 0 8 0.00
sram_ctrl_smoke 1.362s 0.000us 0 8 0.00
sec_cm_instr_bus_lc_gated 0 8 0.00
sram_ctrl_executable 1.885s 0.000us 0 8 0.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 5 0.00
sram_ctrl_sec_cm 1.824s 0.000us 0 5 0.00
sec_cm_key_global_esc 0 8 0.00
sram_ctrl_lc_escalation 0.882s 0.000us 0 8 0.00
sec_cm_key_local_esc 0 5 0.00
sram_ctrl_sec_cm 1.824s 0.000us 0 5 0.00
sec_cm_init_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.824s 0.000us 0 5 0.00
sec_cm_scramble_key_sideload 0 8 0.00
sram_ctrl_smoke 1.362s 0.000us 0 8 0.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 1.824s 0.000us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 8 0.00
sram_ctrl_stress_all_with_rand_reset 1.480s 0.000us 0 8 0.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 248 test runs
sram_ctrl_smoke 19987432019764612693439640134818436473374626762852699625879861665125998589792 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_smoke/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=1719203680 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/0.sram_ctrl_smoke.1719203680 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_smoke.1719203680 -covoverwrite' seed=19987432019764612693439640134818436473374626762852699625879861665125998589792 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19987432019764612693439640134818436473374626762852699625879861665125998589792 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_multiple_keys 90528303611339879580312635204207344960030818218611659212880634023101274953705 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_multiple_keys/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=841127913 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/0.sram_ctrl_multiple_keys.841127913 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_multiple_keys.841127913 -covoverwrite' seed=90528303611339879580312635204207344960030818218611659212880634023101274953705 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90528303611339879580312635204207344960030818218611659212880634023101274953705 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_multiple_keys/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_multiple_keys_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_bijection 43120235753465915923401577496342801459681623590741404444001570144677290052558 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_bijection/latest run_opts='+test_timeout_ns=2000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=290982862 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/0.sram_ctrl_bijection.290982862 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_bijection.290982862 -covoverwrite' seed=43120235753465915923401577496342801459681623590741404444001570144677290052558 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43120235753465915923401577496342801459681623590741404444001570144677290052558 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_bijection/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_bijection_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_pipeline 54167179568101367924102288318569027596191283459209783172842684028565935669373 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_stress_pipeline/latest run_opts='+zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=37273725 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/0.sram_ctrl_stress_pipeline.37273725 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_stress_pipeline.37273725 -covoverwrite' seed=54167179568101367924102288318569027596191283459209783172842684028565935669373 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54167179568101367924102288318569027596191283459209783172842684028565935669373 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_stress_pipeline/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_pipeline_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_partial_access 27932875892117666869917608867960695320185631200588509689245224378422511252461 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_partial_access/latest run_opts='+partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3848254445 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/0.sram_ctrl_partial_access.3848254445 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_partial_access.3848254445 -covoverwrite' seed=27932875892117666869917608867960695320185631200588509689245224378422511252461 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27932875892117666869917608867960695320185631200588509689245224378422511252461 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_partial_access_b2b 110611155706898070836183812652108590692353531912046904116219910664797651757472 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_partial_access_b2b/latest run_opts='+partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=1216899488 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/0.sram_ctrl_partial_access_b2b.1216899488 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_partial_access_b2b.1216899488 -covoverwrite' seed=110611155706898070836183812652108590692353531912046904116219910664797651757472 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110611155706898070836183812652108590692353531912046904116219910664797651757472 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_partial_access_b2b/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_pipeline_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_max_throughput 27227107361602145493769927759260895324608089865064319374339849898432211351620 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_max_throughput/latest run_opts='+zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3377100868 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/0.sram_ctrl_max_throughput.3377100868 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_max_throughput.3377100868 -covoverwrite' seed=27227107361602145493769927759260895324608089865064319374339849898432211351620 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27227107361602145493769927759260895324608089865064319374339849898432211351620 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_max_throughput/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_throughput_w_partial_write 28875873103266834852573205552753938463111014608650733028779897315403671282532 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_throughput_w_partial_write/latest run_opts='+zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3273401188 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/0.sram_ctrl_throughput_w_partial_write.3273401188 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_throughput_w_partial_write.3273401188 -covoverwrite' seed=28875873103266834852573205552753938463111014608650733028779897315403671282532 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28875873103266834852573205552753938463111014608650733028779897315403671282532 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_throughput_w_partial_write/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_throughput_w_readback 49221649939647644208477812881448248646415158024413248002724864864646647392680 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_throughput_w_readback/latest run_opts='+zero_delays=1 +partial_access_pct=0 +init_w_readback=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3192269224 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/0.sram_ctrl_throughput_w_readback.3192269224 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_throughput_w_readback.3192269224 -covoverwrite' seed=49221649939647644208477812881448248646415158024413248002724864864646647392680 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49221649939647644208477812881448248646415158024413248002724864864646647392680 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_throughput_w_readback/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_lc_escalation 78406556389903217739834053719262452863984078454487902801184538782794997144173 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_lc_escalation/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=4083522157 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/0.sram_ctrl_lc_escalation.4083522157 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_lc_escalation.4083522157 -covoverwrite' seed=78406556389903217739834053719262452863984078454487902801184538782794997144173 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78406556389903217739834053719262452863984078454487902801184538782794997144173 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_access_during_key_req 27361044283005947976145767441814311765093280413476661877352520478494273906184 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_access_during_key_req/latest run_opts='+zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=4245497352 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/0.sram_ctrl_access_during_key_req.4245497352 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_access_during_key_req.4245497352 -covoverwrite' seed=27361044283005947976145767441814311765093280413476661877352520478494273906184 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27361044283005947976145767441814311765093280413476661877352520478494273906184 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_access_during_key_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_access_during_key_req_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_executable 14280397725344040552016414895131576891237216230892666692152878765547394294187 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_executable/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3945390507 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/0.sram_ctrl_executable.3945390507 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_executable.3945390507 -covoverwrite' seed=14280397725344040552016414895131576891237216230892666692152878765547394294187 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=14280397725344040552016414895131576891237216230892666692152878765547394294187 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_executable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_executable_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_regwen 60391964643322372675421550966367825654182375005249722261895218149456849924064 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_regwen/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2637688800 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/0.sram_ctrl_regwen.2637688800 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_regwen.2637688800 -covoverwrite' seed=60391964643322372675421550966367825654182375005249722261895218149456849924064 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=60391964643322372675421550966367825654182375005249722261895218149456849924064 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_ram_cfg 22997329131328589559087713821550278992347421716192809948193615062846910696956 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_ram_cfg/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3968536060 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/0.sram_ctrl_ram_cfg.3968536060 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_ram_cfg.3968536060 -covoverwrite' seed=22997329131328589559087713821550278992347421716192809948193615062846910696956 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22997329131328589559087713821550278992347421716192809948193615062846910696956 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_ram_cfg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_ram_cfg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mem_walk 102279586043051523193588242059671353354871005771441702679203082064381535951518 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_mem_walk/latest run_opts='+csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3805649566 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/0.sram_ctrl_mem_walk.3805649566 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_mem_walk.3805649566 -covoverwrite' seed=102279586043051523193588242059671353354871005771441702679203082064381535951518 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102279586043051523193588242059671353354871005771441702679203082064381535951518 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_mem_walk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mem_partial_access 56865442725767973561890169109621068292766369423747767170859528846937669447250 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_mem_partial_access/latest run_opts='+run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2116234834 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/0.sram_ctrl_mem_partial_access.2116234834 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_mem_partial_access.2116234834 -covoverwrite' seed=56865442725767973561890169109621068292766369423747767170859528846937669447250 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56865442725767973561890169109621068292766369423747767170859528846937669447250 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_mem_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_readback_err 57466512109126721919996621138147756406985597250162383741740482079829872431197 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_readback_err/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2250068061 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/0.sram_ctrl_readback_err.2250068061 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_readback_err.2250068061 -covoverwrite' seed=57466512109126721919996621138147756406985597250162383741740482079829872431197 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57466512109126721919996621138147756406985597250162383741740482079829872431197 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_readback_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_readback_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mubi_enc_err 113102124449760730322877913324450238262239720106044329599906750382581931621463 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_mubi_enc_err/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=586464343 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mubi_enc_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/0.sram_ctrl_mubi_enc_err.586464343 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_mubi_enc_err.586464343 -covoverwrite' seed=113102124449760730322877913324450238262239720106044329599906750382581931621463 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113102124449760730322877913324450238262239720106044329599906750382581931621463 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_mubi_enc_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_mubi_enc_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_all_with_rand_reset 33782355239085932862281828274767278253973893242040569931220751180192926800542 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3833993886 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3833993886 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_stress_all_with_rand_reset.3833993886 -covoverwrite' seed=33782355239085932862281828274767278253973893242040569931220751180192926800542 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33782355239085932862281828274767278253973893242040569931220751180192926800542 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_all 24772752306468519796975830125782702483073815397197003596389002695619242946675 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_stress_all/latest run_opts='+test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=367063155 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/0.sram_ctrl_stress_all.367063155 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_stress_all.367063155 -covoverwrite' seed=24772752306468519796975830125782702483073815397197003596389002695619242946675 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24772752306468519796975830125782702483073815397197003596389002695619242946675 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_sec_cm 101233967017980124378753137432637023234246511759804176869526605481839663950459 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=666282619 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/0.sram_ctrl_sec_cm.666282619 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_sec_cm.666282619 -covoverwrite' seed=101233967017980124378753137432637023234246511759804176869526605481839663950459 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101233967017980124378753137432637023234246511759804176869526605481839663950459 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_passthru_mem_tl_intg_err 104010061746651436829503792881762684746799644013838013930950409742855988549028 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_passthru_mem_tl_intg_err/latest run_opts='+run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2949354916 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.2949354916 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.sram_ctrl_passthru_mem_tl_intg_err.2949354916 -covoverwrite' seed=104010061746651436829503792881762684746799644013838013930950409742855988549028 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104010061746651436829503792881762684746799644013838013930950409742855988549028 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_passthru_mem_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 85283765073488761339115594295806713751204419025490457098285477238721345388636 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4151214172 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/0.sram_ctrl_tl_errors.4151214172 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.sram_ctrl_tl_errors.4151214172 -covoverwrite' seed=85283765073488761339115594295806713751204419025490457098285477238721345388636 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85283765073488761339115594295806713751204419025490457098285477238721345388636 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 68446359629324743693630384568231089526807294001773639011775947020558428598431 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=599584927 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.599584927 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.sram_ctrl_tl_intg_err.599584927 -covoverwrite' seed=68446359629324743693630384568231089526807294001773639011775947020558428598431 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68446359629324743693630384568231089526807294001773639011775947020558428598431 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_alert_test 37289428325697472483404274082324468078915802444336166526290966924478330894589 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2576546045 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/0.sram_ctrl_alert_test.2576546045 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_alert_test.2576546045 -covoverwrite' seed=37289428325697472483404274082324468078915802444336166526290966924478330894589 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37289428325697472483404274082324468078915802444336166526290966924478330894589 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_csr_hw_reset 105888344380734625828714530525500396237869758707828062839112557568859768380681 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_csr_hw_reset/latest run_opts='+csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2020629769 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.2020629769 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.sram_ctrl_csr_hw_reset.2020629769 -covoverwrite' seed=105888344380734625828714530525500396237869758707828062839112557568859768380681 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105888344380734625828714530525500396237869758707828062839112557568859768380681 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_csr_rw 69854546966171076145834914908633491047156760968200759342693296740174492559375 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_csr_rw/latest run_opts='+csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4121651215 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/0.sram_ctrl_csr_rw.4121651215 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.sram_ctrl_csr_rw.4121651215 -covoverwrite' seed=69854546966171076145834914908633491047156760968200759342693296740174492559375 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69854546966171076145834914908633491047156760968200759342693296740174492559375 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_csr_bit_bash 97674692237690364864233309103325233464484299170499977748410558947010650701236 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_csr_bit_bash/latest run_opts='+csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4240571828 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.4240571828 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.sram_ctrl_csr_bit_bash.4240571828 -covoverwrite' seed=97674692237690364864233309103325233464484299170499977748410558947010650701236 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97674692237690364864233309103325233464484299170499977748410558947010650701236 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_csr_aliasing 84957357913054285379940788925829187255805184036329822370096517983202059907073 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_csr_aliasing/latest run_opts='+csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4247154689 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.4247154689 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.sram_ctrl_csr_aliasing.4247154689 -covoverwrite' seed=84957357913054285379940788925829187255805184036329822370096517983202059907073 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84957357913054285379940788925829187255805184036329822370096517983202059907073 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_same_csr_outstanding 90633933144541725256341812226572383850659677342863451691723657760667334655575 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1879096919 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1879096919 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.sram_ctrl_same_csr_outstanding.1879096919 -covoverwrite' seed=90633933144541725256341812226572383850659677342863451691723657760667334655575 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90633933144541725256341812226572383850659677342863451691723657760667334655575 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_csr_mem_rw_with_rand_reset 87901023484800622251025974929746936712102779769301655002459277890918649210923 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1223731243 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.1223731243 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.sram_ctrl_csr_mem_rw_with_rand_reset.1223731243 -covoverwrite' seed=87901023484800622251025974929746936712102779769301655002459277890918649210923 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87901023484800622251025974929746936712102779769301655002459277890918649210923 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_smoke 97229741166257483975940054947112434865504115102508851276308870392914159534275 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_smoke/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3947823299 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/1.sram_ctrl_smoke.3947823299 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_smoke.3947823299 -covoverwrite' seed=97229741166257483975940054947112434865504115102508851276308870392914159534275 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97229741166257483975940054947112434865504115102508851276308870392914159534275 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_multiple_keys 102694978189980177757994271258542384279624420711855357405634409894853729334534 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_multiple_keys/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2106864902 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/1.sram_ctrl_multiple_keys.2106864902 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_multiple_keys.2106864902 -covoverwrite' seed=102694978189980177757994271258542384279624420711855357405634409894853729334534 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102694978189980177757994271258542384279624420711855357405634409894853729334534 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_multiple_keys/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_multiple_keys_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_bijection 24114463121704067651918107810682674115190544169206338734007239162950326381209 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_bijection/latest run_opts='+test_timeout_ns=2000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=236939929 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/1.sram_ctrl_bijection.236939929 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_bijection.236939929 -covoverwrite' seed=24114463121704067651918107810682674115190544169206338734007239162950326381209 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24114463121704067651918107810682674115190544169206338734007239162950326381209 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_bijection/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_bijection_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_pipeline 48314943932650413989745784798809271000858689813276749510722526244574214399224 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_stress_pipeline/latest run_opts='+zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=4140737784 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/1.sram_ctrl_stress_pipeline.4140737784 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_stress_pipeline.4140737784 -covoverwrite' seed=48314943932650413989745784798809271000858689813276749510722526244574214399224 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48314943932650413989745784798809271000858689813276749510722526244574214399224 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_stress_pipeline/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_pipeline_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_partial_access 9681446235826135761191860823491713572178077507321186120771329583760531509773 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_partial_access/latest run_opts='+partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=962843149 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/1.sram_ctrl_partial_access.962843149 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_partial_access.962843149 -covoverwrite' seed=9681446235826135761191860823491713572178077507321186120771329583760531509773 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9681446235826135761191860823491713572178077507321186120771329583760531509773 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_partial_access_b2b 107272351794177184398492366316191767537922695359138579149076915679819575856155 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_partial_access_b2b/latest run_opts='+partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=4255124507 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/1.sram_ctrl_partial_access_b2b.4255124507 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_partial_access_b2b.4255124507 -covoverwrite' seed=107272351794177184398492366316191767537922695359138579149076915679819575856155 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107272351794177184398492366316191767537922695359138579149076915679819575856155 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_partial_access_b2b/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_pipeline_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_max_throughput 42384709814243675244219715659398958053403989351926833098670161518068027433260 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_max_throughput/latest run_opts='+zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3750568236 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/1.sram_ctrl_max_throughput.3750568236 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_max_throughput.3750568236 -covoverwrite' seed=42384709814243675244219715659398958053403989351926833098670161518068027433260 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42384709814243675244219715659398958053403989351926833098670161518068027433260 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_max_throughput/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_throughput_w_partial_write 111626847058848745953774553829494176564122143009012959729070306325888004086190 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_throughput_w_partial_write/latest run_opts='+zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2784319918 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/1.sram_ctrl_throughput_w_partial_write.2784319918 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_throughput_w_partial_write.2784319918 -covoverwrite' seed=111626847058848745953774553829494176564122143009012959729070306325888004086190 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111626847058848745953774553829494176564122143009012959729070306325888004086190 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_throughput_w_partial_write/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_throughput_w_readback 28802823854623297862326259565460276283831437896191224708902981508560895321076 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_throughput_w_readback/latest run_opts='+zero_delays=1 +partial_access_pct=0 +init_w_readback=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=1896063988 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/1.sram_ctrl_throughput_w_readback.1896063988 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_throughput_w_readback.1896063988 -covoverwrite' seed=28802823854623297862326259565460276283831437896191224708902981508560895321076 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28802823854623297862326259565460276283831437896191224708902981508560895321076 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_throughput_w_readback/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_lc_escalation 25283790389997141440151398661874048542039751618647192230787754279794718228186 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_lc_escalation/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=1302019802 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/1.sram_ctrl_lc_escalation.1302019802 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_lc_escalation.1302019802 -covoverwrite' seed=25283790389997141440151398661874048542039751618647192230787754279794718228186 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25283790389997141440151398661874048542039751618647192230787754279794718228186 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_access_during_key_req 68295248895552238144832974381678334333426024404843756824188812150292713161591 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_access_during_key_req/latest run_opts='+zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=1372963703 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/1.sram_ctrl_access_during_key_req.1372963703 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_access_during_key_req.1372963703 -covoverwrite' seed=68295248895552238144832974381678334333426024404843756824188812150292713161591 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68295248895552238144832974381678334333426024404843756824188812150292713161591 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_access_during_key_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_access_during_key_req_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_executable 17397066712054556638023588015426301484488971237433857799159963332423811476584 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_executable/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3076664424 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/1.sram_ctrl_executable.3076664424 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_executable.3076664424 -covoverwrite' seed=17397066712054556638023588015426301484488971237433857799159963332423811476584 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17397066712054556638023588015426301484488971237433857799159963332423811476584 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_executable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_executable_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_regwen 28157890268711185677831601657864896531240141046345808886252223931959268076696 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_regwen/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3392662680 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/1.sram_ctrl_regwen.3392662680 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_regwen.3392662680 -covoverwrite' seed=28157890268711185677831601657864896531240141046345808886252223931959268076696 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28157890268711185677831601657864896531240141046345808886252223931959268076696 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_ram_cfg 108799744667134302532057303332516654243462861249415026082371886285755944840757 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_ram_cfg/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2613095989 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/1.sram_ctrl_ram_cfg.2613095989 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_ram_cfg.2613095989 -covoverwrite' seed=108799744667134302532057303332516654243462861249415026082371886285755944840757 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108799744667134302532057303332516654243462861249415026082371886285755944840757 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_ram_cfg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_ram_cfg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mem_walk 64665303817722170195516799828973174621810388270569371502807474177830280367402 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_mem_walk/latest run_opts='+csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=590744874 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/1.sram_ctrl_mem_walk.590744874 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_mem_walk.590744874 -covoverwrite' seed=64665303817722170195516799828973174621810388270569371502807474177830280367402 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64665303817722170195516799828973174621810388270569371502807474177830280367402 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_mem_walk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mem_partial_access 67581015772171875902492002236446708047365361731091592166427395511101332824941 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_mem_partial_access/latest run_opts='+run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=1664525165 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/1.sram_ctrl_mem_partial_access.1664525165 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_mem_partial_access.1664525165 -covoverwrite' seed=67581015772171875902492002236446708047365361731091592166427395511101332824941 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67581015772171875902492002236446708047365361731091592166427395511101332824941 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_mem_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_readback_err 110123484017092087500988059362399860839444384091826348801526167005011427565770 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_readback_err/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=4226916554 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/1.sram_ctrl_readback_err.4226916554 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_readback_err.4226916554 -covoverwrite' seed=110123484017092087500988059362399860839444384091826348801526167005011427565770 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110123484017092087500988059362399860839444384091826348801526167005011427565770 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_readback_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_readback_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mubi_enc_err 101207968213154981118108274805082624748974439004181755649010375760764568848453 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_mubi_enc_err/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=1966065733 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mubi_enc_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/1.sram_ctrl_mubi_enc_err.1966065733 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_mubi_enc_err.1966065733 -covoverwrite' seed=101207968213154981118108274805082624748974439004181755649010375760764568848453 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101207968213154981118108274805082624748974439004181755649010375760764568848453 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_mubi_enc_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_mubi_enc_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_all_with_rand_reset 43359457342267211423834143371535473990250940249351346134109376971479916743010 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=238553442 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.238553442 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_stress_all_with_rand_reset.238553442 -covoverwrite' seed=43359457342267211423834143371535473990250940249351346134109376971479916743010 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43359457342267211423834143371535473990250940249351346134109376971479916743010 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_all 52615072744982108953255845724387347263151274007893521482600161682310144552409 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_stress_all/latest run_opts='+test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2202103257 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/1.sram_ctrl_stress_all.2202103257 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_stress_all.2202103257 -covoverwrite' seed=52615072744982108953255845724387347263151274007893521482600161682310144552409 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=52615072744982108953255845724387347263151274007893521482600161682310144552409 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_sec_cm 22232289979637724448995893500958432732255243263645874031282199646731279826194 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=1040743698 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/1.sram_ctrl_sec_cm.1040743698 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_sec_cm.1040743698 -covoverwrite' seed=22232289979637724448995893500958432732255243263645874031282199646731279826194 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22232289979637724448995893500958432732255243263645874031282199646731279826194 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_passthru_mem_tl_intg_err 93537526146515387011920197266394265370586600452189122217234985424572854963216 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_passthru_mem_tl_intg_err/latest run_opts='+run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1258163216 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.1258163216 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.sram_ctrl_passthru_mem_tl_intg_err.1258163216 -covoverwrite' seed=93537526146515387011920197266394265370586600452189122217234985424572854963216 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93537526146515387011920197266394265370586600452189122217234985424572854963216 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_passthru_mem_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 24273072398504467821664638768279868023696666004913262110243607198936860471785 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=104608233 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/1.sram_ctrl_tl_errors.104608233 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.sram_ctrl_tl_errors.104608233 -covoverwrite' seed=24273072398504467821664638768279868023696666004913262110243607198936860471785 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24273072398504467821664638768279868023696666004913262110243607198936860471785 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 102891280558060681271791808202170729721289368359193645805825712100320276013986 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3051512738 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.3051512738 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.sram_ctrl_tl_intg_err.3051512738 -covoverwrite' seed=102891280558060681271791808202170729721289368359193645805825712100320276013986 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102891280558060681271791808202170729721289368359193645805825712100320276013986 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_alert_test 94207215224486444526930358440495599108096757893226003822783953861493791157816 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=1374973496 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/1.sram_ctrl_alert_test.1374973496 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_alert_test.1374973496 -covoverwrite' seed=94207215224486444526930358440495599108096757893226003822783953861493791157816 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94207215224486444526930358440495599108096757893226003822783953861493791157816 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_csr_rw 115038130988758723658247888273866765251414663533465029598145134030721769118962 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_csr_rw/latest run_opts='+csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4134378738 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/1.sram_ctrl_csr_rw.4134378738 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.sram_ctrl_csr_rw.4134378738 -covoverwrite' seed=115038130988758723658247888273866765251414663533465029598145134030721769118962 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115038130988758723658247888273866765251414663533465029598145134030721769118962 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_same_csr_outstanding 104885076284156144072073102660765837593378137624632389588027640302089572607850 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=167143274 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.167143274 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.sram_ctrl_same_csr_outstanding.167143274 -covoverwrite' seed=104885076284156144072073102660765837593378137624632389588027640302089572607850 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104885076284156144072073102660765837593378137624632389588027640302089572607850 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_csr_mem_rw_with_rand_reset 104623506180659654478649871719574150189331123483648252117983523699850977660369 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1586417105 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.1586417105 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.sram_ctrl_csr_mem_rw_with_rand_reset.1586417105 -covoverwrite' seed=104623506180659654478649871719574150189331123483648252117983523699850977660369 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104623506180659654478649871719574150189331123483648252117983523699850977660369 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_smoke 47105030882367698299950307143376660012832745320773808484915573974929348946370 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_smoke/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=515828162 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/2.sram_ctrl_smoke.515828162 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_smoke.515828162 -covoverwrite' seed=47105030882367698299950307143376660012832745320773808484915573974929348946370 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47105030882367698299950307143376660012832745320773808484915573974929348946370 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_multiple_keys 1376014219997305535719422466673545077543902978572117527223071113287938944820 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_multiple_keys/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=719662900 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/2.sram_ctrl_multiple_keys.719662900 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_multiple_keys.719662900 -covoverwrite' seed=1376014219997305535719422466673545077543902978572117527223071113287938944820 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1376014219997305535719422466673545077543902978572117527223071113287938944820 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_multiple_keys/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_multiple_keys_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_bijection 45148662570498104506958768117057301546365212764530177065520047020007922522978 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_bijection/latest run_opts='+test_timeout_ns=2000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3763264354 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/2.sram_ctrl_bijection.3763264354 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_bijection.3763264354 -covoverwrite' seed=45148662570498104506958768117057301546365212764530177065520047020007922522978 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45148662570498104506958768117057301546365212764530177065520047020007922522978 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_bijection/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_bijection_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_pipeline 105785577947134295657093827535970016495890162561180508420132039231970847268513 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_stress_pipeline/latest run_opts='+zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=1883283105 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/2.sram_ctrl_stress_pipeline.1883283105 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_stress_pipeline.1883283105 -covoverwrite' seed=105785577947134295657093827535970016495890162561180508420132039231970847268513 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105785577947134295657093827535970016495890162561180508420132039231970847268513 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_stress_pipeline/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_pipeline_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_partial_access 63323894362311188778295279561973444670692618225772562263512788739686896417486 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_partial_access/latest run_opts='+partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3390487246 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/2.sram_ctrl_partial_access.3390487246 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_partial_access.3390487246 -covoverwrite' seed=63323894362311188778295279561973444670692618225772562263512788739686896417486 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63323894362311188778295279561973444670692618225772562263512788739686896417486 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_partial_access_b2b 68593035237298884952843211094095671553094674916680918331716525463082038608167 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_partial_access_b2b/latest run_opts='+partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=906903847 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/2.sram_ctrl_partial_access_b2b.906903847 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_partial_access_b2b.906903847 -covoverwrite' seed=68593035237298884952843211094095671553094674916680918331716525463082038608167 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68593035237298884952843211094095671553094674916680918331716525463082038608167 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_partial_access_b2b/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_pipeline_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_max_throughput 10795811914869916219299574725410610570264818461270125302043691076232629949055 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_max_throughput/latest run_opts='+zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=1512804991 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/2.sram_ctrl_max_throughput.1512804991 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_max_throughput.1512804991 -covoverwrite' seed=10795811914869916219299574725410610570264818461270125302043691076232629949055 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10795811914869916219299574725410610570264818461270125302043691076232629949055 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_max_throughput/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_throughput_w_partial_write 111967857294875025703675335558980266721609967255130635440272922314594079328428 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_throughput_w_partial_write/latest run_opts='+zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=4286695596 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/2.sram_ctrl_throughput_w_partial_write.4286695596 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_throughput_w_partial_write.4286695596 -covoverwrite' seed=111967857294875025703675335558980266721609967255130635440272922314594079328428 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111967857294875025703675335558980266721609967255130635440272922314594079328428 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_throughput_w_partial_write/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_throughput_w_readback 69767416002901768965412087593863201460766620768241767467839470853508438631725 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_throughput_w_readback/latest run_opts='+zero_delays=1 +partial_access_pct=0 +init_w_readback=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3981911341 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/2.sram_ctrl_throughput_w_readback.3981911341 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_throughput_w_readback.3981911341 -covoverwrite' seed=69767416002901768965412087593863201460766620768241767467839470853508438631725 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69767416002901768965412087593863201460766620768241767467839470853508438631725 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_throughput_w_readback/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_lc_escalation 80766870479289141350156231684089209930634843023348837829695051246972522872158 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_lc_escalation/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2057715038 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/2.sram_ctrl_lc_escalation.2057715038 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_lc_escalation.2057715038 -covoverwrite' seed=80766870479289141350156231684089209930634843023348837829695051246972522872158 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80766870479289141350156231684089209930634843023348837829695051246972522872158 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_access_during_key_req 81095091126026885890025422490993955286691149584234742863519076000141242998625 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_access_during_key_req/latest run_opts='+zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=1556553569 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/2.sram_ctrl_access_during_key_req.1556553569 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_access_during_key_req.1556553569 -covoverwrite' seed=81095091126026885890025422490993955286691149584234742863519076000141242998625 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81095091126026885890025422490993955286691149584234742863519076000141242998625 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_access_during_key_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_access_during_key_req_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_executable 58556654613769194023614870571820593235650389497309220779024586206475251567725 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_executable/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3097971821 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/2.sram_ctrl_executable.3097971821 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_executable.3097971821 -covoverwrite' seed=58556654613769194023614870571820593235650389497309220779024586206475251567725 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58556654613769194023614870571820593235650389497309220779024586206475251567725 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_executable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_executable_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_regwen 84672221942071755569324722807261692003134325674680099223831780506024258894140 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_regwen/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=1325201724 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/2.sram_ctrl_regwen.1325201724 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_regwen.1325201724 -covoverwrite' seed=84672221942071755569324722807261692003134325674680099223831780506024258894140 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84672221942071755569324722807261692003134325674680099223831780506024258894140 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_ram_cfg 67946864079009322745658207148992222062139061650338850586887862109406695416752 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_ram_cfg/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=123102128 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/2.sram_ctrl_ram_cfg.123102128 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_ram_cfg.123102128 -covoverwrite' seed=67946864079009322745658207148992222062139061650338850586887862109406695416752 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67946864079009322745658207148992222062139061650338850586887862109406695416752 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_ram_cfg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_ram_cfg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mem_walk 5900965612326944686556909276247017125150757236043650415934864773212013752244 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_mem_walk/latest run_opts='+csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=4019351476 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/2.sram_ctrl_mem_walk.4019351476 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_mem_walk.4019351476 -covoverwrite' seed=5900965612326944686556909276247017125150757236043650415934864773212013752244 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5900965612326944686556909276247017125150757236043650415934864773212013752244 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_mem_walk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mem_partial_access 18604450674361262000833855808103854805048370572823397748195286206819785399099 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_mem_partial_access/latest run_opts='+run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2470861627 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/2.sram_ctrl_mem_partial_access.2470861627 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_mem_partial_access.2470861627 -covoverwrite' seed=18604450674361262000833855808103854805048370572823397748195286206819785399099 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18604450674361262000833855808103854805048370572823397748195286206819785399099 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_mem_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_readback_err 11181179385041029695046864899748541099558930992857358383118511792389606059690 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_readback_err/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2226106026 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/2.sram_ctrl_readback_err.2226106026 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_readback_err.2226106026 -covoverwrite' seed=11181179385041029695046864899748541099558930992857358383118511792389606059690 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11181179385041029695046864899748541099558930992857358383118511792389606059690 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_readback_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_readback_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mubi_enc_err 9864523237984371757219990197458813800927619366928429207421833437468061536017 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_mubi_enc_err/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3122859793 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mubi_enc_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/2.sram_ctrl_mubi_enc_err.3122859793 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_mubi_enc_err.3122859793 -covoverwrite' seed=9864523237984371757219990197458813800927619366928429207421833437468061536017 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9864523237984371757219990197458813800927619366928429207421833437468061536017 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_mubi_enc_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_mubi_enc_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_all_with_rand_reset 100339433496279914519174810322640278413876556412806434232665854688501002084949 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3315278421 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.3315278421 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_stress_all_with_rand_reset.3315278421 -covoverwrite' seed=100339433496279914519174810322640278413876556412806434232665854688501002084949 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100339433496279914519174810322640278413876556412806434232665854688501002084949 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_all 32956637408835531427740336421750204478049532372317548826777902642650794101619 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_stress_all/latest run_opts='+test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2859928435 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/2.sram_ctrl_stress_all.2859928435 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_stress_all.2859928435 -covoverwrite' seed=32956637408835531427740336421750204478049532372317548826777902642650794101619 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32956637408835531427740336421750204478049532372317548826777902642650794101619 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_sec_cm 107715331610318045703040695273850084110305630271104003990497151188087664413417 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2389052137 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/2.sram_ctrl_sec_cm.2389052137 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_sec_cm.2389052137 -covoverwrite' seed=107715331610318045703040695273850084110305630271104003990497151188087664413417 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107715331610318045703040695273850084110305630271104003990497151188087664413417 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_passthru_mem_tl_intg_err 50800497497777847617241891450439347566423044200777383084440594991078510498001 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_passthru_mem_tl_intg_err/latest run_opts='+run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2391085265 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2391085265 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.sram_ctrl_passthru_mem_tl_intg_err.2391085265 -covoverwrite' seed=50800497497777847617241891450439347566423044200777383084440594991078510498001 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50800497497777847617241891450439347566423044200777383084440594991078510498001 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_passthru_mem_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 73803407944546074655164703478919745420096457191093775509038875540787434905099 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=23354891 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/2.sram_ctrl_tl_errors.23354891 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.sram_ctrl_tl_errors.23354891 -covoverwrite' seed=73803407944546074655164703478919745420096457191093775509038875540787434905099 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73803407944546074655164703478919745420096457191093775509038875540787434905099 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 58150856306440940086112722260024211312945800232128599480442365264347388382643 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1088097715 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.1088097715 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.sram_ctrl_tl_intg_err.1088097715 -covoverwrite' seed=58150856306440940086112722260024211312945800232128599480442365264347388382643 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58150856306440940086112722260024211312945800232128599480442365264347388382643 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_alert_test 111225102648294711386737379870802494699120871666580430884295436979016613254673 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3863238161 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/2.sram_ctrl_alert_test.3863238161 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_alert_test.3863238161 -covoverwrite' seed=111225102648294711386737379870802494699120871666580430884295436979016613254673 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111225102648294711386737379870802494699120871666580430884295436979016613254673 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_csr_rw 31914504346472827459793136475976954516752722281132445380723553195556418968934 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_csr_rw/latest run_opts='+csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1771658598 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1771658598 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.sram_ctrl_csr_rw.1771658598 -covoverwrite' seed=31914504346472827459793136475976954516752722281132445380723553195556418968934 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31914504346472827459793136475976954516752722281132445380723553195556418968934 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_same_csr_outstanding 31900345973669895589256333411676648502320128171264776023573743230220167339703 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1050468023 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.1050468023 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.sram_ctrl_same_csr_outstanding.1050468023 -covoverwrite' seed=31900345973669895589256333411676648502320128171264776023573743230220167339703 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31900345973669895589256333411676648502320128171264776023573743230220167339703 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_csr_mem_rw_with_rand_reset 49704717423073670040499138816748165439297095534052975611689212675819905713580 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3033499052 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.3033499052 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.sram_ctrl_csr_mem_rw_with_rand_reset.3033499052 -covoverwrite' seed=49704717423073670040499138816748165439297095534052975611689212675819905713580 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49704717423073670040499138816748165439297095534052975611689212675819905713580 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_smoke 12048977644867019439763414072475176683325237616250861947689571156512259532057 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_smoke/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2070242585 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/3.sram_ctrl_smoke.2070242585 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_smoke.2070242585 -covoverwrite' seed=12048977644867019439763414072475176683325237616250861947689571156512259532057 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12048977644867019439763414072475176683325237616250861947689571156512259532057 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_multiple_keys 105466967170053145819847416947783826646288761760394711481139459415143129210216 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_multiple_keys/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3750944104 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/3.sram_ctrl_multiple_keys.3750944104 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_multiple_keys.3750944104 -covoverwrite' seed=105466967170053145819847416947783826646288761760394711481139459415143129210216 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105466967170053145819847416947783826646288761760394711481139459415143129210216 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_multiple_keys/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_multiple_keys_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_bijection 94294723851387574652294688957786074601543441390619022824949412067624894643017 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_bijection/latest run_opts='+test_timeout_ns=2000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3153902409 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/3.sram_ctrl_bijection.3153902409 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_bijection.3153902409 -covoverwrite' seed=94294723851387574652294688957786074601543441390619022824949412067624894643017 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94294723851387574652294688957786074601543441390619022824949412067624894643017 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_bijection/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_bijection_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_pipeline 79134553739734370250597048004386978287315481980741787341344630331956346351132 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_stress_pipeline/latest run_opts='+zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=286912028 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/3.sram_ctrl_stress_pipeline.286912028 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_stress_pipeline.286912028 -covoverwrite' seed=79134553739734370250597048004386978287315481980741787341344630331956346351132 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79134553739734370250597048004386978287315481980741787341344630331956346351132 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_stress_pipeline/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_pipeline_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_partial_access 51900501641415783018741555751001088531830832537485791295904418402439786063169 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_partial_access/latest run_opts='+partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=1058727233 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/3.sram_ctrl_partial_access.1058727233 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_partial_access.1058727233 -covoverwrite' seed=51900501641415783018741555751001088531830832537485791295904418402439786063169 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51900501641415783018741555751001088531830832537485791295904418402439786063169 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_partial_access_b2b 64328356734824996281609673864079153931500711790857119900549557455024404934551 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_partial_access_b2b/latest run_opts='+partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3336417175 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/3.sram_ctrl_partial_access_b2b.3336417175 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_partial_access_b2b.3336417175 -covoverwrite' seed=64328356734824996281609673864079153931500711790857119900549557455024404934551 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64328356734824996281609673864079153931500711790857119900549557455024404934551 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_partial_access_b2b/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_pipeline_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_max_throughput 93569252210155981525566875732652605151363914645297753607255569665321268472113 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_max_throughput/latest run_opts='+zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=4262258993 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/3.sram_ctrl_max_throughput.4262258993 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_max_throughput.4262258993 -covoverwrite' seed=93569252210155981525566875732652605151363914645297753607255569665321268472113 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93569252210155981525566875732652605151363914645297753607255569665321268472113 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_max_throughput/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_throughput_w_partial_write 101229501801964187265337407473286367613216130407899155289058326278562856303035 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_throughput_w_partial_write/latest run_opts='+zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=4280809915 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/3.sram_ctrl_throughput_w_partial_write.4280809915 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_throughput_w_partial_write.4280809915 -covoverwrite' seed=101229501801964187265337407473286367613216130407899155289058326278562856303035 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=101229501801964187265337407473286367613216130407899155289058326278562856303035 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_throughput_w_partial_write/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_throughput_w_readback 7438061328982481393967204959705423944839366266757718999438192918640897617096 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_throughput_w_readback/latest run_opts='+zero_delays=1 +partial_access_pct=0 +init_w_readback=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2461592776 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/3.sram_ctrl_throughput_w_readback.2461592776 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_throughput_w_readback.2461592776 -covoverwrite' seed=7438061328982481393967204959705423944839366266757718999438192918640897617096 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7438061328982481393967204959705423944839366266757718999438192918640897617096 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_throughput_w_readback/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_lc_escalation 34654445442036593418270865966703122585977914803944697151343761595800470280934 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_lc_escalation/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2647775974 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/3.sram_ctrl_lc_escalation.2647775974 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_lc_escalation.2647775974 -covoverwrite' seed=34654445442036593418270865966703122585977914803944697151343761595800470280934 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34654445442036593418270865966703122585977914803944697151343761595800470280934 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_access_during_key_req 110034297699562267249552060242592563353799821683286410503675668591490062074915 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_access_during_key_req/latest run_opts='+zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2349581347 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/3.sram_ctrl_access_during_key_req.2349581347 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_access_during_key_req.2349581347 -covoverwrite' seed=110034297699562267249552060242592563353799821683286410503675668591490062074915 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110034297699562267249552060242592563353799821683286410503675668591490062074915 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_access_during_key_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_access_during_key_req_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_executable 34670346546534285316154416919423888374472664011463669677233393560784195879368 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_executable/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3752395208 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/3.sram_ctrl_executable.3752395208 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_executable.3752395208 -covoverwrite' seed=34670346546534285316154416919423888374472664011463669677233393560784195879368 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34670346546534285316154416919423888374472664011463669677233393560784195879368 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_executable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_executable_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_regwen 32338316388145484504335769556079991694433520982986960476502408250186009870270 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_regwen/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2486370238 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/3.sram_ctrl_regwen.2486370238 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_regwen.2486370238 -covoverwrite' seed=32338316388145484504335769556079991694433520982986960476502408250186009870270 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32338316388145484504335769556079991694433520982986960476502408250186009870270 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_ram_cfg 80213476376398896570312716129305717540695001970930452608889686686835556142498 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_ram_cfg/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2206649762 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/3.sram_ctrl_ram_cfg.2206649762 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_ram_cfg.2206649762 -covoverwrite' seed=80213476376398896570312716129305717540695001970930452608889686686835556142498 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80213476376398896570312716129305717540695001970930452608889686686835556142498 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_ram_cfg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_ram_cfg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mem_walk 69307247777569669288723167646124139853602005037885189304869837005005671151492 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_mem_walk/latest run_opts='+csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=4021598084 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/3.sram_ctrl_mem_walk.4021598084 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_mem_walk.4021598084 -covoverwrite' seed=69307247777569669288723167646124139853602005037885189304869837005005671151492 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69307247777569669288723167646124139853602005037885189304869837005005671151492 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_mem_walk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mem_partial_access 88415366166913727300534126462365587679091663039760635111182176531793378901883 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_mem_partial_access/latest run_opts='+run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2002878331 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/3.sram_ctrl_mem_partial_access.2002878331 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_mem_partial_access.2002878331 -covoverwrite' seed=88415366166913727300534126462365587679091663039760635111182176531793378901883 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88415366166913727300534126462365587679091663039760635111182176531793378901883 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_mem_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_readback_err 106779333867215849377029328499240725428771137112727395068042918453466101415792 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_readback_err/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2308669296 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/3.sram_ctrl_readback_err.2308669296 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_readback_err.2308669296 -covoverwrite' seed=106779333867215849377029328499240725428771137112727395068042918453466101415792 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106779333867215849377029328499240725428771137112727395068042918453466101415792 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_readback_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_readback_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mubi_enc_err 47754782277137424175986485328325397260679659179880683548849556953241512379217 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_mubi_enc_err/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=821887825 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mubi_enc_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/3.sram_ctrl_mubi_enc_err.821887825 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_mubi_enc_err.821887825 -covoverwrite' seed=47754782277137424175986485328325397260679659179880683548849556953241512379217 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47754782277137424175986485328325397260679659179880683548849556953241512379217 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_mubi_enc_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_mubi_enc_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_all_with_rand_reset 59633925240576072192718547329740405844016332123153595316674300644516249007175 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=1484321863 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.1484321863 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_stress_all_with_rand_reset.1484321863 -covoverwrite' seed=59633925240576072192718547329740405844016332123153595316674300644516249007175 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=59633925240576072192718547329740405844016332123153595316674300644516249007175 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_all 36577908304650638955580797531958518953571024991039599418389961979931384243399 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_stress_all/latest run_opts='+test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=1181377735 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/3.sram_ctrl_stress_all.1181377735 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_stress_all.1181377735 -covoverwrite' seed=36577908304650638955580797531958518953571024991039599418389961979931384243399 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36577908304650638955580797531958518953571024991039599418389961979931384243399 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_sec_cm 286311161034681642439866873235548949518414069771136157858659129182703557753 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3916143737 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/3.sram_ctrl_sec_cm.3916143737 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_sec_cm.3916143737 -covoverwrite' seed=286311161034681642439866873235548949518414069771136157858659129182703557753 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=286311161034681642439866873235548949518414069771136157858659129182703557753 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_passthru_mem_tl_intg_err 111692572061154094766670762053860557743904404107692812610358327079888536329405 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_passthru_mem_tl_intg_err/latest run_opts='+run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=343530685 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.343530685 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.sram_ctrl_passthru_mem_tl_intg_err.343530685 -covoverwrite' seed=111692572061154094766670762053860557743904404107692812610358327079888536329405 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111692572061154094766670762053860557743904404107692812610358327079888536329405 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_passthru_mem_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 71836884116819922396898114445788458783284189874511169081606595862777741904731 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2726759259 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/3.sram_ctrl_tl_errors.2726759259 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.sram_ctrl_tl_errors.2726759259 -covoverwrite' seed=71836884116819922396898114445788458783284189874511169081606595862777741904731 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71836884116819922396898114445788458783284189874511169081606595862777741904731 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 26150197808464722294742627602788562588099490769219401171163376888903507024171 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=803117355 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.803117355 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.sram_ctrl_tl_intg_err.803117355 -covoverwrite' seed=26150197808464722294742627602788562588099490769219401171163376888903507024171 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26150197808464722294742627602788562588099490769219401171163376888903507024171 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_alert_test 102736862151186635200034329266180548944135579811724358152456366393848838266756 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=117743492 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/3.sram_ctrl_alert_test.117743492 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_alert_test.117743492 -covoverwrite' seed=102736862151186635200034329266180548944135579811724358152456366393848838266756 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102736862151186635200034329266180548944135579811724358152456366393848838266756 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_csr_rw 54342754050536231078781816864623043793858703698085468689540637201316922053292 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_csr_rw/latest run_opts='+csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3776762540 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/3.sram_ctrl_csr_rw.3776762540 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.sram_ctrl_csr_rw.3776762540 -covoverwrite' seed=54342754050536231078781816864623043793858703698085468689540637201316922053292 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54342754050536231078781816864623043793858703698085468689540637201316922053292 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_same_csr_outstanding 20885772526514710608447905678913955524360987584509809888830459680037470556696 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=33378840 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.33378840 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.sram_ctrl_same_csr_outstanding.33378840 -covoverwrite' seed=20885772526514710608447905678913955524360987584509809888830459680037470556696 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20885772526514710608447905678913955524360987584509809888830459680037470556696 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_csr_mem_rw_with_rand_reset 19030145241380990596700548617619385097600533123767581957395567893322885396030 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2773644862 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.2773644862 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.sram_ctrl_csr_mem_rw_with_rand_reset.2773644862 -covoverwrite' seed=19030145241380990596700548617619385097600533123767581957395567893322885396030 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19030145241380990596700548617619385097600533123767581957395567893322885396030 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_smoke 9394312712148529468091666170747826597984189380734463114609213618698537166084 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_smoke/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3402917124 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/4.sram_ctrl_smoke.3402917124 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_smoke.3402917124 -covoverwrite' seed=9394312712148529468091666170747826597984189380734463114609213618698537166084 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9394312712148529468091666170747826597984189380734463114609213618698537166084 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_multiple_keys 81895016369471443257139619133941795763328275617256363745761326361247548398892 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_multiple_keys/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=1467440428 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/4.sram_ctrl_multiple_keys.1467440428 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_multiple_keys.1467440428 -covoverwrite' seed=81895016369471443257139619133941795763328275617256363745761326361247548398892 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81895016369471443257139619133941795763328275617256363745761326361247548398892 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_multiple_keys/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_multiple_keys_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_bijection 108779738358700886610562915971941547574644783801847156164498890261262798684675 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_bijection/latest run_opts='+test_timeout_ns=2000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=158335491 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/4.sram_ctrl_bijection.158335491 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_bijection.158335491 -covoverwrite' seed=108779738358700886610562915971941547574644783801847156164498890261262798684675 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108779738358700886610562915971941547574644783801847156164498890261262798684675 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_bijection/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_bijection_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_pipeline 31815842276821251506024871272771905223481316728121068340097021528487200295206 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_stress_pipeline/latest run_opts='+zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=226756902 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/4.sram_ctrl_stress_pipeline.226756902 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_stress_pipeline.226756902 -covoverwrite' seed=31815842276821251506024871272771905223481316728121068340097021528487200295206 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31815842276821251506024871272771905223481316728121068340097021528487200295206 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_stress_pipeline/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_pipeline_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_partial_access 62501341427938919263197249611178111967180995621227930513801498806820811168056 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_partial_access/latest run_opts='+partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3733051704 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/4.sram_ctrl_partial_access.3733051704 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_partial_access.3733051704 -covoverwrite' seed=62501341427938919263197249611178111967180995621227930513801498806820811168056 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62501341427938919263197249611178111967180995621227930513801498806820811168056 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_partial_access_b2b 6188102819482348507497448097898081685549350313985641142370657333470664124651 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_partial_access_b2b/latest run_opts='+partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2251352299 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/4.sram_ctrl_partial_access_b2b.2251352299 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_partial_access_b2b.2251352299 -covoverwrite' seed=6188102819482348507497448097898081685549350313985641142370657333470664124651 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6188102819482348507497448097898081685549350313985641142370657333470664124651 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_partial_access_b2b/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_pipeline_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_max_throughput 64799872034374215844519070208568497162621735126482635059560289064856500171945 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_max_throughput/latest run_opts='+zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3177051305 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/4.sram_ctrl_max_throughput.3177051305 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_max_throughput.3177051305 -covoverwrite' seed=64799872034374215844519070208568497162621735126482635059560289064856500171945 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64799872034374215844519070208568497162621735126482635059560289064856500171945 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_max_throughput/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_throughput_w_partial_write 16817162395838483030444131566057607379648690286203017840610719301949018983139 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_throughput_w_partial_write/latest run_opts='+zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=1204669155 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/4.sram_ctrl_throughput_w_partial_write.1204669155 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_throughput_w_partial_write.1204669155 -covoverwrite' seed=16817162395838483030444131566057607379648690286203017840610719301949018983139 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16817162395838483030444131566057607379648690286203017840610719301949018983139 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_throughput_w_partial_write/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_throughput_w_readback 13279401931640328435852608128280041293372592195940671736664716588418636101966 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_throughput_w_readback/latest run_opts='+zero_delays=1 +partial_access_pct=0 +init_w_readback=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2505488718 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/4.sram_ctrl_throughput_w_readback.2505488718 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_throughput_w_readback.2505488718 -covoverwrite' seed=13279401931640328435852608128280041293372592195940671736664716588418636101966 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13279401931640328435852608128280041293372592195940671736664716588418636101966 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_throughput_w_readback/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_lc_escalation 17067440982752050790002071203682710169377027593297129409780538787341942244655 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_lc_escalation/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3644966191 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/4.sram_ctrl_lc_escalation.3644966191 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_lc_escalation.3644966191 -covoverwrite' seed=17067440982752050790002071203682710169377027593297129409780538787341942244655 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17067440982752050790002071203682710169377027593297129409780538787341942244655 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_access_during_key_req 68723181672507632584383191297765167080662815224993676793046880862732664227924 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_access_during_key_req/latest run_opts='+zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3253520468 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/4.sram_ctrl_access_during_key_req.3253520468 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_access_during_key_req.3253520468 -covoverwrite' seed=68723181672507632584383191297765167080662815224993676793046880862732664227924 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68723181672507632584383191297765167080662815224993676793046880862732664227924 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_access_during_key_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_access_during_key_req_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_executable 52308143323463270992451125628582532366827438543721309999166313052460819265156 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_executable/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3177821828 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/4.sram_ctrl_executable.3177821828 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_executable.3177821828 -covoverwrite' seed=52308143323463270992451125628582532366827438543721309999166313052460819265156 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=52308143323463270992451125628582532366827438543721309999166313052460819265156 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_executable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_executable_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_regwen 9047139266877550564839501739323888011477909887741241410199245197016394206623 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_regwen/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2854587807 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/4.sram_ctrl_regwen.2854587807 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_regwen.2854587807 -covoverwrite' seed=9047139266877550564839501739323888011477909887741241410199245197016394206623 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9047139266877550564839501739323888011477909887741241410199245197016394206623 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_ram_cfg 42824527555027076156444261847000458460282571343429607395733638203552297673127 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_ram_cfg/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3997983143 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/4.sram_ctrl_ram_cfg.3997983143 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_ram_cfg.3997983143 -covoverwrite' seed=42824527555027076156444261847000458460282571343429607395733638203552297673127 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42824527555027076156444261847000458460282571343429607395733638203552297673127 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_ram_cfg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_ram_cfg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mem_walk 28172781344857032882690761918240454743930215373139320170525387663168648453980 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_mem_walk/latest run_opts='+csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2854166364 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/4.sram_ctrl_mem_walk.2854166364 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_mem_walk.2854166364 -covoverwrite' seed=28172781344857032882690761918240454743930215373139320170525387663168648453980 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28172781344857032882690761918240454743930215373139320170525387663168648453980 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_mem_walk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mem_partial_access 11294904797381149014610699027652885140455180036930096005592882243721818010358 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_mem_partial_access/latest run_opts='+run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=1017639670 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/4.sram_ctrl_mem_partial_access.1017639670 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_mem_partial_access.1017639670 -covoverwrite' seed=11294904797381149014610699027652885140455180036930096005592882243721818010358 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11294904797381149014610699027652885140455180036930096005592882243721818010358 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_mem_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_readback_err 82263541293333867857941982025878444804213399670751611058309989954309503817055 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_readback_err/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3905656159 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/4.sram_ctrl_readback_err.3905656159 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_readback_err.3905656159 -covoverwrite' seed=82263541293333867857941982025878444804213399670751611058309989954309503817055 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82263541293333867857941982025878444804213399670751611058309989954309503817055 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_readback_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_readback_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mubi_enc_err 90957643297165060739650459259961904278171942797145347951780951139156323123261 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_mubi_enc_err/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3836395581 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mubi_enc_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/4.sram_ctrl_mubi_enc_err.3836395581 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_mubi_enc_err.3836395581 -covoverwrite' seed=90957643297165060739650459259961904278171942797145347951780951139156323123261 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90957643297165060739650459259961904278171942797145347951780951139156323123261 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_mubi_enc_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_mubi_enc_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_all_with_rand_reset 59964088566374102423763651105670385602773876054428967440486346631062712638029 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=1660049997 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.1660049997 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_stress_all_with_rand_reset.1660049997 -covoverwrite' seed=59964088566374102423763651105670385602773876054428967440486346631062712638029 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=59964088566374102423763651105670385602773876054428967440486346631062712638029 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_all 21225319914655344141141615233774712636286828547619738955269194131278433026152 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_stress_all/latest run_opts='+test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3216965736 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/4.sram_ctrl_stress_all.3216965736 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_stress_all.3216965736 -covoverwrite' seed=21225319914655344141141615233774712636286828547619738955269194131278433026152 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21225319914655344141141615233774712636286828547619738955269194131278433026152 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_sec_cm 106606090308372888483412239192148897359733632735034667932074039575725366315051 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2291664939 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/4.sram_ctrl_sec_cm.2291664939 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_sec_cm.2291664939 -covoverwrite' seed=106606090308372888483412239192148897359733632735034667932074039575725366315051 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106606090308372888483412239192148897359733632735034667932074039575725366315051 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_passthru_mem_tl_intg_err 108607255275302438924022124157532497274861309566884287867003552704616952014608 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_passthru_mem_tl_intg_err/latest run_opts='+run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3291522832 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3291522832 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.sram_ctrl_passthru_mem_tl_intg_err.3291522832 -covoverwrite' seed=108607255275302438924022124157532497274861309566884287867003552704616952014608 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108607255275302438924022124157532497274861309566884287867003552704616952014608 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_passthru_mem_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 87141816391132345276148422291393480683476702233059998115929339747361989141278 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3397460766 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/4.sram_ctrl_tl_errors.3397460766 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.sram_ctrl_tl_errors.3397460766 -covoverwrite' seed=87141816391132345276148422291393480683476702233059998115929339747361989141278 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=87141816391132345276148422291393480683476702233059998115929339747361989141278 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 48547128733772359370143707839107423875472487784792376842998594928874980846980 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3857919364 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.3857919364 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.sram_ctrl_tl_intg_err.3857919364 -covoverwrite' seed=48547128733772359370143707839107423875472487784792376842998594928874980846980 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48547128733772359370143707839107423875472487784792376842998594928874980846980 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_alert_test 2627984890707909298357783982621400518680745994862787374018678506984793682254 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2751967566 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/4.sram_ctrl_alert_test.2751967566 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_alert_test.2751967566 -covoverwrite' seed=2627984890707909298357783982621400518680745994862787374018678506984793682254 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2627984890707909298357783982621400518680745994862787374018678506984793682254 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_csr_rw 81898878559118111439057047705201024353265650700806561588870764412070740572878 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_csr_rw/latest run_opts='+csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3906681550 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3906681550 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.sram_ctrl_csr_rw.3906681550 -covoverwrite' seed=81898878559118111439057047705201024353265650700806561588870764412070740572878 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81898878559118111439057047705201024353265650700806561588870764412070740572878 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_same_csr_outstanding 25426091913299884051777131175022650392940512260996621836439177757956591538101 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2929676213 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2929676213 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.sram_ctrl_same_csr_outstanding.2929676213 -covoverwrite' seed=25426091913299884051777131175022650392940512260996621836439177757956591538101 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25426091913299884051777131175022650392940512260996621836439177757956591538101 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_csr_mem_rw_with_rand_reset 30935394367441435052778289838978236267229509095536849176107611312557856547680 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3348259680 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.3348259680 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.sram_ctrl_csr_mem_rw_with_rand_reset.3348259680 -covoverwrite' seed=30935394367441435052778289838978236267229509095536849176107611312557856547680 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30935394367441435052778289838978236267229509095536849176107611312557856547680 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_smoke 67441225559179230529726675774802367252600060930001197075781121074955932137121 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_smoke/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=494663329 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/5.sram_ctrl_smoke.494663329 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_smoke.494663329 -covoverwrite' seed=67441225559179230529726675774802367252600060930001197075781121074955932137121 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67441225559179230529726675774802367252600060930001197075781121074955932137121 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_multiple_keys 73412149490777254866232453735081509786700705422049616702239197345826284587142 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_multiple_keys/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3535095942 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/5.sram_ctrl_multiple_keys.3535095942 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_multiple_keys.3535095942 -covoverwrite' seed=73412149490777254866232453735081509786700705422049616702239197345826284587142 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73412149490777254866232453735081509786700705422049616702239197345826284587142 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_multiple_keys/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_multiple_keys_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_bijection 112566081324000752135496731318164433446052282657952381650323295040865150266695 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_bijection/latest run_opts='+test_timeout_ns=2000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2616028487 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/5.sram_ctrl_bijection.2616028487 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_bijection.2616028487 -covoverwrite' seed=112566081324000752135496731318164433446052282657952381650323295040865150266695 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112566081324000752135496731318164433446052282657952381650323295040865150266695 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_bijection/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_bijection_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_pipeline 72877897794193298847912891175196172409739297993636808873060870453417375260292 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_stress_pipeline/latest run_opts='+zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2738708100 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/5.sram_ctrl_stress_pipeline.2738708100 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_stress_pipeline.2738708100 -covoverwrite' seed=72877897794193298847912891175196172409739297993636808873060870453417375260292 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=72877897794193298847912891175196172409739297993636808873060870453417375260292 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_stress_pipeline/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_pipeline_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_partial_access 82276684543402789878542449658111228216363194697571029601532264856474407015371 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_partial_access/latest run_opts='+partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3756921803 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/5.sram_ctrl_partial_access.3756921803 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_partial_access.3756921803 -covoverwrite' seed=82276684543402789878542449658111228216363194697571029601532264856474407015371 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82276684543402789878542449658111228216363194697571029601532264856474407015371 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_partial_access_b2b 2906765970850712342749257573179982341613737893645539782063377410380384914980 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_partial_access_b2b/latest run_opts='+partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3401535012 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/5.sram_ctrl_partial_access_b2b.3401535012 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_partial_access_b2b.3401535012 -covoverwrite' seed=2906765970850712342749257573179982341613737893645539782063377410380384914980 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2906765970850712342749257573179982341613737893645539782063377410380384914980 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_partial_access_b2b/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_pipeline_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_max_throughput 5844185458720153878192847774925798095979308883629085354761022783986480866414 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_max_throughput/latest run_opts='+zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3947258990 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/5.sram_ctrl_max_throughput.3947258990 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_max_throughput.3947258990 -covoverwrite' seed=5844185458720153878192847774925798095979308883629085354761022783986480866414 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5844185458720153878192847774925798095979308883629085354761022783986480866414 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_max_throughput/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_throughput_w_partial_write 36528231073074617221359998107507517578446965372612525457987992424010451570642 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_throughput_w_partial_write/latest run_opts='+zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3098857426 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/5.sram_ctrl_throughput_w_partial_write.3098857426 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_throughput_w_partial_write.3098857426 -covoverwrite' seed=36528231073074617221359998107507517578446965372612525457987992424010451570642 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36528231073074617221359998107507517578446965372612525457987992424010451570642 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_throughput_w_partial_write/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_throughput_w_readback 11949939021077267323403803057501285672508171369736274800059286182671585463677 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_throughput_w_readback/latest run_opts='+zero_delays=1 +partial_access_pct=0 +init_w_readback=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2059750781 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/5.sram_ctrl_throughput_w_readback.2059750781 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_throughput_w_readback.2059750781 -covoverwrite' seed=11949939021077267323403803057501285672508171369736274800059286182671585463677 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11949939021077267323403803057501285672508171369736274800059286182671585463677 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_throughput_w_readback/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_lc_escalation 38331128310807408667728693901105949551970449128781823078886222023058587620809 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_lc_escalation/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=719820233 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/5.sram_ctrl_lc_escalation.719820233 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_lc_escalation.719820233 -covoverwrite' seed=38331128310807408667728693901105949551970449128781823078886222023058587620809 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38331128310807408667728693901105949551970449128781823078886222023058587620809 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_access_during_key_req 18385469188956457418663826552170767135987876042198649590316760091546858029476 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_access_during_key_req/latest run_opts='+zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3832545700 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/5.sram_ctrl_access_during_key_req.3832545700 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_access_during_key_req.3832545700 -covoverwrite' seed=18385469188956457418663826552170767135987876042198649590316760091546858029476 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18385469188956457418663826552170767135987876042198649590316760091546858029476 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_access_during_key_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_access_during_key_req_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_executable 81332626065115040014999065703519381074204268625157281753182870863700982481420 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_executable/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=529515020 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/5.sram_ctrl_executable.529515020 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_executable.529515020 -covoverwrite' seed=81332626065115040014999065703519381074204268625157281753182870863700982481420 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81332626065115040014999065703519381074204268625157281753182870863700982481420 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_executable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_executable_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_regwen 69243733416321957948378012159544892048857930637206467185560316810430432648746 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_regwen/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=510893610 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/5.sram_ctrl_regwen.510893610 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_regwen.510893610 -covoverwrite' seed=69243733416321957948378012159544892048857930637206467185560316810430432648746 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69243733416321957948378012159544892048857930637206467185560316810430432648746 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_ram_cfg 103513956575599109271664821048986674633530856271349434354939258922786940377119 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_ram_cfg/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=4074887199 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/5.sram_ctrl_ram_cfg.4074887199 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_ram_cfg.4074887199 -covoverwrite' seed=103513956575599109271664821048986674633530856271349434354939258922786940377119 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103513956575599109271664821048986674633530856271349434354939258922786940377119 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_ram_cfg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_ram_cfg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mem_walk 63078103441333025195145750534676058012526448579716657313021446889818361203469 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_mem_walk/latest run_opts='+csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3405548301 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/5.sram_ctrl_mem_walk.3405548301 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_mem_walk.3405548301 -covoverwrite' seed=63078103441333025195145750534676058012526448579716657313021446889818361203469 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63078103441333025195145750534676058012526448579716657313021446889818361203469 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_mem_walk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mem_partial_access 39760309272927384581815317334132808825306197456137946193695864626901095259002 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_mem_partial_access/latest run_opts='+run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=1210293114 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/5.sram_ctrl_mem_partial_access.1210293114 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_mem_partial_access.1210293114 -covoverwrite' seed=39760309272927384581815317334132808825306197456137946193695864626901095259002 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39760309272927384581815317334132808825306197456137946193695864626901095259002 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_mem_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_readback_err 103136894560434686874518632741855678844365284071488161708647770429884556792223 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_readback_err/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3935719839 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/5.sram_ctrl_readback_err.3935719839 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_readback_err.3935719839 -covoverwrite' seed=103136894560434686874518632741855678844365284071488161708647770429884556792223 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103136894560434686874518632741855678844365284071488161708647770429884556792223 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_readback_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_readback_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mubi_enc_err 38278106980725353479846928841641023727033109877838372252406608368773328764035 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_mubi_enc_err/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=1422621827 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mubi_enc_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/5.sram_ctrl_mubi_enc_err.1422621827 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_mubi_enc_err.1422621827 -covoverwrite' seed=38278106980725353479846928841641023727033109877838372252406608368773328764035 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=38278106980725353479846928841641023727033109877838372252406608368773328764035 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_mubi_enc_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_mubi_enc_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_all_with_rand_reset 51607546749637537099917061562891193240934901597133196887938973685255915051238 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2527205606 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.2527205606 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_stress_all_with_rand_reset.2527205606 -covoverwrite' seed=51607546749637537099917061562891193240934901597133196887938973685255915051238 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51607546749637537099917061562891193240934901597133196887938973685255915051238 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_all 29973374344305265603089026967538905930540343231957322053088243612425559108105 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_stress_all/latest run_opts='+test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=64121353 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/5.sram_ctrl_stress_all.64121353 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_stress_all.64121353 -covoverwrite' seed=29973374344305265603089026967538905930540343231957322053088243612425559108105 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29973374344305265603089026967538905930540343231957322053088243612425559108105 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 58932190750326291890111421636429798701923540894848142767211613324972444145235 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1630852691 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/5.sram_ctrl_tl_errors.1630852691 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.sram_ctrl_tl_errors.1630852691 -covoverwrite' seed=58932190750326291890111421636429798701923540894848142767211613324972444145235 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58932190750326291890111421636429798701923540894848142767211613324972444145235 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 55080257831109879126464370618261925148809123622660483593169589221939178082074 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4013395738 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.4013395738 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.sram_ctrl_tl_intg_err.4013395738 -covoverwrite' seed=55080257831109879126464370618261925148809123622660483593169589221939178082074 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55080257831109879126464370618261925148809123622660483593169589221939178082074 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_alert_test 88265626343087796717020626982561395528337853741549276157486384787708401164980 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2099782324 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/5.sram_ctrl_alert_test.2099782324 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_alert_test.2099782324 -covoverwrite' seed=88265626343087796717020626982561395528337853741549276157486384787708401164980 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88265626343087796717020626982561395528337853741549276157486384787708401164980 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/5.sram_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_smoke 57416220804737070797108279911004104264012549480002342753788504295629921940558 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_smoke/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=364344398 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/6.sram_ctrl_smoke.364344398 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_smoke.364344398 -covoverwrite' seed=57416220804737070797108279911004104264012549480002342753788504295629921940558 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57416220804737070797108279911004104264012549480002342753788504295629921940558 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_multiple_keys 5979258641625220958946042905432208693116085257899421672560652090627985492151 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_multiple_keys/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3996108983 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/6.sram_ctrl_multiple_keys.3996108983 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_multiple_keys.3996108983 -covoverwrite' seed=5979258641625220958946042905432208693116085257899421672560652090627985492151 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5979258641625220958946042905432208693116085257899421672560652090627985492151 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_multiple_keys/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_multiple_keys_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_bijection 81928886627855068376597678625340342570411511136797224283730511276390289380855 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_bijection/latest run_opts='+test_timeout_ns=2000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2672170487 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/6.sram_ctrl_bijection.2672170487 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_bijection.2672170487 -covoverwrite' seed=81928886627855068376597678625340342570411511136797224283730511276390289380855 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81928886627855068376597678625340342570411511136797224283730511276390289380855 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_bijection/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_bijection_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_pipeline 107052022329060631337209033179520830814780068713593490425648398476296072698725 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_stress_pipeline/latest run_opts='+zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2643696485 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/6.sram_ctrl_stress_pipeline.2643696485 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_stress_pipeline.2643696485 -covoverwrite' seed=107052022329060631337209033179520830814780068713593490425648398476296072698725 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107052022329060631337209033179520830814780068713593490425648398476296072698725 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_stress_pipeline/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_pipeline_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_partial_access 62261408787543195296653988625057512081248389663578311903747523718827153583568 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_partial_access/latest run_opts='+partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2094558672 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/6.sram_ctrl_partial_access.2094558672 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_partial_access.2094558672 -covoverwrite' seed=62261408787543195296653988625057512081248389663578311903747523718827153583568 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62261408787543195296653988625057512081248389663578311903747523718827153583568 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_partial_access_b2b 12341299957486561089293190275532730510863604085581987577861823583330067384189 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_partial_access_b2b/latest run_opts='+partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=479037309 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/6.sram_ctrl_partial_access_b2b.479037309 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_partial_access_b2b.479037309 -covoverwrite' seed=12341299957486561089293190275532730510863604085581987577861823583330067384189 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12341299957486561089293190275532730510863604085581987577861823583330067384189 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_partial_access_b2b/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_pipeline_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_max_throughput 31596418041662001063673583606571272983266747742458365184714330084969402593864 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_max_throughput/latest run_opts='+zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3755471432 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/6.sram_ctrl_max_throughput.3755471432 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_max_throughput.3755471432 -covoverwrite' seed=31596418041662001063673583606571272983266747742458365184714330084969402593864 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31596418041662001063673583606571272983266747742458365184714330084969402593864 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_max_throughput/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_throughput_w_partial_write 8952994160945183356976229508515639391233256215611351576979548164415137616810 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_throughput_w_partial_write/latest run_opts='+zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3711275946 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/6.sram_ctrl_throughput_w_partial_write.3711275946 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_throughput_w_partial_write.3711275946 -covoverwrite' seed=8952994160945183356976229508515639391233256215611351576979548164415137616810 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8952994160945183356976229508515639391233256215611351576979548164415137616810 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_throughput_w_partial_write/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_throughput_w_readback 106198576989285598600948955201698167842705686438953938998510101233684516153566 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_throughput_w_readback/latest run_opts='+zero_delays=1 +partial_access_pct=0 +init_w_readback=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=1541122270 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/6.sram_ctrl_throughput_w_readback.1541122270 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_throughput_w_readback.1541122270 -covoverwrite' seed=106198576989285598600948955201698167842705686438953938998510101233684516153566 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106198576989285598600948955201698167842705686438953938998510101233684516153566 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_throughput_w_readback/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_lc_escalation 18410369769724588627358181440196590911495534985992437927952081714368487389804 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_lc_escalation/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3103554156 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/6.sram_ctrl_lc_escalation.3103554156 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_lc_escalation.3103554156 -covoverwrite' seed=18410369769724588627358181440196590911495534985992437927952081714368487389804 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=18410369769724588627358181440196590911495534985992437927952081714368487389804 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_access_during_key_req 11157409517863068801307550672907534781374224710657974240936650977495690732338 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_access_during_key_req/latest run_opts='+zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2232116018 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/6.sram_ctrl_access_during_key_req.2232116018 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_access_during_key_req.2232116018 -covoverwrite' seed=11157409517863068801307550672907534781374224710657974240936650977495690732338 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11157409517863068801307550672907534781374224710657974240936650977495690732338 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_access_during_key_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_access_during_key_req_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_executable 115368196592666662727453153987199566886369125887434562890326862888833084079095 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_executable/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=205044727 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/6.sram_ctrl_executable.205044727 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_executable.205044727 -covoverwrite' seed=115368196592666662727453153987199566886369125887434562890326862888833084079095 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115368196592666662727453153987199566886369125887434562890326862888833084079095 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_executable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_executable_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_regwen 39126041354704296297325003332301631779771629053241211606362617081859729381697 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_regwen/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2745817409 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/6.sram_ctrl_regwen.2745817409 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_regwen.2745817409 -covoverwrite' seed=39126041354704296297325003332301631779771629053241211606362617081859729381697 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39126041354704296297325003332301631779771629053241211606362617081859729381697 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_ram_cfg 19765586689913418543908119050868855600758715188678282231443396772017878870989 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_ram_cfg/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2766678989 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/6.sram_ctrl_ram_cfg.2766678989 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_ram_cfg.2766678989 -covoverwrite' seed=19765586689913418543908119050868855600758715188678282231443396772017878870989 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19765586689913418543908119050868855600758715188678282231443396772017878870989 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_ram_cfg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_ram_cfg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mem_walk 4267659318848289007011098149296956836746284545447887302029062753938951965328 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_mem_walk/latest run_opts='+csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3314616976 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/6.sram_ctrl_mem_walk.3314616976 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_mem_walk.3314616976 -covoverwrite' seed=4267659318848289007011098149296956836746284545447887302029062753938951965328 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4267659318848289007011098149296956836746284545447887302029062753938951965328 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_mem_walk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mem_partial_access 9622385852115870180188805026767635456193385339569377338839231608706245671377 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_mem_partial_access/latest run_opts='+run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=799357393 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/6.sram_ctrl_mem_partial_access.799357393 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_mem_partial_access.799357393 -covoverwrite' seed=9622385852115870180188805026767635456193385339569377338839231608706245671377 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9622385852115870180188805026767635456193385339569377338839231608706245671377 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_mem_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_readback_err 68584782329464004468239752510234668799901304004403478487308960364508529053731 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_readback_err/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=1718898723 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/6.sram_ctrl_readback_err.1718898723 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_readback_err.1718898723 -covoverwrite' seed=68584782329464004468239752510234668799901304004403478487308960364508529053731 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68584782329464004468239752510234668799901304004403478487308960364508529053731 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_readback_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_readback_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mubi_enc_err 9843229574433531319963801483103769333823417867253789811892409333610491818182 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_mubi_enc_err/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3259904198 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mubi_enc_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/6.sram_ctrl_mubi_enc_err.3259904198 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_mubi_enc_err.3259904198 -covoverwrite' seed=9843229574433531319963801483103769333823417867253789811892409333610491818182 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9843229574433531319963801483103769333823417867253789811892409333610491818182 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_mubi_enc_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_mubi_enc_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_all_with_rand_reset 50430700535638358476443869631940722882005644420811649062614348201209119268978 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=696410226 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.696410226 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_stress_all_with_rand_reset.696410226 -covoverwrite' seed=50430700535638358476443869631940722882005644420811649062614348201209119268978 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50430700535638358476443869631940722882005644420811649062614348201209119268978 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_all 54017830781647556837103390367787185548283890475492563963933784168804086839482 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_stress_all/latest run_opts='+test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2581461178 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/6.sram_ctrl_stress_all.2581461178 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_stress_all.2581461178 -covoverwrite' seed=54017830781647556837103390367787185548283890475492563963933784168804086839482 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54017830781647556837103390367787185548283890475492563963933784168804086839482 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 81431662551638503434369866857054031494641277159823769472131494760250071555746 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3534462626 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/6.sram_ctrl_tl_errors.3534462626 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.sram_ctrl_tl_errors.3534462626 -covoverwrite' seed=81431662551638503434369866857054031494641277159823769472131494760250071555746 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81431662551638503434369866857054031494641277159823769472131494760250071555746 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 4731161306391256578038902896222741371020805786064461139073229657114374740954 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3419839450 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.3419839450 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.sram_ctrl_tl_intg_err.3419839450 -covoverwrite' seed=4731161306391256578038902896222741371020805786064461139073229657114374740954 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4731161306391256578038902896222741371020805786064461139073229657114374740954 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_alert_test 69640964488268110513026513108265250731550854559999334154808617826231840479547 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2678397243 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/6.sram_ctrl_alert_test.2678397243 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_alert_test.2678397243 -covoverwrite' seed=69640964488268110513026513108265250731550854559999334154808617826231840479547 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69640964488268110513026513108265250731550854559999334154808617826231840479547 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/6.sram_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_smoke 61186204112834110526570873360693517666793481819570592004952991638908590607478 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_smoke/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=4066364534 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/7.sram_ctrl_smoke.4066364534 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_smoke.4066364534 -covoverwrite' seed=61186204112834110526570873360693517666793481819570592004952991638908590607478 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61186204112834110526570873360693517666793481819570592004952991638908590607478 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_multiple_keys 89841379857519883205275662544681340516371466447601740062371799611812846852040 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_multiple_keys/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=1537038280 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/7.sram_ctrl_multiple_keys.1537038280 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_multiple_keys.1537038280 -covoverwrite' seed=89841379857519883205275662544681340516371466447601740062371799611812846852040 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89841379857519883205275662544681340516371466447601740062371799611812846852040 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_multiple_keys/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_multiple_keys_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_bijection 11333174941910500961383715845398006992617994436014747967040098460604630141585 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_bijection/latest run_opts='+test_timeout_ns=2000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2220460689 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/7.sram_ctrl_bijection.2220460689 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_bijection.2220460689 -covoverwrite' seed=11333174941910500961383715845398006992617994436014747967040098460604630141585 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11333174941910500961383715845398006992617994436014747967040098460604630141585 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_bijection/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_bijection_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_pipeline 41918571499537969027419902320501524723452353299599269679770122183858062810312 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_stress_pipeline/latest run_opts='+zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=189193416 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/7.sram_ctrl_stress_pipeline.189193416 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_stress_pipeline.189193416 -covoverwrite' seed=41918571499537969027419902320501524723452353299599269679770122183858062810312 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41918571499537969027419902320501524723452353299599269679770122183858062810312 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_stress_pipeline/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_pipeline_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_partial_access 104467649448654289910644653023693467912748722915917482213863877115676061732277 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_partial_access/latest run_opts='+partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3654421941 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/7.sram_ctrl_partial_access.3654421941 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_partial_access.3654421941 -covoverwrite' seed=104467649448654289910644653023693467912748722915917482213863877115676061732277 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104467649448654289910644653023693467912748722915917482213863877115676061732277 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_partial_access_b2b 44287156638748724490523919448073039984307900842338347032746945595489029911115 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_partial_access_b2b/latest run_opts='+partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=20902475 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/7.sram_ctrl_partial_access_b2b.20902475 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_partial_access_b2b.20902475 -covoverwrite' seed=44287156638748724490523919448073039984307900842338347032746945595489029911115 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44287156638748724490523919448073039984307900842338347032746945595489029911115 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_partial_access_b2b/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_pipeline_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_max_throughput 106619018456319909768175363050981455755082978699769124133820974569802145200744 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_max_throughput/latest run_opts='+zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3407870568 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/7.sram_ctrl_max_throughput.3407870568 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_max_throughput.3407870568 -covoverwrite' seed=106619018456319909768175363050981455755082978699769124133820974569802145200744 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106619018456319909768175363050981455755082978699769124133820974569802145200744 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_max_throughput/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_throughput_w_partial_write 50365007888306944387016620581450650502289040979103784307501452438098476133030 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_throughput_w_partial_write/latest run_opts='+zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=1729751718 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/7.sram_ctrl_throughput_w_partial_write.1729751718 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_throughput_w_partial_write.1729751718 -covoverwrite' seed=50365007888306944387016620581450650502289040979103784307501452438098476133030 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50365007888306944387016620581450650502289040979103784307501452438098476133030 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_throughput_w_partial_write/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_throughput_w_readback 13599762956448345014396301753226723434768670619320656646994805876568056352543 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_throughput_w_readback/latest run_opts='+zero_delays=1 +partial_access_pct=0 +init_w_readback=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=366432031 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/7.sram_ctrl_throughput_w_readback.366432031 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_throughput_w_readback.366432031 -covoverwrite' seed=13599762956448345014396301753226723434768670619320656646994805876568056352543 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13599762956448345014396301753226723434768670619320656646994805876568056352543 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_throughput_w_readback/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_lc_escalation 40795675482987740544820309566392095493794186655414252862252690045058321503616 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_lc_escalation/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3849606528 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/7.sram_ctrl_lc_escalation.3849606528 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_lc_escalation.3849606528 -covoverwrite' seed=40795675482987740544820309566392095493794186655414252862252690045058321503616 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40795675482987740544820309566392095493794186655414252862252690045058321503616 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_access_during_key_req 14280869814185630983399886422115807482673722728265337616844381524975247521232 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_access_during_key_req/latest run_opts='+zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=910259664 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/7.sram_ctrl_access_during_key_req.910259664 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_access_during_key_req.910259664 -covoverwrite' seed=14280869814185630983399886422115807482673722728265337616844381524975247521232 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=14280869814185630983399886422115807482673722728265337616844381524975247521232 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_access_during_key_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_access_during_key_req_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_executable 17891197239831760708178966097217727474527111820611946918487859338795521601676 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_executable/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=1271066764 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/7.sram_ctrl_executable.1271066764 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_executable.1271066764 -covoverwrite' seed=17891197239831760708178966097217727474527111820611946918487859338795521601676 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17891197239831760708178966097217727474527111820611946918487859338795521601676 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_executable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_executable_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_regwen 82054194283293966318239045184804802374658034170187847334657818075020015550883 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_regwen/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=722059683 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/7.sram_ctrl_regwen.722059683 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_regwen.722059683 -covoverwrite' seed=82054194283293966318239045184804802374658034170187847334657818075020015550883 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82054194283293966318239045184804802374658034170187847334657818075020015550883 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_ram_cfg 93167252198188502269691943318876978849643796244657868653122849204110841118460 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_ram_cfg/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2823061244 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/7.sram_ctrl_ram_cfg.2823061244 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_ram_cfg.2823061244 -covoverwrite' seed=93167252198188502269691943318876978849643796244657868653122849204110841118460 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93167252198188502269691943318876978849643796244657868653122849204110841118460 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_ram_cfg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_ram_cfg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mem_walk 86254935080195698138870378596316288808353034622905361521924052196983086724815 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_mem_walk/latest run_opts='+csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=483079887 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/7.sram_ctrl_mem_walk.483079887 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_mem_walk.483079887 -covoverwrite' seed=86254935080195698138870378596316288808353034622905361521924052196983086724815 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86254935080195698138870378596316288808353034622905361521924052196983086724815 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_mem_walk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mem_partial_access 70134974565256213763673954540545264002881472009406181596714239540007217033947 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_mem_partial_access/latest run_opts='+run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=1041396443 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/7.sram_ctrl_mem_partial_access.1041396443 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_mem_partial_access.1041396443 -covoverwrite' seed=70134974565256213763673954540545264002881472009406181596714239540007217033947 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70134974565256213763673954540545264002881472009406181596714239540007217033947 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_mem_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_readback_err 85441173939817006311583964181755498104075683841510293405674389556541344090534 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_readback_err/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=3760621990 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/7.sram_ctrl_readback_err.3760621990 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_readback_err.3760621990 -covoverwrite' seed=85441173939817006311583964181755498104075683841510293405674389556541344090534 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85441173939817006311583964181755498104075683841510293405674389556541344090534 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_readback_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_readback_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mubi_enc_err 32148898386853981823372240468650065893917534749171396383235261193798726737379 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_mubi_enc_err/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=1154506211 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mubi_enc_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/7.sram_ctrl_mubi_enc_err.1154506211 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_mubi_enc_err.1154506211 -covoverwrite' seed=32148898386853981823372240468650065893917534749171396383235261193798726737379 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32148898386853981823372240468650065893917534749171396383235261193798726737379 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_mubi_enc_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_mubi_enc_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_all_with_rand_reset 66039983677479190448878716746775311379179738031226335931855524189510777486646 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=515685686 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.515685686 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_stress_all_with_rand_reset.515685686 -covoverwrite' seed=66039983677479190448878716746775311379179738031226335931855524189510777486646 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66039983677479190448878716746775311379179738031226335931855524189510777486646 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_all 94801828472023154340023903102835460067372949276271835024451839144801222768226 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_stress_all/latest run_opts='+test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2938877538 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/7.sram_ctrl_stress_all.2938877538 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_stress_all.2938877538 -covoverwrite' seed=94801828472023154340023903102835460067372949276271835024451839144801222768226 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94801828472023154340023903102835460067372949276271835024451839144801222768226 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 15745202714790665419098189483860650972188449759775686296762462822153729866784 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=568851488 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/7.sram_ctrl_tl_errors.568851488 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.sram_ctrl_tl_errors.568851488 -covoverwrite' seed=15745202714790665419098189483860650972188449759775686296762462822153729866784 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15745202714790665419098189483860650972188449759775686296762462822153729866784 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 9369942186872834601205386896358350918868482699919404749580751891195073796580 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=751704548 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.751704548 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.sram_ctrl_tl_intg_err.751704548 -covoverwrite' seed=9369942186872834601205386896358350918868482699919404749580751891195073796580 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9369942186872834601205386896358350918868482699919404749580751891195073796580 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_alert_test 89591008178835805199705239168986712282385165436610484437738779888435511467391 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=880844159 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/7.sram_ctrl_alert_test.880844159 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_alert_test.880844159 -covoverwrite' seed=89591008178835805199705239168986712282385165436610484437738779888435511467391 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89591008178835805199705239168986712282385165436610484437738779888435511467391 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/7.sram_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 105458924595973202729722977925646035697746016139524065565746892021945258765177 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/8.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1284008825 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1284008825 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.sram_ctrl_tl_errors.1284008825 -covoverwrite' seed=105458924595973202729722977925646035697746016139524065565746892021945258765177 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105458924595973202729722977925646035697746016139524065565746892021945258765177 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/8.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 41515379886764617482756028231197965435926086004407950843047521127127692441581 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/8.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3005839341 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3005839341 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.sram_ctrl_tl_intg_err.3005839341 -covoverwrite' seed=41515379886764617482756028231197965435926086004407950843047521127127692441581 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41515379886764617482756028231197965435926086004407950843047521127127692441581 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/8.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_alert_test 76425978055611069300322359331928634663270960257173521087500156892356627426796 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/8.sram_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=2842717676 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/8.sram_ctrl_alert_test.2842717676 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 8.sram_ctrl_alert_test.2842717676 -covoverwrite' seed=76425978055611069300322359331928634663270960257173521087500156892356627426796 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76425978055611069300322359331928634663270960257173521087500156892356627426796 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/8.sram_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 90387184614654605913774466410441056197115676734466069573644384213705427176169 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/9.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4001549033 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/9.sram_ctrl_tl_errors.4001549033 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.sram_ctrl_tl_errors.4001549033 -covoverwrite' seed=90387184614654605913774466410441056197115676734466069573644384213705427176169 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90387184614654605913774466410441056197115676734466069573644384213705427176169 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/9.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 4032817057048335552836806346093590568999547695254211006420669008826003412665 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/9.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=207148729 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.207148729 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.sram_ctrl_tl_intg_err.207148729 -covoverwrite' seed=4032817057048335552836806346093590568999547695254211006420669008826003412665 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4032817057048335552836806346093590568999547695254211006420669008826003412665 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/9.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_alert_test 80388797085454453387339550359051808018074546223844196968197799509905265594747 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/9.sram_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/default/xcelium.d -r tb +SVSEED=1521947003 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/default/9.sram_ctrl_alert_test.1521947003 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope default -covtest 9.sram_ctrl_alert_test.1521947003 -covoverwrite' seed=80388797085454453387339550359051808018074546223844196968197799509905265594747 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80388797085454453387339550359051808018074546223844196968197799509905265594747 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/9.sram_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 66283125195922004613181154011754473554715865318018412304758902784844887042973 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/10.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1882270621 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/10.sram_ctrl_tl_errors.1882270621 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 10.sram_ctrl_tl_errors.1882270621 -covoverwrite' seed=66283125195922004613181154011754473554715865318018412304758902784844887042973 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66283125195922004613181154011754473554715865318018412304758902784844887042973 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/10.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 67531606727771429610615465975256558463321736282503254518543872059545429429065 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/10.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3744156489 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.3744156489 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 10.sram_ctrl_tl_intg_err.3744156489 -covoverwrite' seed=67531606727771429610615465975256558463321736282503254518543872059545429429065 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67531606727771429610615465975256558463321736282503254518543872059545429429065 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/10.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 36200766136837933413605256946425754326649875827762488925746738906450887079314 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/11.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4175852946 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/11.sram_ctrl_tl_errors.4175852946 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 11.sram_ctrl_tl_errors.4175852946 -covoverwrite' seed=36200766136837933413605256946425754326649875827762488925746738906450887079314 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=36200766136837933413605256946425754326649875827762488925746738906450887079314 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/11.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 31205161027605440233602078868722818632094665156919851805869495982608224636520 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/11.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=949243496 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.949243496 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 11.sram_ctrl_tl_intg_err.949243496 -covoverwrite' seed=31205161027605440233602078868722818632094665156919851805869495982608224636520 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31205161027605440233602078868722818632094665156919851805869495982608224636520 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/11.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 91282787891507894422008666177273938004104696934708377971687849634761890979779 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/12.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1385291715 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1385291715 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 12.sram_ctrl_tl_errors.1385291715 -covoverwrite' seed=91282787891507894422008666177273938004104696934708377971687849634761890979779 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91282787891507894422008666177273938004104696934708377971687849634761890979779 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/12.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 71987519992845362270999599969540260664598964213118398824914121915201593148441 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/12.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2411070489 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.2411070489 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 12.sram_ctrl_tl_intg_err.2411070489 -covoverwrite' seed=71987519992845362270999599969540260664598964213118398824914121915201593148441 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71987519992845362270999599969540260664598964213118398824914121915201593148441 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/12.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 112093927575056978310783477649767318771048029216242771549635038299920754016855 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/13.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=144966231 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/13.sram_ctrl_tl_errors.144966231 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 13.sram_ctrl_tl_errors.144966231 -covoverwrite' seed=112093927575056978310783477649767318771048029216242771549635038299920754016855 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112093927575056978310783477649767318771048029216242771549635038299920754016855 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/13.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 113600763762432727508107079547846967792915796775498844128151828706778693368667 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/13.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2532703067 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.2532703067 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 13.sram_ctrl_tl_intg_err.2532703067 -covoverwrite' seed=113600763762432727508107079547846967792915796775498844128151828706778693368667 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113600763762432727508107079547846967792915796775498844128151828706778693368667 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/13.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 56514083106473620209362980582563219324058656266544001999874277787641876761898 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/14.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3554069802 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3554069802 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 14.sram_ctrl_tl_errors.3554069802 -covoverwrite' seed=56514083106473620209362980582563219324058656266544001999874277787641876761898 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56514083106473620209362980582563219324058656266544001999874277787641876761898 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/14.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 46210330846488803739519624878585725364322917404139660111669123896897311695690 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/14.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1555915594 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1555915594 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 14.sram_ctrl_tl_intg_err.1555915594 -covoverwrite' seed=46210330846488803739519624878585725364322917404139660111669123896897311695690 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46210330846488803739519624878585725364322917404139660111669123896897311695690 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/14.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 49885146088554467604651649845360031140805883355949235343488342290723711077213 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/15.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1991625565 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/15.sram_ctrl_tl_errors.1991625565 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 15.sram_ctrl_tl_errors.1991625565 -covoverwrite' seed=49885146088554467604651649845360031140805883355949235343488342290723711077213 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49885146088554467604651649845360031140805883355949235343488342290723711077213 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/15.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 32869323548222758992129547358988481119545712417781339336132824716875181514484 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/15.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2651250420 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.2651250420 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 15.sram_ctrl_tl_intg_err.2651250420 -covoverwrite' seed=32869323548222758992129547358988481119545712417781339336132824716875181514484 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32869323548222758992129547358988481119545712417781339336132824716875181514484 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/15.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 67538025717808672937467987107278365299877686277082048814089324024955937438733 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/16.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3750181901 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/16.sram_ctrl_tl_errors.3750181901 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 16.sram_ctrl_tl_errors.3750181901 -covoverwrite' seed=67538025717808672937467987107278365299877686277082048814089324024955937438733 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67538025717808672937467987107278365299877686277082048814089324024955937438733 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/16.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 11914410020519066070072776490849172857682121890764022030969441333362441329072 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/16.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1042028976 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1042028976 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 16.sram_ctrl_tl_intg_err.1042028976 -covoverwrite' seed=11914410020519066070072776490849172857682121890764022030969441333362441329072 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11914410020519066070072776490849172857682121890764022030969441333362441329072 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/16.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 106330432870760236715656841866565630730936207196501260743329390002882552846869 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/17.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4191476245 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/17.sram_ctrl_tl_errors.4191476245 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 17.sram_ctrl_tl_errors.4191476245 -covoverwrite' seed=106330432870760236715656841866565630730936207196501260743329390002882552846869 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106330432870760236715656841866565630730936207196501260743329390002882552846869 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/17.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 96052089615322416964481020807711288772680137864465937461414151970796104378644 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/17.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2430658836 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2430658836 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 17.sram_ctrl_tl_intg_err.2430658836 -covoverwrite' seed=96052089615322416964481020807711288772680137864465937461414151970796104378644 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96052089615322416964481020807711288772680137864465937461414151970796104378644 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/17.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 107275607911831735899010731279098443078879376489307314157246586378930122914019 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/18.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=234354915 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/18.sram_ctrl_tl_errors.234354915 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 18.sram_ctrl_tl_errors.234354915 -covoverwrite' seed=107275607911831735899010731279098443078879376489307314157246586378930122914019 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107275607911831735899010731279098443078879376489307314157246586378930122914019 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/18.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 45438511142745303741124338654356432607330332626608820078164340613518908465422 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/18.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=487334158 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.487334158 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 18.sram_ctrl_tl_intg_err.487334158 -covoverwrite' seed=45438511142745303741124338654356432607330332626608820078164340613518908465422 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45438511142745303741124338654356432607330332626608820078164340613518908465422 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/18.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 111211439981548880894765124480623729180401090081184863154893778790309884210272 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/19.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2990419040 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/19.sram_ctrl_tl_errors.2990419040 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 19.sram_ctrl_tl_errors.2990419040 -covoverwrite' seed=111211439981548880894765124480623729180401090081184863154893778790309884210272 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111211439981548880894765124480623729180401090081184863154893778790309884210272 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/19.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 48602138003760026366217193588246328034743987915230610991136789320685448590158 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/19.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3397907278 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.3397907278 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 19.sram_ctrl_tl_intg_err.3397907278 -covoverwrite' seed=48602138003760026366217193588246328034743987915230610991136789320685448590158 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48602138003760026366217193588246328034743987915230610991136789320685448590158 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/19.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 5426320526150457014238082248907129595166581077471796715390796435509356039579 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/20.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3303312795 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/20.sram_ctrl_tl_errors.3303312795 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 20.sram_ctrl_tl_errors.3303312795 -covoverwrite' seed=5426320526150457014238082248907129595166581077471796715390796435509356039579 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=5426320526150457014238082248907129595166581077471796715390796435509356039579 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/20.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 57361287747380729639149442040469306572176462166348202068887081027674589625633 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/20.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2833251617 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/20.sram_ctrl_tl_intg_err.2833251617 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 20.sram_ctrl_tl_intg_err.2833251617 -covoverwrite' seed=57361287747380729639149442040469306572176462166348202068887081027674589625633 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57361287747380729639149442040469306572176462166348202068887081027674589625633 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/20.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 58223174626663330979624771518664347947666353330959305100783627411438173624650 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/21.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1454840138 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/21.sram_ctrl_tl_errors.1454840138 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 21.sram_ctrl_tl_errors.1454840138 -covoverwrite' seed=58223174626663330979624771518664347947666353330959305100783627411438173624650 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58223174626663330979624771518664347947666353330959305100783627411438173624650 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/21.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 73267644132379879115840389654389591170438529390679863662088479559891716521 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/21.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4063398313 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/21.sram_ctrl_tl_intg_err.4063398313 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 21.sram_ctrl_tl_intg_err.4063398313 -covoverwrite' seed=73267644132379879115840389654389591170438529390679863662088479559891716521 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=73267644132379879115840389654389591170438529390679863662088479559891716521 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/21.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 7534010920745403816966925552322308555253094892689804012682892621767694108416 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/22.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=572016384 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/22.sram_ctrl_tl_errors.572016384 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 22.sram_ctrl_tl_errors.572016384 -covoverwrite' seed=7534010920745403816966925552322308555253094892689804012682892621767694108416 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7534010920745403816966925552322308555253094892689804012682892621767694108416 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/22.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 85629365089658341703253092572230743316918696570956984848075858066392199725104 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/22.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2567962672 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/22.sram_ctrl_tl_intg_err.2567962672 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 22.sram_ctrl_tl_intg_err.2567962672 -covoverwrite' seed=85629365089658341703253092572230743316918696570956984848075858066392199725104 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85629365089658341703253092572230743316918696570956984848075858066392199725104 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/22.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 85099864307233501912302133683281087479485733507838748001865504039757134371511 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/23.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=674175671 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/23.sram_ctrl_tl_errors.674175671 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 23.sram_ctrl_tl_errors.674175671 -covoverwrite' seed=85099864307233501912302133683281087479485733507838748001865504039757134371511 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85099864307233501912302133683281087479485733507838748001865504039757134371511 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/23.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 12546627998773721657521230205645230346674534868082536950378845380875770635182 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/23.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=664773550 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/23.sram_ctrl_tl_intg_err.664773550 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 23.sram_ctrl_tl_intg_err.664773550 -covoverwrite' seed=12546627998773721657521230205645230346674534868082536950378845380875770635182 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12546627998773721657521230205645230346674534868082536950378845380875770635182 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/23.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 71703054367103648552922827944398050583617341914195225745490509499455194555128 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/24.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=371745528 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/24.sram_ctrl_tl_errors.371745528 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 24.sram_ctrl_tl_errors.371745528 -covoverwrite' seed=71703054367103648552922827944398050583617341914195225745490509499455194555128 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71703054367103648552922827944398050583617341914195225745490509499455194555128 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/24.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 43714331627093291916196861754701057569641561595360034439939709574217087198380 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/24.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3513656492 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage/cover_reg_top/24.sram_ctrl_tl_intg_err.3513656492 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/coverage -covscope cover_reg_top -covtest 24.sram_ctrl_tl_intg_err.3513656492 -covoverwrite' seed=43714331627093291916196861754701057569641561595360034439939709574217087198380 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43714331627093291916196861754701057569641561595360034439939709574217087198380 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_main-sim-xcelium/24.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
Job cancelled because all of its dependencies failed or were killed. 1 test run
sram_ctrl None None
Job cancelled because one of its dependencies failed or was killed. 1 test run
sram_ctrl None None