Simulation Results: sram_ctrl/ret

 
28/08/2026 21:54:34 DVSim: v1.49.0 sha: a099412 json Branch: master Tool: xcelium [unknown]
Validation stages
V1
0.00%
V2
0.00%
V2S
0.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 0 8 0.00
sram_ctrl_smoke 1.538s 0.000us 0 8 0.00
csr_hw_reset 0 1 0.00
sram_ctrl_csr_hw_reset 0.895s 0.000us 0 1 0.00
csr_rw 0 5 0.00
sram_ctrl_csr_rw 0.862s 0.000us 0 5 0.00
csr_bit_bash 0 1 0.00
sram_ctrl_csr_bit_bash 0.860s 0.000us 0 1 0.00
csr_aliasing 0 1 0.00
sram_ctrl_csr_aliasing 0.838s 0.000us 0 1 0.00
csr_mem_rw_with_rand_reset 0 5 0.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.564s 0.000us 0 5 0.00
regwen_csr_and_corresponding_lockable_csr 0 6 0.00
sram_ctrl_csr_rw 0.862s 0.000us 0 5 0.00
sram_ctrl_csr_aliasing 0.838s 0.000us 0 1 0.00
mem_walk 0 8 0.00
sram_ctrl_mem_walk 1.536s 0.000us 0 8 0.00
mem_partial_access 0 8 0.00
sram_ctrl_mem_partial_access 0.890s 0.000us 0 8 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 0 8 0.00
sram_ctrl_multiple_keys 1.510s 0.000us 0 8 0.00
stress_pipeline 0 8 0.00
sram_ctrl_stress_pipeline 0.873s 0.000us 0 8 0.00
bijection 0 8 0.00
sram_ctrl_bijection 0.909s 0.000us 0 8 0.00
access_during_key_req 0 8 0.00
sram_ctrl_access_during_key_req 0.890s 0.000us 0 8 0.00
lc_escalation 0 8 0.00
sram_ctrl_lc_escalation 0.870s 0.000us 0 8 0.00
executable 0 8 0.00
sram_ctrl_executable 0.861s 0.000us 0 8 0.00
partial_access 0 16 0.00
sram_ctrl_partial_access 0.850s 0.000us 0 8 0.00
sram_ctrl_partial_access_b2b 0.875s 0.000us 0 8 0.00
max_throughput 0 24 0.00
sram_ctrl_max_throughput 0.865s 0.000us 0 8 0.00
sram_ctrl_throughput_w_partial_write 0.924s 0.000us 0 8 0.00
sram_ctrl_throughput_w_readback 1.458s 0.000us 0 8 0.00
regwen 0 8 0.00
sram_ctrl_regwen 0.868s 0.000us 0 8 0.00
ram_cfg 0 8 0.00
sram_ctrl_ram_cfg 1.549s 0.000us 0 8 0.00
non_pow2_mem_size 0 24 0.00
sram_ctrl_smoke 1.538s 0.000us 0 8 0.00
sram_ctrl_partial_access 0.850s 0.000us 0 8 0.00
sram_ctrl_access_during_key_req 0.890s 0.000us 0 8 0.00
stress_all 0 8 0.00
sram_ctrl_stress_all 0.595s 0.000us 0 8 0.00
alert_test 0 10 0.00
sram_ctrl_alert_test 0.931s 0.000us 0 10 0.00
tl_d_oob_addr_access 0 25 0.00
sram_ctrl_tl_errors 1.603s 0.000us 0 25 0.00
tl_d_illegal_access 0 25 0.00
sram_ctrl_tl_errors 1.603s 0.000us 0 25 0.00
tl_d_outstanding_access 0 12 0.00
sram_ctrl_csr_hw_reset 0.895s 0.000us 0 1 0.00
sram_ctrl_csr_rw 0.862s 0.000us 0 5 0.00
sram_ctrl_csr_aliasing 0.838s 0.000us 0 1 0.00
sram_ctrl_same_csr_outstanding 1.543s 0.000us 0 5 0.00
tl_d_partial_access 0 12 0.00
sram_ctrl_csr_hw_reset 0.895s 0.000us 0 1 0.00
sram_ctrl_csr_rw 0.862s 0.000us 0 5 0.00
sram_ctrl_csr_aliasing 0.838s 0.000us 0 1 0.00
sram_ctrl_same_csr_outstanding 1.543s 0.000us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 0 5 0.00
sram_ctrl_passthru_mem_tl_intg_err 0.881s 0.000us 0 5 0.00
tl_intg_err 0 30 0.00
sram_ctrl_sec_cm 0.893s 0.000us 0 5 0.00
sram_ctrl_tl_intg_err 1.608s 0.000us 0 25 0.00
prim_count_check 0 5 0.00
sram_ctrl_sec_cm 0.893s 0.000us 0 5 0.00
sec_cm_bus_integrity 0 25 0.00
sram_ctrl_tl_intg_err 1.608s 0.000us 0 25 0.00
sec_cm_ctrl_config_regwen 0 8 0.00
sram_ctrl_regwen 0.868s 0.000us 0 8 0.00
sec_cm_readback_config_regwen 0 8 0.00
sram_ctrl_regwen 0.868s 0.000us 0 8 0.00
sec_cm_exec_config_regwen 0 5 0.00
sram_ctrl_csr_rw 0.862s 0.000us 0 5 0.00
sec_cm_exec_config_mubi 0 8 0.00
sram_ctrl_executable 0.861s 0.000us 0 8 0.00
sec_cm_exec_intersig_mubi 0 8 0.00
sram_ctrl_executable 0.861s 0.000us 0 8 0.00
sec_cm_lc_hw_debug_en_intersig_mubi 0 8 0.00
sram_ctrl_executable 0.861s 0.000us 0 8 0.00
sec_cm_lc_escalate_en_intersig_mubi 0 8 0.00
sram_ctrl_lc_escalation 0.870s 0.000us 0 8 0.00
sec_cm_prim_ram_ctrl_mubi 0 8 0.00
sram_ctrl_mubi_enc_err 0.865s 0.000us 0 8 0.00
sec_cm_mem_integrity 0 5 0.00
sram_ctrl_passthru_mem_tl_intg_err 0.881s 0.000us 0 5 0.00
sec_cm_mem_readback 0 8 0.00
sram_ctrl_readback_err 0.867s 0.000us 0 8 0.00
sec_cm_mem_scramble 0 8 0.00
sram_ctrl_smoke 1.538s 0.000us 0 8 0.00
sec_cm_addr_scramble 0 8 0.00
sram_ctrl_smoke 1.538s 0.000us 0 8 0.00
sec_cm_instr_bus_lc_gated 0 8 0.00
sram_ctrl_executable 0.861s 0.000us 0 8 0.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 5 0.00
sram_ctrl_sec_cm 0.893s 0.000us 0 5 0.00
sec_cm_key_global_esc 0 8 0.00
sram_ctrl_lc_escalation 0.870s 0.000us 0 8 0.00
sec_cm_key_local_esc 0 5 0.00
sram_ctrl_sec_cm 0.893s 0.000us 0 5 0.00
sec_cm_init_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 0.893s 0.000us 0 5 0.00
sec_cm_scramble_key_sideload 0 8 0.00
sram_ctrl_smoke 1.538s 0.000us 0 8 0.00
sec_cm_tlul_fifo_ctr_redun 0 5 0.00
sram_ctrl_sec_cm 0.893s 0.000us 0 5 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 8 0.00
sram_ctrl_stress_all_with_rand_reset 1.571s 0.000us 0 8 0.00

Error Messages

   Test seed line log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$'] 248 test runs
sram_ctrl_smoke 13101727353683520668848611222044645150658207353061922310786204884669475648357 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_smoke/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=1624044389 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/0.sram_ctrl_smoke.1624044389 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_smoke.1624044389 -covoverwrite' seed=13101727353683520668848611222044645150658207353061922310786204884669475648357 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13101727353683520668848611222044645150658207353061922310786204884669475648357 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_multiple_keys 110845538271559101841089523252180922037660919313638846496239177957151043468746 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_multiple_keys/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=529251786 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/0.sram_ctrl_multiple_keys.529251786 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_multiple_keys.529251786 -covoverwrite' seed=110845538271559101841089523252180922037660919313638846496239177957151043468746 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110845538271559101841089523252180922037660919313638846496239177957151043468746 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_multiple_keys/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_multiple_keys_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_bijection 9553168050676962606398050831777724332112607250733064767003383168063175678205 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_bijection/latest run_opts='+test_timeout_ns=2000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3328727293 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/0.sram_ctrl_bijection.3328727293 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_bijection.3328727293 -covoverwrite' seed=9553168050676962606398050831777724332112607250733064767003383168063175678205 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9553168050676962606398050831777724332112607250733064767003383168063175678205 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_bijection/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_bijection_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_pipeline 110453519860639985304314554085709535587165422913280073491295952618422180807986 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_stress_pipeline/latest run_opts='+zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=783320370 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/0.sram_ctrl_stress_pipeline.783320370 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_stress_pipeline.783320370 -covoverwrite' seed=110453519860639985304314554085709535587165422913280073491295952618422180807986 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110453519860639985304314554085709535587165422913280073491295952618422180807986 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_stress_pipeline/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_pipeline_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_partial_access 16436955892431384662691421087529316699705058594656425170647994399797391422017 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_partial_access/latest run_opts='+partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=221803073 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/0.sram_ctrl_partial_access.221803073 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_partial_access.221803073 -covoverwrite' seed=16436955892431384662691421087529316699705058594656425170647994399797391422017 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16436955892431384662691421087529316699705058594656425170647994399797391422017 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_partial_access_b2b 28239431694020563920546564482381968308588806795124679499041566556441970029733 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_partial_access_b2b/latest run_opts='+partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=4105778341 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/0.sram_ctrl_partial_access_b2b.4105778341 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_partial_access_b2b.4105778341 -covoverwrite' seed=28239431694020563920546564482381968308588806795124679499041566556441970029733 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28239431694020563920546564482381968308588806795124679499041566556441970029733 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_partial_access_b2b/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_pipeline_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_max_throughput 27691239320138766788019251712792971986099632465733080440904892723675163132833 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_max_throughput/latest run_opts='+zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2026767265 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/0.sram_ctrl_max_throughput.2026767265 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_max_throughput.2026767265 -covoverwrite' seed=27691239320138766788019251712792971986099632465733080440904892723675163132833 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27691239320138766788019251712792971986099632465733080440904892723675163132833 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_max_throughput/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_throughput_w_partial_write 49839713529721271202239911381550045427912962384304525712669657219194037795325 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_throughput_w_partial_write/latest run_opts='+zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=1116011005 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/0.sram_ctrl_throughput_w_partial_write.1116011005 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_throughput_w_partial_write.1116011005 -covoverwrite' seed=49839713529721271202239911381550045427912962384304525712669657219194037795325 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49839713529721271202239911381550045427912962384304525712669657219194037795325 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_throughput_w_partial_write/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_throughput_w_readback 82363914735076753280105245469714333313079445690317194851886476950024717096380 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_throughput_w_readback/latest run_opts='+zero_delays=1 +partial_access_pct=0 +init_w_readback=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=1792562620 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/0.sram_ctrl_throughput_w_readback.1792562620 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_throughput_w_readback.1792562620 -covoverwrite' seed=82363914735076753280105245469714333313079445690317194851886476950024717096380 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82363914735076753280105245469714333313079445690317194851886476950024717096380 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_throughput_w_readback/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_lc_escalation 92770437468947060250310332062233637682611978405317856079381366453561819108991 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_lc_escalation/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=1578866303 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/0.sram_ctrl_lc_escalation.1578866303 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_lc_escalation.1578866303 -covoverwrite' seed=92770437468947060250310332062233637682611978405317856079381366453561819108991 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=92770437468947060250310332062233637682611978405317856079381366453561819108991 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_access_during_key_req 26076206515956635956425522021133096417915069728967475533462303179548288661152 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_access_during_key_req/latest run_opts='+zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=192984736 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/0.sram_ctrl_access_during_key_req.192984736 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_access_during_key_req.192984736 -covoverwrite' seed=26076206515956635956425522021133096417915069728967475533462303179548288661152 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26076206515956635956425522021133096417915069728967475533462303179548288661152 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_access_during_key_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_access_during_key_req_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_executable 56199384889044505555057009804251065877643741089612889216992285316642910751302 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_executable/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=280218182 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/0.sram_ctrl_executable.280218182 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_executable.280218182 -covoverwrite' seed=56199384889044505555057009804251065877643741089612889216992285316642910751302 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56199384889044505555057009804251065877643741089612889216992285316642910751302 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_executable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_executable_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_regwen 48918536291424503660539403351539893970052210745285199269430888151177744643640 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_regwen/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=661157432 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/0.sram_ctrl_regwen.661157432 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_regwen.661157432 -covoverwrite' seed=48918536291424503660539403351539893970052210745285199269430888151177744643640 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48918536291424503660539403351539893970052210745285199269430888151177744643640 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_ram_cfg 94584977571409268478072135483125047163846776289181035517763921849783736342645 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_ram_cfg/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=1259083893 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/0.sram_ctrl_ram_cfg.1259083893 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_ram_cfg.1259083893 -covoverwrite' seed=94584977571409268478072135483125047163846776289181035517763921849783736342645 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94584977571409268478072135483125047163846776289181035517763921849783736342645 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_ram_cfg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_ram_cfg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mem_walk 90727929398744068015752120099161637950585396684078793372380171077283153674489 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_mem_walk/latest run_opts='+csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=1433633017 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/0.sram_ctrl_mem_walk.1433633017 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_mem_walk.1433633017 -covoverwrite' seed=90727929398744068015752120099161637950585396684078793372380171077283153674489 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90727929398744068015752120099161637950585396684078793372380171077283153674489 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_mem_walk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mem_partial_access 22389961560022439972628744487845786658942746352316541196929670229751701601006 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_mem_partial_access/latest run_opts='+run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=4252400366 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/0.sram_ctrl_mem_partial_access.4252400366 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_mem_partial_access.4252400366 -covoverwrite' seed=22389961560022439972628744487845786658942746352316541196929670229751701601006 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22389961560022439972628744487845786658942746352316541196929670229751701601006 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_mem_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_readback_err 47614636135602678656535556889362513604212873157766571755616650142530192261257 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_readback_err/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2868625545 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/0.sram_ctrl_readback_err.2868625545 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_readback_err.2868625545 -covoverwrite' seed=47614636135602678656535556889362513604212873157766571755616650142530192261257 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47614636135602678656535556889362513604212873157766571755616650142530192261257 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_readback_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_readback_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mubi_enc_err 40055418052244126825448588510670976165958005465910256532613530875997147388493 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_mubi_enc_err/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2226412109 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mubi_enc_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/0.sram_ctrl_mubi_enc_err.2226412109 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_mubi_enc_err.2226412109 -covoverwrite' seed=40055418052244126825448588510670976165958005465910256532613530875997147388493 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40055418052244126825448588510670976165958005465910256532613530875997147388493 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_mubi_enc_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_mubi_enc_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_all_with_rand_reset 20564206227918402587125838904741280606024878141919511852035826848225259041211 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3286643131 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/0.sram_ctrl_stress_all_with_rand_reset.3286643131 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_stress_all_with_rand_reset.3286643131 -covoverwrite' seed=20564206227918402587125838904741280606024878141919511852035826848225259041211 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20564206227918402587125838904741280606024878141919511852035826848225259041211 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_all 37335990398909223609780204861722065437628949945261873100588738648460122870788 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_stress_all/latest run_opts='+test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2830324740 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/0.sram_ctrl_stress_all.2830324740 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_stress_all.2830324740 -covoverwrite' seed=37335990398909223609780204861722065437628949945261873100588738648460122870788 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37335990398909223609780204861722065437628949945261873100588738648460122870788 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_sec_cm 6900603420502109018840183823677960038572550616078795615952716157595382972259 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3711958883 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/0.sram_ctrl_sec_cm.3711958883 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_sec_cm.3711958883 -covoverwrite' seed=6900603420502109018840183823677960038572550616078795615952716157595382972259 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6900603420502109018840183823677960038572550616078795615952716157595382972259 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_passthru_mem_tl_intg_err 91135388570209831951983080015794335423147597611133829437447968768980778080291 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_passthru_mem_tl_intg_err/latest run_opts='+run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1282267171 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/0.sram_ctrl_passthru_mem_tl_intg_err.1282267171 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.sram_ctrl_passthru_mem_tl_intg_err.1282267171 -covoverwrite' seed=91135388570209831951983080015794335423147597611133829437447968768980778080291 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91135388570209831951983080015794335423147597611133829437447968768980778080291 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_passthru_mem_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 80439361347257591191393669679339595214319899531282273758081621838523770574343 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3798177287 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/0.sram_ctrl_tl_errors.3798177287 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.sram_ctrl_tl_errors.3798177287 -covoverwrite' seed=80439361347257591191393669679339595214319899531282273758081621838523770574343 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80439361347257591191393669679339595214319899531282273758081621838523770574343 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 49057182538956534976411832062848525536657706292920126707254403338720304849838 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3271975854 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/0.sram_ctrl_tl_intg_err.3271975854 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.sram_ctrl_tl_intg_err.3271975854 -covoverwrite' seed=49057182538956534976411832062848525536657706292920126707254403338720304849838 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49057182538956534976411832062848525536657706292920126707254403338720304849838 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_alert_test 52859821812989589274883754137034903297390783012173451046151661183563669422762 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3683893930 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/0.sram_ctrl_alert_test.3683893930 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 0.sram_ctrl_alert_test.3683893930 -covoverwrite' seed=52859821812989589274883754137034903297390783012173451046151661183563669422762 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=52859821812989589274883754137034903297390783012173451046151661183563669422762 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_csr_hw_reset 78418869430481187108274917097449926363999235372407929883181166991839205839503 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_csr_hw_reset/latest run_opts='+csr_hw_reset +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3168064143 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/0.sram_ctrl_csr_hw_reset.3168064143 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.sram_ctrl_csr_hw_reset.3168064143 -covoverwrite' seed=78418869430481187108274917097449926363999235372407929883181166991839205839503 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78418869430481187108274917097449926363999235372407929883181166991839205839503 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_csr_hw_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_csr_rw 25894872477107651692634426562723362561247569111528837138841176117116765169983 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_csr_rw/latest run_opts='+csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=913008959 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/0.sram_ctrl_csr_rw.913008959 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.sram_ctrl_csr_rw.913008959 -covoverwrite' seed=25894872477107651692634426562723362561247569111528837138841176117116765169983 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25894872477107651692634426562723362561247569111528837138841176117116765169983 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_csr_bit_bash 48139089780147842896375171860572532512281042882294151564874384954611507690220 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_csr_bit_bash/latest run_opts='+csr_bit_bash +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3564665580 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/0.sram_ctrl_csr_bit_bash.3564665580 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.sram_ctrl_csr_bit_bash.3564665580 -covoverwrite' seed=48139089780147842896375171860572532512281042882294151564874384954611507690220 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=48139089780147842896375171860572532512281042882294151564874384954611507690220 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_csr_bit_bash/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_csr_aliasing 103042032842958508921532700244127670077269917811158662188664500405066690249857 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_csr_aliasing/latest run_opts='+csr_aliasing +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2998977665 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/0.sram_ctrl_csr_aliasing.2998977665 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.sram_ctrl_csr_aliasing.2998977665 -covoverwrite' seed=103042032842958508921532700244127670077269917811158662188664500405066690249857 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103042032842958508921532700244127670077269917811158662188664500405066690249857 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_csr_aliasing/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_same_csr_outstanding 76829992482969144810829439175874492648035675088994570840087719781585296982560 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1970962976 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/0.sram_ctrl_same_csr_outstanding.1970962976 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.sram_ctrl_same_csr_outstanding.1970962976 -covoverwrite' seed=76829992482969144810829439175874492648035675088994570840087719781585296982560 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76829992482969144810829439175874492648035675088994570840087719781585296982560 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_csr_mem_rw_with_rand_reset 78218236659208224748370202206380517392553391662224807878719733255390040269144 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=513384792 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/0.sram_ctrl_csr_mem_rw_with_rand_reset.513384792 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 0.sram_ctrl_csr_mem_rw_with_rand_reset.513384792 -covoverwrite' seed=78218236659208224748370202206380517392553391662224807878719733255390040269144 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78218236659208224748370202206380517392553391662224807878719733255390040269144 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_smoke 1266683749494554832039156748695854383390430593908641963259487496803362849585 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_smoke/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2426454833 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/1.sram_ctrl_smoke.2426454833 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_smoke.2426454833 -covoverwrite' seed=1266683749494554832039156748695854383390430593908641963259487496803362849585 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1266683749494554832039156748695854383390430593908641963259487496803362849585 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_multiple_keys 57456184634017430973855402149591050570992540168603472802398936496971022201433 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_multiple_keys/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2310664793 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/1.sram_ctrl_multiple_keys.2310664793 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_multiple_keys.2310664793 -covoverwrite' seed=57456184634017430973855402149591050570992540168603472802398936496971022201433 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57456184634017430973855402149591050570992540168603472802398936496971022201433 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_multiple_keys/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_multiple_keys_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_bijection 7895277351340876456569791742636411365377500663712033262277437247787483150092 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_bijection/latest run_opts='+test_timeout_ns=2000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2209756940 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/1.sram_ctrl_bijection.2209756940 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_bijection.2209756940 -covoverwrite' seed=7895277351340876456569791742636411365377500663712033262277437247787483150092 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7895277351340876456569791742636411365377500663712033262277437247787483150092 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_bijection/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_bijection_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_pipeline 46169095049100400786360280338794584904922163645477731575401155965133087281205 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_stress_pipeline/latest run_opts='+zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3540488245 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/1.sram_ctrl_stress_pipeline.3540488245 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_stress_pipeline.3540488245 -covoverwrite' seed=46169095049100400786360280338794584904922163645477731575401155965133087281205 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46169095049100400786360280338794584904922163645477731575401155965133087281205 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_stress_pipeline/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_pipeline_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_partial_access 110992121706527107012630773171431329659143735037199640615169069259072392264910 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_partial_access/latest run_opts='+partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3536714958 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/1.sram_ctrl_partial_access.3536714958 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_partial_access.3536714958 -covoverwrite' seed=110992121706527107012630773171431329659143735037199640615169069259072392264910 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110992121706527107012630773171431329659143735037199640615169069259072392264910 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_partial_access_b2b 50344884053883713648611988420635012230618559612995743450846313239758853543549 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_partial_access_b2b/latest run_opts='+partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=750163581 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/1.sram_ctrl_partial_access_b2b.750163581 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_partial_access_b2b.750163581 -covoverwrite' seed=50344884053883713648611988420635012230618559612995743450846313239758853543549 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50344884053883713648611988420635012230618559612995743450846313239758853543549 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_partial_access_b2b/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_pipeline_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_max_throughput 102162599118899098248198017940079324351263507306506137478433377606653688622624 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_max_throughput/latest run_opts='+zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=1104358944 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/1.sram_ctrl_max_throughput.1104358944 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_max_throughput.1104358944 -covoverwrite' seed=102162599118899098248198017940079324351263507306506137478433377606653688622624 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102162599118899098248198017940079324351263507306506137478433377606653688622624 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_max_throughput/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_throughput_w_partial_write 16157407716613526619450795918510524700354065921074986818995685350471466871379 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_throughput_w_partial_write/latest run_opts='+zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3311004243 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/1.sram_ctrl_throughput_w_partial_write.3311004243 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_throughput_w_partial_write.3311004243 -covoverwrite' seed=16157407716613526619450795918510524700354065921074986818995685350471466871379 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16157407716613526619450795918510524700354065921074986818995685350471466871379 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_throughput_w_partial_write/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_throughput_w_readback 34956886699210527428760867039344547809561496501987457155877211949141889150130 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_throughput_w_readback/latest run_opts='+zero_delays=1 +partial_access_pct=0 +init_w_readback=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2117364914 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/1.sram_ctrl_throughput_w_readback.2117364914 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_throughput_w_readback.2117364914 -covoverwrite' seed=34956886699210527428760867039344547809561496501987457155877211949141889150130 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34956886699210527428760867039344547809561496501987457155877211949141889150130 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_throughput_w_readback/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_lc_escalation 103455029014589707440537323035204351106002973055127881964310319582367194566867 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_lc_escalation/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=800346323 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/1.sram_ctrl_lc_escalation.800346323 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_lc_escalation.800346323 -covoverwrite' seed=103455029014589707440537323035204351106002973055127881964310319582367194566867 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103455029014589707440537323035204351106002973055127881964310319582367194566867 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_access_during_key_req 31601466380101840185723340164229794436743301717959769583268287155846758801082 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_access_during_key_req/latest run_opts='+zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3578535610 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/1.sram_ctrl_access_during_key_req.3578535610 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_access_during_key_req.3578535610 -covoverwrite' seed=31601466380101840185723340164229794436743301717959769583268287155846758801082 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=31601466380101840185723340164229794436743301717959769583268287155846758801082 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_access_during_key_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_access_during_key_req_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_executable 70717328634510016873343752180249356395742017883889223429520334286202325716923 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_executable/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=1664110523 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/1.sram_ctrl_executable.1664110523 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_executable.1664110523 -covoverwrite' seed=70717328634510016873343752180249356395742017883889223429520334286202325716923 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70717328634510016873343752180249356395742017883889223429520334286202325716923 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_executable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_executable_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_regwen 98735227384122531709463010619205349817882603204885483782871819584405287803737 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_regwen/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=4187822937 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/1.sram_ctrl_regwen.4187822937 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_regwen.4187822937 -covoverwrite' seed=98735227384122531709463010619205349817882603204885483782871819584405287803737 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98735227384122531709463010619205349817882603204885483782871819584405287803737 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_ram_cfg 90985497585599370661325377210953820813858691950939269743327631800659362093733 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_ram_cfg/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3325991589 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/1.sram_ctrl_ram_cfg.3325991589 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_ram_cfg.3325991589 -covoverwrite' seed=90985497585599370661325377210953820813858691950939269743327631800659362093733 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90985497585599370661325377210953820813858691950939269743327631800659362093733 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_ram_cfg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_ram_cfg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mem_walk 115268591924386592770083723754191581816332454210831585446682773756677013732745 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_mem_walk/latest run_opts='+csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=1881505161 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/1.sram_ctrl_mem_walk.1881505161 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_mem_walk.1881505161 -covoverwrite' seed=115268591924386592770083723754191581816332454210831585446682773756677013732745 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115268591924386592770083723754191581816332454210831585446682773756677013732745 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_mem_walk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mem_partial_access 111524773762885030415107911236869921194442853945600478643798527033018874197079 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_mem_partial_access/latest run_opts='+run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2524836951 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/1.sram_ctrl_mem_partial_access.2524836951 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_mem_partial_access.2524836951 -covoverwrite' seed=111524773762885030415107911236869921194442853945600478643798527033018874197079 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=111524773762885030415107911236869921194442853945600478643798527033018874197079 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_mem_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_readback_err 85943451408723754816249800747111927041664741051652155539095231784127346517676 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_readback_err/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2198611628 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/1.sram_ctrl_readback_err.2198611628 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_readback_err.2198611628 -covoverwrite' seed=85943451408723754816249800747111927041664741051652155539095231784127346517676 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85943451408723754816249800747111927041664741051652155539095231784127346517676 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_readback_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_readback_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mubi_enc_err 110038909772533978729497560456660189986036193681544501201999079965416616839237 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_mubi_enc_err/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3281995845 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mubi_enc_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/1.sram_ctrl_mubi_enc_err.3281995845 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_mubi_enc_err.3281995845 -covoverwrite' seed=110038909772533978729497560456660189986036193681544501201999079965416616839237 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110038909772533978729497560456660189986036193681544501201999079965416616839237 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_mubi_enc_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_mubi_enc_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_all_with_rand_reset 29205341410303769059732776119685984885056067975260597472963353445699148560450 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2588915778 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/1.sram_ctrl_stress_all_with_rand_reset.2588915778 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_stress_all_with_rand_reset.2588915778 -covoverwrite' seed=29205341410303769059732776119685984885056067975260597472963353445699148560450 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29205341410303769059732776119685984885056067975260597472963353445699148560450 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_all 7044530724769163220184434606804133664802735582599828660099635861895873515772 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_stress_all/latest run_opts='+test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=1105940732 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/1.sram_ctrl_stress_all.1105940732 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_stress_all.1105940732 -covoverwrite' seed=7044530724769163220184434606804133664802735582599828660099635861895873515772 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7044530724769163220184434606804133664802735582599828660099635861895873515772 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_sec_cm 16590605069348643929764027821778638285294416027388879604155420103046759983801 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2436639417 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/1.sram_ctrl_sec_cm.2436639417 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_sec_cm.2436639417 -covoverwrite' seed=16590605069348643929764027821778638285294416027388879604155420103046759983801 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16590605069348643929764027821778638285294416027388879604155420103046759983801 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_passthru_mem_tl_intg_err 3927681801985713938497742473439849216026370430079101620707172795785237400749 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_passthru_mem_tl_intg_err/latest run_opts='+run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4151217325 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/1.sram_ctrl_passthru_mem_tl_intg_err.4151217325 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.sram_ctrl_passthru_mem_tl_intg_err.4151217325 -covoverwrite' seed=3927681801985713938497742473439849216026370430079101620707172795785237400749 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3927681801985713938497742473439849216026370430079101620707172795785237400749 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_passthru_mem_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 1662946098393802663086767490772420163888974150591165251637355995801136996098 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=738270978 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/1.sram_ctrl_tl_errors.738270978 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.sram_ctrl_tl_errors.738270978 -covoverwrite' seed=1662946098393802663086767490772420163888974150591165251637355995801136996098 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1662946098393802663086767490772420163888974150591165251637355995801136996098 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 3295685813461133418727678180356972569486610926793925969266917953759962774725 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1163443397 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/1.sram_ctrl_tl_intg_err.1163443397 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.sram_ctrl_tl_intg_err.1163443397 -covoverwrite' seed=3295685813461133418727678180356972569486610926793925969266917953759962774725 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3295685813461133418727678180356972569486610926793925969266917953759962774725 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_alert_test 100729124190862307169281165066073718945651465703125886869266762027636641361243 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=1174875 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/1.sram_ctrl_alert_test.1174875 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 1.sram_ctrl_alert_test.1174875 -covoverwrite' seed=100729124190862307169281165066073718945651465703125886869266762027636641361243 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=100729124190862307169281165066073718945651465703125886869266762027636641361243 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_csr_rw 19042799694033267488387527784739070350852806625422145746126694893261394400397 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_csr_rw/latest run_opts='+csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1420940429 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/1.sram_ctrl_csr_rw.1420940429 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.sram_ctrl_csr_rw.1420940429 -covoverwrite' seed=19042799694033267488387527784739070350852806625422145746126694893261394400397 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19042799694033267488387527784739070350852806625422145746126694893261394400397 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_same_csr_outstanding 26525396652171380039001265314568304312762257879296871539049987068326650511113 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1594818313 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/1.sram_ctrl_same_csr_outstanding.1594818313 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.sram_ctrl_same_csr_outstanding.1594818313 -covoverwrite' seed=26525396652171380039001265314568304312762257879296871539049987068326650511113 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=26525396652171380039001265314568304312762257879296871539049987068326650511113 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_csr_mem_rw_with_rand_reset 41149265771088962307586881674958521372968905416000919701901899552815238550465 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2937263041 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/1.sram_ctrl_csr_mem_rw_with_rand_reset.2937263041 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 1.sram_ctrl_csr_mem_rw_with_rand_reset.2937263041 -covoverwrite' seed=41149265771088962307586881674958521372968905416000919701901899552815238550465 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=41149265771088962307586881674958521372968905416000919701901899552815238550465 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/1.sram_ctrl_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_smoke 22284729983488137519478159066318634996973637297716158343396852270387956914014 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_smoke/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3016857438 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/2.sram_ctrl_smoke.3016857438 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_smoke.3016857438 -covoverwrite' seed=22284729983488137519478159066318634996973637297716158343396852270387956914014 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22284729983488137519478159066318634996973637297716158343396852270387956914014 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_multiple_keys 17928202106928429494182106896840738645004278297513938144099018341136775912095 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_multiple_keys/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3053066911 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/2.sram_ctrl_multiple_keys.3053066911 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_multiple_keys.3053066911 -covoverwrite' seed=17928202106928429494182106896840738645004278297513938144099018341136775912095 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17928202106928429494182106896840738645004278297513938144099018341136775912095 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_multiple_keys/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_multiple_keys_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_bijection 109238314401465896195649501525876792954413172938522328656049354021967775977237 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_bijection/latest run_opts='+test_timeout_ns=2000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=4229746453 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/2.sram_ctrl_bijection.4229746453 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_bijection.4229746453 -covoverwrite' seed=109238314401465896195649501525876792954413172938522328656049354021967775977237 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109238314401465896195649501525876792954413172938522328656049354021967775977237 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_bijection/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_bijection_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_pipeline 93110430441516651387872531671923596223545704032712857184123348589278146449713 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_stress_pipeline/latest run_opts='+zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2843332913 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/2.sram_ctrl_stress_pipeline.2843332913 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_stress_pipeline.2843332913 -covoverwrite' seed=93110430441516651387872531671923596223545704032712857184123348589278146449713 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93110430441516651387872531671923596223545704032712857184123348589278146449713 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_stress_pipeline/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_pipeline_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_partial_access 107803911683551788915772050425304733699958023012517971468107281495659893870674 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_partial_access/latest run_opts='+partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3558199378 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/2.sram_ctrl_partial_access.3558199378 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_partial_access.3558199378 -covoverwrite' seed=107803911683551788915772050425304733699958023012517971468107281495659893870674 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107803911683551788915772050425304733699958023012517971468107281495659893870674 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_partial_access_b2b 104609330142391153040434658990114371814792994741306625400128572775541649880711 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_partial_access_b2b/latest run_opts='+partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=890418823 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/2.sram_ctrl_partial_access_b2b.890418823 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_partial_access_b2b.890418823 -covoverwrite' seed=104609330142391153040434658990114371814792994741306625400128572775541649880711 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104609330142391153040434658990114371814792994741306625400128572775541649880711 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_partial_access_b2b/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_pipeline_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_max_throughput 95203535007227194639558413600876019733199993989731072561646842749457444450557 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_max_throughput/latest run_opts='+zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3768135933 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/2.sram_ctrl_max_throughput.3768135933 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_max_throughput.3768135933 -covoverwrite' seed=95203535007227194639558413600876019733199993989731072561646842749457444450557 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95203535007227194639558413600876019733199993989731072561646842749457444450557 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_max_throughput/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_throughput_w_partial_write 109776650042020644815969939624035220736073005729823469806297555999723692911041 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_throughput_w_partial_write/latest run_opts='+zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3048368577 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/2.sram_ctrl_throughput_w_partial_write.3048368577 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_throughput_w_partial_write.3048368577 -covoverwrite' seed=109776650042020644815969939624035220736073005729823469806297555999723692911041 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=109776650042020644815969939624035220736073005729823469806297555999723692911041 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_throughput_w_partial_write/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_throughput_w_readback 75553736381149456898733845546316489073864199466094111585594478926412383339157 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_throughput_w_readback/latest run_opts='+zero_delays=1 +partial_access_pct=0 +init_w_readback=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2085700245 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/2.sram_ctrl_throughput_w_readback.2085700245 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_throughput_w_readback.2085700245 -covoverwrite' seed=75553736381149456898733845546316489073864199466094111585594478926412383339157 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75553736381149456898733845546316489073864199466094111585594478926412383339157 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_throughput_w_readback/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_lc_escalation 15664592452949792101200140158911870994602810158323781574821455480870196529544 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_lc_escalation/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2441136520 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/2.sram_ctrl_lc_escalation.2441136520 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_lc_escalation.2441136520 -covoverwrite' seed=15664592452949792101200140158911870994602810158323781574821455480870196529544 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15664592452949792101200140158911870994602810158323781574821455480870196529544 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_access_during_key_req 42528174501985806889028704285443569017109984208900326838575882720304460650092 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_access_during_key_req/latest run_opts='+zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=113432172 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/2.sram_ctrl_access_during_key_req.113432172 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_access_during_key_req.113432172 -covoverwrite' seed=42528174501985806889028704285443569017109984208900326838575882720304460650092 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42528174501985806889028704285443569017109984208900326838575882720304460650092 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_access_during_key_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_access_during_key_req_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_executable 11218428956076425280053130172504891628795955305021823655068618750096007681081 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_executable/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=238474297 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/2.sram_ctrl_executable.238474297 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_executable.238474297 -covoverwrite' seed=11218428956076425280053130172504891628795955305021823655068618750096007681081 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11218428956076425280053130172504891628795955305021823655068618750096007681081 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_executable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_executable_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_regwen 24850060277098470588853091165226401077314934251686301402380341812283108855180 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_regwen/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2940308876 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/2.sram_ctrl_regwen.2940308876 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_regwen.2940308876 -covoverwrite' seed=24850060277098470588853091165226401077314934251686301402380341812283108855180 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24850060277098470588853091165226401077314934251686301402380341812283108855180 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_ram_cfg 61052401917453551829440906654286158151817532595821388938451593459722189158917 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_ram_cfg/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2164406789 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/2.sram_ctrl_ram_cfg.2164406789 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_ram_cfg.2164406789 -covoverwrite' seed=61052401917453551829440906654286158151817532595821388938451593459722189158917 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61052401917453551829440906654286158151817532595821388938451593459722189158917 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_ram_cfg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_ram_cfg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mem_walk 20302128548620534949882200254143294472237871764761450338916998843286624170429 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_mem_walk/latest run_opts='+csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3767824829 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/2.sram_ctrl_mem_walk.3767824829 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_mem_walk.3767824829 -covoverwrite' seed=20302128548620534949882200254143294472237871764761450338916998843286624170429 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20302128548620534949882200254143294472237871764761450338916998843286624170429 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_mem_walk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mem_partial_access 35876157347011654915525472702525445681558998370413088480743925558423719069311 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_mem_partial_access/latest run_opts='+run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3890300543 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/2.sram_ctrl_mem_partial_access.3890300543 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_mem_partial_access.3890300543 -covoverwrite' seed=35876157347011654915525472702525445681558998370413088480743925558423719069311 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35876157347011654915525472702525445681558998370413088480743925558423719069311 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_mem_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_readback_err 34267076133903014785796676230557253703628422246096517421272110296576756234183 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_readback_err/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2447325127 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/2.sram_ctrl_readback_err.2447325127 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_readback_err.2447325127 -covoverwrite' seed=34267076133903014785796676230557253703628422246096517421272110296576756234183 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34267076133903014785796676230557253703628422246096517421272110296576756234183 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_readback_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_readback_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mubi_enc_err 79070809625271962907676535654130606771356687243249493136292069579570280576309 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_mubi_enc_err/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3393369397 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mubi_enc_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/2.sram_ctrl_mubi_enc_err.3393369397 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_mubi_enc_err.3393369397 -covoverwrite' seed=79070809625271962907676535654130606771356687243249493136292069579570280576309 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79070809625271962907676535654130606771356687243249493136292069579570280576309 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_mubi_enc_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_mubi_enc_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_all_with_rand_reset 19212094887049781980330221094227114096931049310680443471487381409119788011100 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=1034620508 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/2.sram_ctrl_stress_all_with_rand_reset.1034620508 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_stress_all_with_rand_reset.1034620508 -covoverwrite' seed=19212094887049781980330221094227114096931049310680443471487381409119788011100 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19212094887049781980330221094227114096931049310680443471487381409119788011100 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_all 49092748899814661773634459786193628282421621908344434344952659946447192963142 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_stress_all/latest run_opts='+test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=1754773574 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/2.sram_ctrl_stress_all.1754773574 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_stress_all.1754773574 -covoverwrite' seed=49092748899814661773634459786193628282421621908344434344952659946447192963142 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=49092748899814661773634459786193628282421621908344434344952659946447192963142 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_sec_cm 74926183364895260844332534238895256682062889258370831856265482768125688030889 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2366121641 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/2.sram_ctrl_sec_cm.2366121641 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_sec_cm.2366121641 -covoverwrite' seed=74926183364895260844332534238895256682062889258370831856265482768125688030889 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=74926183364895260844332534238895256682062889258370831856265482768125688030889 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_passthru_mem_tl_intg_err 97651837602204493622822794755244762071284239005004849633865501474350148359005 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_passthru_mem_tl_intg_err/latest run_opts='+run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2618561373 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/2.sram_ctrl_passthru_mem_tl_intg_err.2618561373 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.sram_ctrl_passthru_mem_tl_intg_err.2618561373 -covoverwrite' seed=97651837602204493622822794755244762071284239005004849633865501474350148359005 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97651837602204493622822794755244762071284239005004849633865501474350148359005 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_passthru_mem_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 115567481534809917402658215992883657860917925964670895098791138451734996314905 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=289008409 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/2.sram_ctrl_tl_errors.289008409 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.sram_ctrl_tl_errors.289008409 -covoverwrite' seed=115567481534809917402658215992883657860917925964670895098791138451734996314905 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115567481534809917402658215992883657860917925964670895098791138451734996314905 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 61631261487287390099925429882300969916753834925167750475815489643741224165887 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2925847039 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/2.sram_ctrl_tl_intg_err.2925847039 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.sram_ctrl_tl_intg_err.2925847039 -covoverwrite' seed=61631261487287390099925429882300969916753834925167750475815489643741224165887 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61631261487287390099925429882300969916753834925167750475815489643741224165887 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_alert_test 43240825447370234041427266814349054433509670885712420987532442665621782632062 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2001835646 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/2.sram_ctrl_alert_test.2001835646 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 2.sram_ctrl_alert_test.2001835646 -covoverwrite' seed=43240825447370234041427266814349054433509670885712420987532442665621782632062 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=43240825447370234041427266814349054433509670885712420987532442665621782632062 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_csr_rw 29462711245377262959591314400140145636715410272542068067357550294328596038909 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_csr_rw/latest run_opts='+csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1614087421 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/2.sram_ctrl_csr_rw.1614087421 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.sram_ctrl_csr_rw.1614087421 -covoverwrite' seed=29462711245377262959591314400140145636715410272542068067357550294328596038909 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29462711245377262959591314400140145636715410272542068067357550294328596038909 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_same_csr_outstanding 52559244363544335130496453109564902422691611327225519600570573442900316363680 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=519805856 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/2.sram_ctrl_same_csr_outstanding.519805856 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.sram_ctrl_same_csr_outstanding.519805856 -covoverwrite' seed=52559244363544335130496453109564902422691611327225519600570573442900316363680 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=52559244363544335130496453109564902422691611327225519600570573442900316363680 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_csr_mem_rw_with_rand_reset 107691801743935719856729425708095662648691948689022917847710004749845808898832 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1608868624 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/2.sram_ctrl_csr_mem_rw_with_rand_reset.1608868624 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 2.sram_ctrl_csr_mem_rw_with_rand_reset.1608868624 -covoverwrite' seed=107691801743935719856729425708095662648691948689022917847710004749845808898832 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=107691801743935719856729425708095662648691948689022917847710004749845808898832 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/2.sram_ctrl_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_smoke 11608358406252060226305179677387449256561946566914282756807886794836847335071 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_smoke/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3987445407 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/3.sram_ctrl_smoke.3987445407 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_smoke.3987445407 -covoverwrite' seed=11608358406252060226305179677387449256561946566914282756807886794836847335071 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=11608358406252060226305179677387449256561946566914282756807886794836847335071 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_multiple_keys 47252261750509139952120749798774625662378981218127727117651751088025654769279 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_multiple_keys/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2912925311 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/3.sram_ctrl_multiple_keys.2912925311 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_multiple_keys.2912925311 -covoverwrite' seed=47252261750509139952120749798774625662378981218127727117651751088025654769279 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47252261750509139952120749798774625662378981218127727117651751088025654769279 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_multiple_keys/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_multiple_keys_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_bijection 27901366250046233692702262783529198534022647214752118410112202945765848134647 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_bijection/latest run_opts='+test_timeout_ns=2000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=1208759287 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/3.sram_ctrl_bijection.1208759287 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_bijection.1208759287 -covoverwrite' seed=27901366250046233692702262783529198534022647214752118410112202945765848134647 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27901366250046233692702262783529198534022647214752118410112202945765848134647 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_bijection/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_bijection_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_pipeline 46600448299940372880065630647134890218426459590140004464414033393477423047955 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_stress_pipeline/latest run_opts='+zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=4048921875 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/3.sram_ctrl_stress_pipeline.4048921875 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_stress_pipeline.4048921875 -covoverwrite' seed=46600448299940372880065630647134890218426459590140004464414033393477423047955 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46600448299940372880065630647134890218426459590140004464414033393477423047955 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_stress_pipeline/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_pipeline_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_partial_access 91730500111322516565022827108735733884368165532116885453686197476117390686329 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_partial_access/latest run_opts='+partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3100244089 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/3.sram_ctrl_partial_access.3100244089 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_partial_access.3100244089 -covoverwrite' seed=91730500111322516565022827108735733884368165532116885453686197476117390686329 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=91730500111322516565022827108735733884368165532116885453686197476117390686329 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_partial_access_b2b 28513478293480560825587134139031002621879554023821079654248384565285065891423 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_partial_access_b2b/latest run_opts='+partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=904699487 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/3.sram_ctrl_partial_access_b2b.904699487 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_partial_access_b2b.904699487 -covoverwrite' seed=28513478293480560825587134139031002621879554023821079654248384565285065891423 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=28513478293480560825587134139031002621879554023821079654248384565285065891423 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_partial_access_b2b/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_pipeline_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_max_throughput 102762823731959402374197622357201796706902382174400217435282202184193623403882 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_max_throughput/latest run_opts='+zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=388443498 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/3.sram_ctrl_max_throughput.388443498 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_max_throughput.388443498 -covoverwrite' seed=102762823731959402374197622357201796706902382174400217435282202184193623403882 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102762823731959402374197622357201796706902382174400217435282202184193623403882 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_max_throughput/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_throughput_w_partial_write 54129160951536961386494871005524612012428287341146813428522309641632990939452 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_throughput_w_partial_write/latest run_opts='+zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=411093308 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/3.sram_ctrl_throughput_w_partial_write.411093308 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_throughput_w_partial_write.411093308 -covoverwrite' seed=54129160951536961386494871005524612012428287341146813428522309641632990939452 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=54129160951536961386494871005524612012428287341146813428522309641632990939452 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_throughput_w_partial_write/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_throughput_w_readback 82046024930585143575513783839315154327232999327924412658746964062510377135449 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_throughput_w_readback/latest run_opts='+zero_delays=1 +partial_access_pct=0 +init_w_readback=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=217378137 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/3.sram_ctrl_throughput_w_readback.217378137 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_throughput_w_readback.217378137 -covoverwrite' seed=82046024930585143575513783839315154327232999327924412658746964062510377135449 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82046024930585143575513783839315154327232999327924412658746964062510377135449 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_throughput_w_readback/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_lc_escalation 20670027356153082495570918451380847529725234707620866845210346539609232734462 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_lc_escalation/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2903734526 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/3.sram_ctrl_lc_escalation.2903734526 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_lc_escalation.2903734526 -covoverwrite' seed=20670027356153082495570918451380847529725234707620866845210346539609232734462 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20670027356153082495570918451380847529725234707620866845210346539609232734462 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_access_during_key_req 1004868528187588284704677341754520881672685124322359142253545031516383317990 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_access_during_key_req/latest run_opts='+zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=1191153638 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/3.sram_ctrl_access_during_key_req.1191153638 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_access_during_key_req.1191153638 -covoverwrite' seed=1004868528187588284704677341754520881672685124322359142253545031516383317990 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=1004868528187588284704677341754520881672685124322359142253545031516383317990 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_access_during_key_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_access_during_key_req_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_executable 22624887917784956673449336554973814042587078472335459901717976169184869208840 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_executable/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=1073992456 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/3.sram_ctrl_executable.1073992456 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_executable.1073992456 -covoverwrite' seed=22624887917784956673449336554973814042587078472335459901717976169184869208840 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=22624887917784956673449336554973814042587078472335459901717976169184869208840 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_executable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_executable_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_regwen 66299919655909657843866501245328592934687564773448189840843939459880529577233 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_regwen/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2080261393 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/3.sram_ctrl_regwen.2080261393 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_regwen.2080261393 -covoverwrite' seed=66299919655909657843866501245328592934687564773448189840843939459880529577233 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=66299919655909657843866501245328592934687564773448189840843939459880529577233 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_ram_cfg 63944522907227479223454192827545028993320445307413799724279975434081998019847 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_ram_cfg/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3100187911 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/3.sram_ctrl_ram_cfg.3100187911 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_ram_cfg.3100187911 -covoverwrite' seed=63944522907227479223454192827545028993320445307413799724279975434081998019847 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63944522907227479223454192827545028993320445307413799724279975434081998019847 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_ram_cfg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_ram_cfg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mem_walk 105302894277040560143619978244528207096034155838127939716656850543557252628410 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_mem_walk/latest run_opts='+csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2664054714 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/3.sram_ctrl_mem_walk.2664054714 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_mem_walk.2664054714 -covoverwrite' seed=105302894277040560143619978244528207096034155838127939716656850543557252628410 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105302894277040560143619978244528207096034155838127939716656850543557252628410 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_mem_walk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mem_partial_access 105093646354881556269610763981820219074812630754982854397620524116696713181219 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_mem_partial_access/latest run_opts='+run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=46184483 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/3.sram_ctrl_mem_partial_access.46184483 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_mem_partial_access.46184483 -covoverwrite' seed=105093646354881556269610763981820219074812630754982854397620524116696713181219 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=105093646354881556269610763981820219074812630754982854397620524116696713181219 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_mem_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_readback_err 56891479388783276285637274497806416701738770960422736566457672533908719125509 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_readback_err/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=803193861 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/3.sram_ctrl_readback_err.803193861 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_readback_err.803193861 -covoverwrite' seed=56891479388783276285637274497806416701738770960422736566457672533908719125509 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56891479388783276285637274497806416701738770960422736566457672533908719125509 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_readback_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_readback_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mubi_enc_err 62691717044275388214336335887858584368414271047751880485674574059808713206304 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_mubi_enc_err/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=76933664 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mubi_enc_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/3.sram_ctrl_mubi_enc_err.76933664 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_mubi_enc_err.76933664 -covoverwrite' seed=62691717044275388214336335887858584368414271047751880485674574059808713206304 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62691717044275388214336335887858584368414271047751880485674574059808713206304 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_mubi_enc_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_mubi_enc_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_all_with_rand_reset 29941819071643576793063812242220276460501451261088893732023244429417475817580 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3519627372 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/3.sram_ctrl_stress_all_with_rand_reset.3519627372 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_stress_all_with_rand_reset.3519627372 -covoverwrite' seed=29941819071643576793063812242220276460501451261088893732023244429417475817580 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=29941819071643576793063812242220276460501451261088893732023244429417475817580 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_all 45632943819048180959156700670236043657654335670150784201164317861842736210718 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_stress_all/latest run_opts='+test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=4154549022 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/3.sram_ctrl_stress_all.4154549022 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_stress_all.4154549022 -covoverwrite' seed=45632943819048180959156700670236043657654335670150784201164317861842736210718 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45632943819048180959156700670236043657654335670150784201164317861842736210718 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_sec_cm 17884033592194398695297398337846821658674812618744241666039562444514373007299 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=1250817987 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/3.sram_ctrl_sec_cm.1250817987 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_sec_cm.1250817987 -covoverwrite' seed=17884033592194398695297398337846821658674812618744241666039562444514373007299 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17884033592194398695297398337846821658674812618744241666039562444514373007299 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_passthru_mem_tl_intg_err 51866334762057959564418007290002869560631364698498176792939107202269660533722 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_passthru_mem_tl_intg_err/latest run_opts='+run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2902938586 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/3.sram_ctrl_passthru_mem_tl_intg_err.2902938586 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.sram_ctrl_passthru_mem_tl_intg_err.2902938586 -covoverwrite' seed=51866334762057959564418007290002869560631364698498176792939107202269660533722 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51866334762057959564418007290002869560631364698498176792939107202269660533722 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_passthru_mem_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 110845892688306636819452755536011456792916232114073805332744355415788170879300 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3634209092 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/3.sram_ctrl_tl_errors.3634209092 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.sram_ctrl_tl_errors.3634209092 -covoverwrite' seed=110845892688306636819452755536011456792916232114073805332744355415788170879300 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=110845892688306636819452755536011456792916232114073805332744355415788170879300 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 2517863249192672442398942901215851068612401739183475651927151403631793428619 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2713475211 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/3.sram_ctrl_tl_intg_err.2713475211 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.sram_ctrl_tl_intg_err.2713475211 -covoverwrite' seed=2517863249192672442398942901215851068612401739183475651927151403631793428619 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=2517863249192672442398942901215851068612401739183475651927151403631793428619 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_alert_test 81718504264697730038058230702556341997106269927667640723750450137001710613320 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3020976968 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/3.sram_ctrl_alert_test.3020976968 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 3.sram_ctrl_alert_test.3020976968 -covoverwrite' seed=81718504264697730038058230702556341997106269927667640723750450137001710613320 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81718504264697730038058230702556341997106269927667640723750450137001710613320 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_csr_rw 3629942505570849098205950624548303017245417568817863651677973768760680036213 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_csr_rw/latest run_opts='+csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1158199157 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/3.sram_ctrl_csr_rw.1158199157 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.sram_ctrl_csr_rw.1158199157 -covoverwrite' seed=3629942505570849098205950624548303017245417568817863651677973768760680036213 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=3629942505570849098205950624548303017245417568817863651677973768760680036213 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_same_csr_outstanding 30489660765282401532073241742864066478639223513857448004118438001359586320931 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3286229539 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/3.sram_ctrl_same_csr_outstanding.3286229539 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.sram_ctrl_same_csr_outstanding.3286229539 -covoverwrite' seed=30489660765282401532073241742864066478639223513857448004118438001359586320931 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30489660765282401532073241742864066478639223513857448004118438001359586320931 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_csr_mem_rw_with_rand_reset 16870333978438564344161808519427190134787099653169134020226883071980365274257 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1838013585 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/3.sram_ctrl_csr_mem_rw_with_rand_reset.1838013585 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 3.sram_ctrl_csr_mem_rw_with_rand_reset.1838013585 -covoverwrite' seed=16870333978438564344161808519427190134787099653169134020226883071980365274257 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16870333978438564344161808519427190134787099653169134020226883071980365274257 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/3.sram_ctrl_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_smoke 108146219095264603400901868795564678708245867225089694495252665643179973472453 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_smoke/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2773151941 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/4.sram_ctrl_smoke.2773151941 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_smoke.2773151941 -covoverwrite' seed=108146219095264603400901868795564678708245867225089694495252665643179973472453 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108146219095264603400901868795564678708245867225089694495252665643179973472453 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_multiple_keys 82842410201716016892190220070480393446959148096345354192040071751598681268473 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_multiple_keys/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=1360437497 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/4.sram_ctrl_multiple_keys.1360437497 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_multiple_keys.1360437497 -covoverwrite' seed=82842410201716016892190220070480393446959148096345354192040071751598681268473 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82842410201716016892190220070480393446959148096345354192040071751598681268473 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_multiple_keys/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_multiple_keys_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_bijection 108667445174859480249260519043251615651812602673179246308686750976253650946341 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_bijection/latest run_opts='+test_timeout_ns=2000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=370559269 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/4.sram_ctrl_bijection.370559269 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_bijection.370559269 -covoverwrite' seed=108667445174859480249260519043251615651812602673179246308686750976253650946341 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108667445174859480249260519043251615651812602673179246308686750976253650946341 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_bijection/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_bijection_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_pipeline 104171082668274109951231357148562128115409889740375497811790142374676207129290 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_stress_pipeline/latest run_opts='+zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3167638218 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/4.sram_ctrl_stress_pipeline.3167638218 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_stress_pipeline.3167638218 -covoverwrite' seed=104171082668274109951231357148562128115409889740375497811790142374676207129290 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104171082668274109951231357148562128115409889740375497811790142374676207129290 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_stress_pipeline/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_pipeline_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_partial_access 106687672101047518624231259765806210583347813859128878612352792283592385546142 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_partial_access/latest run_opts='+partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=327337886 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/4.sram_ctrl_partial_access.327337886 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_partial_access.327337886 -covoverwrite' seed=106687672101047518624231259765806210583347813859128878612352792283592385546142 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106687672101047518624231259765806210583347813859128878612352792283592385546142 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_partial_access_b2b 89563597866947339111226189528641735145979831044837657860822733218067985292846 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_partial_access_b2b/latest run_opts='+partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3401670190 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/4.sram_ctrl_partial_access_b2b.3401670190 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_partial_access_b2b.3401670190 -covoverwrite' seed=89563597866947339111226189528641735145979831044837657860822733218067985292846 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89563597866947339111226189528641735145979831044837657860822733218067985292846 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_partial_access_b2b/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_pipeline_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_max_throughput 45464981060667737896793100992897600549284327123067817838114802748034787833129 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_max_throughput/latest run_opts='+zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=888403241 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/4.sram_ctrl_max_throughput.888403241 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_max_throughput.888403241 -covoverwrite' seed=45464981060667737896793100992897600549284327123067817838114802748034787833129 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45464981060667737896793100992897600549284327123067817838114802748034787833129 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_max_throughput/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_throughput_w_partial_write 25039589766406044563680210966029658599728152316705783479155951641929245731649 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_throughput_w_partial_write/latest run_opts='+zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=670772033 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/4.sram_ctrl_throughput_w_partial_write.670772033 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_throughput_w_partial_write.670772033 -covoverwrite' seed=25039589766406044563680210966029658599728152316705783479155951641929245731649 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25039589766406044563680210966029658599728152316705783479155951641929245731649 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_throughput_w_partial_write/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_throughput_w_readback 93723643853506534687242696518383133035124491770737534097311028135495824598833 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_throughput_w_readback/latest run_opts='+zero_delays=1 +partial_access_pct=0 +init_w_readback=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2370856753 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/4.sram_ctrl_throughput_w_readback.2370856753 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_throughput_w_readback.2370856753 -covoverwrite' seed=93723643853506534687242696518383133035124491770737534097311028135495824598833 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93723643853506534687242696518383133035124491770737534097311028135495824598833 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_throughput_w_readback/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_lc_escalation 25498455049874864192110821344972210353204260007871820616662147721740890140703 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_lc_escalation/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=1559490591 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/4.sram_ctrl_lc_escalation.1559490591 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_lc_escalation.1559490591 -covoverwrite' seed=25498455049874864192110821344972210353204260007871820616662147721740890140703 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25498455049874864192110821344972210353204260007871820616662147721740890140703 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_access_during_key_req 16745946794000695952498371251273874018281256711647234894100856563024986956856 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_access_during_key_req/latest run_opts='+zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2279924792 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/4.sram_ctrl_access_during_key_req.2279924792 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_access_during_key_req.2279924792 -covoverwrite' seed=16745946794000695952498371251273874018281256711647234894100856563024986956856 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16745946794000695952498371251273874018281256711647234894100856563024986956856 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_access_during_key_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_access_during_key_req_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_executable 33953693909978580476259477345384668206329720839552158780252133523653737933353 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_executable/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2988010025 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/4.sram_ctrl_executable.2988010025 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_executable.2988010025 -covoverwrite' seed=33953693909978580476259477345384668206329720839552158780252133523653737933353 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33953693909978580476259477345384668206329720839552158780252133523653737933353 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_executable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_executable_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_regwen 94741999239353491812103235768784383863103596771676598617684103286057338041154 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_regwen/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2058515266 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/4.sram_ctrl_regwen.2058515266 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_regwen.2058515266 -covoverwrite' seed=94741999239353491812103235768784383863103596771676598617684103286057338041154 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=94741999239353491812103235768784383863103596771676598617684103286057338041154 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_ram_cfg 4139576672009383107028822343713574771427700759261617424358599317988847244956 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_ram_cfg/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=949343900 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/4.sram_ctrl_ram_cfg.949343900 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_ram_cfg.949343900 -covoverwrite' seed=4139576672009383107028822343713574771427700759261617424358599317988847244956 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4139576672009383107028822343713574771427700759261617424358599317988847244956 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_ram_cfg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_ram_cfg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mem_walk 78115617559209818231504189961747416229646924493701798339089409799886042835287 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_mem_walk/latest run_opts='+csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2721589591 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/4.sram_ctrl_mem_walk.2721589591 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_mem_walk.2721589591 -covoverwrite' seed=78115617559209818231504189961747416229646924493701798339089409799886042835287 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=78115617559209818231504189961747416229646924493701798339089409799886042835287 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_mem_walk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mem_partial_access 64398781128157616719925614344630256410181348097939742163179033019722144982899 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_mem_partial_access/latest run_opts='+run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3520374643 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/4.sram_ctrl_mem_partial_access.3520374643 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_mem_partial_access.3520374643 -covoverwrite' seed=64398781128157616719925614344630256410181348097939742163179033019722144982899 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64398781128157616719925614344630256410181348097939742163179033019722144982899 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_mem_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_readback_err 95483928584589702386727710829247495499411097978356333966308451149634364088928 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_readback_err/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3252789856 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/4.sram_ctrl_readback_err.3252789856 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_readback_err.3252789856 -covoverwrite' seed=95483928584589702386727710829247495499411097978356333966308451149634364088928 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95483928584589702386727710829247495499411097978356333966308451149634364088928 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_readback_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_readback_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mubi_enc_err 44697925048352676777573066228601667725882746855747157891575328223765582224406 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_mubi_enc_err/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3755645974 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mubi_enc_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/4.sram_ctrl_mubi_enc_err.3755645974 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_mubi_enc_err.3755645974 -covoverwrite' seed=44697925048352676777573066228601667725882746855747157891575328223765582224406 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44697925048352676777573066228601667725882746855747157891575328223765582224406 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_mubi_enc_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_mubi_enc_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_all_with_rand_reset 12460980864771838241864933558880197244055489783058897132871900342214539383977 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=312775849 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/4.sram_ctrl_stress_all_with_rand_reset.312775849 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_stress_all_with_rand_reset.312775849 -covoverwrite' seed=12460980864771838241864933558880197244055489783058897132871900342214539383977 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12460980864771838241864933558880197244055489783058897132871900342214539383977 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_all 8044226970460041780922425695116138933150818476865086831443470594490799846927 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_stress_all/latest run_opts='+test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2194503183 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/4.sram_ctrl_stress_all.2194503183 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_stress_all.2194503183 -covoverwrite' seed=8044226970460041780922425695116138933150818476865086831443470594490799846927 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=8044226970460041780922425695116138933150818476865086831443470594490799846927 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_sec_cm 9935917469395807844336670145365590191831176275024494226001014690350353231184 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_sec_cm/latest run_opts='+run_sec_cm_fi +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=420621648 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/4.sram_ctrl_sec_cm.420621648 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_sec_cm.420621648 -covoverwrite' seed=9935917469395807844336670145365590191831176275024494226001014690350353231184 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=9935917469395807844336670145365590191831176275024494226001014690350353231184 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_sec_cm/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_passthru_mem_tl_intg_err 98558463266069247497371610672473303760247851178712845937662462316627179691163 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_passthru_mem_tl_intg_err/latest run_opts='+run_passthru_mem_tl_intg_err +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3255131291 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/4.sram_ctrl_passthru_mem_tl_intg_err.3255131291 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.sram_ctrl_passthru_mem_tl_intg_err.3255131291 -covoverwrite' seed=98558463266069247497371610672473303760247851178712845937662462316627179691163 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98558463266069247497371610672473303760247851178712845937662462316627179691163 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_passthru_mem_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 65530729229248694964004210142641746871430749055800863062452953269762058186031 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1021930799 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/4.sram_ctrl_tl_errors.1021930799 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.sram_ctrl_tl_errors.1021930799 -covoverwrite' seed=65530729229248694964004210142641746871430749055800863062452953269762058186031 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=65530729229248694964004210142641746871430749055800863062452953269762058186031 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 62032587577548149130388274306383546406240693826638748970384378984686594776498 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1074486706 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/4.sram_ctrl_tl_intg_err.1074486706 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.sram_ctrl_tl_intg_err.1074486706 -covoverwrite' seed=62032587577548149130388274306383546406240693826638748970384378984686594776498 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62032587577548149130388274306383546406240693826638748970384378984686594776498 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_alert_test 15195351636134035715517034148625722423009571333853673293762242509140884981903 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=4077127823 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/4.sram_ctrl_alert_test.4077127823 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 4.sram_ctrl_alert_test.4077127823 -covoverwrite' seed=15195351636134035715517034148625722423009571333853673293762242509140884981903 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15195351636134035715517034148625722423009571333853673293762242509140884981903 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_csr_rw 98640187447802202404438867216869968078695789113642231569926319526167666205290 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_csr_rw/latest run_opts='+csr_rw +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3968311914 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/4.sram_ctrl_csr_rw.3968311914 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.sram_ctrl_csr_rw.3968311914 -covoverwrite' seed=98640187447802202404438867216869968078695789113642231569926319526167666205290 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98640187447802202404438867216869968078695789113642231569926319526167666205290 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_csr_rw/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_same_csr_outstanding 35455885427107419190932910352768621294027206970064304697321599887053487977019 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_same_csr_outstanding/latest run_opts='+run_same_csr_outstanding +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2122691131 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/4.sram_ctrl_same_csr_outstanding.2122691131 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.sram_ctrl_same_csr_outstanding.2122691131 -covoverwrite' seed=35455885427107419190932910352768621294027206970064304697321599887053487977019 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=35455885427107419190932910352768621294027206970064304697321599887053487977019 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_same_csr_outstanding/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_csr_mem_rw_with_rand_reset 58506973874822916650492762424633969147502655744198664991734442759010325981121 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest run_opts='+run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=565012417 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/4.sram_ctrl_csr_mem_rw_with_rand_reset.565012417 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 4.sram_ctrl_csr_mem_rw_with_rand_reset.565012417 -covoverwrite' seed=58506973874822916650492762424633969147502655744198664991734442759010325981121 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58506973874822916650492762424633969147502655744198664991734442759010325981121 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/4.sram_ctrl_csr_mem_rw_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_smoke 13198178499800853302095434261101752719593238968461602907883467153820053089977 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_smoke/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=478621369 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/5.sram_ctrl_smoke.478621369 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_smoke.478621369 -covoverwrite' seed=13198178499800853302095434261101752719593238968461602907883467153820053089977 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=13198178499800853302095434261101752719593238968461602907883467153820053089977 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_multiple_keys 15837450250150480259359750080333922078011073538264178579482603328123538279505 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_multiple_keys/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3064499281 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/5.sram_ctrl_multiple_keys.3064499281 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_multiple_keys.3064499281 -covoverwrite' seed=15837450250150480259359750080333922078011073538264178579482603328123538279505 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15837450250150480259359750080333922078011073538264178579482603328123538279505 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_multiple_keys/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_multiple_keys_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_bijection 27667602005471508654043126558210187585460037692631973403863622251132569279929 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_bijection/latest run_opts='+test_timeout_ns=2000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=987520441 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/5.sram_ctrl_bijection.987520441 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_bijection.987520441 -covoverwrite' seed=27667602005471508654043126558210187585460037692631973403863622251132569279929 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=27667602005471508654043126558210187585460037692631973403863622251132569279929 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_bijection/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_bijection_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_pipeline 51905087312627571395478867207151922376406159514910196294384692907737388603097 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_stress_pipeline/latest run_opts='+zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3001734873 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/5.sram_ctrl_stress_pipeline.3001734873 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_stress_pipeline.3001734873 -covoverwrite' seed=51905087312627571395478867207151922376406159514910196294384692907737388603097 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=51905087312627571395478867207151922376406159514910196294384692907737388603097 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_stress_pipeline/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_pipeline_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_partial_access 30398885015550865423337912358735894709855416993518203074230166130595748871289 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_partial_access/latest run_opts='+partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2735176825 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/5.sram_ctrl_partial_access.2735176825 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_partial_access.2735176825 -covoverwrite' seed=30398885015550865423337912358735894709855416993518203074230166130595748871289 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30398885015550865423337912358735894709855416993518203074230166130595748871289 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_partial_access_b2b 4639305715299364073364024449549116616954632443834268798005908853213018878184 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_partial_access_b2b/latest run_opts='+partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3937038568 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/5.sram_ctrl_partial_access_b2b.3937038568 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_partial_access_b2b.3937038568 -covoverwrite' seed=4639305715299364073364024449549116616954632443834268798005908853213018878184 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4639305715299364073364024449549116616954632443834268798005908853213018878184 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_partial_access_b2b/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_pipeline_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_max_throughput 15834084232631359655924978482780767856586998238954043727859011333489732415079 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_max_throughput/latest run_opts='+zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3044863591 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/5.sram_ctrl_max_throughput.3044863591 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_max_throughput.3044863591 -covoverwrite' seed=15834084232631359655924978482780767856586998238954043727859011333489732415079 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15834084232631359655924978482780767856586998238954043727859011333489732415079 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_max_throughput/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_throughput_w_partial_write 20379721260641300819816369585673508434493382617251863959067308512508045616499 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_throughput_w_partial_write/latest run_opts='+zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=308209011 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/5.sram_ctrl_throughput_w_partial_write.308209011 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_throughput_w_partial_write.308209011 -covoverwrite' seed=20379721260641300819816369585673508434493382617251863959067308512508045616499 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=20379721260641300819816369585673508434493382617251863959067308512508045616499 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_throughput_w_partial_write/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_throughput_w_readback 37555663579100560956891942261618339972225212644774729024217673693581583462692 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_throughput_w_readback/latest run_opts='+zero_delays=1 +partial_access_pct=0 +init_w_readback=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3850514724 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/5.sram_ctrl_throughput_w_readback.3850514724 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_throughput_w_readback.3850514724 -covoverwrite' seed=37555663579100560956891942261618339972225212644774729024217673693581583462692 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37555663579100560956891942261618339972225212644774729024217673693581583462692 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_throughput_w_readback/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_lc_escalation 39258554602606019864142489455198402139461959199251316345112280396240676043484 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_lc_escalation/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=1731836636 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/5.sram_ctrl_lc_escalation.1731836636 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_lc_escalation.1731836636 -covoverwrite' seed=39258554602606019864142489455198402139461959199251316345112280396240676043484 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39258554602606019864142489455198402139461959199251316345112280396240676043484 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_access_during_key_req 70346712565674673420799346553384947126358025771435767263511168110429125697719 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_access_during_key_req/latest run_opts='+zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2567921847 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/5.sram_ctrl_access_during_key_req.2567921847 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_access_during_key_req.2567921847 -covoverwrite' seed=70346712565674673420799346553384947126358025771435767263511168110429125697719 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70346712565674673420799346553384947126358025771435767263511168110429125697719 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_access_during_key_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_access_during_key_req_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_executable 25233602208349495851978457979539349434528535497251137830651591275808962108690 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_executable/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2223234322 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/5.sram_ctrl_executable.2223234322 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_executable.2223234322 -covoverwrite' seed=25233602208349495851978457979539349434528535497251137830651591275808962108690 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=25233602208349495851978457979539349434528535497251137830651591275808962108690 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_executable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_executable_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_regwen 90755232221833001919608441722089227911809529197567458214710097052605448218258 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_regwen/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=324822674 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/5.sram_ctrl_regwen.324822674 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_regwen.324822674 -covoverwrite' seed=90755232221833001919608441722089227911809529197567458214710097052605448218258 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90755232221833001919608441722089227911809529197567458214710097052605448218258 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_ram_cfg 64649213683179842008943805291825230700256803088412235515119158341049126782688 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_ram_cfg/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=955025120 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/5.sram_ctrl_ram_cfg.955025120 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_ram_cfg.955025120 -covoverwrite' seed=64649213683179842008943805291825230700256803088412235515119158341049126782688 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=64649213683179842008943805291825230700256803088412235515119158341049126782688 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_ram_cfg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_ram_cfg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mem_walk 84988088387111141814628900297085313071271170919467665436936285716304326716960 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_mem_walk/latest run_opts='+csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=1762553376 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/5.sram_ctrl_mem_walk.1762553376 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_mem_walk.1762553376 -covoverwrite' seed=84988088387111141814628900297085313071271170919467665436936285716304326716960 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=84988088387111141814628900297085313071271170919467665436936285716304326716960 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_mem_walk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mem_partial_access 24924560017149957749281947664979627894058895204103556501350318837345494221151 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_mem_partial_access/latest run_opts='+run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3978805599 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/5.sram_ctrl_mem_partial_access.3978805599 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_mem_partial_access.3978805599 -covoverwrite' seed=24924560017149957749281947664979627894058895204103556501350318837345494221151 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=24924560017149957749281947664979627894058895204103556501350318837345494221151 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_mem_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_readback_err 70231231948532751288571955206980434385949173364954320943728685826241879674429 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_readback_err/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=950079037 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/5.sram_ctrl_readback_err.950079037 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_readback_err.950079037 -covoverwrite' seed=70231231948532751288571955206980434385949173364954320943728685826241879674429 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=70231231948532751288571955206980434385949173364954320943728685826241879674429 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_readback_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_readback_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mubi_enc_err 14613030356041221286810600275737054254552931024129995333886504427063562782071 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_mubi_enc_err/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2012792183 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mubi_enc_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/5.sram_ctrl_mubi_enc_err.2012792183 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_mubi_enc_err.2012792183 -covoverwrite' seed=14613030356041221286810600275737054254552931024129995333886504427063562782071 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=14613030356041221286810600275737054254552931024129995333886504427063562782071 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_mubi_enc_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_mubi_enc_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_all_with_rand_reset 57561927073644276284007817182150330205939211812700081904904336340178285661553 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3246951793 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/5.sram_ctrl_stress_all_with_rand_reset.3246951793 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_stress_all_with_rand_reset.3246951793 -covoverwrite' seed=57561927073644276284007817182150330205939211812700081904904336340178285661553 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57561927073644276284007817182150330205939211812700081904904336340178285661553 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_all 58543473888130027139512451379293771152081638032237343658924222993691880651906 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_stress_all/latest run_opts='+test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3001220226 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/5.sram_ctrl_stress_all.3001220226 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_stress_all.3001220226 -covoverwrite' seed=58543473888130027139512451379293771152081638032237343658924222993691880651906 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=58543473888130027139512451379293771152081638032237343658924222993691880651906 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 69350797457389119930286495220749962329037710213663958367409058749700202395857 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2942138577 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/5.sram_ctrl_tl_errors.2942138577 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.sram_ctrl_tl_errors.2942138577 -covoverwrite' seed=69350797457389119930286495220749962329037710213663958367409058749700202395857 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=69350797457389119930286495220749962329037710213663958367409058749700202395857 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 52110079537204749496967182607016179819573349989035271429026122889735495495571 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2953326483 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/5.sram_ctrl_tl_intg_err.2953326483 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 5.sram_ctrl_tl_intg_err.2953326483 -covoverwrite' seed=52110079537204749496967182607016179819573349989035271429026122889735495495571 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=52110079537204749496967182607016179819573349989035271429026122889735495495571 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_alert_test 75267557247095889999551285852603742338285551969682109292592671343697782046032 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=658439504 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/5.sram_ctrl_alert_test.658439504 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 5.sram_ctrl_alert_test.658439504 -covoverwrite' seed=75267557247095889999551285852603742338285551969682109292592671343697782046032 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=75267557247095889999551285852603742338285551969682109292592671343697782046032 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/5.sram_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_smoke 85929641220608294195002750844029973878504493604347314872510948059932853214328 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_smoke/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=532094072 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/6.sram_ctrl_smoke.532094072 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_smoke.532094072 -covoverwrite' seed=85929641220608294195002750844029973878504493604347314872510948059932853214328 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85929641220608294195002750844029973878504493604347314872510948059932853214328 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_multiple_keys 56803932444731646274808044102077966501686912703787407017795970801043450579691 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_multiple_keys/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=1503611627 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/6.sram_ctrl_multiple_keys.1503611627 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_multiple_keys.1503611627 -covoverwrite' seed=56803932444731646274808044102077966501686912703787407017795970801043450579691 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56803932444731646274808044102077966501686912703787407017795970801043450579691 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_multiple_keys/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_multiple_keys_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_bijection 98546911794479312489958855437882886680167400030621921872119988844778272528379 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_bijection/latest run_opts='+test_timeout_ns=2000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3563788283 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/6.sram_ctrl_bijection.3563788283 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_bijection.3563788283 -covoverwrite' seed=98546911794479312489958855437882886680167400030621921872119988844778272528379 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=98546911794479312489958855437882886680167400030621921872119988844778272528379 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_bijection/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_bijection_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_pipeline 14121496928574762632739843371507356018314157341266791139916362000394910925825 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_stress_pipeline/latest run_opts='+zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2363982849 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/6.sram_ctrl_stress_pipeline.2363982849 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_stress_pipeline.2363982849 -covoverwrite' seed=14121496928574762632739843371507356018314157341266791139916362000394910925825 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=14121496928574762632739843371507356018314157341266791139916362000394910925825 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_stress_pipeline/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_pipeline_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_partial_access 104537842516014718085170642324031472003262433325770974289594083410753279163413 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_partial_access/latest run_opts='+partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3058629653 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/6.sram_ctrl_partial_access.3058629653 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_partial_access.3058629653 -covoverwrite' seed=104537842516014718085170642324031472003262433325770974289594083410753279163413 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104537842516014718085170642324031472003262433325770974289594083410753279163413 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_partial_access_b2b 7161530706503529785941104994280841225181848663273250281627269415154841594006 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_partial_access_b2b/latest run_opts='+partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2734467222 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/6.sram_ctrl_partial_access_b2b.2734467222 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_partial_access_b2b.2734467222 -covoverwrite' seed=7161530706503529785941104994280841225181848663273250281627269415154841594006 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=7161530706503529785941104994280841225181848663273250281627269415154841594006 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_partial_access_b2b/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_pipeline_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_max_throughput 59006190273452612930997109229103629448848950916083877449725038358340741604380 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_max_throughput/latest run_opts='+zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=1944560668 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/6.sram_ctrl_max_throughput.1944560668 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_max_throughput.1944560668 -covoverwrite' seed=59006190273452612930997109229103629448848950916083877449725038358340741604380 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=59006190273452612930997109229103629448848950916083877449725038358340741604380 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_max_throughput/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_throughput_w_partial_write 30612460088161061726845820461533924576444932122408409952525723959990250670875 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_throughput_w_partial_write/latest run_opts='+zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=647007003 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/6.sram_ctrl_throughput_w_partial_write.647007003 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_throughput_w_partial_write.647007003 -covoverwrite' seed=30612460088161061726845820461533924576444932122408409952525723959990250670875 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=30612460088161061726845820461533924576444932122408409952525723959990250670875 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_throughput_w_partial_write/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_throughput_w_readback 106257517629553056609975715054101671608352598096305044298421956626414513064320 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_throughput_w_readback/latest run_opts='+zero_delays=1 +partial_access_pct=0 +init_w_readback=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=1434618240 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/6.sram_ctrl_throughput_w_readback.1434618240 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_throughput_w_readback.1434618240 -covoverwrite' seed=106257517629553056609975715054101671608352598096305044298421956626414513064320 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=106257517629553056609975715054101671608352598096305044298421956626414513064320 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_throughput_w_readback/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_lc_escalation 46665466453132326202187272670804593887547946663955821550857332425590290010988 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_lc_escalation/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=1577079660 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/6.sram_ctrl_lc_escalation.1577079660 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_lc_escalation.1577079660 -covoverwrite' seed=46665466453132326202187272670804593887547946663955821550857332425590290010988 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46665466453132326202187272670804593887547946663955821550857332425590290010988 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_access_during_key_req 23927937989357106491301792060524527729658728201227023488343299824161627459505 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_access_during_key_req/latest run_opts='+zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2682146737 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/6.sram_ctrl_access_during_key_req.2682146737 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_access_during_key_req.2682146737 -covoverwrite' seed=23927937989357106491301792060524527729658728201227023488343299824161627459505 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=23927937989357106491301792060524527729658728201227023488343299824161627459505 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_access_during_key_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_access_during_key_req_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_executable 4307941894633292791417184164114860254656407376572422280173647343033351047309 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_executable/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2185922701 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/6.sram_ctrl_executable.2185922701 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_executable.2185922701 -covoverwrite' seed=4307941894633292791417184164114860254656407376572422280173647343033351047309 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4307941894633292791417184164114860254656407376572422280173647343033351047309 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_executable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_executable_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_regwen 97620702040370067570488842605846478928127699152234469764104278371171904447648 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_regwen/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2352145568 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/6.sram_ctrl_regwen.2352145568 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_regwen.2352145568 -covoverwrite' seed=97620702040370067570488842605846478928127699152234469764104278371171904447648 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=97620702040370067570488842605846478928127699152234469764104278371171904447648 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_ram_cfg 4998659070238600121460020819817152623945979948426461059795293302520537899854 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_ram_cfg/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3285148494 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/6.sram_ctrl_ram_cfg.3285148494 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_ram_cfg.3285148494 -covoverwrite' seed=4998659070238600121460020819817152623945979948426461059795293302520537899854 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=4998659070238600121460020819817152623945979948426461059795293302520537899854 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_ram_cfg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_ram_cfg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mem_walk 37126046905111728136334301756031882888400502900629511102545800962453154881309 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_mem_walk/latest run_opts='+csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=4183613213 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/6.sram_ctrl_mem_walk.4183613213 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_mem_walk.4183613213 -covoverwrite' seed=37126046905111728136334301756031882888400502900629511102545800962453154881309 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=37126046905111728136334301756031882888400502900629511102545800962453154881309 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_mem_walk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mem_partial_access 86551765069988008088398089876823897876180616489856560290832729772340049136487 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_mem_partial_access/latest run_opts='+run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=231263079 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/6.sram_ctrl_mem_partial_access.231263079 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_mem_partial_access.231263079 -covoverwrite' seed=86551765069988008088398089876823897876180616489856560290832729772340049136487 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=86551765069988008088398089876823897876180616489856560290832729772340049136487 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_mem_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_readback_err 6788019076355130014756301165057972469831948905898014970477860458289655796081 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_readback_err/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3096269169 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/6.sram_ctrl_readback_err.3096269169 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_readback_err.3096269169 -covoverwrite' seed=6788019076355130014756301165057972469831948905898014970477860458289655796081 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=6788019076355130014756301165057972469831948905898014970477860458289655796081 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_readback_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_readback_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mubi_enc_err 115695291549116722339421740592452765375787269490924393444707224300096576244848 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_mubi_enc_err/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=1261390960 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mubi_enc_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/6.sram_ctrl_mubi_enc_err.1261390960 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_mubi_enc_err.1261390960 -covoverwrite' seed=115695291549116722339421740592452765375787269490924393444707224300096576244848 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115695291549116722339421740592452765375787269490924393444707224300096576244848 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_mubi_enc_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_mubi_enc_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_all_with_rand_reset 15032501698969623944803850602651232511416618173566374410605861645002545313622 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=348665686 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/6.sram_ctrl_stress_all_with_rand_reset.348665686 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_stress_all_with_rand_reset.348665686 -covoverwrite' seed=15032501698969623944803850602651232511416618173566374410605861645002545313622 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=15032501698969623944803850602651232511416618173566374410605861645002545313622 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_all 79848605557074134654349760891150624713512706711264370589727328260995998315187 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_stress_all/latest run_opts='+test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=1093956275 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/6.sram_ctrl_stress_all.1093956275 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_stress_all.1093956275 -covoverwrite' seed=79848605557074134654349760891150624713512706711264370589727328260995998315187 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79848605557074134654349760891150624713512706711264370589727328260995998315187 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 89144454296412164401489090102428764000807765818284415117360021613344723062178 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4183838114 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/6.sram_ctrl_tl_errors.4183838114 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.sram_ctrl_tl_errors.4183838114 -covoverwrite' seed=89144454296412164401489090102428764000807765818284415117360021613344723062178 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89144454296412164401489090102428764000807765818284415117360021613344723062178 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 39237216013212139158496098196596316253804936110355168996024397354402303311175 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4145675591 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/6.sram_ctrl_tl_intg_err.4145675591 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 6.sram_ctrl_tl_intg_err.4145675591 -covoverwrite' seed=39237216013212139158496098196596316253804936110355168996024397354402303311175 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39237216013212139158496098196596316253804936110355168996024397354402303311175 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_alert_test 59545530479932753794182614324282823310768784373870345891945557149130681643029 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=490106901 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/6.sram_ctrl_alert_test.490106901 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 6.sram_ctrl_alert_test.490106901 -covoverwrite' seed=59545530479932753794182614324282823310768784373870345891945557149130681643029 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=59545530479932753794182614324282823310768784373870345891945557149130681643029 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/6.sram_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_smoke 88675438127248810677480260218687181595771144856415558376537398315055343680142 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_smoke/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3627498126 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/7.sram_ctrl_smoke.3627498126 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_smoke.3627498126 -covoverwrite' seed=88675438127248810677480260218687181595771144856415558376537398315055343680142 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88675438127248810677480260218687181595771144856415558376537398315055343680142 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_smoke/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_multiple_keys 81702311575824541126997307284155924603059099047899697548744692351578618689535 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_multiple_keys/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2304735231 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_multiple_keys_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/7.sram_ctrl_multiple_keys.2304735231 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_multiple_keys.2304735231 -covoverwrite' seed=81702311575824541126997307284155924603059099047899697548744692351578618689535 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81702311575824541126997307284155924603059099047899697548744692351578618689535 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_multiple_keys/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_multiple_keys_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_bijection 53031324372147488268008157915188781667190758201396650783291671764655986669364 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_bijection/latest run_opts='+test_timeout_ns=2000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=1489729332 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_bijection_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/7.sram_ctrl_bijection.1489729332 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_bijection.1489729332 -covoverwrite' seed=53031324372147488268008157915188781667190758201396650783291671764655986669364 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53031324372147488268008157915188781667190758201396650783291671764655986669364 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_bijection/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_bijection_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_pipeline 102820221804088738259153158272259317588962061273345590152327852951888498886245 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_stress_pipeline/latest run_opts='+zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=708150885 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/7.sram_ctrl_stress_pipeline.708150885 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_stress_pipeline.708150885 -covoverwrite' seed=102820221804088738259153158272259317588962061273345590152327852951888498886245 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=102820221804088738259153158272259317588962061273345590152327852951888498886245 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_stress_pipeline/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_pipeline_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_partial_access 19447936415327458066221367895494498290759310869118580842424602713799335580014 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_partial_access/latest run_opts='+partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=1115656558 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_smoke_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/7.sram_ctrl_partial_access.1115656558 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_partial_access.1115656558 -covoverwrite' seed=19447936415327458066221367895494498290759310869118580842424602713799335580014 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19447936415327458066221367895494498290759310869118580842424602713799335580014 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_smoke_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_partial_access_b2b 93338435213179463188423900343147914309157479197288710529671051244017454279176 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_partial_access_b2b/latest run_opts='+partial_access_pct=90 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=519432712 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_pipeline_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/7.sram_ctrl_partial_access_b2b.519432712 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_partial_access_b2b.519432712 -covoverwrite' seed=93338435213179463188423900343147914309157479197288710529671051244017454279176 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93338435213179463188423900343147914309157479197288710529671051244017454279176 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_partial_access_b2b/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_pipeline_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_max_throughput 47839622040703323966935858042987202258433298771766688744260949544793733426678 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_max_throughput/latest run_opts='+zero_delays=1 +partial_access_pct=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=593325558 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/7.sram_ctrl_max_throughput.593325558 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_max_throughput.593325558 -covoverwrite' seed=47839622040703323966935858042987202258433298771766688744260949544793733426678 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=47839622040703323966935858042987202258433298771766688744260949544793733426678 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_max_throughput/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_throughput_w_partial_write 46584949245790275769630754589668984238091500274425227503129991585254409971804 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_throughput_w_partial_write/latest run_opts='+zero_delays=1 +partial_access_pct=20 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=912468060 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/7.sram_ctrl_throughput_w_partial_write.912468060 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_throughput_w_partial_write.912468060 -covoverwrite' seed=46584949245790275769630754589668984238091500274425227503129991585254409971804 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=46584949245790275769630754589668984238091500274425227503129991585254409971804 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_throughput_w_partial_write/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_throughput_w_readback 76902818295748207783356544525520863153326086795923783917599516531269972964532 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_throughput_w_readback/latest run_opts='+zero_delays=1 +partial_access_pct=0 +init_w_readback=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3543839924 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_throughput_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/7.sram_ctrl_throughput_w_readback.3543839924 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_throughput_w_readback.3543839924 -covoverwrite' seed=76902818295748207783356544525520863153326086795923783917599516531269972964532 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=76902818295748207783356544525520863153326086795923783917599516531269972964532 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_throughput_w_readback/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_throughput_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_lc_escalation 45456496935251822968005364657842978701106386711236809917766963256287669644622 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_lc_escalation/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=797830478 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_lc_escalation_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/7.sram_ctrl_lc_escalation.797830478 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_lc_escalation.797830478 -covoverwrite' seed=45456496935251822968005364657842978701106386711236809917766963256287669644622 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45456496935251822968005364657842978701106386711236809917766963256287669644622 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_lc_escalation/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_lc_escalation_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_access_during_key_req 19132105249241399260229283756923375044751224012068972656288315941733789461890 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_access_during_key_req/latest run_opts='+zero_delays=1 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=4072533378 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_access_during_key_req_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/7.sram_ctrl_access_during_key_req.4072533378 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_access_during_key_req.4072533378 -covoverwrite' seed=19132105249241399260229283756923375044751224012068972656288315941733789461890 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19132105249241399260229283756923375044751224012068972656288315941733789461890 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_access_during_key_req/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_access_during_key_req_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_executable 82114437333575827702460635510318152936041508344554799111488336545157254977596 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_executable/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3255801916 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_executable_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/7.sram_ctrl_executable.3255801916 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_executable.3255801916 -covoverwrite' seed=82114437333575827702460635510318152936041508344554799111488336545157254977596 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=82114437333575827702460635510318152936041508344554799111488336545157254977596 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_executable/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_executable_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_regwen 57730279825545608614111317652709450857642535571528244897398806577433465896288 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_regwen/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=4255956320 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_regwen_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/7.sram_ctrl_regwen.4255956320 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_regwen.4255956320 -covoverwrite' seed=57730279825545608614111317652709450857642535571528244897398806577433465896288 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=57730279825545608614111317652709450857642535571528244897398806577433465896288 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_regwen/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_regwen_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_ram_cfg 71899273867708331472931013171555657049781271608056476360796518942314137687266 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_ram_cfg/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2903020770 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_ram_cfg_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/7.sram_ctrl_ram_cfg.2903020770 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_ram_cfg.2903020770 -covoverwrite' seed=71899273867708331472931013171555657049781271608056476360796518942314137687266 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71899273867708331472931013171555657049781271608056476360796518942314137687266 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_ram_cfg/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_ram_cfg_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mem_walk 33572330007811668829936247557563434152235660452088874632799397811855797492052 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_mem_walk/latest run_opts='+csr_mem_walk +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3864762708 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/7.sram_ctrl_mem_walk.3864762708 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_mem_walk.3864762708 -covoverwrite' seed=33572330007811668829936247557563434152235660452088874632799397811855797492052 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=33572330007811668829936247557563434152235660452088874632799397811855797492052 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_mem_walk/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mem_partial_access 67001490579654100670805523320416424218343146982645387150684791276915911389693 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_mem_partial_access/latest run_opts='+run_mem_partial_access +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3217912317 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/7.sram_ctrl_mem_partial_access.3217912317 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_mem_partial_access.3217912317 -covoverwrite' seed=67001490579654100670805523320416424218343146982645387150684791276915911389693 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=67001490579654100670805523320416424218343146982645387150684791276915911389693 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_mem_partial_access/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_readback_err 71008564523590782009329959238187522367185250070607678735250971986591394386932 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_readback_err/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=1435063284 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_readback_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/7.sram_ctrl_readback_err.1435063284 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_readback_err.1435063284 -covoverwrite' seed=71008564523590782009329959238187522367185250070607678735250971986591394386932 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=71008564523590782009329959238187522367185250070607678735250971986591394386932 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_readback_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_readback_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_mubi_enc_err 55870700161592299925835744659359434201645940321164935578605301575505256134085 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_mubi_enc_err/latest run_opts='+test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=592721349 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_mubi_enc_err_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/7.sram_ctrl_mubi_enc_err.592721349 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_mubi_enc_err.592721349 -covoverwrite' seed=55870700161592299925835744659359434201645940321164935578605301575505256134085 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=55870700161592299925835744659359434201645940321164935578605301575505256134085 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_mubi_enc_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_mubi_enc_err_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_all_with_rand_reset 12030655453396534375709117239299191822920717399565464842102014530152181410906 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_stress_all_with_rand_reset/latest run_opts='+run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=sram_ctrl_stress_all_vseq +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=862334042 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/7.sram_ctrl_stress_all_with_rand_reset.862334042 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_stress_all_with_rand_reset.862334042 -covoverwrite' seed=12030655453396534375709117239299191822920717399565464842102014530152181410906 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=12030655453396534375709117239299191822920717399565464842102014530152181410906 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_stress_all_with_rand_reset/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_stress_all 21961994118831617499967987881193609140515586928816621271021134898996678600517 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_stress_all/latest run_opts='+test_timeout_ns=10000000000 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=2905188165 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_stress_all_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/7.sram_ctrl_stress_all.2905188165 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_stress_all.2905188165 -covoverwrite' seed=21961994118831617499967987881193609140515586928816621271021134898996678600517 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=21961994118831617499967987881193609140515586928816621271021134898996678600517 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_stress_all/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_stress_all_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 96703809870135727199688976469342877720262367729467439557428087082051235574094 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3599069518 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/7.sram_ctrl_tl_errors.3599069518 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.sram_ctrl_tl_errors.3599069518 -covoverwrite' seed=96703809870135727199688976469342877720262367729467439557428087082051235574094 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96703809870135727199688976469342877720262367729467439557428087082051235574094 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 50275014102344935668753468856928405654105717890651023494765582454050841678002 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1274794162 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/7.sram_ctrl_tl_intg_err.1274794162 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 7.sram_ctrl_tl_intg_err.1274794162 -covoverwrite' seed=50275014102344935668753468856928405654105717890651023494765582454050841678002 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=50275014102344935668753468856928405654105717890651023494765582454050841678002 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_alert_test 53086519792081027306371554679779057718304706778782617673548188193499192602193 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=1511632465 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/7.sram_ctrl_alert_test.1511632465 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 7.sram_ctrl_alert_test.1511632465 -covoverwrite' seed=53086519792081027306371554679779057718304706778782617673548188193499192602193 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=53086519792081027306371554679779057718304706778782617673548188193499192602193 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/7.sram_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 34979949782629848762790022683010826601115630323738552144127870512112347949034 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/8.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1774757866 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/8.sram_ctrl_tl_errors.1774757866 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.sram_ctrl_tl_errors.1774757866 -covoverwrite' seed=34979949782629848762790022683010826601115630323738552144127870512112347949034 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34979949782629848762790022683010826601115630323738552144127870512112347949034 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/8.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 104770717279775150128540961497548251409018798235840929571503353332554494586784 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/8.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3415682976 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/8.sram_ctrl_tl_intg_err.3415682976 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 8.sram_ctrl_tl_intg_err.3415682976 -covoverwrite' seed=104770717279775150128540961497548251409018798235840929571503353332554494586784 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=104770717279775150128540961497548251409018798235840929571503353332554494586784 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/8.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_alert_test 88684369666353718552795714389317726351168428654474992263380537872518796992953 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/8.sram_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=3760644537 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/8.sram_ctrl_alert_test.3760644537 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 8.sram_ctrl_alert_test.3760644537 -covoverwrite' seed=88684369666353718552795714389317726351168428654474992263380537872518796992953 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=88684369666353718552795714389317726351168428654474992263380537872518796992953 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/8.sram_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 19956872311438510228117556671681084126777326028724125310334898598952657161514 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/9.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1071844650 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/9.sram_ctrl_tl_errors.1071844650 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.sram_ctrl_tl_errors.1071844650 -covoverwrite' seed=19956872311438510228117556671681084126777326028724125310334898598952657161514 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=19956872311438510228117556671681084126777326028724125310334898598952657161514 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/9.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 40786119603950747384957313274433948648069135316571287721392133245205742788754 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/9.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1293066386 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/9.sram_ctrl_tl_intg_err.1293066386 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 9.sram_ctrl_tl_intg_err.1293066386 -covoverwrite' seed=40786119603950747384957313274433948648069135316571287721392133245205742788754 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=40786119603950747384957313274433948648069135316571287721392133245205742788754 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/9.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_alert_test 112501435741100373425868172649705165959756267969328698677882937346402883010381 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/9.sram_ctrl_alert_test/latest run_opts='+run_alert_test +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/default/xcelium.d -r tb +SVSEED=1023213389 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/default/9.sram_ctrl_alert_test.1023213389 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope default -covtest 9.sram_ctrl_alert_test.1023213389 -covoverwrite' seed=112501435741100373425868172649705165959756267969328698677882937346402883010381 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=112501435741100373425868172649705165959756267969328698677882937346402883010381 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/9.sram_ctrl_alert_test/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 95741246504793831377201032380911520092563194542276970795155002845167884305964 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/10.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2742945324 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/10.sram_ctrl_tl_errors.2742945324 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 10.sram_ctrl_tl_errors.2742945324 -covoverwrite' seed=95741246504793831377201032380911520092563194542276970795155002845167884305964 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=95741246504793831377201032380911520092563194542276970795155002845167884305964 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/10.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 39376214873343102770684180328705005911537394400823052465119104428420966499922 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/10.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=876987986 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/10.sram_ctrl_tl_intg_err.876987986 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 10.sram_ctrl_tl_intg_err.876987986 -covoverwrite' seed=39376214873343102770684180328705005911537394400823052465119104428420966499922 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=39376214873343102770684180328705005911537394400823052465119104428420966499922 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/10.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 45960276686106269436285820566269627986650582033389169264042263016483735507300 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/11.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1334350180 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/11.sram_ctrl_tl_errors.1334350180 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 11.sram_ctrl_tl_errors.1334350180 -covoverwrite' seed=45960276686106269436285820566269627986650582033389169264042263016483735507300 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=45960276686106269436285820566269627986650582033389169264042263016483735507300 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/11.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 90797239222164908554389308332301692940302704624681566469274044725122333441427 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/11.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=660635027 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/11.sram_ctrl_tl_intg_err.660635027 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 11.sram_ctrl_tl_intg_err.660635027 -covoverwrite' seed=90797239222164908554389308332301692940302704624681566469274044725122333441427 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=90797239222164908554389308332301692940302704624681566469274044725122333441427 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/11.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 61370943863522883061358543662386345913506894175526747910463084595020379465072 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/12.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1628972400 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/12.sram_ctrl_tl_errors.1628972400 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 12.sram_ctrl_tl_errors.1628972400 -covoverwrite' seed=61370943863522883061358543662386345913506894175526747910463084595020379465072 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=61370943863522883061358543662386345913506894175526747910463084595020379465072 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/12.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 108675325943606644572619262382734241239663732467091862963256476777610452451184 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/12.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=432062320 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/12.sram_ctrl_tl_intg_err.432062320 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 12.sram_ctrl_tl_intg_err.432062320 -covoverwrite' seed=108675325943606644572619262382734241239663732467091862963256476777610452451184 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=108675325943606644572619262382734241239663732467091862963256476777610452451184 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/12.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 17806885061775852579207187481712431951270214233378002787149102117973813005195 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/13.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2002946955 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/13.sram_ctrl_tl_errors.2002946955 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 13.sram_ctrl_tl_errors.2002946955 -covoverwrite' seed=17806885061775852579207187481712431951270214233378002787149102117973813005195 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=17806885061775852579207187481712431951270214233378002787149102117973813005195 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/13.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 56644723105195882797114967607099834283118261299700111854661956504700616672364 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/13.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3895690348 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/13.sram_ctrl_tl_intg_err.3895690348 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 13.sram_ctrl_tl_intg_err.3895690348 -covoverwrite' seed=56644723105195882797114967607099834283118261299700111854661956504700616672364 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=56644723105195882797114967607099834283118261299700111854661956504700616672364 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/13.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 350560225840631970022734102181578434817048282879307234433783372911020244819 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/14.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3781853011 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/14.sram_ctrl_tl_errors.3781853011 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 14.sram_ctrl_tl_errors.3781853011 -covoverwrite' seed=350560225840631970022734102181578434817048282879307234433783372911020244819 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=350560225840631970022734102181578434817048282879307234433783372911020244819 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/14.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 93985256666954616236159066051475012021076626398866608820744860756491649153156 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/14.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1039923332 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/14.sram_ctrl_tl_intg_err.1039923332 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 14.sram_ctrl_tl_intg_err.1039923332 -covoverwrite' seed=93985256666954616236159066051475012021076626398866608820744860756491649153156 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93985256666954616236159066051475012021076626398866608820744860756491649153156 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/14.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 68327042971161623940053453487087813491280814777933919458961977038059564650524 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/15.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2953269276 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/15.sram_ctrl_tl_errors.2953269276 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 15.sram_ctrl_tl_errors.2953269276 -covoverwrite' seed=68327042971161623940053453487087813491280814777933919458961977038059564650524 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=68327042971161623940053453487087813491280814777933919458961977038059564650524 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/15.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 10180535339705617508199855533783840367707713508846878138570598525329215756117 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/15.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=971151189 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/15.sram_ctrl_tl_intg_err.971151189 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 15.sram_ctrl_tl_intg_err.971151189 -covoverwrite' seed=10180535339705617508199855533783840367707713508846878138570598525329215756117 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=10180535339705617508199855533783840367707713508846878138570598525329215756117 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/15.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 63406313536160448031153487068194083724420721984969447229739198056637340698272 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/16.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4226139808 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/16.sram_ctrl_tl_errors.4226139808 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 16.sram_ctrl_tl_errors.4226139808 -covoverwrite' seed=63406313536160448031153487068194083724420721984969447229739198056637340698272 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=63406313536160448031153487068194083724420721984969447229739198056637340698272 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/16.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 16702802095894914931999902336309038237227736814515576165068740652940415218429 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/16.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1123824381 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/16.sram_ctrl_tl_intg_err.1123824381 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 16.sram_ctrl_tl_intg_err.1123824381 -covoverwrite' seed=16702802095894914931999902336309038237227736814515576165068740652940415218429 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=16702802095894914931999902336309038237227736814515576165068740652940415218429 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/16.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 96406167582382448636920105715395997123349872695135322314211137296819962210475 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/17.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2555340971 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/17.sram_ctrl_tl_errors.2555340971 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 17.sram_ctrl_tl_errors.2555340971 -covoverwrite' seed=96406167582382448636920105715395997123349872695135322314211137296819962210475 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=96406167582382448636920105715395997123349872695135322314211137296819962210475 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/17.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 85370357601273093897949380799078835226216600352103335416978553036517486832635 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/17.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2611424251 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/17.sram_ctrl_tl_intg_err.2611424251 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 17.sram_ctrl_tl_intg_err.2611424251 -covoverwrite' seed=85370357601273093897949380799078835226216600352103335416978553036517486832635 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=85370357601273093897949380799078835226216600352103335416978553036517486832635 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/17.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 113969305376085467150577751302063194903616232718500797144855554524796851892164 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/18.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2239541188 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/18.sram_ctrl_tl_errors.2239541188 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 18.sram_ctrl_tl_errors.2239541188 -covoverwrite' seed=113969305376085467150577751302063194903616232718500797144855554524796851892164 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=113969305376085467150577751302063194903616232718500797144855554524796851892164 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/18.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 79964724034130042782187636743316138018135314312658748191052356115299356205777 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/18.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=853893841 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/18.sram_ctrl_tl_intg_err.853893841 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 18.sram_ctrl_tl_intg_err.853893841 -covoverwrite' seed=79964724034130042782187636743316138018135314312658748191052356115299356205777 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=79964724034130042782187636743316138018135314312658748191052356115299356205777 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/18.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 34523356465965448160905224096527441526942902079549309915762340982247561696957 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/19.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3207141053 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/19.sram_ctrl_tl_errors.3207141053 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 19.sram_ctrl_tl_errors.3207141053 -covoverwrite' seed=34523356465965448160905224096527441526942902079549309915762340982247561696957 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=34523356465965448160905224096527441526942902079549309915762340982247561696957 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/19.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 62158949243355440330864874585002038838750142694643223213813968138006636324664 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/19.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2245060408 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/19.sram_ctrl_tl_intg_err.2245060408 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 19.sram_ctrl_tl_intg_err.2245060408 -covoverwrite' seed=62158949243355440330864874585002038838750142694643223213813968138006636324664 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=62158949243355440330864874585002038838750142694643223213813968138006636324664 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/19.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 42891087850369069688171188519034222106022552823491396119798446801787709369945 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/20.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3682938457 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/20.sram_ctrl_tl_errors.3682938457 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 20.sram_ctrl_tl_errors.3682938457 -covoverwrite' seed=42891087850369069688171188519034222106022552823491396119798446801787709369945 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=42891087850369069688171188519034222106022552823491396119798446801787709369945 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/20.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 44234568892428784503397757748703179154240840250864305309089800491686999988839 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/20.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=4079852135 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/20.sram_ctrl_tl_intg_err.4079852135 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 20.sram_ctrl_tl_intg_err.4079852135 -covoverwrite' seed=44234568892428784503397757748703179154240840250864305309089800491686999988839 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=44234568892428784503397757748703179154240840250864305309089800491686999988839 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/20.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 81455402592241491015372782956276428080266416055971985576982796608671992932662 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/21.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=163211574 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/21.sram_ctrl_tl_errors.163211574 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 21.sram_ctrl_tl_errors.163211574 -covoverwrite' seed=81455402592241491015372782956276428080266416055971985576982796608671992932662 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=81455402592241491015372782956276428080266416055971985576982796608671992932662 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/21.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 89374184864149197999090907154997743288238163238378747884978229194179388585578 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/21.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1720923754 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/21.sram_ctrl_tl_intg_err.1720923754 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 21.sram_ctrl_tl_intg_err.1720923754 -covoverwrite' seed=89374184864149197999090907154997743288238163238378747884978229194179388585578 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=89374184864149197999090907154997743288238163238378747884978229194179388585578 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/21.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 115388904656938693756017824309794368488324663729870190797891197776674164614441 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/22.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=933012777 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/22.sram_ctrl_tl_errors.933012777 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 22.sram_ctrl_tl_errors.933012777 -covoverwrite' seed=115388904656938693756017824309794368488324663729870190797891197776674164614441 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=115388904656938693756017824309794368488324663729870190797891197776674164614441 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/22.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 32921981876170454577317435867157607535643073380577335402509728344001794046316 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/22.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3175905644 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/22.sram_ctrl_tl_intg_err.3175905644 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 22.sram_ctrl_tl_intg_err.3175905644 -covoverwrite' seed=32921981876170454577317435867157607535643073380577335402509728344001794046316 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=32921981876170454577317435867157607535643073380577335402509728344001794046316 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/22.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 103141355259563444183991191021100262059059545708286611970715926759759915933275 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/23.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=3950403163 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/23.sram_ctrl_tl_errors.3950403163 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 23.sram_ctrl_tl_errors.3950403163 -covoverwrite' seed=103141355259563444183991191021100262059059545708286611970715926759759915933275 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=103141355259563444183991191021100262059059545708286611970715926759759915933275 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/23.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 80311243720904802766743923875957575797003293924542380975477083121503737161742 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/23.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=740763662 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/23.sram_ctrl_tl_intg_err.740763662 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 23.sram_ctrl_tl_intg_err.740763662 -covoverwrite' seed=80311243720904802766743923875957575797003293924542380975477083121503737161742 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=80311243720904802766743923875957575797003293924542380975477083121503737161742 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/23.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_errors 83324290015230494149563622662912864891811911548538837400400258300536070462437 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/24.sram_ctrl_tl_errors/latest run_opts='+run_tl_errors +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=1829100517 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/24.sram_ctrl_tl_errors.1829100517 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 24.sram_ctrl_tl_errors.1829100517 -covoverwrite' seed=83324290015230494149563622662912864891811911548538837400400258300536070462437 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=83324290015230494149563622662912864891811911548538837400400258300536070462437 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/24.sram_ctrl_tl_errors/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
sram_ctrl_tl_intg_err 93863142659373883183683716118216924092963960445278583714685593449375044814764 None
[Executing]:
make -f /nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk run build_seed=None post_run_cmds='' pre_run_cmds='' proj_root=/nightly/current_run/opentitan run_cmd=xrun run_dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/24.sram_ctrl_tl_intg_err/latest run_opts='+run_tl_intg_err +en_scb=0 +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -input /nightly/current_run/opentitan/hw/dv/tools/sim.tcl -nocopyright -licqueue -64bit -xmlibdirname /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/cover_reg_top/xcelium.d -r tb +SVSEED=2676836268 +UVM_TESTNAME=sram_ctrl_base_test +UVM_TEST_SEQ=sram_ctrl_common_vseq -nowarn DSEM2009 +en_cov=1 -covmodeldir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage/cover_reg_top/24.sram_ctrl_tl_intg_err.2676836268 -covworkdir /nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/coverage -covscope cover_reg_top -covtest 24.sram_ctrl_tl_intg_err.2676836268 -covoverwrite' seed=93863142659373883183683716118216924092963960445278583714685593449375044814764 sw_build_cmd='python /nightly/current_run/opentitan/util/py/scripts/build_sw_collateral_for_sim.py --sw-images='"'"''"'"' --sw-build-opts='"'"''"'"' --sw-build-device= --seed=93863142659373883183683716118216924092963960445278583714685593449375044814764 --run-dir=/nightly/current_run/scratch/master/sram_ctrl_ret-sim-xcelium/24.sram_ctrl_tl_intg_err/latest' sw_build_device='' sw_build_opts='' sw_images='' uvm_test=sram_ctrl_base_test uvm_test_seq=sram_ctrl_common_vseq
/usr/bin/env: ‘bash’: Input/output error
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:50: pre_run] Error 126
Job cancelled because all of its dependencies failed or were killed. 1 test run
sram_ctrl None None
Job cancelled because one of its dependencies failed or was killed. 1 test run
sram_ctrl None None